1
FEATURES
25ns maximum (5 volt supply) address access time
Asynchronous operation for compatible with industry
standard 512K x 8 SRAMs
TTL compatible inputs and output levels, three-state
bidirectional data bus
Operational environment:
- Total dose: 50 krads(Si)
- SEL Immune >110 MeV-cm2/mg
- LETTH(0.25) = >52 MeV-cm2/mg
- Saturated Cross Section (cm2) per bit, 2.8E-8
- <1.1E-9 errors/bit-day , Adams 90% geosynchronous
heavy ion
Packaging:
- 68-lead dual cavity ceramic quad flatpack (CQFP)
(11.0 grams)
Standard Microcircuit Drawing 5962-01511
- QML Q and Q+ compliant part
- QML V pending
INTRODUCTION
The UT9Q512K32E RadT ol product is a high-performance 2M
byte (16Mbit) CMOS static RAM multi-chip module (MCM),
organized as four individual 524,288 x 8 bit SRAMs with a
common output enable. Mem ory expansion is provided by an
active LOW chip enable (En), an active LOW output enable (G),
and three-state drivers. This device has a power-down feature
that reduces power consumption by more than 90% when
deselected.
W riting to each memory is accomplished by taking chip enable
(En) input LOW and write enable (Wn) inputs LOW. Data on
the eight I/O pins (DQ0 through DQ7) is then written into th e
location specified on the address pins (A0 through A18). Reading
from the device is accomplished by taking chip enable (En) and
output enable (G) LOW while forcing write enable (Wn) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
Perform 8, 16, 24 or 32 bit accesses by making Wn along with
En a common input to any combination of the discrete memory
die.
Standard Products
UT9Q512K32E 16 Megabit Rad SRAM MCM
Data Sheet
June 25, 2010
512K x 8 512K x 8 512K x 8 512K x 8
DQ(31:24)
or
DQ3(7:0)
DQ(23:16)
or
DQ2(7:0)
DQ(15:8)
or
DQ1(7:0)
DQ(7:0)
or
DQ0(7:0)
G
A(18:0)
W3
E3 E2E1 E0
W2 W1W0
Figure 1. UT9Q512K32E SRAM Block Diagram
2
PIN NAMES
DEVICE OPERATION
The UT9Q512K32E has three control inputs called Enable 1
(En), Write Enable (Wn), and Output Enable (G); 19 address
inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). En
Device Enable controls device selection, active, and standby
modes. Asserting En enables the device, causes IDD to rise to its
active value, and decodes the 19 address inputs to select one of
524,288 words in the memory. Wn controls read and write
operations. During a read cycle, G must be asserted to enable
the outputs.
Table 1. Device Operation Truth Table
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of Wn greater than VIH (min) and En less than
VIL (max) defines a read cycle. Read access time is measured
from the latter of Device Enable, Output Enable, or valid address
to valid data output.
SRAM Read Cycle 1, the Address Access in figure 3a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and Wn deasserted. Valid data appears on data
outputs DQ(7:0) after the specified tAVQV is satisf ied . Outputs
remain active throughout the entire cycl e. As long as Device
Enable and Output Enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (tAVAV).
SRAM read Cycle 2, the Chip Enable - Controlled Access in
figure 3b, is initiated by En going active while G remains
asserted, Wn remains deasserted, and the addresses remain
stable for the entire cycle. After the specified tETQV is satisfied,
the eight-bit word addressed by A(18:0) is accessed and appears
at the data outputs DQ(7:0).
SRAM read Cycle 3, the Output Enable - Controlled Access in
figure 3c, is initiated by G going active while En is asserted, Wn
is deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
A(18:0) Address Wn Write Enable
DQn(7:0) Data Input/Output GOutput Enable
En Enable VDD Power
VSS Ground
G Wn En I/O Mode Mode
X1X 1 3-state Standby
X 0 0 Data in Write
1 1 0 3-state Read2
0 1 0 Data out Read
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Top View
DQ0(0)
DQ1(0)
DQ2(0)
DQ3(0)
DQ4(0)
DQ5(0)
DQ6(0)
DQ7(0)
VSS
DQ0(1)
DQ1(1)
DQ2(1)
DQ3(1)
DQ4(1)
DQ5(1)
DQ6(1)
DQ7(1)
NC
A0
A1
A2
A3
A4
A5
E2
VSS
E3
W0
A6
A7
A8
A9
A10
VDD
VDD
A11
A12
A13
A14
A15
A16
E0
G
E1
A17
W1
W2
W3
A18
NC
NC
DQ0(2)
DQ1(2)
DQ2(2)
DQ3(2)
DQ4(2)
DQ5(2)
DQ6(2)
DQ7(2)
VSS
DQ0(3)
DQ1(3)
DQ2(3)
DQ3(3)
DQ4(3)
DQ5(3)
DQ6(3)
DQ7(3)
Figure 2. 25ns SRAM Pinout (68)
3
WRITE CYCLE
A combination of Wn less than VIL(max) and En less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than VIH(min), or when Wn is less
than VIL(max).
Write Cycle 1, the Write Enable-controlled Access is defined by
a write terminated by Wn going high, with En still active. The
write pulse width is defined by tWLWH when the write is initiated
by Wn, and by t ETWH when the write is initiated by En. Unless
the outputs have been previously placed in the high-impedance
state by G, the user must wait tWLQZ before applying data to the
nine bidirectional pins DQ(7:0) to avoid bus contention.
W rite Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the latter of En going inactive. The write
pulse width is defined by tWLEF when the write is initiated by
Wn, and by tETEF when the write is initiated by the En going
active. For the Wn initiated write, unless the outputs have been
previously placed in the high-impedance state by G, the user
must wait tWLQZ before applying data to the eight bidirectional
pins DQ(7:0) to avoid bus contention.
OPERATIONAL ENVIRONMENT
The UT9Q512K32E SRAM incorporates features which allows
operation in a limited environm ent .
Table 2. Operational Environment
Design Specifications1
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
Total Dose 50 krad(Si)
Heavy Ion
Error Rate2<1.1E-9 Errors/Bit-Day
4
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only , and functional operatio n of the device
at these or any other conditions beyon d limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS
VDD DC supply voltage -0.5 to 7.0V
VI/O Voltage on any pin -0.5 to 7.0V
TSTG Storage temperature -65 to +150°C
PDMaximum power dissipation 1.0W (per byte)
TJMaximum junctio n temperature +150°C
ΘJC Thermal resistance, junction-to-case 10°C/W
IIDC input current ±10 mA
SYMBOL PARAMETER LIMITS
VDD Positive supply voltage 4.5 to 5.5V
TCCase temperature range (W) Screen - 40°C to 105°C
VIN DC input voltage 0V to VDD
5
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
-40°C to +105°C (VDD = 5.0V + 10% for (W) screenin g)
Notes:
* Post-radiation pe rfo rm ance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could af fect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltage (TTL) 2.0 V
VIL Low-level input voltage (TTL) 0.8 V
VOL1 Low-level output voltage IOL = 8mA, VDD =4.5V (TTL) 0.4 V
VOL2 Low-level output voltage IOL = 200μA,VDD =4.5V (CMOS) 0.08 V
VOH1 High-level output voltage IOH = -4mA,VDD =4.5V (TTL) 2.4 V
VOH2 High-level output voltage IOH = 200μA,VDD =4.5V (CMOS) 3.0 V
CIN1Input capacitance ƒ = 1MHz @ 0V 45 pF
CIO1Bidirectional I/O capacitance ƒ = 1MHz @ 0V 25 pF
IIN Input leakage current VIN = VDD and VSS, VDD = VDD (max) -2 2 μA
IOZ Three-state output leakage current VO = VDD and VSS
VDD = VDD (max)
G = VDD (max)
-2 2 μA
IOS2, 3 Short-circuit output current VDD = VDD (max), VO = VDD
VDD = VDD (max), VO = 0V
-90 90 mA
IDD(OP) Supply current operating
@ 1MHz
(per byte)
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
40 mA
IDD1(OP) Supply current operating
@40MHz
(per byte)
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
70 mA
IDD2(SB) Supply current standby
@0MHz
(per byte)
Inputs: VIL = VSS
IOUT = 0mA
E1 = VDD - 0.5, VDD = VDD (max)
VIH = VDD - 0.5V
9
24
mA
mA
-40°C and
25°C
105°C
6
AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*
-40°C to +105°C (VDD = 5.0V + 10% for (W) screening)
Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test.
2. Three-state is defined as a 500mV change from steady-state output voltage.
3. The ET (enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters.
4. The EF (enable false) notation refers to the rising edge of En. SEU immunity does not affect the read parameters.
SYMBOL PARAMETER MIN MAX UNIT
tAVAV1Read cycle time 25 ns
tAVQV Read access time 25 ns
tAXQX2Output hold time 3ns
tGLQX2G-controlled Output Enable tim e 0ns
tGLQV G-controlled Output Enable time (Read Cycle 3) 10 ns
tGHQZ2G-controlled output three-state time 10 ns
tETQX2,3 En-controlled Output Enable time 3ns
tETQV3En-controlled access time 25 ns
tEFQZ1,2,4 En-controlled output th ree-state time 10 ns
{
{}
}
VLOAD + 500mV
VLOAD - 500mV
VLOAD
VH - 500mV
VL + 500mV
Active to High Z LevelsHigh Z to Active Levels
Figure 3. 5-Volt SRAM Loading
7
Assumptions:
1. En and G < VIL (max) and Wn > VIH (min)
A(18:0)
DQn(7:0)
Figure 4a. SRAM Read Cycle 1: Address Access
tAVAV
tAVQV
tAXQX
Previous Valid Data Valid Data
Assumptions:
1. G < VIL (max) and Wn > VIH (min)
A(18:0)
Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access
En
DATA VALID
tEFQZ
tETQV tETQX
DQn(7:0)
Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access
A(18:0)
Qn(7:0)
tGHQZ
ssumptions:
En < VIL (max) and Wn > VIH (min)
tGLQV
tGLQX
tAVQV
DATA VALID
8
AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)*
-40°C to +105°C (VDD = 5.0V + 10% for (W) screening)
Notes:
* Post-radiation performan c e guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test performed with outputs disab l ed (G high).
2. Three-state is defined as 500mV change from steady-state output voltage.
SYMBOL PARAMETER MIN MAX UNIT
tAVAV1Write cyc le time 25 ns
tETWH Device Enable to end of write 20 ns
tAVET Address setup time for write (En - controlled) 1 ns
tAVWL Address setup time for write (Wn - controlled) 0 ns
tWLWH Write pulse width 20 ns
tWHAX Address hold time for write (Wn - controlled) 0 ns
tEFAX Address hold time for Device Enable (En - controlled) 0 ns
tWLQZ2Wn - controlled three-state time 10 ns
tWHQX2Wn - controlled Output Enable time 5 ns
tETEF Device Enable pulse width (En - controlled) 20 ns
tDVWH Data setup time 15 ns
tWHDX Data hold time 2 ns
tWLEF Device Enable controlled write pulse width 20 ns
tDVEF Data setup time 15 ns
tEFDX Data hold time 2 ns
tAVWH Address valid to end of write 20 ns
tWHWL1Write disable time 5 ns
9
Assumptions:
1. G < VIL (max). If G > VIH (min) then Qn(7:0) will be
in three-state for the entire cycle.
2. G high for tAVAV cycle.
Wn
tAVWL
Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access
A(18:0)
Qn(7:0)
En
tAVAV2
Dn(7:0) APPLIED DATA
tDVWH tWHDX
tETWH
tWLWH tWHAX
tWHQX
tWLQZ
tAVWH
tWHWL
10
tEFDX
Assumptions & Notes:
1. G < VIL (max). If G > VIH (min) then Qn(7:0) will be in three-state for the entire cycle.
2. Either En scenario above can occur.
3. G high for tAVAV cycle.
A(18:0)
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access
Wn
En
Dn(7:0) APPLIED DATA
En
Qn(7:0) tWLQZ
tETEF
tWLEF
tDVEF
tAVAV3
tAVET
tAVET
tETEF
tEFAX
tEFAX
or
Notes:
1. 50pF including scope probe and test socket capacitance.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(i.e., CMOS input = VDD/2).
90%
Figure 6. AC Test Loads and Input Waveforms
Input Pulses
10%
< 5ns < 5ns
VLOAD = 1.55V
300 ohms
50pF
CMOS
0.5V
VDD-0.05V
10%
11
DA T A RETENTION CHARACTERISTICS (Pre-Radiation) *(VDD2 = VDD2 (min), 1 Sec DR
Pulse)
Notes:
*Post-radiation performance guaranteed at 25oC per MIL-
STD-883 Method 10 19.
1. E n= VDD all other inputs = VDD or VSS
VDD
DATA RETENTION MODE
tR
4.5V
4.5V VDR > 2.5V
Figure 7. Low VDD Data Retention Waveform
tEFR
EN VDD = VDR
SYMBOL PARAMETER TEMP MINIMUM MAXIMUM UNIT
VDR VDD1 for data retention -- 2.5 -- V
IDDR 1 Data retention current
(per byte) -40oC
25oC
105oC
--
--
--
9
9
24
mA
mA
mA
tEFR1Chip deselect to data retention time -- 0 -- ns
tR1Operation recovery time -- tAVAV -- ns
12
PACKAGING
Notes:
1. All exposed metallized areas are gold plated over nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Packages may be shipped with repaired leads as shown.
4. Coplanarity requirements do not apply in repaired area.
5. Letter designations are to cross reference to MIL-STD- 1835.
6. Lead true position tolerances are coplanarity are not measured.
7. Capacitor pads are sized to fit CDR32 (1206) capacitors.
Figure 8. 68-Lead Ceramic Quad Flatpack
13
ORDERING INFORMATION
512K32 16Megabit SRAM MCM:
Device Type:
- = 25ns access time, 5.0V operation
Package Type:
(S) = 68-lead dual cavity CQFP
Screening: (Notes 2 & 3)
(P) = Prototype flow
(W) = -40oC to +105oC
Lead Finish: (Note 1)
(C) = Gold
Notes:
1. Gold lead finish only.
2. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at 25oC. Radiation neither tested nor guaranteed.
3. Extended Industrial T emperature Range flow per Aeroflex Colorado Springs M anufacturing Flows Document. Devices are tested at -40°C to +105°C.
Radiation neither tested nor guaranteed.
UT9Q512K32E -* * * *
Aeroflex Core Part Number
14
512K32E 16Megabit SRAM MCM: SMD
5962 - 01511 * * ** *
Notes:
1. Lead finish is "C" (Gold) only.
2. Aeroflex’ s Q+ assembly flow, as defined in section 4.2.2.d of the SMD, provides QM L-Q product throug h the SMD that is m anufactured
with Aeroflex’s standard QML-V flow.
3. Total dose radiation must be specified when ordering.
Federal Stoc k Class Designator: No Options
Total Dose: (Note 3)
(D) = 1E4 (10krad(Si) )
(P) = 3E4 (30krad(S i))
(L) = 5E4 (50krad(Si))
Drawing Number: 01511
Device Type (Note 2)
02 = 25 ns access time, 5.0V operation, (-40oC to +105oC)
03 = 25 ns access time, 5.0V operation, (-40°C to +105°C) manufactured to QML- Q+ flow
Class Designator:
(Q) = QML Class Q
(V) = QML Class V (Pending, Contact Factory)
Case Outline:
(Y) = 68-lead dual cavity CQFP
Lead Finish: (Note 1)
(C) = Gold
15
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Aeroflex Colorado Springs, Inc., reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
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convey a license under any patent rights, copyrights,
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced HiRel
