"74LV00DB,118" - NXP SEMICONDUCTORS

1. General description

The 74LV00 is a low-voltage Si-gate CMOS device that is pin and function compatible with

74HC00 and 74HCT00.

The 74LV00 provides a quad 2-input NAND function.

2. Features

■Wide operating voltage: 1.0 V to 5.5 V

■Optimized for low voltage applications: 1.0 V to 3.6 V

■Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

■Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C

■Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and

Tamb =25°C

■ESD protection:

◆HBM JESD22-A114E exceeds 2000 V

◆MM JESD22-A115-A exceeds 200 V

■Multiple package options

■Speciﬁed from −40 °Cto+85°C and from −40 °C to +125 °C

3. Ordering information

74LV00

Quad 2-input NAND gate

Rev. 03 — 20 December 2007 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74LV00N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74LV00D −40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm SOT108-1

74LV00DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads;

body width 5.3 mm SOT337-1

74LV00PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm SOT402-1

74LV00BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 14 terminals;

body 2.5 ×3×0.85 mm

SOT762-1

Product data sheet Rev. 03 — 20 December 2007 2 of 14

NXP Semiconductors 74LV00

Quad 2-input NAND gate

4. Functional diagram

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)

mna212

1A 1Y

2A 2Y

3A 3Y

10 8

4A 4Y

13 11

mna246

10 &

13 &

mna211

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as

a supply pin or input.

Fig 4. Pin conﬁguration DIP14, SO14 and (T)SSOP14 Fig 5. Pin conﬁguration DHVQFN14

1A VCC

1B 4B

1Y 4A

2A 4Y

2B 3B

2Y 3A

GND 3Y

001aac938

7 8

001aah092

74LV00

Transparent top view

VCC(1)

2Y 3A

2B 3B

2A 4Y

1Y 4A

1B 4B

GND

VCC

6 9

5 10

4 11

3 12

2 13

terminal 1

index area

Table 2. Pin description

Symbol Pin Description

1A 1 data input

1B 2 data input

1Y 3 data output

2A 4 data input

2B 5 data input

2Y 6 data output

Product data sheet Rev. 03 — 20 December 2007 3 of 14

NXP Semiconductors 74LV00

Quad 2-input NAND gate

6. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] Ptot derates linearly with 12 mW/K above 70 °C.

[3] Ptot derates linearly with 8 mW/K above 70 °C.

[4] Ptot derates linearly with 5.5 mW/K above 60 °C.

[5] Ptot derates linearly with 4.5 mW/K above 60 °C.

GND 7 ground (0 V)

3Y 8 data output

3A 9 data input

3B 10 data input

4Y 11 data output

4A 12 data input

4B 13 data input

VCC 14 supply voltage

Table 2. Pin description

…continued

Symbol Pin Description

Table 3. Function table[1]

Input Output

nA nB nY

LXH

XLH

HHL

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +7.0 V

IIK input clamping current VI < −0.5 V or VI>V

CC + 0.5 V [1] -±20 mA

IOK output clamping current VO<−0.5 V or VO>V

CC + 0.5 V [1] -±50 mA

IOoutput current VO = −0.5 V to (VCC + 0.5 V) - ±25 mA

ICC supply current - 50 mA

IGND ground current −50 - mA

Tstg storage temperature −65 +150 °C

Ptot total power dissipation Tamb = −40 °C to +125 °C

DIP14 package [2] - 750 mW

SO14 package [3] - 500 mW

(T)SSOP14 package [4] - 500 mW

DHVQFN14 package [5] - 500 mW

Product data sheet Rev. 03 — 20 December 2007 4 of 14

NXP Semiconductors 74LV00

Quad 2-input NAND gate

8. Recommended operating conditions

[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to

VCC = 1.0 V (with input levels GND or VCC).

9. Static characteristics

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage [1] 1.0 3.3 5.5 V

VIinput voltage 0 - VCC V

VOoutput voltage 0 - VCC V

Tamb ambient temperature −40 +25 +125 °C

∆t/∆V input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V

VCC = 2.0 V to 2.7 V - - 200 ns/V

VCC = 2.7 V to 3.6 V - - 100 ns/V

VCC = 3.6 V to 5.5 V - - 50 ns/V

Table 6. Static characteristics

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max

VIH HIGH-level input voltage VCC = 1.2 V 0.9 - - 0.9 - V

VCC = 2.0 V 1.4 - - 1.4 - V

VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V

VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC -V

VIL LOW-level input voltage VCC = 1.2 V - - 0.3 - 0.3 V

VCC = 2.0 V - - 0.6 - 0.6 V

VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V

VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V

VOH HIGH-level output voltage VI = VIH or VIL

IO = −100 µA; VCC = 1.2 V - 1.2 - - - V

IO = −100 µA; VCC = 2.0 V 1.8 2.0 - 1.8 - V

IO = −100 µA; VCC = 2.7 V 2.5 2.7 - 2.5 - V

IO = −100 µA; VCC = 3.0 V 2.8 3.0 - 2.8 - V

IO = −100 µA; VCC = 4.5 V 4.3 4.5 - 4.3 - V

IO = −6 mA; VCC = 3.0 V 2.4 2.82 - 2.2 - V

IO = −12 mA; VCC = 4.5 V 3.6 4.2 - 3.5 - V

Product data sheet Rev. 03 — 20 December 2007 5 of 14

NXP Semiconductors 74LV00

Quad 2-input NAND gate

[1] Typical values are measured at Tamb = 25 °C.

10. Dynamic characteristics

[1] All typical values are measured at Tamb =25°C.

[2] tpd is the same as tPLH and tPHL.

[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).

[4] CPD is used to determine the dynamic power dissipation (PDin µW).

PD=C

PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:

fi= input frequency in MHz, fo= output frequency in MHz

CL= output load capacitance in pF

VCC = supply voltage in V

N = number of inputs switching

Σ(CL×VCC2×fo) = sum of the outputs.

VOL LOW-level output voltage VI = VIH or VIL

IO = 100 µA; VCC = 1.2 V - 0 - - - V

IO = 100 µA; VCC = 2.0 V - 0 0.2 - 0.2 V

IO = 100 µA; VCC = 2.7 V - 0 0.2 - 0.2 V

IO = 100 µA; VCC = 3.0 V - 0 0.2 - 0.2 V

IO = 100 µA; VCC = 4.5 V - 0 0.2 - 0.2 V

IO = 6 mA; VCC = 3.0 V - 0.25 0.40 - 0.50 V

IO = 12 mA; VCC = 4.5 V - 0.35 0.55 - 0.65 V

IIinput leakage current VI=V

CC or GND; VCC = 5.5 V - - 1.0 - 1.0 µA

ICC supply current VI = VCC or GND; IO = 0 A;

VCC = 5.5 V - - 20.0 - 40 µA

∆ICC additional supply current per input; VI = VCC − 0.6 V;

VCC = 2.7 V to 3.6 V - - 500 - 850 µA

CIinput capacitance - 3.5 - - - pF

Table 6. Static characteristics

…continued

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max

Table 7. Dynamic characteristics

GND = 0 V; For test circuit see Figure 7.

Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max

tpd propagation delay nA, nB to nY; see Figure 6 [2]

VCC = 1.2 V - 45 - - - ns

VCC = 2.0 V - 15 26 - 31 ns

VCC = 2.7 V - 11 18 - 23 ns

VCC = 3.0 V to 3.6 V; CL=15pF [3] -7- - -ns

VCC = 3.0 V to 3.6 V [3] - 9.0 15 - 18 ns

VCC = 4.5 V to 5.5 V [3] - 6.5 11 - 14 ns

CPD power dissipation

capacitance CL= 50 pF; fi = 1 MHz;

VI= GND to VCC

[4] -22- - -pF

Product data sheet Rev. 03 — 20 December 2007 6 of 14

NXP Semiconductors 74LV00

Quad 2-input NAND gate

11. Waveforms

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 6. The input (nA, nB) to output (nY) propagation delays

001aah088

tPHL

tPLH

nY output

nA, nB input

GND

VOH

VOL

Table 8. Measurement points

Supply voltage Input Output

VCC VMVM

< 2.7 V 0.5VCC 0.5VCC

2.7 V to 3.6 V 1.5 V 1.5 V

≥ 4.5 V 0.5VCC 0.5VCC

Test data is given in Table 9.

Deﬁnitions test circuit:

RT = Termination resistance should be equal to output impedance Zoof the pulse generator.

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

Fig 7. Load circuit for switching times

VCC

VIVO

001aaa663

D.U.T. CL

50 pF

RTRL

1 kΩ

PULSE

GENERATOR

Table 9. Test data

Supply voltage Input

VCC VItr, tf

< 2.7 V VCC ≤ 2.5 ns

2.7 V to 3.6 V 2.7 V ≤ 2.5 ns

≥ 4.5 V VCC ≤ 2.5 ns

Product data sheet Rev. 03 — 20 December 2007 7 of 14

NXP Semiconductors 74LV00

Quad 2-input NAND gate

12. Package outline

Fig 8. Package outline SOT27-1 (DIP14)

UNIT A

max. 1 2 (1) (1)

b1cD (1)

Ee M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT27-1 99-12-27

03-02-13

min. A

max. bmax.

1.73

1.13 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 2.24.2 0.51 3.2

0.068

0.044 0.021

0.015 0.77

0.73

0.014

0.009 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0870.17 0.02 0.13

050G04 MO-001 SC-501-14

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

Product data sheet Rev. 03 — 20 December 2007 8 of 14

NXP Semiconductors 74LV00

Quad 2-input NAND gate

Fig 9. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 03 — 20 December 2007 9 of 14

NXP Semiconductors 74LV00

Quad 2-input NAND gate

Fig 10. Package outline SOT337-1 (SSOP14)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25 0.2

7.9

7.6 1.03

0.63 0.9

0.7 1.4

0.9 8

0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT337-1 99-12-27

03-02-19

(1)

vMA

14 8

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1

max.

Product data sheet Rev. 03 — 20 December 2007 10 of 14

NXP Semiconductors 74LV00

Quad 2-input NAND gate

Fig 11. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 03 — 20 December 2007 11 of 14

NXP Semiconductors 74LV00

Quad 2-input NAND gate

Fig 12. Package outline SOT762-1 (DHVQFN14)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.65

1.35

2.6

2.4 1.15

0.85

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT762-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT762-1

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 9

02-10-17

03-01-27

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 03 — 20 December 2007 12 of 14

NXP Semiconductors 74LV00

Quad 2-input NAND gate

13. Abbreviations

14. Revision history

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LV00_3 20071220 Product data sheet - 74LV00_2

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Section 3: DHVQFN14 package added.

•Section 7: derating values added for DHVQFN14 package.

•Section 12: outline drawing added for DHVQFN14 package.

74LV00_2 19980420 Product speciﬁcation - 74LV00_1

74LV00_1 19970203 Product speciﬁcation - -

Product data sheet Rev. 03 — 20 December 2007 13 of 14

NXP Semiconductors 74LV00

Quad 2-input NAND gate

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74LV00

Quad 2-input NAND gate

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 20 December 2007

Document identifier: 74LV00_3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Functional description . . . . . . . . . . . . . . . . . . . 3

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

8 Recommended operating conditions. . . . . . . . 4

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13

15.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

16 Contact information. . . . . . . . . . . . . . . . . . . . . 13

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14