LMC6035, LMC6035-Q1, LMC6036 www.ti.com SNOS875G - JANUARY 2000 - REVISED APRIL 2013 LMC6035/LMC6035-Q1/LMC6036 Low Power 2.7V Single Supply CMOS Operational Amplifiers Check for Samples: LMC6035, LMC6036 FEATURES APPLICATIONS * * * * * * * * * * * * 1 2 * * * * * * (Typical Unless Otherwise Noted) LMC6035 in DSBGA Package Ensured 2.7V, 3V, 5V and 15V Performance Specified for 2 k and 600 Loads Wide Operating Range: 2.0V to 15.5V Ultra Low Input Current: 20fA Rail-to-Rail Output Swing - @ 600: 200mV from Either Rail at 2.7V - @ 100k: 5mV from Either Rail at 2.7V High Voltage Gain: 126dB Wide Input Common-Mode Voltage Range - -0.1V to 2.3V at VS = 2.7V Low Distortion: 0.01% at 10kHz LMC6035 Dual LMC6036 Quad See AN-1112 (Literature Number SNVA009) for DSBGA Considerations AEC-Q100 Grade 3 Qualified (LMC6035-Q1) Filters High Impedance Buffer or Preamplifier Battery Powered Electronics Medical Instrumentation Automotive Applications DESCRIPTION The LMC6035/6 is an economical, low voltage op amp capable of rail-to-rail output swing into loads of 600. LMC6035 is available in a chip sized package (8-Bump DSBGA) using micro SMD package technology. Both allow for single supply operation and are ensured for 2.7V, 3V, 5V and 15V supply voltage. The 2.7 supply voltage corresponds to the End-of-Life voltage (0.9V/cell) for three NiCd or NiMH batteries in series, making the LMC6035/6 well suited for portable and rechargeable systems. It also features a well behaved decrease in its specifications at supply voltages below its ensured 2.7V operation. This provides a "comfort zone" for adequate operation at voltages significantly below 2.7V. Its ultra low input currents (IIN) makes it well suited for low power active filter application, because it allows the use of higher resistor values and lower capacitor values. In addition, the drive capability of the LMC6035/6 gives these op amps a broad range of applications for low voltage systems. Connection Diagram Top View Figure 1. 8-Bump DSBGA Package (Bump Side Down) See Package Number YZR0008 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2013, Texas Instruments Incorporated LMC6035, LMC6035-Q1, LMC6036 SNOS875G - JANUARY 2000 - REVISED APRIL 2013 www.ti.com Table 1. DSBGA Connection Table LM6035IBP LMC6035IBPX Bump Number A1 OUTPUT A B1 LMC6035ITL LMC6035ITLX OUTPUT B - V+ + IN A C1 IN A OUTPUT A C2 V- IN A- C3 + IN A+ - IN B B3 IN B V- A3 OUTPUT B IN B+ A2 V+ IN B- These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) ESD Tolerance (3) Human Body Model (LMC6035, LMC6036) 3000V Human Body Model (LMC6035-Q1) 2000V Machine Model 300V Differential Input Voltage Supply Voltage Supply Voltage (V+ - V-) 16V Output Short Circuit to V + See (4) Output Short Circuit to V - See (5) Lead Temperature (soldering, 10 sec.) 260C Current at Output Pin 18mA Current at Input Pin 5mA Current at Power Supply Pin 35mA Storage Temperature Range -65C to +150C Junction Temperature (6) (1) (2) (3) (4) (5) (6) 150C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. Human body model, 1.5k in series with 100pF. Do not short circuit output to V+ when V+ is greater than 13V or reliability will be adversely affected. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150C. Output currents in excess of 30mA over long term may adversely affect reliability. The maximum power dissipation is a function of TJ(MAX), JA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) -TA)/ JA. All numbers apply for packages soldered directly onto a PC board with no air flow. Operating Ratings (1) Supply Voltage 2.0V to 15.5V -40C T J +85C Temperature Range LMC6035I and LMC6036I Thermal Resistance (JA) 8-pin VSSOP 230C/W 8-pin SOIC 175C/W 14-pin SOIC 127C/W 14-pin TSSOP 137C/W 8-Bump (6 mil) DSBGA 220C/W 8-Bump (12 mil) Thin DSBGA 220C/W (1) 2 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 LMC6035, LMC6035-Q1, LMC6036 www.ti.com SNOS875G - JANUARY 2000 - REVISED APRIL 2013 DC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C, V+ = 2.7V, V- = 0V, VCM = 1.0V, VO = 1.35V and RL > 1M. Boldface limits apply at the temperature extremes. Parameter LMC6035I/LMC6036I Test Conditions Min (1) Typ (2) Max (1) 5 6 Units VOS Input Offset Voltage 0.5 TCVOS Input Offset Voltage Average Drift 2.3 IIN Input Current See (3) 0.02 90 pA IOS Input Offset Current See (3) 0.01 45 PA RIN Input Resistance CMRR Common Mode Rejection Ratio 0.7V VCM 12.7V, V+ = 15V +PSRR Positive Power Supply Rejection Ratio -PSRR VCM Tera 63 60 96 dB 5V V+ 15V, VO = 2.5V 63 60 93 dB Negative Power Supply Rejection Ratio 0V V- -10V, VO = 2.5V, V+ = 5V 74 70 97 dB Input Common-Mode Voltage Range V+ = 2.7V For CMRR 40dB -0.1 V+ = 3V For CMRR 40dB V+ = 5V For CMRR 50dB V+ = 15V For CMRR 50dB Large Signal Voltage Gain (4) RL = 600 RL = 2k V 0.1 0.3 V 2.6 -0.5 4.2 3.9 0.3 0.5 2.3 -0.3 2.3 2.0 (1) (2) (3) (4) V/C > 10 2.0 1.7 AV mV -0.2 0.0 V 4.5 -0.5 -0.2 0.0 V 14.0 13.7 14.4 Sourcing 100 75 1000 V/mV Sinking 25 20 250 V/mV Sourcing 2000 V/mV Sinking 500 V/mV All limits are specified by testing or statistical analysis. Typical Values represent the most likely parametric norm or one sigma value. Ensured by design. V+ = 15V, VCM = 7.5V and R L connected to 7.5V. For Sourcing tests, 7.5V VO 11.5V. For Sinking tests, 3.5V VO 7.5V. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 Submit Documentation Feedback 3 LMC6035, LMC6035-Q1, LMC6036 SNOS875G - JANUARY 2000 - REVISED APRIL 2013 www.ti.com DC Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25C, V+ = 2.7V, V- = 0V, VCM = 1.0V, VO = 1.35V and RL > 1M. Boldface limits apply at the temperature extremes. Parameter VO LMC6035I/LMC6036I Test Conditions V + = 2.7V RL = 600 to 1.35V Output Swing Min (1) Typ (2) 2.0 1.8 2.5 0.2 V + = 2.7V RL = 2k to 1.35V 2.4 2.2 13.5 13.0 14.2 13.5 Output Current IS Supply Current V 0.2 0.4 V 1.25 1.50 14.8 0.12 IO V 0.5 0.7 14.5 0.36 V + = 15V, RL = 2 k to 7.5V Units 2.62 0.07 V + = 15V RL = 600 to 7.5V Max (1) V O = 0V Sourcing 4 3 8 V O = 2.7V Sinking 3 2 5 V 0.4 0.5 mA LMC6035 for Both Amplifiers V O = 1.35V 0.65 1.6 1.9 LMC6036 for All Four Amplifiers V O = 1.35V 1.3 2.7 3.0 mA AC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C, V+ = 2.7V, V- = 0V, VCM = 1.0V, V O = 1.35V and RL > 1 M. Boldface limits apply at the temperature extremes. Parameter Test Conditions Typ (1) Units (2) 1.5 V/s 1.4 MHz SR Slew Rate See GBW Gain Bandwidth Product V + = 15V m Phase Margin 48 Gm Gain Margin 17 dB Amp-to-Amp Isolation See (3) 130 dB en Input-Referred Voltage Noise f = 1kHz V CM = 1V 27 nV/Hz in Input Referred Current Noise f = 1kHz 0.2 fA/Hz THD Total Harmonic Distortion f = 10kHz, AV = -10 R L = 2k, VO = 8 VPP V + = 10V 0.01 % (1) (2) (3) 4 Typical Values represent the most likely parametric norm or one sigma value. V+ = 15V. Connected as voltage follower with 10V step input. Number specified is the slower of the positive and negative slew rates. Input referred, V + = 15V and RL = 100k connected to 7.5V. Each amp excited in turn with 1kHz to produce VO = 12 VPP. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 LMC6035, LMC6035-Q1, LMC6036 www.ti.com SNOS875G - JANUARY 2000 - REVISED APRIL 2013 Typical Performance Characteristics Unless otherwise specified, VS = 2.7V, single supply, TA = 25C Supply Current vs. Supply Voltage (Per Amplifier) Input Current vs. Temperature Figure 2. Figure 3. Sourcing Current vs. Output Voltage Sourcing Current vs. Output Voltage Figure 4. Figure 5. Sinking Current vs. Output Voltage Sinking Current vs. Output Voltage Figure 6. Figure 7. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 Submit Documentation Feedback 5 LMC6035, LMC6035-Q1, LMC6036 SNOS875G - JANUARY 2000 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, VS = 2.7V, single supply, TA = 25C 6 Output Voltage Swing vs. Supply Voltage Input Noise vs. Frequency Figure 8. Figure 9. Input Noise vs. Frequency Amp to Amp Isolation vs. Frequency Figure 10. Figure 11. Amp to Amp Isolation vs. Frequency +PSRR vs. Frequency Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 LMC6035, LMC6035-Q1, LMC6036 www.ti.com SNOS875G - JANUARY 2000 - REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified, VS = 2.7V, single supply, TA = 25C -PSRR vs. Frequency CMRR vs. Frequency Figure 14. Figure 15. CMRR vs. Input Voltage CMRR vs. Input Voltage Figure 16. Figure 17. Input Voltage vs. Output Voltage Input Voltage vs. Output Voltage Figure 18. Figure 19. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 Submit Documentation Feedback 7 LMC6035, LMC6035-Q1, LMC6036 SNOS875G - JANUARY 2000 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, VS = 2.7V, single supply, TA = 25C 8 Frequency Response vs. Temperature Frequency Response vs. Temperature Figure 20. Figure 21. Gain and Phase vs. Capacitive Load Gain and Phase vs. Capacitive Load Figure 22. Figure 23. Slew Rate vs. Supply Voltage Non-Inverting Large Signal Response Figure 24. Figure 25. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 LMC6035, LMC6035-Q1, LMC6036 www.ti.com SNOS875G - JANUARY 2000 - REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified, VS = 2.7V, single supply, TA = 25C Non-Inverting Large Signal Response Non-Inverting Large Signal Response Figure 26. Figure 27. Non-Inverting Small Signal Response Non-Inverting Small Signal Response Figure 28. Figure 29. Non-Inverting Large Signal Response Inverting Large Signal Response Figure 30. Figure 31. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 Submit Documentation Feedback 9 LMC6035, LMC6035-Q1, LMC6036 SNOS875G - JANUARY 2000 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, VS = 2.7V, single supply, TA = 25C 10 Inverting Large Signal Response Inverting Large Signal Response Figure 32. Figure 33. Inverting Small Signal Response Inverting Small Signal Response Figure 34. Figure 35. Inverting Small Signal Response Stability vs. Capacitive Load Figure 36. Figure 37. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 LMC6035, LMC6035-Q1, LMC6036 www.ti.com SNOS875G - JANUARY 2000 - REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified, VS = 2.7V, single supply, TA = 25C Stability vs. Capacitive Load Stability vs. Capacitive Load Figure 38. Figure 39. Stability vs. Capacitive Load Stability vs. Capacitive Load Figure 40. Figure 41. Stability vs. Capacitive Load Figure 42. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 Submit Documentation Feedback 11 LMC6035, LMC6035-Q1, LMC6036 SNOS875G - JANUARY 2000 - REVISED APRIL 2013 www.ti.com APPLICATION NOTES Background The LMC6035/6 is exceptionally well suited for low voltage applications. A desirable feature that the LMC6035/6 brings to low voltage applications is its output drive capability--a hallmark for TI's CMOS amplifiers. The circuit of Figure 43 illustrates the drive capability of the LMC6035/6 at 3V of supply. It is a differential output driver for a one-to-one audio transformer, like those used for isolating ground from the telephone lines. The transformer (T1) loads the op amps with about 600 of AC load, at 1 kHz. Capacitor C1 functions to block DC from the low winding resistance of T1. Although the value of C1 is relatively high, its load reactance (Xc) is negligible compared to inductive reactance (XI) of T1. Figure 43. Differential Driver The circuit in Figure 43 consists of one input signal and two output signals. U1A amplifies the input with an inverting gain of -2, while the U1B amplifies the input with a non-inverting gain of +2. Since the two outputs are 180 out of phase with each other, the gain across the differential output is 4. As the differential output swings between the supply rails, one of the op amps sources the current to the load, while the other op amp sinks the current. How good a CMOS op amp can sink or source a current is an important factor in determining its output swing capability. The output stage of the LMC6035/6--like many op amps--sources and sinks output current through two complementary transistors in series. This "totem pole" arrangement translates to a channel resistance (Rdson) at each supply rail which acts to limit the output swing. Most CMOS op amps are able to swing the outputs very close to the rails--except, however, under the difficult conditions of low supply voltage and heavy load. The LMC6035/6 exhibits exceptional output swing capability under these conditions. The scope photos of Figure 44 and Figure 45 represent measurements taken directly at the output (relative to GND) of U1A, in Figure 43. Figure 44 illustrates the output swing capability of the LMC6035, while Figure 45 provides a benchmark comparison. (The benchmark op amp is another low voltage (3V) op amp manufactured by one of our reputable competitors.) 12 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 LMC6035, LMC6035-Q1, LMC6036 www.ti.com SNOS875G - JANUARY 2000 - REVISED APRIL 2013 Figure 44. Output Swing Performance of the LMC6035 per the Circuit of Figure 43 Figure 45. Output Swing Performance of Benchmark Op Amp per the Circuit of Figure 43 Notice the superior drive capability of LMC6035 when compared with the benchmark measurement--even though the benchmark op amp uses twice the supply current. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 Submit Documentation Feedback 13 LMC6035, LMC6035-Q1, LMC6036 SNOS875G - JANUARY 2000 - REVISED APRIL 2013 www.ti.com Not only does the LMC6035/6 provide excellent output swing capability at low supply voltages, it also maintains high open loop gain (A VOL) with heavy loads. To illustrate this, the LMC6035 and the benchmark op amp were compared for their distortion performance in the circuit of Figure 43. The graph of Figure 46 shows this comparison. The y-axis represents percent Total Harmonic Distortion (THD plus noise) across the loaded secondary of T1. The x-axis represents the input amplitude of a 1 kHz sine wave. (Note that T1 loses about 20% of the voltage to the voltage divider of RL (600) and T1's winding resistances--a performance deficiency of the transformer.) Figure 46. THD+Noise Performance of LMC6035 and "Benchmark" per Circuit of Figure 43 Figure 46 shows the superior distortion performance of LMC6035/6 over that of the benchmark op amp. The heavy loading of the circuit causes the AVOL of the benchmark part to drop significantly which causes increased distortion. APPLICATION CIRCUITS Low-Pass Active Filter A common application for low voltage systems would be active filters, in cordless and cellular phones for example. The ultra low input currents (IIN) of the LMC6035/6 makes it well suited for low power active filter applications, because it allows the use of higher resistor values and lower capacitor values. This reduces power consumption and space. Figure 47 shows a low pass, active filter with a Butterworth (maximally flat) frequency response. Its topology is a Sallen and Key filter with unity gain. Note the normalized component values in parenthesis which are obtainable from standard filter design handbooks. These values provide a 1Hz cutoff frequency, but they can be easily scaled for a desired cutoff frequency (fc). The bold component values of Figure 47 provide a cutoff frequency of 3kHz. An example of the scaling procedure follows Figure 47. Figure 47. 2-Pole, 3kHz, Active, Sallen and Key, Lowpass Filter with Butterworth Response 14 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 LMC6035, LMC6035-Q1, LMC6036 www.ti.com SNOS875G - JANUARY 2000 - REVISED APRIL 2013 Low-Pass Frequency Scaling Procedure The actual component values represented in bold of Figure 47 were obtained with the following scaling procedure: 1. First determine the frequency scaling factor (FSF) for the desired cutoff frequency. Choosing fc at 3kHz, provides the following FSF computation: - FSF = 2 x 3kHz (desired cutoff freq.) = 18.84 x 10 3 2. Then divide all of the normalized capacitor values by the FSF as follows: C1' = C(Normalized)/FSF C1' = 0.707/18.84 x 103 = 37.93 x 10-6 C2' = 1.414/18.84 x 103 = 75.05 x 10-6 (C1' and C2': prior to impedance scaling) 3. Last, choose an impedance scaling factor (Z). This Z factor can be calculated from a standard value for C2. Then Z can be used to determine the remaining component values as follows: Z = C2'/C2(chosen) = 75.05 x 10 -6/6.8nF = 8.4k C1 = C1'/Z = 37.93 x 10-6 /8.4k = 4.52nF (Standard capacitor value chosen for C1 is 4.7nF ) R2(normalized) x Z = 1 x 8.4k = 8.4k R1 = R1(normalized) x Z = 1 x 8.4k = 8.4k R2 = (Standard value chosen for R1 and R2 is 8.45k ) High Pass Active Filter The previous low-pass filter circuit of Figure 47 converts to a high-pass active filter per Figure 48. Figure 48. 2 Pole, 300Hz, Sallen and Key, High-Pass Filter High-Pass Frequency Scaling Procedure Choose a standard capacitor value and scale the impedances in the circuit according to the desired cutoff frequency (300Hz) as follows: C = C1 = C2 Z = 1 Farad/C(chosen) x 2 x (desired cutoff freq.) = 1 Farad/6.8nF x 2 x 300 Hz = 78.05k R1 = Z x R1(normalized) = 78.05k x (1/0.707) = 110.4k (Standard value chosen for R1 is 110k ) R2 = Z x R2(normalized) = 78.05k x (1/1.414) = 55.2k (Standard value chosen for R1 is 54.9k ) Dual Amplifier Bandpass Filter The dual amplifier bandpass (DABP) filter features the ability to independently adjust fc and Q. In most other bandpass topologies, the fc and Q adjustments interact with each other. The DABP filter also offers both low sensitivity to component values and high Qs. The following application of Figure 49, provides a 1kHz center frequency and a Q of 100. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 Submit Documentation Feedback 15 LMC6035, LMC6035-Q1, LMC6036 SNOS875G - JANUARY 2000 - REVISED APRIL 2013 www.ti.com Figure 49. 2 Pole, 1kHz Active, Bandpass Filter DABP Component Selection Procedure Component selection for the DABP filter is performed as follows: 1. First choose a center frequency (fc). Figure 49 represents component values that were obtained from the following computation for a center frequency of 1kHz. R2 = R3 = 1/(2 f cC) Given: fc = 1kHz and C R2 = R3 = 1/(2 x 3kHz x 6.8nF) = 23.4k (chosen) = 6.8nF - (Chosen standard value is 23.7k ) 2. Then compute R1 for a desired Q (fc/BW) as follows: R1 = Q x R2. Choosing a Q of 100, R1 = 100 x 23.7k = 2.37M. PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with < 1000pA of leakage current requires special layout of the PC board. If one wishes to take advantage of the ultra-low bias current of the LMC6035/6, typically < 0.04pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may at times appear acceptably low. Under conditions of high humidity, dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6035 or LMC6036 inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op amp's inputs. See Figure 50. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012, which is normally considered a very large resistance, could leak 5pA if the trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the amplifiers actual performance. However, if a guard ring is held within 5mV of the inputs, then even a resistance of 1011 would cause only 0.05pA of leakage current, or perhaps a minor (2:1) degradation of the amplifier's performance. See Figure 51(a) through Figure 51(c) for typical connections of guard rings for standard op amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground and still provide some protection; see Figure 51(d). 16 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 LMC6035, LMC6035-Q1, LMC6036 www.ti.com SNOS875G - JANUARY 2000 - REVISED APRIL 2013 Figure 50. Example, using the LMC6036 of Guard Ring in PC Board Layout (a) Inverting Amplifier (Guard Ring Connections) (b) Non-Inverting Amplifier (Guard Ring Connections) (c) Follower (Guard Ring Connections) (d) Howland Current Pump Figure 51. Guard Ring Connections CAPACITIVE LOAD TOLERANCE Like many other op amps, the LMC6035/6 may oscillate when its applied load appears capacitive. The threshold of oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain follower. See the Typical Performance Characteristics. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 Submit Documentation Feedback 17 LMC6035, LMC6035-Q1, LMC6036 SNOS875G - JANUARY 2000 - REVISED APRIL 2013 www.ti.com The load capacitance interacts with the op amp's output resistance to create an additional pole. If this pole frequency is sufficiently low, it will degrade the op amp's phase margin so that the amplifier is no longer stable at low gains. As shown in Figure 52, the addition of a small resistor (50-100) in series with the op amp's output, and a capacitor (5pF-10pF) from inverting input to output pins, returns the phase margin to a safe value without interfering with lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without oscillation. Note that in all cases, the output will ring heavily when the load capacitance is near the threshold for oscillation. DSBGA Considerations Contrary to what might be guessed, the DSBGA package does not follow the trend of smaller packages having higher thermal resistance. LMC6035 in DSBGA has thermal resistance of 220C/W compared to 230C/W in VSSOP. Even when driving a 600 load and operating from 7.5V supplies, the maximum temperature rise will be under 4.5C. For application information specific to DSBGA, see Application note AN-1112 (Literature Number SNVA009). Figure 52. Rx, Cx Improve Capacitive Load Tolerance Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 53). Typically a pull up resistor conducting 500A or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics). Figure 53. Compensating for Large Capacitive Loads with a Pull Up Resistor Connection Diagrams Top View Figure 54. 8-Pin SOIC or VSSOP Package See Package Number D0008A or DGK0008A 18 Submit Documentation Feedback Top View Figure 55. 14-Pin SOIC or TSSOP Package See Package Number D0014A or PW0014A Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6035 LMC6035-Q1 LMC6036 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMC6035IM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60 35IM LMC6035IMM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A06B LMC6035IMMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A06B LMC6035IMQ1 ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60 35IMQ LMC6035IMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60 35IM LMC6035IMXQ1 ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60 35IMQ LMC6035ITL/NOPB ACTIVE DSBGA YZR 8 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 A 80 LMC6035ITLX/NOPB ACTIVE DSBGA YZR 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 A 80 LMC6036IM/NOPB ACTIVE SOIC D 14 55 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC6036IM LMC6036IMT/NOPB ACTIVE TSSOP PW 14 94 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC603 6IMT LMC6036IMTX/NOPB ACTIVE TSSOP PW 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC603 6IMT LMC6036IMX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC6036IM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LMC6035, LMC6035-Q1 : * Catalog: LMC6035 * Automotive: LMC6035-Q1 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMC6035IMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMC6035IMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMC6035IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6035IMXQ1 SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6035ITL/NOPB DSBGA YZR 8 250 178.0 8.4 1.85 2.01 0.76 4.0 8.0 Q1 LMC6035ITLX/NOPB DSBGA YZR 8 3000 178.0 8.4 1.85 2.01 0.76 4.0 8.0 Q1 LMC6036IMTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 LMC6036IMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6035IMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMC6035IMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMC6035IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6035IMXQ1 SOIC D 8 2500 367.0 367.0 35.0 LMC6035ITL/NOPB DSBGA YZR 8 250 210.0 185.0 35.0 LMC6035ITLX/NOPB DSBGA YZR 8 3000 210.0 185.0 35.0 LMC6036IMTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0 LMC6036IMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com MECHANICAL DATA YZR0008xxx D 0.6000.075 E TLA08XXX (Rev C) D: Max = 1.921 mm, Min = 1.86 mm E: Max = 1.768 mm, Min =1.708 mm 4215045/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI's products are provided subject to TI's Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI's provision of these resources does not expand or otherwise alter TI's applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2020, Texas Instruments Incorporated