LMC6036IMX/NOPB - NATIONAL SEMICONDUCTOR

LMC6035, LMC6035-Q1, LMC6036

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SNOS875G –JANUARY 2000–REVISED APRIL 2013

LMC6035/LMC6035-Q1/LMC6036 Low Power 2.7V Single Supply CMOS Operational

Amplifiers

Check for Samples: LMC6035,LMC6036

1FEATURES APPLICATIONS

2• (Typical Unless Otherwise Noted) • Filters

• LMC6035 in DSBGA Package • High Impedance Buffer or Preamplifier

• Ensured 2.7V, 3V, 5V and 15V Performance • Battery Powered Electronics

• Specified for 2 kΩand 600ΩLoads • Medical Instrumentation

• Wide Operating Range: 2.0V to 15.5V • Automotive Applications

DESCRIPTION

• Ultra Low Input Current: 20fA The LMC6035/6 is an economical, low voltage op

• Rail-to-Rail Output Swing amp capable of rail-to-rail output swing into loads of

– @ 600Ω: 200mV from Either Rail at 2.7V 600Ω. LMC6035 is available in a chip sized package

– @ 100kΩ: 5mV from Either Rail at 2.7V (8-Bump DSBGA) using micro SMD package

technology. Both allow for single supply operation

• High Voltage Gain: 126dB and are ensured for 2.7V, 3V, 5V and 15V supply

• Wide Input Common-Mode Voltage Range voltage. The 2.7 supply voltage corresponds to the

– -0.1V to 2.3V at VS= 2.7V End-of-Life voltage (0.9V/cell) for three NiCd or NiMH

batteries in series, making the LMC6035/6 well suited

• Low Distortion: 0.01% at 10kHz for portable and rechargeable systems. It also

• LMC6035 Dual LMC6036 Quad features a well behaved decrease in its specifications

• See AN-1112 (Literature Number SNVA009) for at supply voltages below its ensured 2.7V operation.

DSBGA Considerations This provides a “comfort zone” for adequate operation

at voltages significantly below 2.7V. Its ultra low input

• AEC-Q100 Grade 3 Qualified (LMC6035-Q1) currents (IIN) makes it well suited for low power active

filter application, because it allows the use of higher

resistor values and lower capacitor values. In

addition, the drive capability of the LMC6035/6 gives

these op amps a broad range of applications for low

voltage systems.

Connection Diagram

Top View

Figure 1. 8-Bump DSBGA Package

(Bump Side Down)

See Package Number YZR0008

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LMC6035, LMC6035-Q1, LMC6036

SNOS875G –JANUARY 2000–REVISED APRIL 2013

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Table 1. DSBGA Connection Table

LM6035IBP LMC6035ITL

Bump Number LMC6035IBPX LMC6035ITLX

A1 OUTPUT A OUTPUT B

B1 IN A−V+

C1 IN A+OUTPUT A

C2 V−IN A−

C3 IN B+IN A+

B3 IN B−V−

A3 OUTPUT B IN B+

A2 V+IN B−

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)(2)

ESD Tolerance(3) Human Body Model (LMC6035, LMC6036) 3000V

Human Body Model (LMC6035-Q1) 2000V

Machine Model 300V

Differential Input Voltage ± Supply Voltage

Supply Voltage (V+−V−) 16V

Output Short Circuit to V +See(4)

Output Short Circuit to V −See(5)

Lead Temperature (soldering, 10 sec.) 260°C

Current at Output Pin ±18mA

Current at Input Pin ±5mA

Current at Power Supply Pin 35mA

Storage Temperature Range −65°C to +150°C

Junction Temperature(6) 150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test

conditions, see the Electrical Characteristics.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

(3) Human body model, 1.5kΩin series with 100pF.

(4) Do not short circuit output to V+when V+is greater than 13V or reliability will be adversely affected.

(5) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in

exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 30mA over long term may adversely affect

reliability.

(6) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(MAX) −TA)/θJA. All numbers apply for packages soldered directly onto a PC board with no air flow.

Operating Ratings(1)

Supply Voltage 2.0V to 15.5V

Temperature Range LMC6035I and LMC6036I −40°C ≤TJ≤+85°C

Thermal Resistance (θJA) 8-pin VSSOP 230°C/W

8-pin SOIC 175°C/W

14-pin SOIC 127°C/W

14-pin TSSOP 137°C/W

8-Bump (6 mil) DSBGA 220°C/W

8-Bump (12 mil) Thin DSBGA 220°C/W

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test

conditions, see the Electrical Characteristics.

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SNOS875G –JANUARY 2000–REVISED APRIL 2013

DC Electrical Characteristics

Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 2.7V, V−= 0V, VCM = 1.0V, VO= 1.35V and RL> 1MΩ.

Boldface limits apply at the temperature extremes. LMC6035I/LMC6036I

Parameter Test Conditions Units

Min(1) Typ(2) Max(1)

VOS Input Offset Voltage 0.5 5 mV

TCVOS Input Offset Voltage 2.3 μV/°C

Average Drift

IIN Input Current See(3) 0.02 90 pA

IOS Input Offset Current See(3) 0.01 45 PA

RIN Input Resistance > 10 Tera Ω

CMRR Common Mode Rejection Ratio 0.7V ≤VCM ≤12.7V, 63 96 dB

V+= 15V 60

+PSRR Positive Power Supply 5V ≤V+≤15V, 63 93 dB

Rejection Ratio VO= 2.5V 60

−PSRR Negative Power Supply 0V ≤V−≤ −10V, 74 97 dB

Rejection Ratio VO= 2.5V, V+= 5V 70

VCM Input Common-Mode Voltage V+= 2.7V −0.1 0.3

Range For CMRR ≥40dB 0.5 V

2.0 2.3

1.7

V+= 3V −0.3 0.1

For CMRR ≥40dB 0.3 V

2.3 2.6

2.0

V+= 5V −0.5 −0.2

For CMRR ≥50dB 0.0 V

4.2 4.5

3.9

V+= 15V −0.5 −0.2

For CMRR ≥50dB 0.0 V

14.0 14.4

13.7

AVLarge Signal Voltage Gain(4) RL= 600ΩSourcing 100 1000 V/mV

Sinking 25 250 V/mV

RL= 2kΩSourcing 2000 V/mV

Sinking 500 V/mV

(1) All limits are specified by testing or statistical analysis.

(2) Typical Values represent the most likely parametric norm or one sigma value.

(3) Ensured by design.

(4) V+= 15V, VCM = 7.5V and R Lconnected to 7.5V. For Sourcing tests, 7.5V ≤VO≤11.5V. For Sinking tests, 3.5V ≤VO≤7.5V.

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DC Electrical Characteristics (continued)

Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 2.7V, V−= 0V, VCM = 1.0V, VO= 1.35V and RL> 1MΩ.

Boldface limits apply at the temperature extremes. LMC6035I/LMC6036I

Parameter Test Conditions Units

Min(1) Typ(2) Max(1)

VOOutput Swing V += 2.7V 2.0 2.5

RL= 600Ωto 1.35V 1.8 V

0.2 0.5

0.7

V+= 2.7V 2.4 2.62

RL= 2kΩto 1.35V 2.2 V

0.07 0.2

0.4

V+= 15V 13.5 14.5

RL= 600Ωto 7.5V 13.0 V

0.36 1.25

1.50

V+= 15V, 14.2 14.8

RL= 2 kΩto 7.5V 13.5 V

0.12 0.4

0.5

IOOutput Current V O= 0V Sourcing 4 8

3mA

VO= 2.7V Sinking 3 5

ISSupply Current LMC6035 for Both Amplifiers 0.65 1.6

VO= 1.35V 1.9 mA

LMC6036 for All Four Amplifiers 1.3 2.7

VO= 1.35V 3.0

AC Electrical Characteristics

Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 2.7V, V−= 0V, VCM = 1.0V, V O= 1.35V and RL> 1 MΩ.

Boldface limits apply at the temperature extremes.

Parameter Test Conditions Typ(1) Units

SR Slew Rate See(2) 1.5 V/μs

GBW Gain Bandwidth Product V += 15V 1.4 MHz

θmPhase Margin 48 °

GmGain Margin 17 dB

Amp-to-Amp Isolation See(3) 130 dB

enInput-Referred Voltage Noise f = 1kHz 27 nV/√Hz

VCM = 1V

inInput Referred Current Noise f = 1kHz 0.2 fA/√Hz

THD Total Harmonic Distortion f = 10kHz, AV=−10 0.01 %

RL= 2kΩ, VO= 8 VPP

V+= 10V

(1) Typical Values represent the most likely parametric norm or one sigma value.

(2) V+= 15V. Connected as voltage follower with 10V step input. Number specified is the slower of the positive and negative slew rates.

(3) Input referred, V += 15V and RL= 100kΩconnected to 7.5V. Each amp excited in turn with 1kHz to produce VO= 12 VPP.

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Typical Performance Characteristics

Unless otherwise specified, VS= 2.7V, single supply, TA= 25°C

Supply Current Input Current

vs. vs.

Supply Voltage (Per Amplifier) Temperature

Figure 2. Figure 3.

Sourcing Current Sourcing Current

vs. vs.

Output Voltage Output Voltage

Figure 4. Figure 5.

Sinking Current Sinking Current

vs. vs.

Output Voltage Output Voltage

Figure 6. Figure 7.

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Typical Performance Characteristics (continued)

Unless otherwise specified, VS= 2.7V, single supply, TA= 25°C

Output Voltage Swing Input Noise

vs. vs.

Supply Voltage Frequency

Figure 8. Figure 9.

Input Noise Amp to Amp Isolation

vs. vs.

Frequency Frequency

Figure 10. Figure 11.

Amp to Amp Isolation +PSRR

vs. vs.

Frequency Frequency

Figure 12. Figure 13.

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Typical Performance Characteristics (continued)

Unless otherwise specified, VS= 2.7V, single supply, TA= 25°C

−PSRR CMRR

vs. vs.

Frequency Frequency

Figure 14. Figure 15.

CMRR CMRR

vs. vs.

Input Voltage Input Voltage

Figure 16. Figure 17.

Input Voltage Input Voltage

vs. vs.

Output Voltage Output Voltage

Figure 18. Figure 19.

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Typical Performance Characteristics (continued)

Unless otherwise specified, VS= 2.7V, single supply, TA= 25°C

Frequency Response Frequency Response

vs. vs.

Temperature Temperature

Figure 20. Figure 21.

Gain and Phase Gain and Phase

vs. vs.

Capacitive Load Capacitive Load

Figure 22. Figure 23.

Slew Rate

vs.

Supply Voltage Non-Inverting Large Signal Response

Figure 24. Figure 25.

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Typical Performance Characteristics (continued)

Unless otherwise specified, VS= 2.7V, single supply, TA= 25°C

Non-Inverting Large Signal Response Non-Inverting Large Signal Response

Figure 26. Figure 27.

Non-Inverting Small Signal Response Non-Inverting Small Signal Response

Figure 28. Figure 29.

Non-Inverting Large Signal Response Inverting Large Signal Response

Figure 30. Figure 31.

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Typical Performance Characteristics (continued)

Unless otherwise specified, VS= 2.7V, single supply, TA= 25°C

Inverting Large Signal Response Inverting Large Signal Response

Figure 32. Figure 33.

Inverting Small Signal Response Inverting Small Signal Response

Figure 34. Figure 35.

Stability

vs.

Inverting Small Signal Response Capacitive Load

Figure 36. Figure 37.

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Typical Performance Characteristics (continued)

Unless otherwise specified, VS= 2.7V, single supply, TA= 25°C

Stability Stability

vs. vs.

Capacitive Load Capacitive Load

Figure 38. Figure 39.

Stability Stability

vs. vs.

Capacitive Load Capacitive Load

Figure 40. Figure 41.

Stability

vs.

Capacitive Load

Figure 42.

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APPLICATION NOTES

Background

The LMC6035/6 is exceptionally well suited for low voltage applications. A desirable feature that the LMC6035/6

brings to low voltage applications is its output drive capability—a hallmark for TI's CMOS amplifiers. The circuit of

Figure 43 illustrates the drive capability of the LMC6035/6 at 3V of supply. It is a differential output driver for a

one-to-one audio transformer, like those used for isolating ground from the telephone lines. The transformer (T1)

loads the op amps with about 600Ωof AC load, at 1 kHz. Capacitor C1 functions to block DC from the low

winding resistance of T1. Although the value of C1 is relatively high, its load reactance (Xc) is negligible

compared to inductive reactance (XI) of T1.

Figure 43. Differential Driver

The circuit in Figure 43 consists of one input signal and two output signals. U1A amplifies the input with an

inverting gain of −2, while the U1B amplifies the input with a non-inverting gain of +2. Since the two outputs are

180° out of phase with each other, the gain across the differential output is 4. As the differential output swings

between the supply rails, one of the op amps sources the current to the load, while the other op amp sinks the

current.

How good a CMOS op amp can sink or source a current is an important factor in determining its output swing

capability. The output stage of the LMC6035/6—like many op amps—sources and sinks output current through

two complementary transistors in series. This “totem pole” arrangement translates to a channel resistance (Rdson)

at each supply rail which acts to limit the output swing. Most CMOS op amps are able to swing the outputs very

close to the rails—except, however, under the difficult conditions of low supply voltage and heavy load. The

LMC6035/6 exhibits exceptional output swing capability under these conditions.

The scope photos of Figure 44 and Figure 45 represent measurements taken directly at the output (relative to

GND) of U1A, in Figure 43.Figure 44 illustrates the output swing capability of the LMC6035, while Figure 45

provides a benchmark comparison. (The benchmark op amp is another low voltage (3V) op amp manufactured

by one of our reputable competitors.)

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Figure 44. Output Swing Performance of

the LMC6035 per the Circuit of Figure 43

Figure 45. Output Swing Performance of Benchmark

Op Amp per the Circuit of Figure 43

Notice the superior drive capability of LMC6035 when compared with the benchmark measurement—even

though the benchmark op amp uses twice the supply current.

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Not only does the LMC6035/6 provide excellent output swing capability at low supply voltages, it also maintains

high open loop gain (A VOL) with heavy loads. To illustrate this, the LMC6035 and the benchmark op amp were

compared for their distortion performance in the circuit of Figure 43. The graph of Figure 46 shows this

comparison. The y-axis represents percent Total Harmonic Distortion (THD plus noise) across the loaded

secondary of T1. The x-axis represents the input amplitude of a 1 kHz sine wave. (Note that T1 loses about 20%

of the voltage to the voltage divider of RL(600Ω) and T1's winding resistances—a performance deficiency of the

transformer.)

Figure 46. THD+Noise Performance of LMC6035 and “Benchmark” per Circuit of Figure 43

Figure 46 shows the superior distortion performance of LMC6035/6 over that of the benchmark op amp. The

heavy loading of the circuit causes the AVOL of the benchmark part to drop significantly which causes increased

distortion.

APPLICATION CIRCUITS

Low-Pass Active Filter

A common application for low voltage systems would be active filters, in cordless and cellular phones for

example. The ultra low input currents (IIN) of the LMC6035/6 makes it well suited for low power active filter

applications, because it allows the use of higher resistor values and lower capacitor values. This reduces power

consumption and space.

Figure 47 shows a low pass, active filter with a Butterworth (maximally flat) frequency response. Its topology is a

Sallen and Key filter with unity gain. Note the normalized component values in parenthesis which are obtainable

from standard filter design handbooks. These values provide a 1Hz cutoff frequency, but they can be easily

scaled for a desired cutoff frequency (fc). The bold component values of Figure 47 provide a cutoff frequency of

3kHz. An example of the scaling procedure follows Figure 47.

Figure 47. 2-Pole, 3kHz, Active, Sallen and Key, Lowpass Filter with Butterworth Response

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Low-Pass Frequency Scaling Procedure

The actual component values represented in bold of Figure 47 were obtained with the following scaling

procedure:

1. First determine the frequency scaling factor (FSF) for the desired cutoff frequency. Choosing fcat 3kHz,

provides the following FSF computation:

– FSF = 2πx 3kHz (desired cutoff freq.) = 18.84 x 10 3

2. Then divide all of the normalized capacitor values by the FSF as follows: C1' = C(Normalized)/FSF C1' =

0.707/18.84 x 103= 37.93 x 10−6C2' = 1.414/18.84 x 103= 75.05 x 10−6(C1' and C2': prior to

impedance scaling)

3. Last, choose an impedance scaling factor (Z). This Z factor can be calculated from a standard value for C2.

Then Z can be used to determine the remaining component values as follows:

Z = C2'/C2(chosen) = 75.05 x 10 −6/6.8nF = 8.4k

C1 = C1'/Z = 37.93 x 10−6/8.4k = 4.52nF

(Standard capacitor value chosen for C1 is 4.7nF ) R1 = R1(normalized) xZ=1Ωx 8.4k = 8.4kΩR2 =

R2(normalized) xZ=1Ωx 8.4k = 8.4kΩ

(Standard value chosen for R1 and R2 is 8.45kΩ)

High Pass Active Filter

The previous low-pass filter circuit of Figure 47 converts to a high-pass active filter per Figure 48.

Figure 48. 2 Pole, 300Hz, Sallen and Key, High-Pass Filter

High-Pass Frequency Scaling Procedure

Choose a standard capacitor value and scale the impedances in the circuit according to the desired cutoff

frequency (300Hz) as follows: C = C1 = C2 Z = 1 Farad/C(chosen) x 2πx (desired cutoff freq.) = 1

Farad/6.8nF x 2πx 300 Hz = 78.05k

R1=ZxR1(normalized) = 78.05k x (1/0.707) = 110.4kΩ

(Standard value chosen for R1 is 110kΩ)

R2=ZxR2(normalized) = 78.05k x (1/1.414) = 55.2kΩ

(Standard value chosen for R1 is 54.9kΩ)

Dual Amplifier Bandpass Filter

The dual amplifier bandpass (DABP) filter features the ability to independently adjust fcand Q. In most other

bandpass topologies, the fcand Q adjustments interact with each other. The DABP filter also offers both low

sensitivity to component values and high Qs. The following application of Figure 49, provides a 1kHz center

frequency and a Q of 100.

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Figure 49. 2 Pole, 1kHz Active, Bandpass Filter

DABP Component Selection Procedure

Component selection for the DABP filter is performed as follows:

1. First choose a center frequency (fc). Figure 49 represents component values that were obtained from the

following computation for a center frequency of 1kHz. R2 = R3 = 1/(2 πfcC) Given: fc= 1kHz and C

(chosen) =6.8nF R2 = R3 = 1/(2πx 3kHz x 6.8nF) = 23.4kΩ

– (Chosen standard value is 23.7kΩ)

2. Then compute R1 for a desired Q (fc/BW) as follows: R1 = Q x R2. Choosing a Q of 100, R1 = 100

x 23.7kΩ=2.37MΩ.

PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK

It is generally recognized that any circuit which must operate with < 1000pA of leakage current requires special

layout of the PC board. If one wishes to take advantage of the ultra-low bias current of the LMC6035/6, typically

< 0.04pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining low leakages are

quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may at times

appear acceptably low. Under conditions of high humidity, dust or contamination, the surface leakage will be

appreciable.

To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6035 or

LMC6036 inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to

the op amp's inputs. See Figure 50. To have a significant effect, guard rings should be placed on both the top

and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as

the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a

PC board trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5pA

if the trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the

amplifiers actual performance. However, if a guard ring is held within 5mV of the inputs, then even a resistance

of 1011Ωwould cause only 0.05pA of leakage current, or perhaps a minor (2:1) degradation of the amplifier's

performance. See Figure 51(a) through Figure 51(c) for typical connections of guard rings for standard op amp

configurations. If both inputs are active and at high impedance, the guard can be tied to ground and still provide

some protection; see Figure 51(d).

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Figure 50. Example, using the LMC6036 of Guard Ring in PC Board Layout

(a) Inverting Amplifier (Guard Ring Connections) (b) Non-Inverting Amplifier (Guard Ring Connections)

Figure 51. Guard Ring Connections

CAPACITIVE LOAD TOLERANCE

Like many other op amps, the LMC6035/6 may oscillate when its applied load appears capacitive. The threshold

of oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain

follower. See the Typical Performance Characteristics.

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The load capacitance interacts with the op amp's output resistance to create an additional pole. If this pole

frequency is sufficiently low, it will degrade the op amp's phase margin so that the amplifier is no longer stable at

low gains. As shown in Figure 52, the addition of a small resistor (50Ω–100Ω) in series with the op amp's output,

and a capacitor (5pF–10pF) from inverting input to output pins, returns the phase margin to a safe value without

interfering with lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without

oscillation. Note that in all cases, the output will ring heavily when the load capacitance is near the threshold for

oscillation.

DSBGA Considerations

Contrary to what might be guessed, the DSBGA package does not follow the trend of smaller packages having

higher thermal resistance. LMC6035 in DSBGA has thermal resistance of 220°C/W compared to 230°C/W in

VSSOP. Even when driving a 600Ωload and operating from ±7.5V supplies, the maximum temperature rise will

be under 4.5°C. For application information specific to DSBGA, see Application note AN-1112 (Literature Number

SNVA009).

Figure 52. Rx, Cx Improve Capacitive Load Tolerance

Capacitive load driving capability is enhanced by using a pull up resistor to V+(Figure 53). Typically a pull up

resistor conducting 500μA or more will significantly improve capacitive load responses. The value of the pull up

resistor must be determined based on the current sinking capability of the amplifier with respect to the desired

output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical

Characteristics).

Figure 53. Compensating for Large Capacitive Loads with a Pull Up Resistor

Connection Diagrams

Top View Top View

Figure 54. 8-Pin SOIC or VSSOP Package Figure 55. 14-Pin SOIC or TSSOP Package

See Package Number D0008A or DGK0008A See Package Number D0014A or PW0014A

Product Folder Links: LMC6035 LMC6035-Q1 LMC6036

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMC6035IM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60

35IM

LMC6035IMM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A06B

LMC6035IMMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A06B

LMC6035IMQ1 ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60

35IMQ

LMC6035IMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60

35IM

LMC6035IMXQ1 ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60

35IMQ

LMC6035ITL/NOPB ACTIVE DSBGA YZR 8 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 A

LMC6035ITLX/NOPB ACTIVE DSBGA YZR 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 A

LMC6036IM/NOPB ACTIVE SOIC D 14 55 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC6036IM

LMC6036IMT/NOPB ACTIVE TSSOP PW 14 94 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC603

6IMT

LMC6036IMTX/NOPB ACTIVE TSSOP PW 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC603

6IMT

LMC6036IMX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC6036IM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LMC6035, LMC6035-Q1 :

•Catalog: LMC6035

•Automotive: LMC6035-Q1

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMC6035IMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LMC6035IMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LMC6035IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LMC6035IMXQ1 SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LMC6035ITL/NOPB DSBGA YZR 8 250 178.0 8.4 1.85 2.01 0.76 4.0 8.0 Q1

LMC6035ITLX/NOPB DSBGA YZR 8 3000 178.0 8.4 1.85 2.01 0.76 4.0 8.0 Q1

LMC6036IMTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1

LMC6036IMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Aug-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMC6035IMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0

LMC6035IMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0

LMC6035IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

LMC6035IMXQ1 SOIC D 8 2500 367.0 367.0 35.0

LMC6035ITL/NOPB DSBGA YZR 8 250 210.0 185.0 35.0

LMC6035ITLX/NOPB DSBGA YZR 8 3000 210.0 185.0 35.0

LMC6036IMTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0

LMC6036IMX/NOPB SOIC D 14 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Aug-2017

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

MECHANICAL DATA

YZR0008xxx

www.ti.com

TLA08XXX (Rev C)

0.600±0.075 D

. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

4215045/A 12/12

D: Max =

E: Max =

1.921 mm, Min =

1.768 mm, Min =

1.86 mm

1.708 mm

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