LT3669/LT3669-2 IO-Link Transceiver with Integrated Step-Down Regulator and LDO DESCRIPTION FEATURES n n n n n n n n n n IO-Link(R) PHY Compatible (COM1/COM2/COM3) Cable Interface Protected to 60V Operation from 7.5V to 40V Integrated Step-Down Switching Regulator n Max Load Current: 100mA (LT3669)/ 300mA (LT3669-2) n Synchronizable and Adjustable Switching Frequency: 250kHz to 2.2MHz n Output Voltage: 0.8V to 16V Integrated 150mA LDO Linear Regulator Rugged Line Drivers with Adjustable Slew Rate and Current Limit Adaptive Line Driver Pulsing Scheme to Switch Heavy Loads Safely Drivers Configurable as Push-Pull, Pull-Up or Pull-Down Adjustable Power-On Reset Timer Small 28-Pin Thermally Enhanced 4mm x 5mm QFN Package The LT(R)3669 is an industrial transceiver that includes a step-down switching regulator and a low dropout linear regulator. Wake-up detect functionality, as well as a programmable power-on reset timer are also included. The current limit and slew rate of the transmitters are externally adjustable for optimum EMC performance. The line drivers can source/sink up to 250mA of current each or 500mA when connected together, with a minimal residual voltage of less than 2.1V. An internal adaptive pulsing scheme allows the drivers to safely switch heavy capacitive loads and incandescent bulbs. Thermal shutdown provides additional protection. Line protection of 60V in the line interface pins allows the use of standard TVS diodes with L+ operating voltages up to 40V. The switching regulator integrates the catch diode in LT3669 (up to 100mA load current) and requires an external catch diode in LT3669-2 (up to 300mA load current). The LT3669 implements an IO-Link device PHY. For IO-Link master designs, see the LTC2874. APPLICATIONS n L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap is a trademark of Linear Technology Corporation. IO-Link is a registered trademark of PROFIBUS User Organization (PNO). All other trademarks are the property of their respective owners. Industrial Sensors and Actuators TYPICAL APPLICATION 82H LDOIN 0.1F 0.1F SW CPOR BST SYNC RT SR ILIM RESET RST LDO I/O SC1 FBLDO I/O SC2 AGND I/O WAKE I/O RXD1 DIO I/O TXEN1 EN/UVLO I/O TXD1 I/O TXEN2 Q2 I/O TXD2 CQ1 C 53.6k LT3669 FBOUT BD 10.2k TXD1 5V/DIV 10F 38.3k 0V RXD1 5V/DIV tRST = 12.5ms fSW = 600kHz 0V 42.2k 14k 4.42k CQ1 5V/DIV 3.3V 100mA 1F 10s/DIV VL+, 7.5V TO 40V TRANSIENT TO 60V L+ GND Operating Waveforms 5V 100mA 250mA 470pF 4.7F 36692 TA01b 1 250mA 470pF (RXD1 PULL-UP RESISTOR = 10k) 0V 2 4 3 36692 TA01a For more information www.linear.com/LT3669 3669fa 1 LT3669/LT3669-2 ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2) L+, EN/UVLO Voltage (Note 3)..................... -60V to 60V CQ1, Q2 Voltage........................................... -60V to 60V (L+ to CQ1), (L+ to Q2) Voltage.................... -60V to 60V DIO, LDOIN Voltage (Note 3)....................... -0.3V to 60V DIO Above L+ Voltage................................................90V BST Voltage...............................................................50V BST Above SW Voltage..............................................30V BD Voltage.................................................................30V LDO Voltage.................................................................8V LDO Above LDOIN Voltage........................................0.3V FBOUT, FBLDO, SYNC Voltage........................................6V CPOR, RT, ILIM Voltage...............................................3V SR, TXEN1, TXD1, TXEN2, TXD2 Voltage..................30V SC1, SC2, WAKE, RST, RXD1 Voltage........................30V Operating Junction Temperature Range (Notes 4 and 5) LT3669E............................................. -40C to 125C LT3669I.............................................. -40C to 125C LT3669H............................................. -40C to 150C Storage Temperature Range................... -65C to 150C PIN CONFIGURATION LT3669-2 AGND SYNC SR RST 28 27 26 25 24 23 ILIM TOP VIEW AGND SYNC SR ILIM CPOR RST TOP VIEW CPOR LT3669 28 27 26 25 24 23 SC1 1 22 RT SC1 1 22 RT SC2 2 21 FBOUT SC2 2 21 FBOUT WAKE 3 20 FBLDO WAKE 3 19 LDO RXD1 4 29 GND RXD1 4 TXEN1 5 18 LDOIN 20 FBLDO 29 GND 19 LDO TXEN1 5 18 LDOIN TXD1 6 17 BD TXD1 6 TXEN2 7 16 BST TXEN2 7 16 BST TXD2 8 15 SW TXD2 8 15 SW DA DIO EN/UVLO L+ Q2 CQ1 9 10 11 12 13 14 GND DIO EN/UVLO L+ Q2 CQ1 9 10 11 12 13 14 17 BD UFD PACKAGE 28-LEAD (4mm x 5mm) PLASTIC QFN UFD PACKAGE 28-LEAD (4mm x 5mm) PLASTIC QFN JA = 44C/W, JC = 8C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB JA = 44C/W, JC = 8C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB 3669fa 2 For more information www.linear.com/LT3669 LT3669/LT3669-2 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3669EUFD#PBF LT3669EUFD#TRPBF 3669 28-Lead (4mm x 5mm) Plastic QFN -40C to 125C LT3669IUFD#PBF LT3669IUFD#TRPBF 3669 28-Lead (4mm x 5mm) Plastic QFN -40C to 125C LT3669HUFD#PBF LT3669HUFD#TRPBF 3669 28-Lead (4mm x 5mm) Plastic QFN -40C to 150C LT3669EUFD-2#PBF LT3669EUFD-2#TRPBF 36692 28-Lead (4mm x 5mm) Plastic QFN -40C to 125C LT3669IUFD-2#PBF LT3669IUFD-2#TRPBF 36692 28-Lead (4mm x 5mm) Plastic QFN -40C to 125C LT3669HUFD-2#PBF LT3669HUFD-2#TRPBF 36692 28-Lead (4mm x 5mm) Plastic QFN -40C to 150C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VL+ = 24V. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 6.4 7.5 V 43 45 V 1.15 1.65 mA 4 6 mA 794 811 mV -15 -100 nA 2.28 1.04 258 2.62 1.20 297 MHz MHz kHz 130 210 ns Power Supply VOVTH L+ Undervoltage Lockout Threshold VL+ Rising l L+ Overvoltage Lockout Threshold VL+ Rising l Shutdown Current from L+ VEN/UVLO = 0.4V Quiescent Current from L+ Not Switching 40.5 Switching Regulator VFBOUT Switching Regulator Feedback Voltage l FBOUT Pin Bias Current FBOUT Pin Voltage = 800mV FBOUT Voltage Line Regulation 7.5V < VL+ < 40V Switching Frequency RT = 5.36k RT = 19.1k RT = 107k Minimum Switch Off-Time RT = 19.1k Foldback Frequency RT = 19.1k, FBOUT = 0V Switch Current Limit (Note 6) LT3669 LT3669-2 Switch VCESAT (VDIO - VSW) ISW = -100mA (LT3669) ISW = -300mA (LT3669-2) 777 l 0.005 1.94 0.88 219 l %/V 115 l l 240 480 325 650 kHz 410 820 330 550 Switch Leakage Current 0.01 mA mA mV mV 2 Catch Schottky Diode Forward Voltage Drop ISW = -100mA (LT3669) Catch Schottky Diode Current Limit to Stop Internal Oscillator LT3669 LT3669-2 Reverse Protection Diode Forward Voltage Drop IDIO = -100mA (LT3669) IDIO = -300mA (LT3669-2) 720 840 Reverse Protection Diode Reverse Leakage VL+ = 0V, VDI0 = 24V 0.01 Boost Schottky Diode Forward Voltage Drop IBST = -6mA (LT3669) IBST = -15mA (LT3669-2) 700 750 Boost Schottky Diode Reverse Leakage VBST - VBD = 24V 0.01 2 A 1.4 1.8 V Minimum BST Voltage (Note 7) 720 A 140 330 200 450 mV 260 570 mA mA mV mV 2 A mV mV 3669fa For more information www.linear.com/LT3669 3 LT3669/LT3669-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VL+ = 24V. (Note 4) SYMBOL PARAMETER BST Pin Current CONDITIONS MIN ISW = -100mA (LT3669) ISW = -300mA (LT3669-2) SYNC Threshold Voltage 0.5 SYNC Input Frequency 0.3 EN/UVLO Threshold Voltage VEN/UVLO Rising EN/UVLO Pin Hysteresis TYP MAX 5.25 10.5 7.5 15 UNITS 0.9 1.5 V 2.2 MHz mA mA l 1.44 1.5 1.56 V l 50 75 100 mV l 777 794 811 mV -20 -100 nA LDO Linear Regulator VFBLDO LDO Feedback Voltage FBLDO Pin Bias Current FBLDO Pin Voltage = 800mV FBLDO Voltage Line Regulation 7.5V < VL+ < 40V, VL+ - VLDO > 4V LDO Current Limit l 0.005 %/V l 151 180 235 mA 15 35 55 mA LDO Current Limit Foldback VLDOIN = 40V, VLDO = 0V l LDO Dropout Voltage LDO Load Current = 25mA LDO Load Current = 150mA l 60 340 90 mV mV l 150 175 A 90.4 92.7 95 % LDO Minimum Load Current Power-On Reset VRSTTH Reset Threshold as % of VFBOUT (VFBLDO) FBOUT (FBLDO) Pin Voltage Falling (Figure 6) tRST Reset Timeout Period CPOR = 100nF, RST RPU = 100k (Figure 6) l 10 12.5 15 ms tUV UV Detect to RST Asserted Step VFBOUT (VFBLDO) from 0.9V to 0.5V, RST RPU = 100k (Figure 6) l 11 24 37 s l Line Driver Thermal Shutdown Thermal Shutdown Threshold (Note 8) Junction Temperature TJ Increasing 125 140 155 C Thermal Shutdown Threshold (Note 8) Junction Temperature TJ Decreasing 111 128 135 C 10 12 14 C Thermal Shutdown Hysteresis (Note 8) Line Drivers IQH DC Driver Current P-Switching Output (ON State) VILIM 0.3V, 7.5V < VL+ < 40V RILIM = 42.2k, 7.5V < VL+ < 40V l l 105 280 140 330 190 420 mA mA IQL DC Driver Current N-Switching Output (ON State) VILIM 0.3V, 7.5V < VL+ < 40V RILIM = 42.2k, 7.5V < VL+ < 40V l l 105 280 140 330 190 420 mA mA VRQH Residual Voltage High (VL+ to VCQ1,Q2) ICQ1,Q2 = -100mA ICQ1,Q2 = -250mA l l 1.15 1.5 1.65 2.1 V V VRQL Residual Voltage Low (VCQ1,Q2) ICQ1,Q2 = 100mA ICQ1,Q2 = 250mA l l 1.15 1.5 1.65 2.1 V V VRQH (VRQL) Pulsing Threshold VRQH (VRQL) Increasing 2.95 3.2 V 50 80 mV 1.2 1.2 3 8 A A 2.7 VRQH (VRQL) Pulsing Threshold Hysteresis 20 CQ1, Q2 Pin Leakage Current -40C to 125C, VTXENn < 0.4V -40C to 150C, VTXENn < 0.4V l l VTHH Input Threshold "H" VL+ > 18V (Figure 14) l 10.5 11.8 13 V VTHL Input Threshold "L" VL+ > 18V (Figure 14) l 8.0 9.6 11.2 V VHYS Input Hysteresis VL+ > 18V (Figure 14) l 1.8 2.2 2.6 V Receiver 3669fa 4 For more information www.linear.com/LT3669 LT3669/LT3669-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VL+ = 24V. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital IO WAKE, RXD1, SCn Pull-Down Output Current if Asserted VSCn = VWAKE = VRXD1 = 0.3V l 0.7 1.05 mA RST Pull-Down Output Current if Asserted VRST = 0.3V l 0.2 0.3 mA 0.9 VIH TXDn, TXENn, SR Input High Voltage l VIL TXDn, TXENn, SR Input Low Voltage l V ILK TXDn, TXENn, SR Pin Input Leakage Current 0.1 CIN TXDn, TXENn, SR Pin Input Capacitance 2.5 0.4 V 1 A pF SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VL+ = 24V. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Driver and Receiver fDTR tBIT Maximum Data Transfer Rate CCQ1,Q2 4nF VSR 0.4V (for COM1/COM2) VSR 0.9V (for COM3) l l 38.4 230.4 kb/s kb/s Bit Time VSR 0.4V (for COM2) VSR 0.9V (for COM3) Rise Time CCQ1,Q2 4nF (Figure 1) VSR 0.4V (for COM1/COM2) VSR 0.9V (for COM3) l l 1.6 0.26 5.2 0.869 s s CCQ1,Q2 4nF (Figure 1) VSR 0.4V (for COM1/COM2) VSR 0.9V (for COM3) l l 2.1 0.34 5.2 0.869 s s CCQ1,Q2 4nF (Figure 2) VSR 0.4V (for COM1/COM2) VSR 0.9V (for COM3) l l 3.3 0.72 6 1.3 s s tSKEWD = |tPHLD - tPLHD |, CCQ1,Q2 4nF (Figure 2) VSR 0.4V (for COM1/COM2) VSR 0.9V (for COM3) l l 0.25 140 1.5 400 s ns CCQ1,Q2 = 100pF, RPU = RPD = 10k (Figure 3) VSR 0.4V (for COM1/COM2) VSR 0.9V (for COM3) l l 3.4 0.8 6.1 1.4 s s CCQ1,Q2 = 100pF, RPU = RPD = 10k (Figure 3) VSR 0.4V (for COM1/COM2) VSR 0.9V (for COM3) l l 4 4 6 6 s s l 55 75 s 1 s 26.04 4.34 s s Driver tDR tDF tPHLD, tPLHD tSKEWD tZHD, tZLD tHZD, tLZD Fall Time Propagation Delay Skew Enable Time Disable Time tDWU Minimum Wake-Up Pulse Duration to Be Acknowledged RPU = RPD = 10k (Figure 7) WAKE Pull-Up Resistor = 5k tLZW Delay From Handshake Sequence Finished to WAKE High (Note 9) WAKE Pull-Up Resistor = 5k 0.3 Pulsing On-Time VRQH (VRQL) = 24V, Only CQ1 or Q2 Pulsing 320 s 2.2 ms Pulsing Off-Time 3669fa For more information www.linear.com/LT3669 5 LT3669/LT3669-2 SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VL+ = 24V. (Note 4) SYMBOL PARAMETER CONDITIONS MIN Noise Suppression Time VSR 0.4V (for COM1/COM2) (Figure 5) VSR 0.9V (for COM3) (Figure 5) l l Propagation Delay RXD1 Pull-Up Resistor = 5k (Figure 4) VSR 0.4V (for COM1/COM2) VSR 0.9V (for COM3) l l tSKEWR = |tPHLR - tPLHR |, RXD1 RPU = 5k (Figure 4) VSR 0.4V (for COM1/COM2) VSR 0.9V (for COM3) l l TYP MAX UNITS Receiver tPHLR, tPLHR tSKEWR CCQI Receiver Skew CQ1 Pin Input Capacitance 1/16 1/16 3.5/16 5/16 TBIT TBIT 4.6 1.45 6.5 2.1 s s 0.5 100 1.5 400 s ns 20 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to GND. All currents into device pins are positive; all currents out of device pins are negative. Note 3: Absolute maximum voltage at L+, EN/UVLO, DIO and LDOIN pins is 60V for non-repetitive one second transients, and 40V for continuous operation. Note 4: The LT3669E is guaranteed to meet performance specifications from 0C to 125C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3669I is guaranteed over the full -40C to 125C operating junction temperature range. The LT3669H is guaranteed over the full -40C to 150C operating junction temperature range. Specifications for the line driver do not apply above the thermal shutdown temperature. pF Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions and will shut the line drivers off for typical junction temperatures higher than 140C. The LDO and switching regulator will shut off for typical junction temperatures higher than 168C. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 6: Current limit guaranteed by design and/or correlation to static test. Slope compensation reduces current limit at higher duty cycles. Note 7: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the NPN power switch. Note 8: Thermal shutdown guaranteed by design and/or correlation to static test. Note 9: Handshake sequence: set TXEN1 low and then toggle TXD1. 3669fa 6 For more information www.linear.com/LT3669 LT3669/LT3669-2 TYPICAL PERFORMANCE CHARACTERISTICS FBOUT Feedback Voltage 810 795 790 EN/UVLO PIN THRESHOLD (V) 800 785 800 795 790 785 780 -50 -25 0 780 -50 -25 25 50 75 100 125 150 TEMPERATURE (C) 0 36692 G01 L+ Overvoltage Lockout VL+ RISING 1.35 VL+ FALLING 42.5 VL+ RISING VL+ FALLING 6.0 41.5 0 0 0.2 0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 36692 G07 0.4 0 5 10 20 25 VL+ (V) 30 35 40 36692 G06 9 8 4 3 THERMAL SHUTDOWN 2 1 15 No-Load L+ Supply Current, VEN/UVLO = VL+, VTXEN2 = 0V L+ SUPPLY CURRENT (mA) L+ SUPPLY CURRENT (mA) 1.2 0.4 0.6 0 25 50 75 100 125 150 TEMPERATURE (C) 5 VL+ = 24V 0.6 0.8 No-Load L+ Supply Current, VEN/UVLO = VL+ L+ Supply Current, VEN/UVLO < 0.4V 0.8 1.0 36692 G05 36692 G04 1.0 L+ Supply Current, VEN/UVLO < 0.4V 0.2 5.0 -50 -25 25 50 75 100 125 150 TEMPERATURE (C) 25 50 75 100 125 150 TEMPERATURE (C) 1.2 5.5 41.0 -50 -25 0 36692 G03 1.4 6.5 UVLO (V) 43.0 EN/UVLO FALLING 1.40 L+ Undervoltage Lockout 42.0 L+ SUPPLY CURRENT (mA) 1.45 1.30 -50 -25 25 50 75 100 125 150 TEMPERATURE (C) 7.0 43.5 EN/UVLO RISING 1.50 7.5 44.0 1.4 1.55 36692 G02 44.5 OVLO (V) EN/UVLO Pin Threshold 1.60 805 FEEDBACK VOLTAGE (mV) FEEDBACK VOLTAGE (mV) 805 FBLDO Feedback Voltage L+ SUPPLY CURRENT (mA) 810 FRONT PAGE APPLICATION VL+ = 24V VTXEN = 0V 0 -50 -25 0 VTXEN1 = 5V, VTXD1 = 0V 7 VTXEN1 = 5V, VTXD1 = 5V 6 5 VTXEN1 = 0V 4 3 25 50 75 100 125 150 TEMPERATURE (C) 36692 G08 2 5 10 15 20 25 VL+ (V) 30 35 40 36692 G09 3669fa For more information www.linear.com/LT3669 7 LT3669/LT3669-2 TYPICAL PERFORMANCE CHARACTERISTICS Power-On Reset Threshold Reset Timeout Period 94.O FBLDO 93.0 FBOUT 92.5 92.0 91.5 91.0 -50 -25 0 CPOR = 100nF 12.9 12.8 12.7 12.6 12.5 12.4 12.3 12.2 12.1 12.0 -50 -25 25 50 75 100 125 150 TEMPERATURE (C) 0 36692 G10 Switch Current Limit SWITCH CURRENT LIMIT (mA) LT3669 200 100 500 400 300 LT3669 200 CURRENT LIMIT DC = 0% CURRENT LIMIT DC = 100% CATCH DIODE CURRENT LIMIT 100 0 BOOST DIODE FORWARD VOLTAGE (V) 8 7 6 5 4 3 2 1 150 100 200 250 SWITCH CURRENT (mA) 300 250 200 150 100 50 0 25 50 75 100 125 150 TEMPERATURE (C) 300 36692 G16 0 50 300 36692 G15 1.0 1.0 0.8 0.6 0.4 0.2 0 150 100 200 250 SWITCH CURRENT (mA) Reverse-Protection Diode Forward Voltage 1.2 9 50 350 Boost Diode Forward Voltage 10 0 400 36692 G14 BST Pin Current BST PIN CURRENT (mA) Switch Voltage Drop LT3669-2 0 -50 -25 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 36692 G13 0.1 1 10 100 1000 10000 CPOR PIN CAPACITANCE, CPOR (nF) 36692 G12 REVERSE-PROTECTION DIODE VF (V) SWITCH CURRENT LIMIT (mA) 400 0 0.1 450 600 500 0 1 Switch Current Limits LT3669-2 300 10 0.01 0.01 700 600 100 36692 G11 700 0 25 50 75 100 125 150 TEMPERATURE (C) SWITCH VOLTAGE DROP, VCESAT (mV) POR THRESHOLD (%) 93.5 Reset Timeout Period 1000 RESET TIMEOUT PERIOD, tRST (ms) RESET TIMEOUT PERIOD, tRST (ms) 13.0 0 100 150 50 BOOST DIODE CURRENT (mA) 200 36692 G17 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 50 150 200 100 DIODE CURRENT (mA) 250 300 36692 G18 3669fa 8 For more information www.linear.com/LT3669 LT3669/LT3669-2 TYPICAL PERFORMANCE CHARACTERISTICS Switching Frequency VL+ = 24V RT = 38.3k Frequency Foldback 700 2000 SWITCHING FREQUENCY (kHz) 620 FREQUENCY (kHz) Switching Frequency 2200 610 600 590 580 SWITCHING FREQUENCY (kHz) 630 1800 1600 1400 1200 1000 800 600 400 570 -50 -25 0 200 25 50 75 100 125 150 TEMPERATURE (C) 0 20 40 36692 G19 180 500 160 450 120 100 MINIMUM ON-TIME 80 60 40 20 0 -50 -25 0 200 100 Efficiency, VOUT = 5V LT3669-2, L = 33H 250 200 TYPICAL MINIMUM 5 10 15 30 45 15 40 35 0.7 450 80 0.3 0.2 0.1 0 LT3669-2, L = 33H 300 250 200 150 TYPICAL MINIMUM 50 0 10 20 30 40 50 60 70 80 90 100 CATCH DIODE CURRENT (mA) 36692 G25 0 5 10 15 f = 400kHz DIO PIN FLOATING 20 25 VL+ (V) 30 40 35 150 100 200 250 BUCK LOAD CURRENT (mA) 300 36692 G24 Efficiency, VOUT = 3.3V ALL LT3669 CURRENT INCLUDED f = 400kHz, VTXEN = 0V, VILIM = 0V DIO PIN FLOATING 60 50 40 30 LT3669, L = 82H 100 50 LT3669-2 VL+ : 12V 24V 36V 70 350 EFFICIENCY (%) BUCK LOAD CURRENT (mA) 90 0.4 0 36692 G23 Maximum Buck Output Current, VOUT = 3.3V 400 LT3669 VL+ : 12V 24V 36V 25 f = 600kHz DIO PIN FLOATING 20 25 VL+ (V) 55 35 LT3669, L = 82H 100 65 500 0.5 ALL LT3669 CURRENT INCLUDED f = 600kHz, VTXEN = 0V, VILIM = 0V DIO PIN FLOATING 75 300 150 100 200 300 400 500 600 700 800 FBOUT PIN VOLTAGE (mV) 36692 G21 0.8 0.6 0 85 36692 G22 CATCH DIODE FORWARD VOLTAGE (V) 300 36692 G20 350 Catch Diode Forward Voltage (LT3669 Only) 400 95 400 0 25 50 75 100 125 150 TEMPERATURE (C) 500 0 120 100 600 Maximum Buck Output Current, VOUT = 5V 50 BUCK LOAD CURRENT = 150mA 80 EFFICIENCY (%) MINIMUM OFF-TIME 140 BUCK LOAD CURRENT (mA) SWITCH ON-TIME/SWITCH OFF-TIME (ns) Minimum Switch-On Time/ Switch Off-Time 60 RT (k) RT = 38.3k 36692 G25 LT3669 VL+ : 12V 24V 36V 20 10 0 50 LT3669-2 VL+ : 12V 24V 36V 150 100 200 250 BUCK LOAD CURRENT (mA) 300 36692 G27 3669fa For more information www.linear.com/LT3669 9 LT3669/LT3669-2 TYPICAL PERFORMANCE CHARACTERISTICS Buck Load Regulation 1.0 LT3669-2 f = 600kHz, L = 33H REFERENCED TO VOUT AT 150mA LOAD 0.8 0.6 0.4 IOUT 200mA/DIV 10mA -0.4 -1.0 LT3669 FRONT PAGE APPLICATION REFERENCED TO VOUT AT 50mA LOAD 0 50 100 150 200 250 BUCK LOAD CURRENT (mA) 100s/DIV 300 LDO Current Limit 400 LDO CURRENT LIMIT (mA) 300 250 200 150 ILOAD = 30mA 50 140 120 100 VLDOIN - VLDO = 24V 80 VLDOIN - VLDO = 30V 60 VLDOIN - VLDO = 40V 20 -50 -25 VLDO = 300mV VLDO = 400mV VLDO = 500mV VLDO = 600mV VLDO = 700mV 100 80 60 40 25 50 75 100 125 150 TEMPERATURE (C) 20 200 36692 G33 10 15 20 25 30 VLDOIN - VLDO (V) 35 40 36692 G32 VLDO 100mV/DIV -0.03 -0.04 -0.05 -0.06 ILDO 100mA/DIV -0.07 5mA 100s/DIV -0.09 25 50 75 100 125 150 TEMPERATURE (C) 5 VLDO = 3.3V CLDO = 1F -0.08 150 0 LDO Load Transient Response -0.02 250 0 120 REFERENCED TO VLDO AT 0mA LOAD -0.01 300 100 -50 -25 140 LDO Load Regulation 0 LOAD REGULATION (%) LDO MINIMUM LOAD CURRENT (A) 350 0 160 36692 G31 LDO Minimum Load Current 400 180 160 36692 G30 450 LDO Current Limit Foldback VLDOIN - VLDO = 5V 180 40 25 50 75 100 125 150 TEMPERATURE (C) 36692 G29 200 VL+ = 24V 200 ILOAD = 150mA 0 VOUT = 5V 36692 G28 220 0 -50 -25 LT3669 FRONT PAGE APPLICATION VOUT 200mV/DIV LDO Dropout Voltage 100 VOUT = 5V 0 -0.2 -0.8 350 LT3669-2 COUT = 22F f = 600kHz, L = 33H VOUT 200mV/DIV 0.2 -0.6 DROPOUT VOLTAGE, VLDOIN - VLDO (mV) IOUT 200mA/DIV 20mA LDO CURRENT LIMIT (mA) LOAD REGULATION (%) Buck Load Transient Response -0.10 0 25 50 75 100 125 LDO LOAD CURRENT (mA) 36692 G35 150 36692 G34 3669fa 10 For more information www.linear.com/LT3669 LT3669/LT3669-2 TYPICAL PERFORMANCE CHARACTERISTICS VTHL 10 9 8 7 6 5 4 3 11 VTHL 10 9 8 7 6 5 4 3 2 -50 -25 0 2 25 50 75 100 125 150 TEMPERATURE (C) 5 10 15 36692 G36 Line Driver Current Limit RILIM = 42.2k 300 250 200 VILIM 0.3V 150 100 0 -50 -25 0 1.0 1.6 1.4 PULSING ON-TIME, VRQH,L = 5V 0.8 0.6 PULSING ON-TIME, VRQH,L = 24V PULSING ON-TIME, VRQH,L = 40V 0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 36692 G42 0 25 50 75 100 125 150 TEMPERATURE (C) 36692 G38 1.4 IQ = 100mA VRQL 1.2 VRQH 1.0 0.8 0.6 0.4 0.2 2.4 0 25 50 75 100 125 150 TEMPERATURE (C) PULSING OFF-TIME 2.2 PULSING ON-TIME / OFF-TIME (ms) PULSING ON-TIME / OFF-TIME (ms) 1.8 0.2 1.5 0 2.0 1.8 0 25 50 75 100 125 150 175 200 225 250 LINE DRIVER SOURCE/SINK CURRENT (mA) 36692 G41 Line Driver Pulsing On-Time/ Off-Time PULSING OFF-TIME 2.0 0.4 2.0 36692 G40 Line Driver Pulsing On-Time/ Off-Time 1.2 2.5 Line Driver Residual Voltage 1.2 0.6 -50 -25 25 50 75 100 125 150 TEMPERATURE (C) 18V 24V 30V 40V 1.6 1.4 36692 G39 1.0 3.0 36692 G37 IQ = 250mA 1.0 VL+ : 0.5 -50 -25 40 35 0.8 50 2.2 30 VRQH VRQL 1.6 RESIDUAL VOLTAGE (V) LINE DRIVERS CURRENT LIMIT (mA) 350 25 20 VL+ (V) CQ1, Q2 Pin Leakage Current VTXEN < 0.4V 3.5 Line Driver Residual Voltage 1.8 400 2.4 CQ1, Q2 PIN LEAKAGE CURRENT (A) 11 4.0 VTHH 12 RECEIVER THRESHOLDS (V) RECEIVER THRESHOLDS (V) 13 VTHH 12 Receiver Thresholds RESIDUAL VOLTAGE (V) 13 Receiver Thresholds Line Driver Output Waveforms VTXD1 5V/DIV 0V VRXTD1 5V/DIV 1.6 0V 1.4 1.2 1.0 0.8 PULSING ON-TIME 0.6 VCQ1 5V/DIV 0.4 0.2 0 PULSING NOT OCCURRING BELOW 3V 0 5 10 15 20 25 30 35 40 RESIDUAL VOLTAGE, VRQH,L (V) 36692 G43 0V 2s/DIV VSR > 0.9V, RXD1 PULL-UP RESISTOR = 10k 36692 G44 3669fa For more information www.linear.com/LT3669 11 LT3669/LT3669-2 PIN FUNCTIONS SC1 (Pin 1): CQ1 Short-Circuit Detect Open-Collector Output. SC1 pulls low when a short-circuit is detected on the CQ1 driver output or after a thermal shutdown event. Use a 100k pull-up resistor to the C's supply. Lowpass filter this signal before further processing. See the Applications Information section. SC2 (Pin 2): Q2 Short-Circuit Detect Open-Collector Output. SC2 pulls low when a short-circuit is detected on the Q2 driver output or after a thermal shutdown event. Use a 100k pull-up resistor to the C's supply. Lowpass filter this signal before further processing. See the Applications Information section. WAKE (Pin 3): Wake-up Detect Open-Collector Output. WAKE pulls low when driver 1 detects a wake-up pulse longer than 75s at the CQ1 pin (indicating that a data transmission is beginning). WAKE returns to high impedance after the handshaking sequence of setting TXEN1 low and then toggling TXD1 or after an internal reset event. Use a 10k pull-up resistor to the C's supply. RXD1 (Pin 4): CQ1 Receiver Output, Open Collector. Use a pull-up resistor of 10k or less for improved data performance in COM3. RXD1 polarity is inverted with respect to the line data CQ1. TXEN1 (Pin 5): CQ1 Driver Enable. The TXEN1 pin enables the line data CQ1 driver in push-pull mode when pulled high. To use the driver in open-collector mode, tie TXD1 high (for pull-down mode) or low (for pull-up mode) and drive the data signal into the TXEN1 pin. TXD1 (Pin 6): CQ1 Driver Input. The polarity of the driver output is inverted with respect to TXD1. TXEN2 (Pin 7): Q2 Driver Enable. The TXEN2 pin enables the line data Q2 driver in push-pull mode when pulled high. To use the driver in open-collector mode, tie TXD2 high (for pull-down mode) or low (for pull-up mode) and drive the data signal into the TXEN2 pin. TXD2 (Pin 8): Q2 Driver Input. The polarity of the driver output is inverted with respect to TXD2. Q2 (Pin 9): Q2 Driver Output. The driver output polarity is inverted with respect to the driver input TXD2. Connect a capacitor (typically 470pF) from Q2 to ground for improved performance. CQ1 (Pin 10): CQ1 Driver Output and Receiver Input. The driver output polarity is inverted with respect to the driver input TXD1. Tie directly to the industrial line data terminal. Connect a capacitor (typically 470pF) from CQ1 to ground for improved performance. L+ (Pin 11): Power Supply Input and Anode of Internal Reverse Polarity Protection Diode. Connect to the industrial line supply terminal. The L+ pin supplies current to the LT3669's internal circuitry and must be locally bypassed with at least 4.7F. EN/UVLO (Pin 12): The EN/UVLO pin puts the LT3669 in shutdown mode. Pull the pin below 0.4V to shut down the LT3669. The 1.5V threshold functions as an accurate undervoltage lockout (UVLO), preventing the regulators and transceiver from operating until the input voltage has reached the programmed level. DIO (Pin 13): Cathode of Internal Reverse Polarity Protection Diode. Do not use a bypass capacitor at DIO. An external diode from L+ to DIO can be used to improve efficiency. In this case only, a bypass capacitor is allowed at DIO. The external diode must be chosen with a reverse-breakdown voltage higher than the expected reverse-polarity condition, and it must be robust enough to withstand the inrush current of hot plugging. GND (Pin 14, LT3669): Ground in LT3669. Leave this pin floating or tie the pin directly to the ground plane and the industrial line ground terminal L-. DA (Pin 14, LT3669-2): Diode Anode in LT3669-2. Connect the anode of the external catch diode (D1 in LT3669-2's Block Diagram) to this pin. Internal circuitry senses the current through the catch diode providing frequency foldback in extreme situations. SW (Pin 15): Output of the Internal NPN Power Switch. Connect this pin to the inductor and boost capacitor. BST (Pin 16): The BST pin provides drive voltage higher than the input voltage to the internal NPN power switch. Connect a capacitor (typically 0.22F) between BST and SW. BD (Pin 17): An integrated Schottky diode is connected from BD to BST, providing the charging path for the boost capacitor. Connect to the output of the switching regulator. 3669fa 12 For more information www.linear.com/LT3669 LT3669/LT3669-2 PIN FUNCTIONS LDOIN (Pin 18): LDO Power Supply Input. This is the collector of the LDO power NPN. Tie to the output of the switching regulator for maximum efficiency, or to DIO. To preserve reverse-polarity protection, do not connect to L+. SR (Pin 25): Slew Rate Control Pin. Setting SR low adjusts both CQ1 and Q2 drivers' rising and falling times for reduced EMI in COM1/COM2 speed mode. Set SR high for edge times suitable for COM3. LDO (Pin 19): Low Dropout Linear Regulator Output. Bypass to GND with at least 1F of capacitance. ILIM (Pin 26): Line Driver Current Limit Programming Pin. Source and sink current limits for both line drivers are programmed using this pin. Tie a resistor from ILIM to AGND to set the drivers output current limit. Tie ILIM to AGND for a 140mA current limit. FBLDO (Pin 20): The LT3669 regulates this pin to 0.794V. Connect a feedback resistor divider tap to this pin to set the output voltage of the LDO. FBOUT (Pin 21): The LT3669 regulates this pin to 0.794V. Connect a feedback resistor divider tap to this pin to set the output voltage of the switching regulator. RT (Pin 22): Sets the Internal Oscillator Frequency. Tie a resistor from RT to AGND to program the frequency. See Table 2 for resistor values. AGND (Pin 23): Analog Ground Used for Bandgap Voltage References. Connect to the ground node of the passive components connected to RT, FBOUT, FBLDO, ILIM and CPOR, and to the system ground in a star connection manner. SYNC (Pin 24): External Clock Synchronization Input. Ground this pin to run the part using the internal oscillator. For external synchronization, drive the SYNC pin with a logic-level signal with positive and negative pulse widths of at least 80ns. Choose the RT resistor to set the LT3669 switching frequency at least 20% below the lowest synchronization input. For example, if the synchronization signal is 350kHz, the RT pin should be set for 280kHz. CPOR (Pin 27): Reset Delay Timer Programming Pin. Connect an external capacitor (CPOR) to AGND to program a reset delay time of 0.125ms/nF. RST (Pin 28): Active Low, Open-collector Logic Output. After VOUT and VLDO rises above 92.7% of its programmed value, the reset remains asserted for the period set by the capacitor on the CPOR pin. RST will also pull low if VL+ is below the internal undervoltage threshold and VOUT or VLDO are above 1.5V for an RST pull-up resistor of 100k. If using the POR function, connect a 10pF capacitor between the CPOR and RST pins. GND (Pin 29 Exposed Pad): Ground. Tie the exposed pad directly to the ground plane and the industrial line ground terminal. The exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the circuit printed board. It must be soldered to the circuit board for proper operation. 3669fa For more information www.linear.com/LT3669 13 LT3669/LT3669-2 BLOCK DIAGRAM LT3669 LDOIN - + BASE CTRL ENABLE + - VLDO CLDO 19 20 OSCILLATOR 250kHz TO 2.2MHz LDO R Q S QB EN BST SOFT START + - CATCH DIODE + CPOR RT CPOR + - VC 28 RST POWER-ON RESET CONTROL RST 3 FBLDO VC CLAMP FBOUT 0.736V 3V 0.794V 0.736V EN THSD SOFT-START L 15 EN FBOUT 24 22 RT R1 21 R2 REFERENCE GENERATOR EN/UVLO 12 TEMPERATURE AND VOLTAGE MONITORING DIO 13 WAKE EN THSD ENABLE THSD RST + - WAKE-UP DETECT 1 0.794V 16 GND 14 SYNC 27 17 CBST DISABLE SYNC 3V BOOST DIODE SWITCH DRIVER SW EN FBLDO R4 BD SLOPE COMP 0.794V LOW DROPOUT LINEAR REGULATOR R3 COUT - + EN VOUT 18 SC1 L+ 11 CL+ WAKE SC CQ1 Q 5 6 TXEN1 C1 DRIVER 1 CONTROL TXD1 + - SLEW RATE CONTROL 4 RXD1 2 RX + - ENABLE THSD SC2 SC Q2 Q 8 25 26 4 C/Q 3 L- EN 7 L+ 1 Q2 THSD 2 10 9 TXEN2 TXD2 SR ILIM DRIVER 2 CONTROL SLEW RATE CONTROL C2 + - GND 29 AGND 23 36692 BD1 3669fa 14 For more information www.linear.com/LT3669 LT3669/LT3669-2 BLOCK DIAGRAM LT3669-2 LDOIN - + BASE CTRL ENABLE + - VLDO CLDO 19 OSCILLATOR 250kHz TO 2.2MHz LDO 20 R Q S QB EN SWITCH DRIVER BST SOFT START + - DA + SYNC 27 CPOR RT CPOR + - VC 28 POWER-ON RESET CONTROL RST RST FBLDO 3V VC CLAMP FBOUT 0.736V 0.794V 0.794V 0.736V EN THSD 3 16 SOFT-START REFERENCE GENERATOR EN FBOUT L 15 D1 14 24 22 RT R1 21 R2 EN/UVLO TEMPERATURE AND VOLTAGE MONITORING DIO 12 13 WAKE EN THSD ENABLE THSD RST + - WAKE-UP DETECT 1 17 CBST DISABLE SYNC 3V BOOST DIODE SW EN FBLDO R4 BD SLOPE COMP 0.794V LOW DROPOUT LINEAR REGULATOR R3 COUT - + EN VOUT 18 SC1 L+ 11 CL+ WAKE SC CQ1 Q 5 6 TXEN1 C1 DRIVER 1 CONTROL TXD1 + - SLEW RATE CONTROL 4 RXD1 2 RX + - ENABLE THSD SC2 Q2 Q 8 25 26 4 C/Q 3 L- SC 7 L+ 1 Q2 EN THSD 2 10 9 TXEN2 TXD2 SR ILIM DRIVER 2 CONTROL SLEW RATE CONTROL C2 + - GND 29 AGND 23 36692 BD2 3669fa For more information www.linear.com/LT3669 15 LT3669/LT3669-2 TIMING DIAGRAMS CQ1 Q2 TXD1 TXD2 VDD* TXD1 TXD2 0V CCQ t DF TXEN1 TXEN2 t DR VL+ VL+ - 3V 13V CQ1 Q2 VDD 8V 3V 0V 36692 F01 Figure 1. Driver Rising and Falling Times CQ1 Q2 TXD1 TXD2 TXD1 TXD2 CCQ VDD /2 VDD VDD /2 0V t PLHD t PHLD VL+ TXEN1 TXEN2 VDD CQ1 Q2 13V 8V tSKEWD = t PHLD - t PLHD 0V 36692 F02 Figure 2. Driver Propagation Delays * VDD is the external C's supply voltage which can be taken either from the switching regulator's or LDO's output (VOUT or VLDO) 3669fa 16 For more information www.linear.com/LT3669 LT3669/LT3669-2 TIMING DIAGRAMS CQ1 Q2 TXD1 TXD2 TXEN1 TXEN2 CCQ RPD VDD /2 VDD /2 t ZHD t HZD TXEN1 TXEN2 VDD 0V VL+ VL+ - 3V 13V CQ1 Q2 0V VL+ VDD CQ1 Q2 TXD1 TXD2 RPU TXEN1 TXEN2 CCQ VDD /2 VDD VDD /2 t ZLD 0V t LZD VL+ TXEN1 TXEN2 CQ1 Q2 8V 3V 36692 F03 0V Figure 3. Driver Enable and Disable Times 3669fa For more information www.linear.com/LT3669 17 LT3669/LT3669-2 TIMING DIAGRAMS VDD VL+ RPU RXD1 CQ1 CQ1 13V 8V 0V t PHLR t PLHR CQ1 VDD RXD1 0V tSKEWR = t PHLR - t PLHR 36692 F04 Figure 4. Receiver Propagation Delays SHORT GLITCH REJECTED < TBIT /16 > TBIT /16 LONG GLITCH DETECTED VL+ VTHH VTHL CQ1 0V VDD RXD1 0V TBIT TBIT 36692 F05 Figure 5. Receiver Detection and Noise Filter VDD RST RPU VOUT (VLDO) VRSTTH t UV POR CONTROL RST t RST VDD /2 VDD 0V 36692 F06 Figure 6. Power-On Reset Waveforms 3669fa 18 For more information www.linear.com/LT3669 LT3669/LT3669-2 TIMING DIAGRAMS 500mA IPD 100mA 0mA t WU* VL+ VL+ - VRQH VDD CQ1 RPD WAKE WAKE-UP DETECT VL+ - 3V CQ1 0V RPU t HZD IPD TXEN1 TXEN1 TXD1 TXEN1 TXD1 WAKE VDD VDD /2 TXD1 t DWU 0V VDD VDD /2 t LZW VDD /2 VDD /2 0V VDD 0V 500mA IPU 100mA 0mA t WU VL+ VDD VL+ IPU VL+ R PU WAKE WAKE-UP DETECT CQ1 CQ1 3V VRQL RPU 0V t LZD TXEN1 TXEN1 TXD1 TXEN1 t DWU TXD1 WAKE VDD VDD /2 TXD1 VDD /2 0V VDD VDD /2 t LZW VDD /2 0V VDD 0V 36692 F07 * tWU is the width of the applied wake-up pulse >tDWU Figure 7. Wake-Up Waveforms 3669fa For more information www.linear.com/LT3669 19 LT3669/LT3669-2 OPERATION The LT3669/LT3669-2 is a complete industrial slave interface, including a switching voltage regulator, an LDO, a data transceiver with wake-up detect, a second driver and a power-on reset circuit. This set of features allows a typical industrial slave device to be built with just a sensor or actuator, the LT3669 and a microcontroller to provide the digital conversion and signal processing. The line transceiver circuitry includes a receiver that monitors the CQ1 line for data and sets the output RXD1 accordingly, and a driver that drives the CQ1 line controlled by inputs TXEN1 and TXD1. Additionally, a second driver controlled by inputs TXEN2 and TXD2 drives the Q2 line. Both drivers share a common user-adjustable sink/source current limit (up to 330mA, typical) by connecting a resistor to AGND at the ILIM pin. The drivers feature four modes of operation: push-pull, pull-up only, pull-down only, as well as a high impedance mode. The CQ1 driver also includes a built-in wake-up pulse detect circuitry that senses when the output CQ1 is forced opposite of its driven value for a minimum of 75s. When this wake-up signal is detected, the WAKE output pulls low to alert the host system that a data transmission is expected. The WAKE output returns to high impedance again when the host acknowledges the wake-up request by executing the handshake sequence of setting the TXEN1 input low (receive mode) and toggling the TXD1 input, or under an internal reset event. Both drivers support COM1 (4.8kb/s), COM2 (38.4kb/s) and COM3 (230.4kb/s) communication modes. The receiver supports logic swings on the CQ1 pin in accordance with the IO-Link communication standard. Tying CQ1 and Q2 pins together, as well as pins TXD1 and TXD2 and TXEN1 and TXEN2, increases the overall current capability. The drivers are equipped with a pulsing scheme that allows them to safely drive heavy capacitive loads and incandescent bulbs. Outputs SC1 and SC2 will flag if CQ1 or Q2 outputs are forced within 2.95V of the opposite rail they are trying to reach. A blanking time prevents false alarms during normal output transitions. The switching regulator of the LT3669 integrates the catch diode and provides a typical conversion efficiency greater than 60% at its maximum load current of 100mA with a standard industrial supply voltage of 24V at the L+ pin and 5V output. The LT3669-2 requires an external catch diode and provides a typical efficiency greater than 75% at its maximum load current of 300mA. Compared to a linear regulator, this drastically minimizes power dissipation in the slave device, and minimizes current draw on the industrial 24V line. The regulator features an on-chip power switch and built-in compensation, soft-start, current limit, and other support circuits required to maintain a robust, well regulated output voltage. The switching frequency is adjustable with a resistor to AGND at the RT pin to allow the circuit to be optimized either for space or efficiency, and the frequency can be synchronized to an external clock to minimize interference with signal processing circuits. A precision UVLO circuit allows the system to shut down at a user-selectable voltage. An on-chip LDO linear regulator provides a second output voltage at up to 150mA. The LDO has current limit with foldback for robust performance in fault conditions. The reset output (RST) goes low at start-up and remains low until each regulated output is within 7.3% of its final value and the user-adjustable reset timer has expired. This ensures that the supply voltages are in regulation and stable before the signal processing circuitry is allowed to start. The reset timer is programmed with an external capacitor to AGND at the CPOR pin. The LT3669 tolerates transient swings to +60V from GND and -60V from L+ on the CQ1 and Q2 pins without damage. Logic inputs TXD1, TXD2, TXEN1, TXEN2 and SR feature 900mV thresholds and logic input SYNC a 1.5V threshold to interface easily with low voltage logic. All logic outputs (RXD1, RST, SC1, SC2 and WAKE) are open collector. 3669fa 20 For more information www.linear.com/LT3669 LT3669/LT3669-2 APPLICATIONS INFORMATION LINE DRIVERS Setting the Current Limit The LT3669 line drivers have an accurate current limit that is programmed by a resistor tied from the ILIM pin to ground. Table 1 lists the necessary RILIM values for desired current limits. Tying the ILIM pin to ground sets the default current limit of 140mA. Table 1. Current Limit vs RILIM Value CURRENT LIMIT (mA) RILIM VALUE (k) 70 221 90 169 130 113 170 84.5 210 68.1 250 56.2 290 48.7 330 42.2 input pin and are independent of the L+ supply voltage. Forcing SR below 0.4V sets the rising/falling times to a typical value of 1.6s/2.1s. Forcing SR above 0.9V sets these times to a typical value of 260ns/340ns. The LT3669 output drivers achieve a well controlled slew rate for a wide variety of output loads while offering a low residual voltage (< 2.1V) for output load currents of up to 250mA. In order to do so, the output drivers switch to a low residual voltage mode after a defined time once the TXD signal has toggled. This time is dependent on the SR pin input level. For SR low, the drivers will enter this mode after 8.5s; for SR high, after 1.8s. This gives enough time for the controlled slew rate mechanism to bring the outputs to within 2.95V from the supply rails, therefore minimizing EMI during the main part of the level transition. Once the timer is expired the outputs will further approach the supply rails to within 2.1V. Figure 9 depicts the output waveforms during transitions. Driving Heavy Loads The accurate current-limit circuit loop has a time constant of approximately 10s. Additionally, high speed current-limit clamps protect the part in case of heavy loads or shortcircuits. Figure 8 depicts the high and low side driver's output current waveforms in a short-circuit condition. Slew Rate Control The LT3669 line drivers feature a controlled programmable slew rate for optimum EMC performance. CQ1 and Q2 rising and falling times can be programmed using the SR VTXEN1 5V/DIV ICQ1 0.5A/DIV The LT3669 is equipped with a pulsing mechanism to drive heavy output loads like big capacitors and incandescent bulbs, and also protect it against output short-circuit conditions. Under heavy load or output short-circuit conditions, the power dissipated in the switches may increase its local junction temperature to excessive levels if the loads were driven continuously. In order to maintain robust operation, the LT3669 output drivers use pulses of variable on-time and fixed off-time (2.2ms typical) to cool the drivers down VCQ1 10V/DIV LOW SIDE (SHORTED TO L+) 0A ICQ1 0.5A/DIV 100 PULL-UP 0V 100 PULL-DOWN HIGH SIDE (SHORTED TO GND) RILIM = 42.2k VL+ = 24V VCQ1 10V/DIV RILIM = 42.2k VL+ = 24V SR = 0V 0V 0A 100s/DIV 36692 F08 Figure 8. Current Limit Waveform in Short-Circuit 2s/DIV 36692 F09 Figure 9. Output Waveforms During a Transition 3669fa For more information www.linear.com/LT3669 21 LT3669/LT3669-2 APPLICATIONS INFORMATION until the residual voltages approach within 2.95V of the intended power rail, in which case the loads are driven continuously. The on-time depends on the sum of the residual voltages for the active switches (provided that the residual voltage is higher than 2.95V) and since their current limit is fixed, it is inversely proportional to their power dissipation. The lower the power dissipated by the switches, the longer the on-time, thus optimizing the time to drive these heavy loads fully. In order to account for the case of normal load slew rate, the internal on-time timer only increases after a blanking period dependent on the SR setting. A thermal shutdown circuit with a trigger temperature of 140C (typical) provides additional protection. Short-Circuit and Thermal Shutdown Flags SC1 and SC2 A short-circuit is defined as the condition where the driver's output is within 2.95V from the opposite targeted rail, for instance if the CQ1 output is programmed to be high level (close to VL+) but stays within 2.95V from GND. If either CQ1 or Q2 is short-circuited, the internal pulsing mechanism and thermal shutdown circuitry will protect the drivers. Open-collector outputs SC1 and SC2 will pull low during short-circuit events on CQ1 an Q2, respectively. A heavy output load can be interpreted as a short-circuit condition during the first pulses, and SC1 and SC2 outputs will flag it accordingly. This information can be used by an external microcontroller to decide whether there is a real short-circuit or a heavy load is attached to the outputs. A heavy load requires a minimum amount of time to bring the driver's output outside of the short-circuit range. By setting timers using SC1 and SC2, a short-circuit condition can be found and the microcontroller will react accordingly (by disabling the affected driver, for example). Figures 10, 11 and 12 show the behavior of the pulsing scheme when driving a light bulb, a 470F capacitor and a short-circuit. VCQ1/Q2 5V/DIV 12V/5W BULB VL+ = 12V RILIM = 42.2k VSC1 5V/DIV VSC2 5V/DIV 50ms/DIV 36692 F10 Figure 10. SC1 and SC2 Outputs While Driving a Light Bulb RILIM = 42.2k VCQ1 1V/DIV 0V VSC1 5V/DIV 5ms/DIV 36692 F11 Figure 11. SC1 Output While Driving 470F VTXEN1 5V/DIV RILIM = 42.2k VCQ1 0.5V/DIV VSC1 5V/DIV 2ms/DIV 36692 F12 Figure 12. SC1 Output While Driving a Short-Circuit 3669fa 22 For more information www.linear.com/LT3669 LT3669/LT3669-2 APPLICATIONS INFORMATION If the junction temperature exceeds 140C (typical), internal circuitry will shut the line drivers off. During the thermal shutdown event, SC1 and SC2 pull low simultaneously regardless of the level of the enable inputs TXEN1 and TXEN2 (see Figure 13). This behavior can be used to distinguish between short-circuit and thermal shutdown events. In case of short-circuit events without thermal shutdown being triggered, setting TXEN1 and TXEN2 low sets outputs SC1 and SC2 to high impedance, respectively. While in short-circuit, the line drivers will pulse following the pulsing scheme described earlier. Depending on the cable length and nature of the heavy load, outputs SC1 and SC2 may report false information as the voltage across the line drivers exceeds the short-circuit range for a short time due to reflections in the cable at the beginning of each pulse. SC1 and SC2 should then be filtered digitally or by an RC filter before further processing. The analog filter should have a time constant of at least 80s, for example, using pull-up resistors of 100k for SC1 and SC2 with 1nF to ground. Driving Heavy Loads on Q2 During CQ1 Communication The line drivers enter the protecting pulsing mechanism independently from each other. Only the driver under heavy load conditions will shut off after the defined pulsing ontime. While this driver is under overload conditions data can be sent reliably on the other driver in COM2 (SR < 0.4V) provided that it is enabled a minimum of 3ms before the data is actually applied on its TXD input. For IO-Link communication using the CQ1 transceiver in either COM2 (SR < 0.4V) or COM3 (SR > 0.9V), ensure the Q2 driver is not in a heavy load or short-circuit condition after a wake-up request is acknowledged and during the IO-Link start-up phase. Master and device can thus exchange initial data without disruption and establish communication successfully. Thereafter, a message sent by the master must be answered by the device after a short delay. However, the device might need additional time to perform operations before it can receive upcoming messages from the master. To support that, IO-Link defines the cycle time, the time between master messages, configured at the master side to meet the device timing requirements. If the device fails to answer a message sent by the master, as a consequence of the Q2 driver still pulsing the heavy load (disrupting CQ1 communication), the master repeats the message up to two additional times (waiting the cycle time between repetitions) before re-initiating communication by sending a new wake-up request. This master's retry property can be used to set an optimum cycle time for driving heavy loads on Q2 (by request of the IO-Link master) without breaking communication. For instance, a cycle time set to 100ms gives the Q2 driver 300ms to switch the heavy load on fully before the device has its last chance to answer (after 2 message failures) the repeated message from the master successfully. VTXEN1 5V/DIV 0V VSC1 5V/DIV 0V VSC2 5V/DIV 0V VCQ1 0.2V/DIV 0V 500ms/DIV 36692 F13 Figure 13. SC1 and SC2 Waveforms in Thermal Shutdown (CQ1 in Short-Circuit, TXEN2 Low) 3669fa For more information www.linear.com/LT3669 23 LT3669/LT3669-2 APPLICATIONS INFORMATION Receiver Wake-Up The LT3669 line receiver input is connected to pin CQ1 and its output to pin RXD1. The receiver's thresholds are a nonlinear function of the voltage applied to L+, as shown in Figure 14. The LT3669's WAKE output can be used to flag current events on CQ1 when this line is overdriven by an external device. It works in the following way: The receiver has a noise filter that rejects pulses on the CQ1 line shorter than 1/16 of the bit time, i.e., 1.63s for SR low (COM2) and 271ns for SR high (COM3). Pulses longer than 3.5/16 for COM2 and 5/16 for COM3 of the bit time will be detected. Pulses with duration between the mentioned time frame might be detected or rejected. Figure 15 illustrates the rejection and detection bands for a positive noise glitch. a) if TXEN1 is high, WAKE will pull low if CQ1 is forced opposite to its programmed level for more than 75s. Thus, if TXD1 is high, the CQ1 programmed level is low (less than 2.1V from GND) and if an external device forces CQ1 to a voltage higher than 2.95V from GND for more than 75s, WAKE will pull low. Similarly, if TXD1 is low, the CQ1 programmed level is high (higher than VL+ - 2.1V) and if an external device forces CQ1 to a voltage lower than VL+ - 2.95V for more than 75s, WAKE will pull low. RECEIVER THRESHOLDS (V) VTH 11.8V 12 10 VTHH VTHL 9.6V 0.52 x VL+ 5 0.42 x VL+ 0 0 7.5 10 IO-LINK SUPPLY RANGE 14 18 L+ SUPPLY VOLTAGE (V) 30 40 VL+ 36692 F14 REJECTED UNDEFINED DETECTED REJECTED REJECTED REJECTED GLITCH HIGH LEVEL Figure 14. Receiver Thresholds vs L+ Supply Voltage VTHH 0V 1 T 16 BIT 3.5 T (COM2) 16 BIT 5 T (COM3) 16 BIT GLITCH DURATION 36692 F15 Figure 15. Receiver Noise Rejection and Detection Behavior for CQ1 Positive Glitch 3669fa 24 For more information www.linear.com/LT3669 LT3669/LT3669-2 APPLICATIONS INFORMATION b) if TXEN1 is low, WAKE will pull low if CQ1 is forced to a voltage higher than VL+ - 2.95V for more than 75s regardless of the TXD1 level. This relies on the fact that the external device has a current sink or pull-down resistor, meaning that the default level for CQ1 when TXEN1 is low will also be low. Once WAKE pulls low, it will stay low until a defined handshaking sequence is applied to pin TXD1 and TXEN1. This sequence is as follows: TXEN1 must be set low and TXD1 toggled at least once. Figures 16a and 16b show the handshaking mechanism after WAKE pulls low for TXEN1 high and low, respectively. The WAKE output returns to high impedance also after an internal reset event. Note that driving heavy loads or placing an external pullup load to L+ (in case CQ1 is configured in pull-down mode) may cause WAKE to pull low as well, even if there is no external device driving the outputs. This could lead to false wake-up events which need to be handled by the microcontroller. Real wake-up events are normally followed by an exchange of information between the slave and the external device driving the outputs (master). A microcontroller can be programmed to react to a limited number of wake-up events. If no successful communication is established, then most likely there is no external driving device, but a heavy load or a pull-up load attached to the CQ1 output and the microcontroller's reaction to wake up events may be adjusted accordingly. For example, driving a 10F capacitive load high (TXD1 set low) will force the CQ1 output below VL+ - 2.95V for more than 75s (as shown in Figure 17), thus generating a false wake-up event. Similarly, configuring CQ1 in pull-down mode (TXD1 high) with an external 1k pull-up resistor to L+ will generate a false wake-up event as soon as TXEN1 is set low and the CQ1 output is pulled high by the external pull-up resistor for more than 75s. VTXEN1 5V/DIV VTXEN1 5V/DIV VTXD1 5V/DIV VTXD1 5V/DIV VWAKE 5V/DIV VWAKE 5V/DIV ICQ1 0.2A/DIV VCQ1 10V/DIV VILIM = 0V 0A 0V 20s/DIV 36692 F16a 20s/DIV (a) 36692 F16b (b) Figure 16. WAKE Handshaking Sequence When TXEN1 Is (a) High and (b) Low for VL+ = 24V VTXEN1 5V/DIV VWAKE 5V/DIV VCQ1 10V/DIV 0V VTXD1 = 0V 100s/DIV 36692 F17 Figure 17. False Wake-Up Event When Driving a 10F Capacitor 3669fa For more information www.linear.com/LT3669 25 LT3669/LT3669-2 APPLICATIONS INFORMATION LOW DROPOUT VOLTAGE REGULATOR (LDO) LDO Current-Limit Foldback FBLDO Resistor Network The LT3669 LDO has a current-limit foldback circuit that limits the maximum power dissipated by the LDO pass transistor to increase its robustness. Figure 18 shows the transfer function between current limit and voltage across the pass transistor. The LDO output voltage is programmed with a resistor divider between its output and the FBLDO pin. Choose the resistor values according to: V R3 = R4 LDO - 1 0.794V Stability and Output Capacitance The LT3669 LDO requires an output capacitor for stability. It is designed to be stable with most low ESR capacitors (typically ceramic, tantalum or low ESR electrolytic). Use a minimum output capacitor of 1F with an ESR of 0.5 or less to prevent oscillations. Larger values of output capacitance decrease peak deviations and provide improved transient response for larger load current changes. Bypass capacitors, used to decouple individual components powered by the LT3669, increase the effective output capacitor value. If using ceramic capacitors, use X5R or X7R types. LDO Input Considerations For optimum efficiency and highest output current capability, connect the LDO input to the lowest possible available supply that guarantees a regulated output voltage, taking into account the maximum LDO dropout voltage of 750mV. If the programmed output of the switching regulator satisfies this condition, that supply could be a good choice. Otherwise, if no other low supply is available, then it can be connected to the DIO pin. If a bypass capacitor between LDOIN and GND is needed in this configuration, connect an external diode between L+ and DIO to prevent damage on the internal reverse-polarity diode due to surge currents during hot plugging. To guarantee full reverse-polarity protection, do not connect LDOIN directly to L+. 180 LDO CURRENT LIMIT (mA) Reference designators refer to the Block Diagram. Use 1% resistors to maintain output voltage accuracy. 35 0 0 35 6 VLDOIN - VLDO (V) 36692 F18 Figure 18. LDO Current Limit Foldback Minimum LDO Load Current The LT3669 LDO requires a minimum of 175A load current to prevent its output from rising above the programmed voltage. It is recommended to choose the feedback resistors to meet this requirement (for example, R4 and R3 of 4.42k and 14k, respectively, for a 3.3V output voltage). LDO Minimum L+ Voltage The LDO's error amplifier is supplied from the L+ pin. A minimum L+ to LDO voltage difference of 4V is required to guarantee a regulated LDO output. For instance, for an LDO programmed output voltage of 3.3V, a minimum of 7.3V at the L+ pin would meet the requirement. 3669fa 26 For more information www.linear.com/LT3669 LT3669/LT3669-2 APPLICATIONS INFORMATION SWITCHING REGULATOR Operating Frequency Trade-Offs FBOUT Resistor Network Selection of the operating frequency is a trade-off between efficiency, component size, minimum dropout voltage and maximum input voltage. The advantage of high frequency operation is that smaller inductor and capacitor values may be used. The disadvantages are lower efficiency, lower maximum input voltage and higher dropout voltage. The highest acceptable switching frequency (fSW(MAX)) for a given application can be calculated as follows: VOUT + VD fSW(MAX) = tON(MIN) * (VL+ - VSW + VD ) The switching regulator output voltage is programmed with a resistor divider between its output and the FBOUT pin. Choose the resistor values according to: V R1= R2 OUT - 1 0.794V Reference designators refer to the Block Diagram. Use 1% resistors to maintain output voltage accuracy. Setting the Switching Frequency The LT3669 switching regulator uses a constant-frequency PWM architecture that can be programmed to switch from 250kHz to 2.2MHz by using a resistor tied from the RT pin to ground. Table 2 lists the required RT values for various switching frequencies. Table 2. Switching Frequency vs RT Value SWITCHING FREQUENCY (MHz) RT VALUE (k) 0.25 110 0.3 88.7 0.4 63.4 0.5 47.5 0.6 38.3 0.7 31.6 0.8 26.7 0.9 22.6 1.0 19.6 1.2 15.4 1.4 12.1 1.6 10.0 1.8 8.06 2.0 6.65 2.2 5.49 where VL+ is the typical input voltage, VOUT is the output voltage, VD is the catch diode drop (~0.72V in LT3669) and VSW is the internal drop from L+ to SW pins (~1.0V in LT3669 and ~1.4V in LT3669-2 at maximum load). This equation shows that a slower switching frequency is necessary to safely accommodate a high VL+/ VOUT ratio. Lower frequency allows lower dropout voltage. The input voltage range depends on the switching frequency because the LT3669 switch has finite minimum on- and off-times. The switch can turn off for a minimum of ~210ns, but the minimum on-time is a strong function of temperature. Use the minimum switch on-time curve (see Typical Performance Characteristics) to design for an application's maximum temperature, while adding about 30% for LT3669 part-to-part variation. The minimum and maximum duty cycles that can be achieved, taking minimum on- and off-times into account are: DCMIN = fSW * tON(MIN) DCMAX = 1 - fSW * tOFF(MIN) where fSW is the switching frequency, tON(MIN) is the minimum switch-on time, and tOFF(MIN) is the minimum switch-off time. These equations show that the duty cycle range increases when the switching frequency is decreased. A good choice of switching frequency allows adequate input voltage range (see the Input Voltage Range section) and keeps the inductor and capacitor values small. 3669fa For more information www.linear.com/LT3669 27 LT3669/LT3669-2 APPLICATIONS INFORMATION Input Voltage Range The minimum input voltage is determined by either the LT3669's minimum operating voltage of 7.5V or by its maximum duty cycle (see equation in the Operating Frequency Trade-Offs section). The minimum input voltage due to duty cycle is: VOUT + VD VL+(MIN) = - VD + VSW 1- fSW * tOFF(MIN) where VL+(MIN) is the minimum input voltage, and tOFF(MIN) is the minimum switch-off time. Note that higher switching frequency will increase the minimum input voltage. If a lower dropout voltage is desired, a lower switching frequency should be used. The maximum input voltage for LT3669 applications depends on switching frequency, the absolute maximum ratings of the L+ and BST pins, and the operating mode. The LT3669 can operate continuously from input voltages up to 40V. Input voltage transients of up to 60V are also safely withstood. However, note that if VL+ exceeds VOVLO (43V typical), the LT3669 will stop switching, allowing the output to fall out of regulation. For a given application in which the switching frequency and the output voltage are already fixed, the maximum input voltage that guarantees optimum output voltage ripple for that application can be found by applying the following expression: VOUT + VD VL+(MAX) = - VD + VSW fSW * tON(MIN) where VL+(MAX) is the maximum operating input voltage, VOUT is the output voltage, VD is the catch diode drop (~0.72V in LT3669) and VSW is the internal drop from L+ to SW pins (~1.0V in LT3669 and ~1.4V in LT3669-2 at maximum load), fSW is the switching frequency (set by RT), and tON(MIN) is the minimum switch-on time. Note that a higher switching frequency will reduce the maximum operating input voltage. Conversely, a lower switching frequency is necessary to achieve optimum operation at high input voltages. Special attention must be paid when the output is in start-up, short-circuit, or other overload conditions. In these cases, the LT3669 tries to bring the output in regulation by driving lots of current into the output load. During these events, the inductor peak current might easily reach and even exceed the maximum current limit of the LT3669, especially in those cases where the switch already operates at minimum on-time. The circuitry monitoring the current through the catch diode prevents the switch from turning on again if the inductor valley current is above 0.2A and 0.45A nominal values for LT3669 and LT3669-2, respectively. In these cases, the inductor peak current is therefore the maximum current limit of the LT3669 plus the additional current overshoot during the turn-off delay due to minimum on-time: I L(PEAK) = ISW(LIM) + VL+(MAX) - VOUTOL L * tON(MIN) where IL(PEAK) is the peak inductor current, ISW(LIM) is the switch current limit (0.325A in LT3669 and 0.65A in LT3669-2), VL+(MAX) is the maximum expected input voltage, L is the inductor value, tON(MIN) is the minimum on-time and VOUTOL is the output voltage under the overload condition. The part is robust enough to survive prolonged operation under these conditions as long as the peak inductor current does not exceed 0.6A in LT3669 and 1.3A in LT3669-2. Inductor current saturation and excessive junction temperature may further limit performance. Inductor Selection and Maximum Output Current A good first choice for the inductor value is: k L = (VOUT + VD ) * fSW (k = 9 in LT3669, k = 3.6 in LT3669-2) where fSW is the switching frequency in MHz, VOUT is the output voltage, VD is the catch diode drop (~0.72V in LT3669) and L is the inductor value in H. The inductor's RMS current rating must be greater than the maximum load current and its saturation current should be about 30% higher. To keep the efficiency high, the series resistance (DCR) should be less than 0.1, and the core material should be intended for high frequency applications. Table 3 lists several vendors of inductors. 3669fa 28 For more information www.linear.com/LT3669 LT3669/LT3669-2 APPLICATIONS INFORMATION Table 3. Inductor Vendors VENDOR URL Murata www.murata.com TDK www.componenttdk.com Toko www.toko.com Coilcraft www.coilcraft.com Sumida www.sumida.com Wurth Elektronik www.we-online.com Coiltronics www.cooperet.com For robust operation in fault conditions (start-up or short-circuit) and high input voltage (>30V), choose the saturation current high enough to ensure that the inductor peak current does not exceed 0.6A and 1.3A for LT3669 and LT3669-2, respectively. For example, an LT3669-2 application running from an input voltage of 36V using a 33H inductor with a saturation current of 0.8A will tolerate the mentioned fault conditions. The optimum inductor for a given application may differ from the one indicated by this simple design guide. A larger value inductor provides a higher maximum load current and reduces the output voltage ripple. If your load is lower than the maximum load current, then you can relax the value of the inductor and operate with higher ripple current. This allows the use of a physically smaller inductor, or one with a lower DCR resulting in higher efficiency. Be aware that if the inductance differs from the simple rule, then the maximum load current will depend on input voltage. In addition, low inductance may result in discontinuous mode operation, which further reduces maximum load current. For details of maximum output current and discontinuous mode operation, see Linear Technology's Application Note 44. Finally, for duty cycles greater than 50% (VOUT / VL+ > 0.5), a minimum inductance is required to avoid subharmonic oscillations: k LMIN = (VOUT + VD ) * fSW (k = 6.5 in LT3669; k = 2.6 in LT3669-2) The current in the inductor is a triangle wave with an average value equal to the load current. The peak inductor and switch current is: I L ISW(PEAK) = IL(PEAK) = IOUT(MAX) + 2 where IL(PEAK) is the peak inductor current, IOUT(MAX) is the maximum output load current, and IL is the inductor ripple current. The LT3669 limits its switch current in order to protect itself and the system from overload faults. Therefore, the maximum output current that the LT3669 will deliver depends on the switch current limit, the inductor value and the input and output voltages. When the switch is off, the voltage across the inductor is the output voltage plus the catch diode drop. This gives the peak-to-peak ripple current in the inductor: IL = (1- DC) * (VOUT + VD ) L * fSW where fSW is the switching frequency of the LT3669, DC is the duty cycle and L is the value of the inductor. To maintain output regulation, the inductor peak current must be less than the switch current limit ILIM which is 0.325A (LT3669) and 0.65A (LT3669-2) at low duty cycles and decreases to 0.24A (LT3669) and 0.48A (LT3669-2). The maximum output current is also a function of the chosen inductor value and can be approximated by the following expression: IOUT(MAX) = ILIM - IL = 2 ILIM(DC = 0) * (1- 0.26 * DC) - IL 2 (ILIM(DC = 0) = 0.325A in LT3669; ILIM(DC = 0) = 0.65A in LT3669-2) Choosing an inductor value so that the ripple current is small will allow a maximum output current near the switch current limit. One approach to choosing the inductor is to start with the simple rule--look at the available inductors, and choose one to meet cost or space goals. Then use these equations 3669fa For more information www.linear.com/LT3669 29 LT3669/LT3669-2 APPLICATIONS INFORMATION to check that the LT3669 will be able to deliver the required output current. Note again that these equations assume that the inductor current is continuous. Discontinuous operation occurs when IOUT is less than IL /2. provide the best ripple performance. A good starting value is: k COUT = VOUT * fSW (k = 17 in LT3669; k = 43 in LT3669-2) Input Capacitor Bypass the input of the LT3669 circuit with a ceramic capacitor of X7R or X5R type. Do not use Y5V types, which have poor performance over temperature and applied voltage. A 4.7F ceramic capacitor is adequate to bypass the LT3669 and will easily handle the ripple current. Note that larger input capacitance is required when a lower switching frequency is used. If the input power source has high impedance, or there is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. This can be provided with a lower performance electrolytic capacitor. Step-down regulators draw current from the input supply in pulses with very fast rise and fall times. The input capacitor is required to reduce the resulting voltage ripple at the LT3669 and to force this very high frequency switching current into a tight local loop, minimizing EMI. A 4.7F capacitor is capable of this task, but only if it is placed close to the LT3669 (see the PCB Layout section for more information). A second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the LT3669. A ceramic input capacitor combined with trace or cable inductance forms a high-Q (underdamped) tank circuit. If the LT3669 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LT3669's voltage rating. For guidance see Application Note 88. Output Capacitor and Output Ripple The output capacitor has two essential functions. Along with the inductor, it filters the square wave generated by the LT3669 to produce the DC output. In this role, it determines the output ripple. Additionally, low impedance at the switching frequency is important. The second function is to store energy needed to satisfy transient loads and stabilize the LT3669's control loop. Ceramic capacitors have very low equivalent series resistance (ESR) and where fSW is in MHz, and COUT is the recommended output capacitance in F. Use X5R or X7R types. This choice will provide low output ripple and good transient response. Transient performance can be improved with a higher value capacitor if combined with a phase lead capacitor (typically 22pF) between the output and the feedback pin (FBOUT). A lower value of output capacitor can be used to save space and cost but transient performance will suffer. When choosing a capacitor, look carefully through the data sheet to find out what the actual capacitance is under operating conditions (applied voltage and temperature). A physically larger capacitor, or one with a higher voltage rating, may be required. High performance tantalum or electrolytic capacitors can be used for the output capacitor. Low ESR is important, so choose one that is intended for use in switching regulators. The ESR should be 0.05 or less. Such a capacitor will be larger than a ceramic capacitor and will have a larger capacitance, because the capacitor must be large to achieve low ESR. LT3669-2 Diode Selection The catch diode (D1 from the LT3669-2 Block Diagram) conducts current only during the switch-off time. Average forward current in normal operation is ID(AVG) = IOUT * (1-DC) where DC is the duty cycle. However, a diode with 1A current rating is required for overload conditions. For inputs up to the maximum operating voltage of 40V, use a diode with a reverse-voltage rating greater than the input voltage. If transients at the input of up to 60V are expected, use a diode with a reverse-voltage rating only higher than the maximum OVLO of 45V. If operating at high ambient temperatures, consider using a Schottky with low reverse leakage. For example, Diodes, Inc. SBR1U40LP or DFLS160, ON Semiconductor MBRM140, and Central Semiconductor CMMSH1-60 are good choices for the catch diode. 3669fa 30 For more information www.linear.com/LT3669 LT3669/LT3669-2 APPLICATIONS INFORMATION BST and BD Pin Considerations output is already in regulation), then the boost capacitor may not be fully charged. Because the boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. This minimum load will depend on input and output voltages, and on the arrangement of the boost circuit. The minimum load generally goes to zero once the circuit has started. In many cases the discharged output capacitor will present a load to the switcher, which will allow it to start. For a given programmed output voltage VOUT, the minimum input voltage that guarantees a proper start-up regardless of load current is VOUT + 2V. Capacitor CBST and the internal boost Schottky diode (see the Block Diagram) are used to generate a boost voltage that is higher than the input voltage. In most cases a 0.1F (LT3669) and 0.22F (LT3669-2) capacitor will work well. Figure 19 shows two ways to arrange the boost circuit. The BST pin must be more than 1.9V above the SW pin for best efficiency. For outputs of 2.2V and above, the standard circuit (Figure 19a) is best. For outputs between 2.2V and 2.5V, use a 0.22F (LT3669) and 0.47F (LT3669-2) boost capacitor. For output voltages below 2.2V the boost diode can be tied to the input through pin DIO to preserve reverse-polarity protection (Figure 19b), or to another external supply greater than 2.2V. However the circuit in Figure 19a is more efficient because the BST pin current comes from a lower voltage source. Be sure that the maximum voltage ratings of the BST and BD pins are not exceeded. Synchronization Synchronizing the LT3669 oscillator to an external frequency can be done by connecting a square wave (with 20% to 80% duty cycle) to the SYNC pin. The square wave amplitude should have valleys that are below 0.5V and peaks that are above 1.5V (up to 6V). The minimum operating voltage of an LT3669 application is limited by the minimum input voltage and by the maximum duty cycle as outlined previously. For proper start-up, the minimum input voltage is also limited by the boost circuit. If the input voltage is ramped slowly, or the LT3669 is turned on with its EN/UVLO pin (when the The LT3669 may be synchronized over a 300kHz to 2.2MHz range. Choose the RT resistor to set the LT3669 switching frequency 20% below the lowest synchronization input. For example, if the synchronization signal will be 360kHz, choose RT for 300kHz. To assure a reliable VOUT VL+ DIO BD L+ LT3669/ LT3669-2 GND BST CBST SW (a) For VOUT 2.2V VL+ DIO BD L+ LT3669/ LT3669-2 GND BST CBST VOUT SW 36692 F19 (b) For VOUT < 2.2V; VL+ < 25V Figure 19. Two Circuits for Generating the Boost Voltage 3669fa For more information www.linear.com/LT3669 31 LT3669/LT3669-2 APPLICATIONS INFORMATION and safe operation, the LT3669 will only synchronize when the output voltage is near regulation. Therefore, it is necessary to choose a large enough inductor value to supply the required output current at the frequency set by the RT resistor. See the Inductor Selection section for more information. It is also important to note that slope compensation is set by the RT value. To avoid subharmonics, calculate the minimum inductor value using the frequency determined by RT. PCB Layout For proper operation and minimum EMI, care must be taken during printed circuit board layout. Figure 20 shows the recommended component placement with trace, ground plane and via locations. Note that large, switched currents flow in the LT3669's L+, SW and GND pins, the external catch diode (LT3669-2) and the input capacitor (CL+). Place these components, along with the inductor and output capacitor (COUT), on the same side of the circuit board, and connect them on that layer, keeping the loop they form as small as possible. All connections to GND should be made at a common star ground point or directly to a local, unbroken ground plane underneath. The SW and BST nodes should be laid out carefully to avoid interference. If the part is synchronized externally using the SYNC pin, arrange this signal to avoid interference with sensitive nodes, especially FBLDO, FBOUT, CPOR, ILIM and RT. Finally, keep the FBLDO, FBOUT, CPOR, ILIM and RT nodes small so that the ground traces will shield them from the SW and BST nodes. The exposed pad, Pin 29, on the bottom of the package acts as a heat sink and must be soldered to the ground node. To keep thermal resistance low, extend the ground plane as much as possible and add thermal vias under and near the LT3669 to any additional ground planes within the circuit board and on the bottom side. High Temperature Considerations Power dissipation within the LT3669 can be estimated by adding the power dissipated by the switching regulator, LDO and line drivers. The switching regulator's power dissipation can be obtained from an efficiency measurement. The LDO's power dissipation can be extracted simply by calculating the product between load current and voltage drop across the LDO pass device. The line drivers' contribution can be calculated in a similar manner taking the product of residual voltage and load current for each driver. Figure 20. A Good PCB Layout Ensures Proper, Low EMI Operation 3669fa 32 For more information www.linear.com/LT3669 LT3669/LT3669-2 APPLICATIONS INFORMATION The last parameter to take into account is the quiescent current required to keep all circuits working properly which is about 6mA. As an example, assume an L+ voltage of 24V, a programmed VOUT and VLDO voltages of 5V and 3.3V respectively and load currents for both line drivers of 250mA. The LDO input is connected to the switching regulator output and both switching regulator and LDO outputs are driving full load (300mA and 150mA, respectively). The total power dissipation can be estimated as: PD = 24V * 0.006A + (5V - 3.3V) * 0.15A + 5V * 0.3A * 25% + 2 * 1.5V * 0.25A = 1.524W With a JA of 44C/W, the increase in junction temperature compared to ambient will be 67C. The LT3669 protects itself against internal overheating with the help of two independent thermal shutdown circuits. One of them, with a hysteresis of 12C, shuts only the line drivers off if the junction temperature exceeds 140C, and pulls both SC1 and SC2 outputs low during the thermal shutdown event. The LDO and switching regulator outputs keep in regulation, allowing a C to process the event. This thermal shutdown circuit keeps the junction temperature under control in those cases where only the line drivers are under heavy load or short-circuit conditions. In case of fault conditions on the LDO or switching regulator outputs, a second thermal shutdown circuit shuts them off if the junction temperature exceeds 168C. Figure 21 depicts waveforms during a thermal shutdown event. Reverse-Polarity Protection The LT3669 is designed to withstand 60V between any combination of the line driver ports (L+, CQ1, Q2 and GND). The switching regulator's power devices are powered from L+ through an integrated reverse-polarity protection diode whose cathode is also wired to the DIO pin. In order to avoid damaging this diode due to surge currents during hot plugging, do not place any bypass capacitors at the DIO pin (leave it unconnected) unless an external diode is connected to bolster the integrated one. Surge and ESD Protection Considerations The LT3669 contains internal protection against ESD pulses (HBM 100pF/1.5k) of 4kV for the interface ports (L+, CQ1, Q2 and GND) and 2kV for all other pins. In order to protect the LT3669 interface ports against surge and contact/air discharge events based on the IEC 61000-4-5 and IEC 61000-4-2 standards, additional external protection is required. TVS diodes with breakdown voltages above the maximum operating voltage of the application and clamp voltages below 60V (for the maximum expected short-circuit current during the surge/ESD event) are required. SM6T39A or equivalent TVS clamps are recommended for IO-Link and most other applications with L+ operating voltages as high as 36V and will protect the part against VLDO 5V/DIV VOUT 5V/DIV VSC1/SC2 5V/DIV 3.3V LINE DRIVERS ON (PULLING LOAD HIGH) VCQ1/Q2 10V/DIV 100ms/DIV THERMAL SHUTDOWN EVENT 5V 0V THERMAL SHUTDOWN SHUTS LINE DRIVERS OFF 0V 36692 F21 Figure 21. Thermal Shutdown Waveforms 3669fa For more information www.linear.com/LT3669 33 LT3669/LT3669-2 APPLICATIONS INFORMATION 2kV (Level 2) surge and 6kV (Level 3) contact/air discharge events provided that there are bypass capacitors (>470pF) attached to pins CQ1 and Q2 and L+. For IO-Link L+ operation up to 30V, use SM6T36A or equivalent TVS clamps to further increase surge and ESD protection. Use SMCJ36A or equivalent TVS clamps for L+ operation above 36V. Figure 22 shows the placement of the TVS diodes to protect the LT3669 against surge events applied between any combination of the line driver ports. UNDERVOLTAGE LOCKOUT The LT3669 undervoltage lockout circuitry monitors the input supply L+ as well as the input pin EN/UVLO and disables the internal circuitry if various conditions are not met. The LT3669 EN/UVLO pin voltage is internally compared to a precise 1.5V reference and can be used as an adjustable undervoltage lockout (see Figure 23). Setting this pin below the 1.5V threshold disables the switcher, LDO and line drivers. Typically, UVLO is used in situations in which the input supply is current limited, or has a relatively high source resistance. A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. EN/UVLO prevents the LT3669 from operating at source voltages where the problems might occur. Additional circuitry monitors the L+ voltage, too, and disables the line drivers if it falls below 6.5V. The switching regulator and LDO are disabled for VL+ below 6.0V. Current is drawn from L+ as soon as it is above 0.65V. Setting EN/UVLO low reduces the quiescent current to 1.15mA. Keep the connections from the resistors to the EN/UVLO pin short and ensure the interplane or surface capacitance to switching nodes is minimized. If high resistor values are used, bypass the EN/UVLO pin with a 1nF capacitor to prevent coupling problems from the switch node. OUTPUT VOLTAGE MONITORING The LT3669 provides power supply monitoring for microprocessor-based systems including a power-on reset (POR). A precise internal voltage reference and precision POR comparator circuit monitor the LT3669 LDO and switching regulator output voltages. These output voltages must be above 92.7% of the programmed value for RST not to be asserted (refer to the Timing Diagrams section). The LT3669 will assert RST during power-up, power-down and brownout conditions. Once the output voltage rises above the RST threshold, the adjustable reset timer is started and RST is released after the reset timeout period VL+ LT3669/ LT3669-2 L+ LT3669/LT3669-2 R5 EN/UVLO CQ1 C3 R6 + - Q2 GND + - INTERNAL ENABLE 1.5V AGND GND 36692 F23 36692 F22 Figure 22. Placement of TVS Diodes Figure 23. Undervoltage Lockout 3669fa 34 For more information www.linear.com/LT3669 LT3669/LT3669-2 APPLICATIONS INFORMATION (see Figure 24). On power-down, once the output voltage drops below RST threshold, RST is held at a logic low. The reset timer is adjustable using an external capacitor. The POR comparator is designed to be robust against FBOUT and FBLDO pin noise, which could potentially false-trigger the RST pin. The POR comparator lowpass filters the first stage of the comparator. This filter integrates the output of the comparator before asserting the RST. The benefit of adding this filter is that any transients at the buck regulator's output must be of sufficient magnitude and duration before it triggers a logic change in the output. This prevents spurious resets caused by output voltage transients, such as load steps or short brownout conditions, without sacrificing the DC reset threshold accuracy. The RST signal also resets the internal wake-up latch. A wake-up event can then only be flagged when the RST signal goes high. Selecting the Reset Timing Capacitor The reset timeout period is adjustable in order to accommodate a variety of microprocessor applications. Set the reset timeout period, (tRST), by connecting a capacitor, CPOR, between the CPOR pin and ground, with value determined by: CPOR = tRST * 8000 This equation is accurate for reset timeout periods of 1.0ms, or greater. To program faster timeout periods, see the Reset Timeout Period vs Capacitance graph in the Typical Performance Characteristics section. Leaving the CPOR pin unconnected will generate a minimum reset timeout of approximately 22s. Maximum reset timeout is limited by the largest available low leakage capacitor. The accuracy of the timeout period will be affected by capacitor leakage (the nominal charging current is 10A) and capacitor tolerance. A low leakage ceramic capacitor is recommended. To prevent noise from false tripping the comparator on the CPOR pin, place a 10pF capacitor between the RST and CPOR pins. The rising edge of RST coupled into the CPOR pin ensures generating a clean reset signal. IO-Link Disclaimer Linear Technology attempts to maintain compatibility with the IO-Link interface and system specifications. LTC is not a member of the IO-Link Consortium as set forth by PROFIBUS Nutzerorganisation (PNO) e.V. pF ms VEN/UVLO 5V/DIV 0V VRST 5V/DIV VOUT 2V/DIV 0V 12.5ms VLDO 2V/DIV 0V CPOR = 0.1F 5ms/DIV 36692 F24 Figure 24. Reset Timer Waveforms 3669fa For more information www.linear.com/LT3669 35 LT3669/LT3669-2 TYPICAL APPLICATIONS 5V Buck, 3.3V LDO, COM2, 250mA Line Drivers L1 33H LT3669-2 BD BST FBOUT SW CBST 0.22F CPOR 0.1F D1 VOUT OR VLDO DA CPOR RT SYNC 100k 100k 100k 10k 10k ILIM LDOIN SR RESET RST I/O SC1 I/O SC2 I/O WAKE I/O RXD1 DIO I/O TXEN1 EN/UVLO I/O TXD1 L+ I/O TXEN2 Q2 I/O TXD2 CQ1 C COUT 22F RILIM, 42.2k VOUT R3, 14k FBLDO R4 4.42k AGND fSW = 600kHz R2 10.2k RT, 38.3k LDO GND VOUT , IOUT* 5V, 300mA R1, 53.6k VLDO , ILDO* 3.3V, 150mA CLDO 1F VL+, 7.5V TO 40V TRANSIENT TO 60V 250mA C1 470pF C2 470pF 1 250mA CL+ 4.7F 2 4 3 * IOUT(MAX) IS 300mA AND ILDO(MAX) IS 150mA tRST = 12.5ms (REMAINING AVAILABLE IOUT IS 300mA - ILDO) L1: CDRH50D28RNP-330MC 36692 TA02 3.3V Buck, 1.8V LDO, COM2, 250mA Line Drivers L1 33H LT3669-2 BD BST FBOUT SW CBST 0.22F CPOR 0.1F D1 VOUT OR VLDO DA CPOR RT SYNC 100k 100k 100k 10k 10k ILIM LDOIN SR RESET RST I/O SC1 I/O SC2 I/O WAKE I/O RXD1 DIO I/O TXEN1 EN/UVLO I/O TXD1 L+ I/O TXEN2 Q2 I/O TXD2 CQ1 C fSW = 400kHz tRST = 12.5ms R2 10.2k COUT 22F RT, 63.4k RILIM, 42.2k VOUT LDO R3, 5.62k FBLDO R4 4.42k AGND GND VOUT , IOUT* 3.3V, 300mA R1, 31.6k CLDO 1F VLDO , ILDO* 1.8V, 150mA VL+, 7.5V TO 40V TRANSIENT TO 60V 250mA C1 470pF C2 470pF 250mA CL+ 4.7F 1 2 4 3 * IOUT(MAX) IS 300mA AND ILDO(MAX) IS 150mA (REMAINING AVAILABLE IOUT IS 300mA - ILDO) L1: CDRH50D28RNP-330MC 36692 TA03 3669fa 36 For more information www.linear.com/LT3669 LT3669/LT3669-2 TYPICAL APPLICATIONS 3.3V Buck, 3.3V LDO, COM2, 100mA Line Drivers L1 82H CBST 0.1F VOUT OR VLDO BD LT3669 FBOUT SW CPOR BST RT SYNC 100k 100k 100k 10k 10k R2 10.2k COUT 22F RT, 63.4k ILIM SR LDO RESET RST I/O SC1 I/O SC2 I/O WAKE I/O RXD1 DIO I/O TXEN1 EN/UVLO I/O TXD1 L+ I/O TXEN2 Q2 I/O TXD2 CQ1 C VOUT 3.3V, 100mA R1, 32.4k CPOR 0.1F R3, 14k FBLDO R4 4.42k AGND LDOIN GND VLDO 3.3V 20mA, VL+ 30V CLDO 15mA, V 40V L+ 1F VL+, 7.5V TO 40V TRANSIENT TO 60V 100mA C1 470pF C2 470pF 100mA CL+ 4.7F 1 4 2 3 fSW = 400kHz tRST = 12.5ms L1: CDRH4D22HPNP-820MC 36692 TA04 5V Buck, 3.3V LDO, COM2, 500mA Line Driver (Non IO-Link) L1 33H LT3669-2 BD BST FBOUT SW CBST 0.22F CPOR 0.1F D1 VOUT OR VLDO DA CPOR RT SYNC 100k 100k 100k 10k 10k ILIM LDOIN SR RESET RST I/O SC1 I/O SC2 I/O WAKE I/O RXD1 I/O TXEN1 EN/UVLO L+ TXD1 C I/O VOUT R3, 14k R4 4.42k AGND DIO Q2 CQ1 GND COUT 22F RILIM, 42.2k FBLDO TXD2 R2 10.2k RT, 38.3k LDO TXEN2 VOUT , IOUT* 5V, 300mA R1, 53.6k CLDO 1F VLDO , ILDO* 3.3V, 150mA VL+, 7.5V TO 40V TRANSIENT TO 60V C1 470pF 500mA CL+ 10F 1 2 4 3 fSW = 600kHz tRST = 12.5ms L1: CDRH50D28RNP-330MC * IOUT(MAX) IS 300mA AND ILDO(MAX) IS 150mA (REMAINING AVAILABLE IOUT IS 300mA - ILDO) 36692 TA05 3669fa For more information www.linear.com/LT3669 37 LT3669/LT3669-2 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UFD Package 28-Lead Plastic QFN (4mm x 5mm) (Reference LTC DWG # 05-08-1712 Rev B) 0.70 0.05 4.50 0.05 3.10 0.05 2.50 REF 2.65 0.05 3.65 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 3.50 REF 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 (2 SIDES) 0.75 0.05 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER 2.50 REF R = 0.115 TYP 27 28 0.40 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 0.10 (2 SIDES) 3.50 REF 3.65 0.10 2.65 0.10 (UFD28) QFN 0506 REV B 0.200 REF 0.00 - 0.05 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3669fa 38 For more information www.linear.com/LT3669 LT3669/LT3669-2 REVISION HISTORY REV DATE DESCRIPTION A 2/15 Clarified conditions in Electrical Characteristics. PAGE NUMBER 3, 4, 5, 6 Added Driving Heavy Loads on Q2 During CQ1 Communications section. 23 Clarified IOUT(MAX) equations. 29 Clarified power dissipation equation. 33 Clarified Surge and ESD Protection Considerations. 33, 34 3669fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LT3669 39 LT3669/LT3669-2 TYPICAL APPLICATION Complete 24V 3-Wire Power and Signaling Interface (COM3) to Master (One of Four Available Master Ports Is Shown) BD 82H 53.6k LT3669 FBOUT 10.2k 0.1F 0.1F VOUT OR VLDO SW CPOR BST RT SR 10k 2.9V TO 5.5V 10F 1/4 VL LTC2874 24V 38.3k ILIM 100F SYNC LDOIN RESET RST I/O SC1 I/O SC2 I/O WAKE I/O RXD1 DIO I/O TXEN1 EN/UVLO I/O TXD1 L+ I/O TXEN2 Q2 I/O TXD2 C VOUT , IOUT* 5V, 100mA LDO 14k 4.42k AGND 4.7k VDD SENSE+ VOUT FBLDO GND 1F UP TO 20 METERS VLDO , ILDO* 3.3V, 100mA 0.2 - SENSE 1 1F Q1 VL+, 7.5V TO 40V TRANSIENT TO 60V 100mA 470pF 470pF 4.7F 2 4 3 4 5 L+1 100mA 1 2 CQ1 1F 3 IRQ I/O SDI I/O SCK I/O CS I/O SDO I/O C GATE1 200mA 1 100mA CQ1 10 0.1F RXD1 I/O TXEN1 I/O TXD1 I/O GND 36692 TA06 fSW = 600kHz tRST = 12.5ms * IOUT(MAX) IS 100mA AND ILDO(MAX) IS 100mA Q1: FQT7N10 (REMAINING AVAILABLE IOUT IS 100mA - ILDO) RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC 2874 Quad IO-Link Master Hot SwapTM Power Controller and PHY PHY for 4 Ports Compatible with IO-Link Interface and System Specification. Operates from 8V to 34V, Automatic Wake-Up Pulse Generation, 20MHz SPI Interface LT3502/LT3502A 40V, 500mA, 1.1MHz/2.2MHz Step-Down Switching Regulator VIN: 3V to 40V, VOUT(MIN) = 0.8V, IQ = 1.5mA, ISD < 1A, 2mm x 2mm DFN-8 and MSOP-10E Packages (R) LTC3631/LTC3631-3.3/ 45V, 100mA Synchronous Micropower Step-Down LTC3631-5 DC/DC Converter VIN: 4.5V to 45V (60VMAX), VOUT(MIN) = 0.8V, IQ = 12A, ISD = 3A, 3mm x 3mm DFN-8 and MSOP-8E Packages LT3012 250mA, 4V to 80V, Low Dropout Micropower Linear Regulator VIN: 4V to 80V, VOUT: 1.24V to 60V, VDO = 0.4V, IQ = 40A, ISD < 1A, 4mm x 3mm DFN-12 and TSSOP-16E Packages LT3667 40V, 400mA Step-Down Switching Regulator with Dual Fault Protected LDOs BUCK: VIN: 4.3V to 40V (60VMAX), VOUT(MIN) = 1.2V, IOUT = 400mA; LDOs: VIN: 1.6V to 45V (45VMAX), VOUT(MIN) = 0.8V, IOUT = 200mA; IQ = 50A, ISD < 1A, 3mm x 5mm QFN-24 and MSOP-16E Packages LT3082 200mA, Parallelable, Single Resistor, Low Dropout Linear Regulator VIN: 1.2V to 40V, VOUT(MIN) = 0V, Reverse-Battery Protection, 8-Lead SOT-23, 3-Lead SOT-223 and 3mm x 3mm DFN-8 Packages LT8620 62V, 2A, 96% Efficiency, 2.2MHz Synchronous VIN: 3.4V to 62V, VOUT(MIN) = 0.985V, IQ = 2.5A, ISD < 1A, Micropower Step-Down DC/DC Converter with IQ = 2.5A 3mm x 5mm QFN-24 and MSOP-16E Packages and Input/Output Current Limit/Monitor LT8610 42V, 2.5A, 96% Efficiency, 2.2MHz Synchronous VIN: 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5A, ISD < 1A, Micropower Step-Down DC/DC Converter with IQ = 2.5A MSOP-16E Package LT8611 42V, 2.5A, 96% Efficiency, 2.2MHz Synchronous VIN: 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5A, ISD < 1A, Micropower Step-Down DC/DC Converter with IQ = 2.5A 3mm x 5mm QFN-24 Package and Input/Output Current Limit/Monitor 3669fa 40 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LT3669 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LT3669 LT 0215 REV A * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2014