DS-RM25C64C–064E–9/2015
Features
Memory array: 64Kbit EEPROM-compatible serial memory
Single supply voltage: 2.7V - 3.6V
Serial peripheral interface (SPI) compatible
Supports SPI modes 0 and 3
1.6MHz maximum clock rate for normal read
5MHz maximum clock rate for fast read
Page size: 32 byte
-Byte and Page Write from 1 to 32 bytes
-Byte Write within 25µs
-Page Write within 1ms
Self-timed erase and write cycles
Page or chip erase capability
1mA read current, 1.5mA write current, 5µA power-down current
8-lead packages
RoHS-compliant and halogen-free packaging
Based on Adesto's proprietary CBRAM® technology
Data Retention: 10 years
Endurance: 25,000 Write Cycles
Unlimited Read Cycles
Description
The Mavriq™RM25C64C is an EEPROM-compatible, 64Kbit non-volatile serial
memory utilizing Adesto's CBRAM resistive memory technology. The memory device
uses a single low-voltage supply ranging from 2.7V to 3.6V.
The RM25C64C is accessed through a 4-wire SPI interface consisting of a Serial Data
Input (SDI), Serial Data Output (SDO), Serial Clock (SCK), and Chip Select (CS). The
maximum clock (SCK) frequency in normal read mode is 1.6MHz. In fast read mode
the maximum clock frequency is 5MHz.
Writing into the device can be done from one to 32 bytes at a time. All writing is
internally self-timed. The device also features an Erase which can be performed on
32-byte pages, or the whole chip. Writing a single byte to the Mavriq RM25C32C
device consumes only 10% of the energy required by a Byte Write operation of
EEPROM devices of similar size.
RM25C64C
64Kbit 2.7V Minimum
Non-volatile Serial Memory
SPI Bus
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1. Block Diagram
Figure 1-1. Block Diagram
SPI
Interface
CS
SDO
WP
GND
SCK
SDI
HOLD
Status
Registers
&
Control
Logic
I/O Buffers and Data
Latches
Y-Decoder
X-Decoder
Address
Latch
&
Counter
VCC
Page Buffer
64Kb
CBRAM
Memory
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2. Absolute Maximum Ratings
Table 2-1. Absolute Maximum Ratings(1)
1. CAUTION: Stresses greater than Absolute Maximum Ratings may cause permanent damage to the devices. These
are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in other
sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods
may reduce device reliability
Parameter Specification
Operating ambient temp range 0°C to +70° C
Storage temperature range -20°C to +100°C
Input supply voltage, VCC to GND - 0.3V to 3.6V
Voltage on any pin with respect to GND -0.3V to (VCC + 0.3)
ESD protection on all pins (Human Body Model) >2kV
Junction temperature 85°C
DC output current 5mA
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3. Electrical Characteristics
3.1 DC Operating Characteristics
Applicable over recommended operating range: TA = 0°C to +70° C, VCC = 2.7V to 3.6V
Symbol Parameter Condition Min Typ Max Units
VCC Supply Range 2.7 3.6 V
VVCCI VCC Inhibit 2.4 V
ICC1
Supply current, Fast
Read
VCC= 3.6V SCK at 5 MHz
1.2 3mA
SDO = Open, Read
ICC2
Supply Current,
Read Operation
VCC= 3.6V SCK at 1.6 MHz
1 2 mA
SDO = Open, Read
ICC3
Supply Current,
Program or Erase VCC= 3.6V SCK at 5 MHz 1.5 3mA
ICC4
Supply Current,
Standby VCC= 3.6V CS = VCC 100 200 µA
ICC5
Supply Current,
Power Down VCC= 3.6V Power Down 520 µA
IIL Input Leakage SCK, SDI,CS,HOLD,WP
VIN=0V to VCC
1µA
ILO Output Leakage SDO ,CS=VCC
VIN=0V to VCC
1µA
VIL Input Low Voltage SCK, SDI,CS,HOLD,WP -0.3 VCC x 0.3 V
VIH Input High Voltage SCK, SDI,CS,HOLD,WP VCC x 0.7 VCC + 0.3 V
VOL Output Low Voltage IOL = 3.0mA 0.4 V
VOH Output High Voltage IOH = -100µA VCC - 0.2 V
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3.2 AC Operating Characteristics
Applicable over recommended operating range: TA = 0°C to +70° C, VCC = 2.7V to 3.6V
Notes: 1. VCC must be within operating range.
2. AdestomemoryproductsbasedonCBRAMtechnologyare“Direct‐Write”memories.Endurancecyclecalculationsfollow
JEDECspecificationJESD22‐A117B.
3. Subjecttoexpected10‐yeardataretentionspecification.
Symbol Parameter Min Typ Max Units
fSCKF SCK Clock Frequency for Fast Read Mode 0 5 MHz
fSCK SCK Clock Frequency for Normal Read Mode 01.6 MHz
tRI SCK Input Rise Time 1µs
tFL SCK Input Fall Time 1µs
tSCKH SCK High Time 7.5 ns
tSCKL SCK Low Time 7.5 ns
tCS CS High Time 100 ns
tCSS CS Setup Time 10 ns
tCSH CS Hold Time 10 ns
tDS Data In Setup Time 4ns
tDH Data In Hold Time 4ns
tHS HOLD Setup Time 30 ns
tHD HOLD Hold Time 30 ns
tOV Output Valid 6.5 ns
tOH Output Hold Time Normal Mode 0ns
tLZ HOLD to output Low Z 0200 ns
tHZ HOLD to output High Z 200 ns
tDIS Output Disable Time 100 ns
tPW Page Write Cycle Time 1 3 ms
tBP Byte Write Cycle Time 25 100 µs
tPUD Vcc Power-up Delay(1) 75 µs
tRPD Return from Power-Down Time 50 µs
CIN SCK, SDI,CS,HOLD,WP
VIN=0V 6pf
COUT SDO VIN=0V 8pf
Endurance
25000(2) Write
Cycles
Unlimited(3) Read
Cycles
Retention 70C10 Years
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3.3 AC Test Conditions
4. Timing Diagrams
Figure 4-1. Synchronous Data Timing with HOLD high
Figure 4-2. Hold Timing
AC Waveform Timing Measurement
Reference Level
VLO = 0.2V
Input
Output
0.5 Vcc
0.5 Vcc
VHI = 3.4V
CL = 30pF (for 1.6MHz SCK)
CL = 10pF (for 5MHz SCK)
SDI
SCK
VIH
VIL
CS
VIH
VIL
VIH
VIL
VALID IN
tCSS
tSC KH
tDS tDH
tSC KL
SDO
VIH
VIL
HI-Z
tOV
tCS
tCSH
HI-Z
tDIS
tOH
HZ
HOLD
SCK
CS
t
HD
t
HS
SDO
t
t
HD
t
LZ
t
HS
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Figure 4-3. Power-up Timing
5. Pin Descriptions and Pin-out
Table 5-1. Pin Descriptions
Mnemonic Pin Number Pin Name Description
CS 1Chip Select
Making CS low activates the internal circuitry for device operation.
Making CS high deselects the device and switches into standby
mode to reduce power. When the device is not selected (CS high),
data is not accepted via the Serial Data Input pin (SDI) and the
Serial Data Output pin (SDO) remains in a high-impedance state.
SDO 2Serial Data Out Sends read data or status on the falling edge of SCK.
WP 3Write Protect N/A
GND 4Ground
SDI 5Serial Data In Device data input; accepts commands, addresses, and data on the
rising edge of SCK.
SCK 6Serial Clock
Provides timing for the SPI interface. SPI commands, addresses,
and data are latched on the rising edge on the Serial Clock signal,
and output data is shifted out on the falling edge of the Serial Clock
signal.
HOLD 7Hold When pulled low, serial communication with the master device is
paused, without resetting the serial sequence.
Vcc 8Power Power supply pin.
VCC
min
VCC
max
V
VCCI
Device in Reset
Program, Read, Erase and Write Commands Rejected
t
PUD
Device Fully
Accessible
TIME
VCC
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Figure 5-1. Pin Out
6. SPI Modes Description
Multiple Adesto SPI devices can be connected onto a Serial Peripheral Interface (SPI) serial bus controlled by an SPI
master, such as a microcontroller, as shown in Figure 6-1,
Figure 6-1. Connection Diagram, SPI Master and SPI Slaves
The Adesto RM25C64C supports two SPI modes: Mode 0 (0, 0) and Mode 3 (1, 1). The difference between these two
modes is the clock polarity when the SPI master is in standby mode (CS high). In Mode 0, the Serial Clock (SCK) stays
at 0 during standby. In Mode 3, the SCK stays at 1 during standby. An example sequence for the two SPI modes is
shown in Figure 6-2. For both modes, input data (on SDI) is latched in on the rising edge of Serial Clock (SCK), and
output data (SDO) is available beginning with the falling edge of Serial Clock (SCK).
SDO
SPI Memory
Device
SPI Interface with
Mode 0 or Mode 3
SDI
SCK
SPI Master
(i.e. Microcontroller)
CS1CS2CS3
SCK SDO SDI
SPI Memory
Device
SPI Memory
Device
SCK SDO SDI SCK SDO SDI
CS CS CS
SPI
1
CS
2
3
4
SDO
WP
GND
8
7
6
5
VCC
HOLD
SCK
SDI
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Figure 6-2. SPI Modes
7. Registers
7.1 Instruction Register
The Adesto RM25C64C uses a single 8-bit instruction register. The instructions and their operation codes are listed in
Table 7.1. All instructions, addresses, and data are transferred with the MSB first, and begin transferring with the first
low-to-high SCK transition after the CS pin goes low.
Table 7-1. Device Operating Instructions
Instruction Description Operation
Code Address
Cycles Dummy
Cycles Data
Cycles
WR Write 1 to 32 bytes 02H 2 0 1-32
READ Read data from
memory array 03H 2 0 1 to ∞
FREAD Fast Read data
from data memory 0BH 2 1 1 to ∞
WRDI Write Disable 04H 0 0 0
RDSR Read Status
Register 05H 0 0 1 to ∞
WREN Write Enable 06H 0 0 0
PERS Page Erase 32
bytes 42H 2 0 0
CERS Chip Erase
60H 0 0 0
C7H 0 0 0
PD Power Down B9H 0 0 0
RES Resume from
Power Down ABH 0 0 0
SDI
Mode 3 (1,1) SCK
SDO
Mode 0 (0,0) SCK
MSB
MSB
CS
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7.2 Status Register
The Adesto RM25C64C uses a single 8-bit Status Register. The Write In Progress (WIP) and Write Enable (WEL) status
of the device can be determined by reading this register.
The Status Register format is shown in Table 7-2 The Status Register bit definitions are shown in Table 7-3.
Table 7-2. Status Register Format
Table 7-3. Status Register Bit Definitions
8. Command Descriptions
8.1 WREN (Write Enable):
The device powers up with the Write Enable Latch set to zero. This means that no write or erase instructions can be
executed until the Write Enable Latch is set using the Write Enable (WREN) instruction. The Write Enable Latch is also
set to zero automatically after any non-read instruction. Therefore, all page programming instructions and erase
instructions must be preceded by a Write Enable (WREN) instruction. The sequence for the Write Enable instruction is
shown in Figure 8-1.
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
000000WEL WIP
Bit Name Description R/W Non-Volatile Bit
0WIP
Write In Progress
“0” indicates the device is ready
“1” indicates that the program/erase cycle
is in progress and the device is busy
RNo
1WEL Write Enable Latch
“0” Indicates that the device is disabled
“1” indicates that the device is enabled
R/W No
2N/A
Reserved. Read as “0” N/A No3N/A
4N/A
5N/A Reserved. Read as “0” N/A No
6N/A Reserved. Read as “0” N/A No
7N/A Reserved. Read as “0” N/A No
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Figure 8-1. WREN Sequence
The following table is a list of actions that will automatically set the Write Enable Latch to zero when successfully
executed. If an instruction is not successfully executed, for example if the CS pin is brought high before an integer
multiple of 8 bits is clocked, the Write Enable Latch will not be reset.
Table 8-1. Write Enable Latch to Zero
8.2 WRDI (Write Disable):
To protect the device against inadvertent writes, the Write Disable instruction disables all write modes. Since the Write
Enable Latch is automatically reset after each successful write instruction, it is not necessary to issue a WRDI instruction
following a write instruction. The WRDI instruction is independent of the status of the WP pin. The WRDI sequence is
shown in Figure 8-2.
Figure 8-2. WRDI Sequence
Instruction/Operation
Power-Up
WRDI (Write Disable)
WR (Write)
PERS (Page Erase)
CERS (Chip Erase)
PD (Power Down)
SDI
SCK
SDO
CS
01234567
HI-Z
00000110
SDI
SCK
SDO
CS
01234567
HI-Z
00000100
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8.3 RDSR (Read Status Register):
The Read Status Register instruction provides access to the Status Register and indication of write protection status of
the memory.
Caution: The Write In Progress (WIP) and Write Enable Latch (WEL) indicate the status of the device. The RDSR sequence is
shown in Figure 8-3. (Note: The Write Status Register command is not available in this device, and should not be
used. Use of this command may cause unexpected behavior.)
Figure 8-3. RDSR Sequence
8.4 READ (Read Data):
Reading the Adesto RM25C64C via the Serial Data Output (SDO) pin requires the following sequence: First the CS line
is pulled low to select the device; then the READ op-code is transmitted via the SDI line, followed by the address to be
read (A15-A0). Although not all 16 address bits are used, a full 2 bytes of address must be transmitted to the device. For
the 32Kbit device, only address A0 to A11 are used; the rest are don't cares and must be set to "0". For the 64Kbit
device, only address A0 to A12 are used; the rest are don't cares and must be set to "0".
Once the read instruction and address have been sent, any further data on the SDI line will be ignored. The data (D7-D0)
at the specified address is then shifted out onto the SDO line. If only one byte is to be read, the CS line should be driven
high after the byte of data comes out. This completes the reading of one byte of data.
The READ sequence can be automatically continued by keeping the CS low. At the end of the first data byte the byte
address is internally incremented and the next higher address data byte will be shifted out. When the highest address is
reached, the address counter will roll over to the lowest address (00000), thus allowing the entire memory to be read in
one continuous read cycle. The READ sequence is shown in Figure 8-4.
Figure 8-4. Single Byte READ Sequence
SDI
SCK
CS
01 2 4 56
HI-Z
3 789101120 21 22 23 24 25 26 27 28 29 30 31
15 14 13 3210
76543210
2 BYTE ADDRESS
DATA OUT
INSTRUCTION
00000011
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8.5 FREAD (Fast Read Data):
The Adesto RM25C64C also includes the Fast Read Data command, which facilitates reading memory data at higher
clock rates, up to 5MHz. After the CS line is pulled low to select the device, the FREAD op-code is transmitted via the
SDI line. This is followed by the 2-byte address to be read (A15-A0) and then a 1-byte dummy. For the 64Kbit device,
only address A0 to A12 are used; the rest are don't cares and must be set to "0".
The next 8 bits transmitted on the SDI are dummy bits. The data (D7-D0) at the specified address is then shifted out onto
the SDO line. If only one byte is to be read, the CS line should be driven high after the data comes out. This completes
the reading of one byte of data.
The FREAD sequence can be automatically continued by keeping the CS low. At the end of the first data byte, the byte
address is internally incremented and the next higher address data byte is then shifted out. When the highest address is
reached, the address counter rolls over to the lowest address (00000), allowing the entire memory to be read in one
continuous read cycle. The FREAD sequence is shown in Figure 8-5.
Figure 8-5. Two Byte FREAD Sequence
8.6 WRITE (WR):
The Write (WR) instruction allows bytes to be written to the memory. But first, the device must be write-enabled via the
WREN instruction. The CS pin must be brought high after completion of the WREN instruction; then the CS pin can be
brought back low to start the WR instruction. The CS pin going high at the end of the WR input sequence initiates the
internal write cycle. During the internal write cycle, all commands except the RDSR instruction are ignored.
Product Density Page Size (byte)
RM25C64C 64Kbit 32
SDI
SCK
CS
01 2 4 5 6
HI-Z
37891020 21 22
24 25 26 27 28 29 30 31
15 14 13 3210
76543210
2 BYTE ADDRESS
DATA BYTE 1 OUT
INSTRUCTION
00001011
SDO
65432107
DUMMY BYTE
23
32 33 34 35 36 37 38 39
76543210
DATA BYTE 2 OUT
40 41 42 43 44 45 46 47
SDI
SCK
SDO
CS
HI-Z
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A WR instruction requires the following sequence. After the CS line is pulled low to select the device, the WR op-code is
transmitted via the SDI line, followed by the byte address (A15-A0) and the data (D7-D0) to be written. The internal write
cycle sequence will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the
SCK low-time immediately after clocking in the D0 (LSB) data bit.
The Write In Progress status of the device can be determined by initiating a Read Status Register (RDSR) instruction
and monitoring the WIP bit. If the WIP bit (Bit 0) is a “1”, the write cycle is still in progress. If the WIP bit is “0”, the write
cycle has ended. Only the RDSR instruction is enabled during the write cycle. The sequence of a one-byte WR is shown
in Figure 8-6.
Figure 8-6. One Byte Write Sequence
The Adesto RM25C64C is capable of a 32-byte write operation.
For the RM25C64C: After each byte of data is received, the five low-order address bits (A4-A0) are internally
incremented by one; the high-order bits of the address will remain constant. All transmitted data that goes beyond the
end of the current page are written from the start address of the same page (from the address whose 5 least significant
bits [A4-A0] are all zero). If more than 32 bytes are sent to the device, previously latched data are discarded and the last
32 data bytes are ensured to be written correctly within the same page. If less than 32 data bytes are sent to the device,
they are correctly written at the requested addresses without having any effects on the other bytes of the same page.
The Adesto R25C64C is automatically returned to the write disable state at the completion of a program cycle. The
sequence for a 32 byte WR is shown in Figure 8-7. Note that the Multi-Byte Write operation is internally executed by
sequentially writing the words in the Page Buffer.
NOTE: If the device is not write enabled (WREN) previous to the Write instruction, the device will ignore the write instruction and
return to the standby state when CS is brought high. A new CS falling edge is required to reinitiate the serial communication.
SDI
SCK
CS
012 456
HI-Z
3 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
15 14 13 321076543210
2 BYTE ADDRESS DATA ININSTRUCTION
00000010
SDO
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Figure 8-7. WRITE Sequence
8.7 PER (Page Erase 32 bytes):
Page Erase sets all bits inside the addressed 32-byte page to a 1. A Write Enable (WREN) instruction is required prior to
a Page Erase. After the WREN instruction is shifted in, the CS pin must be brought high to set the Write Enable Latch.
The Page Erase sequence is initiated by bringing the CS pin low; this is followed by the instruction code, then 2 address
bytes. Any address inside the page to be erased is valid. This means the bottom five/six bits (A4-A0)/(A5-A0) of the
address are ignored. Once the address is shifted in, the CS pin is brought high, which initiates the self-timed Page Erase
function. The WIP bit in the Status Register can be read, using the RDSR instruction, to determine when the Page Erase
cycle is complete.
The sequence for the PER is shown in Figure 8-8.
Figure 8-8. PERS Sequence
SDI
SCK
CS
012 456
HI-Z
3 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
15 14 13 321076543210
2 BYTE ADDRESS DATA BYTE 1INSTRUCTION
00000010
SDO
SDI
SCK
32
HI-Z
76543210
SDO
76543210
DATA BYTE 2
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
76543210
DATA BYTE 3 DATA BYTE N (N= 32)
CS
SDI
SCK
SDO
CS
012 456
HI-Z
3 7 8 9 10 11 20 21 22 23
15 14 13 3210
2 BYTE ADDRESSINSTRUCTION
01000010
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8.8 CER (Chip Erase):
Chip Erase sets all bits inside the device to a 1. A Write Enable (WREN) instruction is required prior to a Chip Erase.
After the WREN instruction is shifted in, the CS pin must be brought high to set the Write Enable Latch.
The Chip Erase sequence is initiated by bringing the CS pin low; this is followed by the instruction code. There are two
different instruction codes for CER, 60h and C7h. Either instruction code will initiate the Chip Erase sequence. No
address bytes are needed. Once the instruction code is shifted in, the CS pin is brought high, which initiates the self-
timed Chip Erase function. The WIP bit in the Status Register can be read, using the RDSR instruction, to determine
when the Chip Erase cycle is complete.
The sequence for the 60h CER instruction is shown in Figure 8-9. The sequence for the C7h CER instruction is shown in
Figure 8-10.
Figure 8-9. CERS Sequence (60h)
Figure 8-10. CERS Sequence (C7h)
8.9 PD (Power Down):
Power Down mode allows the user to reduce the power of the device to its lowest power consumption state.
All instructions given during the Power Down mode are ignored except the Resume from Power down (RES) instruction.
Therefore this mode can be used as an additional software write protection feature.
The Power Down sequence is initiated by bringing the CS pin low; this is followed by the instruction code. Once the
instruction code is shifted in the CS pin is brought high, which initiates the PD mode. The sequence for PD is shown in
Figure 8-11.
SDI
SCK
SDO
CS
01234567
HI-Z
01100000
SDI
SCK
SDO
CS
01234567
HI-Z
11000111
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Figure 8-11. PD Sequence
8.10 RES (Resume from Power Down):
The Resume from Power Down mode is the only command that will wake the device up from the Power Down mode. All
other commands are ignored.
In the simple instruction command, after the CS pin is brought low, the RES instruction is shifted in. At the end of the
instruction, the CS pin is brought back high.
The rising edge of the SCK clock number 7 (8th rising edge) initiates the internal RES instruction. The device becomes
available for Read and Write instructions 75μS after the 8th rising edge of the SCK (tPUD, see AC Characteristics). The
sequence for simple RES instruction is shown in Figure 8-12.
Figure 8-12. Simple RES Sequence
SDI
SCK
SDO
CS
01234567
HI-Z
10111001
SDI
SCK
SDO
CS
012 456
HI-Z
37
INSTRUCTION
10101011
t
RPD
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9. Package Information
9.1 SN (JEDEC SOIC)
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
ØØ 0° – 8°
ØØ
EE
11
NN
TOP VIEWTOP VIEW
CC
E1E1
END VIEW
AA
bb
LL
A1A1
ee
DD
SIDE VIEWSIDE VIEW
Package Drawing Contact:
contact@adestotech.com
8S1 G
8/20/14
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
8S1, 8-lead (0.150” Wide Body), Plastic Gull
Wing Small Outline (JEDEC SOIC) SWB
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9.2 TA-TSSOP
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A - - 1.20
A1 0.05 - 0.15
A2 0.80 1.00 1.05
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
C 0.09 - 0.20
Side View
End View
Top View
A2
A
L
L1
D
1
E1
N
b
Pin 1 indicator
this corner
E
e
Notes: 1. This drawing is for general information only. Refer to JEDEC
Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion. Allowable
Dambar protrusion shall be 0.08mm total in excess of the b
dimension at maximum material condition. Dambar cannot be
located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
H
8X E
12/8/11
TA, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP) TNR
C
A1
Package Drawing Contact:
contact@adestotech.com
®
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10. Ordering Information
10.1 Ordering Detail
10.2 Ordering Codes
RM25C64C-BSNC-T
Device Type Shipping Carrier Option
RM25C = SPI serial access EEPROM B = Tube
T = Tape & Reel
Density Grade & Temperature
C = Green, Commercial
temperature (0-70°C)
Device/Die Revision
Package Option
C
SN = 8 lead 0.150” SOIC, Narrow
TA = 8 lead TSSOP
Operating Voltage
B = 2.7V to 3.6V
64 = 64Kbit
Ordering Code Package Density Operating
Voltage fSCKF
Device
Grade Ship
Carrier Qty.
Carrier
RM25C64C-BSNC-B
SN 64Kbit 2.7V to 3.6V 5MHz Commercial
(0C to 70C)
Tube 100
RM25C64C-BSNC-T
Reel 4000
RM25C64C-BTAC-B
TA 64Kbit 2.7V to 3.6V 5MHz Commercial
(0C to 70C)
Tube 100
RM25C64C-BTAC-T
Reel 6000
Package Type
SN 8-lead 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
TA 8-lead 3 x 4.4 mm, Thin Shrink Small Outline Package
21
RM25C64C
DS-RM25C64C–064E–9/2015
11. Revision History
Doc. Rev. Date Comments
RM25C64C-064A 10/2014 Initial document release.
RM25C64C-064B 1/2015 Updated Power Down Current.
RM25C64C-064C 3/2015 Updated formatting and syntax.
RM25C64C-064D 4/2015 Updated Endurance specifications for Read and Write cycles.
RM25C64C-064E 9/2015 Removed Preliminary document status (document complete).
Corporate Office
California | USA
Adesto Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: (+1) 408.400.0578
Email: contact@adestotech.com
© 2015 Adesto Technologies. All rights reserved. / Rev.: DS-RM25C64C–064E–9/2015
Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms
and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications
detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the
Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems.
For Release Only Under Non-Disclosure Agreement (NDA)
Adesto®, the Adesto logo, CBRAM®, MavriqTM and DataFlash® are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their
respective owners.