4 TELEDYNE COMPONENTS POH tee TC7106/7106A TC7107/7107A 3-1/2 DIGIT A/D CONVERTER FEATURES @ Internal Reference with Low Temperature Drift ............... 20 ppm/C Typical 50 ppm/C Maximum Drives LCD (TC7106) or LED (TC7107) Display Directly Adjustment Guaranteed Zaro Reading With Zero Input Low Noise for Stable Display Auto-Zero Cycle Eliminates Need for Zero True Polarity Indication for Precisian Null Applications Convenient 9 V Battery Operation (TC7106A) High Impedance CMOS Differential inputs ....10120 Differential Reference Inputs Simplity Ratiametric Measurements Low Power Operation... cssesssceececseeees 10 mW Available in 60-Pin Plastic Flat Package 0.1 pr uf a] cian caer LCO OISPLAY . 1MQ 3 vi 2-19 SEGMENT -_ IGG ANALOG < 228 palatal INPUT, COT PE ve por [22 __] : -o IN 7; MINUSSIGN | BACKPLANE ~ 32 | ANALOG BP onive COMMON vr 4~ 2 TC7106A | Yeurr 47 KQ 0.47 pF Vagr ma bor] Suz Vier (25-190 0.22 pr Cz Vint wv PS OSC, OSC, OSC, TO ANALGG 39 38} Coge | 40 WH Roge 100 pFI 100 kQ ~<! COMMON (PIN 32) 3 CONVERSIONSSEC 200 mV FULL SCALE 486 1LL Fat Figure 1 TC7106A Typical Operating Circuit 1MQ oe Vin ANALOG iN Pur Oot PFE -> ' 0.1 pF uf Ta] Cher Caer 219 25 30} Vin POL ANALOG ap a7 QQ 0.22 pF , COMMON . ae 28 TC7107A Vause VRer a] c - at Vaer Vint v ose, osc; osc, Be -1999 COMMON ANODE LED OSPLAY 2a a6 Yaer 35 100 mV 39 3a! Cose | 40 > Rose 100 pF i 100 ko 28 2 -SVv TO ANALOG ~ COMMON (PIN 32) 3 CONVERSKONS/SEC 200 mY FULL SCALE aor rz! 197 S-1 (4380) Figure 2 TC7107A Typical Operating Circuit 1-115TC7106/7106A TC7107/7107A GENERAL DESCRIPTION The TC7106A and TC7107A 3-1/2 digit direct display drive analog-to-digital converters allow existing 7106/7107 based systems to be upgraded. Each device offers a precision internal voltage reference featuring a 20 pprvC maximum temperature drift coefficient. This represents a 4 to 7 times improvement over similar 3-1/2 digit converters. Existing 7106 and 7107 based systems may be upgraded without changing external passive component values. The need for a costly, space consuming extemal reference is removed. The TC7107A drives common anode light emit- ting diode (LED) displays directly with an 8 mA drive cur- rent per segment. A low cost, high resolution indicating meter requires only a display, four resistors, and four ca- pacitors. The TC7106A low power drain and 9 V hattery operation make it suitable for portable applications. The TC7106A/TC7107A reduces linearity error to less than 1 count. Rollover-errorthe difference in readings for equal magnitude but oppasite polarity input signalsis ~ ORDERING INFORMATION aege at L 3 1/2 DIGIT A/D CONVERTER below +1 count. High impedance differential inputs offer. 1 pA leakage current and a 10'2Q input impedance. The differential reference input allows ratiometric measurements for ohms or bridge transducer measurements. The 15 uVp_p noise performance guarantees a rock solid reading. The auto-zero cycle guarantees a zero display reading with a zero voit input. The TC7106A/TC7107A dual slope conversion tech- nique automatically rejects interference signals if the con- verters integration time is set to a multiple of the interfer- ence signal period. measurement environments W frequency signals are present. The TC7106A/TC7107A are 60-pin flat package for compact designs. DIP devices are offered in an industrial temperature range. This is especially useful in industrial here 50, 60 and 400 Hz line available in a small Part No. Package Pin Layout Temperature Range Display Drive TC7106CPL 40-Pin Plastic DIP Normal 0C ta +70C Lco TC7106RCPL 40-Pin Plastic DIP Reverse OC ta +70C Lco TC71061JL 40-Pin CarDIP Narmal -25C to +85C LCcO TC7106C8Q 60-Pin Plastic Flat Package Formed Leads ac to +70C Lco TC7106CKW 44-Pin Plastic Flat Formed Leads 0 ta +70C Lco TC7106CLW 44-Pin PLCC _ arc to +70S LCQ TC7T107CPL 40-Pin Plastic DIP Normal 0C ta +70C LED TC7107RCPL 40-Pin Plastic DIP Reverse 0C ta +70C LED TC7T107IL 40-Pin CarOIP Normal -25C to +95C LED TC7107C8Q 60-Pin Plastic FjJat Package Formed Leads oC ta +70C -LED | TC7107CKW 44-Pin Plastic Flat Formed Leads O ta +70C LED TC7107CLW 44-Pin PLCC _ Orc to +70C LEO TC7106ACPL 40-Fin Plastic OIP Normal aC to +70C LCcO TC7106ARCPL 40-Pin Plastic DIP Raversa arc to +70C .. LCcO TC7106AIJL 40-Pin CerDIP Normal -25C to +95C LCo TC7106ACBQ 60-Pin Plastic Flat Package Formed Leads arc to +70C LCD TC7106ACKW 44-Pin Plastic Flat Farmed Leads aC ta +70C LCD TC7106ACLW 44-Pin PLCC _ OC to +70C Loco TC7107ACPL 40-Pin Plastic DIP Narmal OC ta +70C LEO TC7107ARCPL 40-Pin Plastic CIP Aleverse aC ta +70C LED TCTIO7AIL 40-Pin CarDIP Normal 2C ta +95C LED TC7107AC8Q 60-Pin Plastic Flat Package Formed Leads 0C ta +70C LED TC7T1IQ7TACKW 44-Pin Plastic Flat Formed Leads arc ta +70C LED TC7107ACLW 44-Pin PLCC _ arC to +70C LEO 1-1163 1/2 DIGIT A/D CONVERTER PIN CONFIGURATIONS TC7106/7106A TC7107/7107A 1090's 1oos~ AB, (19 VS verre MOARMAL PIN D; (2 ] CONFIGURATION ;G] 8, (4) ay (I F, Ce] 6,7] 5,04 o2 [2] c, Gal 7 eee Tena A, fz F, (93) E [14] 03 05 | 83 [16] . F307] E; [73] ~ 40} OSC, [33] OSC2 [33] Osc, 37{| TEST [38] Vier 35] Vier [34] Chee [33] Cree 52] ANALOG COMMON rt] vin 301 Vn [23] Caz [28] Youre [27] Vimy 26) ~ [3] Ga. . [24] cy 100%s fe pot (20 ] 21] sprcNo (MINUS SIGN) (Ptoearia7A) ceoue carcsagst2adcgrea SLL 111 ll L. 3 ACT 39] REF LO Gy Ce] 38] CRer ey Ce Ea Caer bo; [10] ; 36 | COMMON e074 on ' [as] inn Ne [12 TCTIGSACLW [34] nc 8; [3 | ee P33] INLO Oe 32] Az F, Lis] 31] gure & (35) [30] INT 03 117] pa] 184 J 191 [20 27 [2a} foes Nt oser C1 *neversepn FY osc2 (2 | conrauration [39] Oy ose; [3] 38] Cy vest (J [37] 8 Vier C5] P38] Ay Vaer C24 [35] Fs Cher (71 [3a] Gy Cher [3a] Ey cowie 2 Bzjo, | Vin (18 we pat} ca vant Teroea fae, Caz C2 p23] Az Veurr 03 | [za] F, Vine (14) [37] &2 v7 G5 fzs10, | [ Ge (38) [25] By 3 Cr! za] F; 100s 1100's As Gal Fa] & _| l. G3 3] [ 72} AB g~t 1000's aprano (Zo [21] Pot (T106A/7107A) (MINUS SIGH) Na AEF Hi 1-117 & | REF Lo LB) Caer 2] Cher Fae Ps) ina aor an TCTTIOSACKW TCUT1IO7 ACK WwW {FLAT PACKAGE} [a] into rs) az 4350 ILL F932TC7106/7106A TC7107/7107A 3 1/2 DIGIT A/D CONVERTER PIN CONFIGURATIONS | (Cont.) a a eon a a wo = a ~ a < a7] fae af [24] faa 32} [3 cy Ay ay ve & PE ]ne [&) a, fat 5 & Fale e ) sua Viner (22 [30] 05 Vausr 7] [a2] 3 ve (a [as] Fe ya7] Aa [as] a3 sz G2] ne Ca] 3 Ay nC ey Fy By e & re ft) s, P& | nc & 3 3 [=] sus Pa), [& ] cno |) Pou VE) aa, B & rs int [oe] [30] 25 Yourr C7 pe] & ne [aa] aa] Fp Caz (9) aT] A xe [30] 76] a Vin (54 [as] <2 vin 057] ale ue [52 a 74] NC we [s2 3 faa Ne sus [3] TeTIo8A Ta] sua sus (431 ToT97& : Dl sue ne (Ga Fa] xe we (3a Fay me vie (ss P37] oy vin (55 ra] 23 ne Ga] Bl, 0 an COMMON | 57 . . 19] Gy COMMON | $ wy Se Cher Ga pte] Fy chee [38] [re] Fs ches [0] [a7] Ay Cher [3] [ir] ay Vazs [oo . *. 16] By VRer Ce! e [is] a ~ Sf - af TyaT yee GeeeSST, TyTEEEEySyETTS = =z a 3 z 2 =z 2 = 2 zZz2ee'8 - =< =z. s & z 3 = 2 =z a zz? au NOTES: NOTES: +.NG 0 NO INTERNAL COMNMECTION +. a HO INTERNAL CONNECTION LDINS 8, 13, 14 AND 53 AAE CONMECTED TO THE HE $UOSTRATE THE 2 DINS 4, 73, 14 ANO 53 ARE COMMECTED TO THE OIE SUBSTRATE THE POTENTIAL AT THESE PWS |3 APPROXOMATELY Y*. NO EXTERNAL POTENTIAL AT THES PINS TE APPROXIMATELY V*. NO EXTERNAL CONNECTIONS SHOULD BE MACE CONNECTIONS SHOULD SE MADE. 480 ILL FOL ABSOLUTE MAXIMUM RATINGS* TC7106A TC7107A Supply Voltage (V* to V7) oes eeccseseetetseesceeesteneneaeretes 15 V Supply Voltage . Analog Input Voltage (either input) (Note 1) ......... Vt to Vo Vb eccccccccceseeeesenseeececesseeaceeeeceeresnssasecessessaaseeeemseees +6V Reference Input Voltage (ether input) .. caceseseeetteees Vt to VO Vom ccccceccncneaccescaeesetnaeeeeseeeaeseeceeeensansesaasecensreseesaeeres -9V Clock INpUt oo. sees csssscereeeeseetecene tere eens reeereesesaanae Test to V* Analog Input Voltage (either input) (Note 1) ........ V* to V7 Power Dissipation (Note 2} Reference Input Voltage fenher input) Leseeeeeeeceees V* to V- CerDIP Package ......cesscesecrcscssseenetesere terres 1000 mW Clock Input .. veosetececeeteaceee GND to V+ Plastic Package wane ne nnted becnacee eras ceseeeeneteeaesceenen 800 mW Power Dissipation (Note 2) Operating Temperature CerDIP PAcKage oo. ... 1000 mW Cc Devices sesessesesseaneeencennieseetersnereersesenn OPE to +70C Plastic PaCkage ....cecccesceeeeeeseeeeeereeeeeeeeeese BOO MW PP DOVICES oo. eeesesenteteeeneene ce teeeeeeeeerees -25C to +85C Operating Temperature Storage Temperature ....seseveeeeenreeererrre 85C to +150C MO" DeViCOS ooeccsecescccsssnetstseesssneeeeesncenennen OC to +70C Lead Temperature (Soldering, GO S@C) ..........seee 300C P Devices cece: 25C to +85C Storage Temperature .. wee we 65C to +1 50C Lead Temperature (Soldering, 60 sec).. cesaeeenaceeeeaneees 300C Static-sensitive davica. Unused devicas must be stored in conducive material. Protect davicas fram static discharge and static fields, Stresses above thasa listed under Absoluta Maximum Ratings may cause permanent damage to the cevica. Thess ara stress ratings only and tunctional operation af the device at these or any other canditians above those indicatad in the operational sections of the specifications is not implied, Expasure to Absaluta Maximum Rating Conditons for axtended gariads may affect cevica reliability. 4-1183 1/2 DIGIT A/D CONVERTER TC7106/7106A TC7107/7107A ELECTRICAL CHARACTERISTICS (Note 3) TC8i1 i Characteristics Conditions Min Typ | Max | Unit Zero Input Reading Vin=a.aVv 000.0 | +000.0 +000.0 | Digita! Full-Scale = 200.0 mV | ! Reading Ratiometric Reading Vin = Vaer 999 g99/1000 | 1000 : Digital Vrer = 100 mV j Reading Rail-Over Error (Difference in Vin = +Vin = 200 mV 1 +0.2 +1 | Counts Reading for Equal Positive and Negative Reading Near Full-Scale) Linearity (Max. Deviation Fram Full-Scale = 200 mV =i +0.2 +1 Counts Best Straight Line Fit) or Full-Scale = 2.000 V Common-Mode Vom =1V, Vin = OV, _ 50 VV Rejection Ratio (Note 4) Full Scale = 200.0 mV Noise (Pk Pk Value Not Vin = OV - _ 15 _ pV Exceeded 95% of Time) Full-Scale = 200.0 mV Leakage Current @ Input Vin = OV _ 1 i 10 pA Zero Reading Oritt ne Vin=OV C Device = 0C to 70C _ 0.2 1 uwVPC * Vin=av _ I" Device = 25C to +85C _ 1.0 2 uVicCc Scale Factor Vin = 199.0 mV, Temperature Coefficient C Device = 0C to 70C _ 1 5 ppm*C (Ext. Ref = 0 ppmC) Vin = 199.0 mV _ _ 20 pomeC I Device = -25C ta +85C Supply Current (Does Not Vin = 0 _ 0.8 1.8 | mA Include LED Current For TC7107A) | Analag Common Volage 25kQ Between Comman 2.7 3.05 3.35 Vv (With Respect to Pos. Supply) and Pos. Supply Temp. Coeff. af 25kQ Between Common | Analog Common and Pos. Supply (With Respect OC sTas 70C _ 20 50 porm?C to Pos. Supply) ' ~C.* Industrial Tamp. Range Devices i Tamp. Coeff. af 25kQ Between Common i \ Analog Common - and Pos, Supply | (With Respect aC $ Ta < 85C _ _ 75 | pervec ta Pos. Supply) t, Industrial Temp. Range Oevices : TC7106A ONLY Pk - PK Veto Va 9V 4 5 i 6 | v Segment Drive Voltage (Note 5) : \ TC7106A ONLY Pk ~ Pk Vr to V7=9V 4 5 6 / v Backplane Orive Voltage (Note 5) ! TC7107A ONLY Wr =5.0V 5 8.0 i ma Segment Sinking Current (Except Pin 19) Segment Vaitaga =3 V TC7107A ONLY Vr =5.0V 10 16 mA Segment Sinking Current (Pin 19) Segment Valtage = 3 V NOTES: 1. Input valtagas may exceed the supply voltages provided the input currant is Hemited to 100 pA. 2. Dissipation rating assumes device is mounted with all laads soldered to printed circuit board. 3. Uniess otherwise nated, specifications apply to bath the TC7106A and TC7107A at TA = 257, fovocx = 48 kHz. TC7106<A is tested in the circuit of Figure 1. TC7107A is tested in the circuit of Figure 2. 4. Refer to Differential Input" discussion, 5. Backplane drive is in phase with sagrnent drive for off segment. 180 out at phase for an segment. Frequency is 20 times canversion rate. Average DC camponent is less than 50 mV. 1-419TC7106/7106A TC7107/7107A PIN DESCRIPTION 3 1/2 DIGIT A/D CONVERTER 40-Pin DIP 60-Pin Pin Number Flat Package (Normal) (Reverse) Pin Number Name _ Description 1 (40) 13 vr Positive supply voltage. 2 (39) 14 Dy Activates the 0 section of the units display. 3 (38) 15 Cy Activates the C section of the units display. 4 (37) 16 8, Activates the 6 section af the units display. 5 (36) 17 Ay Activates the A section of the units display. 6 (38) 18 Fy Activates the F section of the units display. 7 (34) 19 Gy Activates the G section of the units display. 8 (33) 20 E; Activates the E section of the units display. 9 (32) 21 De Activates the D section of the tens display. 10 (31) . 25 Ca Activates the C section of the tens display. 13 (30) 26 Be Activates the 8 section of the tens display. 12 (29). 27 Aa Activates the A section of tha tens display. 13 (28) 2a F2 Activates the F section of the tens display. 14 (27} 29 E2 Activates the & section of the tens display. 15 (26) 30 D3. Activates the D section of the hundreds display. 16 (25) 3 83 Activates the 8 section of the hundreds display. 17 (24) 32 F3 Activates the F section of the hundreds display. 18 (23) 33 E3 Activates the & section of the hundreds display. 19 (22) 34 ABs Activates both halves of the 1 in the thousands display. 20 (21} 35 POL Activates the negative polarity display. 21 (20) 36 BP LCD Backplane drive cutput (TC7106A). GNO Digital ground (TC7107A). 22 (19) a7 G3 Activates the G section of the hundreds display. 23 (18) 40 Ag Activates the A section cf the hundreds display. 24 (17) 41 Cy Activates the C section af the hundreds display. 25 (18) 43 G2 Activates the G secticn of the tens display. 26 (15) 45, vw Negative power supcly voltage. 27 (14) 46 Vint Integrator output. Connection paint far integration capacitar. See INTEGRATING CAPACITOR section far more details 28 (13) 47 Veuer Integration resistar connection. Use a 47 kQ resister for a 200 mV full- scale range and a 470 kQ resistor for 2V full-scale range. 29 (12) 49 Caz The size of the auta-zere capacitor influences system noise. Use a 0.47-uF capacitor fer 200 mV full scala, and a 0.047-.F capacitor far 2V full scale. See Paragraph on AUTO-ZERO CAPACITOR for more details. 30 (11) 51 Vin The analog low input is connected t this pin. 31 (10) 55 Vin The analog high input signal is connected te this pin. 32 (9} 57 Analog _ This gin is primarily used ta set the analog common-mode vaitage Common for battery operatian or in systems where the input signal is referenced to the power supply. it also acts as a reference voltage source. Sea paragrach an ANALOG COMMON for more details. 33 (8) 58 Chee See pin 34. twee 1-1203 1/2 DIGIT A/D CONVERTER TC7106/7106A TC7107/7107A PIN DESCRIPTION (Cont.) 40-Pin DIP 60-Pin Pin Number Flat Package (Normal) (Reverse) Pin Number Name Description a4 (7) 59 Cher A0.141F capacitor is used in mast applications. if a larga common- made voltage exists (for example, the Vix pin is not at analog common), and a 200-mV scale is used, a 1-4F capacitor is recom- mended and will hold the rcll-over error to 0.5 count. 35 (6) 60 VRer See pin 36. 36 (5) 1 Vibes The analog input required to generate a full-scale output (1999 counts). Place 100 mV between pins 35 and 36 far 199.9 mV full-scale. Place 1V between pins 35 and 36 for 2V full scale. See paragraph on REFERENCE VOLTAGE. 37 (4) 3 Tast Larnp test. When pulled high (to V*) all seqments will be tumed on and the display should read 1888. It may also be used as a negative supply for externally-generated decimal points. See paragraph under TEST for additional information. 38 (3) oe 4 Osc, See pin 40. 33 (2) , 6 OSCz See pin 40. 40 (1) 10. OSC, _ Pins 40, 39, 38 make up the ascillator section. For a 48-kHz clock (3 readings per section), connect pin 40 to the junction of a 100-kQ rasistor and a 100-p9F capacitar, The 100-kQ resistor is tied to pin 39 and the 100-pF capacitor is tied to pin 338. General Theory of Operation where: Dual Slope Conversion Principles Vg = Reference Voltage The TC7106A and TC7107A are dual slope, integrating Ts1 = Signal Integration Time (Fixed) analog-to-digital converters. An understanding of the dual Tar = Reference Voltage Integration Time (Variable) slope conversion technique will aid in failowing the detailed operation theory. 3 The conventional dual slope converter measurement Vin = VR Fe, cycle has two distinct phases: ' s! Foraconstant Vin: * Input Signal Integration ANALOG c * Reference Valtage Integration (Deintegration) SIGNAL COMPARATOA The input signal being converted is integrated far a fixed 1 time period (Ts). Time is measured by counting clock pulses. An opposite polarity constant reference voltage is rowncn then integrated until the integrator output voltage returns to | fexocx | zero, The reference integration time is directly proportional vournGe CONTROL [CONTRO to the input signal (Tai). (Figure 3A). POLARITY CONTROL ina simple dual slope canverter a complete conversion vu - y ee the integrator output to ramp-up and ramp 4 t= COUNTER Asimple mathematical equation relates the input signal, ae Za ~ veueL SCALE reference voltage and integration time: ze eo TN iM = TA MFULL SCALE | Tst SIGNAL REFERENCE 1 Vin(tidt = VaTat INTEGRATE INTEGRATE | AC in(tat = RE 4360 1UL 735 | 0 Figure 3A asic Qual Slope Converter 1-121ge TC7106/7106A TC7107/7107A The dual slope converter accuracy is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. An inherent benefit is noise immunity. Naise spikes are integrated or averaged to zero during the integration periods. Integrating AOGs are immune to the large conversion errors that plaque succes- sive approximation converters in high naise environment. Interfering signals with frequency components at multiples of the averaging period will be attenuated. Integrating ADCs commonly operate with the signal integration period settoa muitiple of the 50/60 Hz power line period. (Figure 38) 30 = id S iN fy bil z Ive |i = 29 fri lal Yr us 7 IY | c iiti a Lh yel Q patdli i ne : (| Heh 3 | | T 2 MEASUREMENT PERIOD | 0 ei EE O1/T 1 107 INPUT FREQUENCY 4350 ILL Foe Figure 38 Normai-Mode Rejection of Dual Slope Converter Analog Section In addition to the basic signal integrate and deintegrate cycles discussed, the circuit incorporates an auto-zero cycle. This cycle removes buffer ampiifier, integrator, and comparator offset voltage error terms ttom the conversion. A true digital zero reading results without external adjusting potentiometers. A complete conversion consists of three cycles: an auto zero, signal integrate and reference inte- grate cycle. Auto-Zero Cycie During the auto-zero cycle the differential input signal is disconnected fram the circuit by opening internal analog gates. The internal nodes are shorted to analog common (ground) ta establish a zero input condition. Additional analog gates close a feedback loop around the integrator and comparator. This loop permits comparator offset valt- age error compensation. The voltage level established on Cazcompensates tor device offset voltages. The offset error referred to the input is less than 10 nV. The auto-zero cycle length is 1000 tc 3000 counts. 3 1/2 DIGIT A/D CONVERTER Signal Integrate Cycle The auto-zera loop in opened, the internal differential inputs connect to Vix and Vin. The differential input signal is integrated for a fixed time period. The signal integration period is 1000 counts. The externally set clock frequency is divided by four before clocking the internal counters. The integration time gericd is: Ts = x 1000 where: fosc = External Clack Frequency . The differential input voltage must be within the device common-mode range (1 V of either supply) when the con- verter and measured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, Vix should be tied to analog cammon. Polarity is determined at the end of signal integrate phase. The sign bit is a true polarity indication in that signals less than 1 LS8 are correctly determined. This allows precision null detection limited only by device noise and auto-zero residual offsets. Reference Integrate Cycie The final phase is reference integrate or de-integrate. Vin is internally connected to analog common and Vin is connected across the previously charged reference capaci- tor, Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal and is between Oand 2000 counts. The digital reading displayedis: VIN 7000 x Vaer Digital Section. (TC7106A) The TC7106A (Figure 5) contains all the segment driv- ers necessary to directly drive a 3 1/2 digit liquid crystal display (LCD). An LCD backplane driver is included. The backplane frequency is the external clock frequency divided by 800. For three conversions/second the backplane fre- quency is 60 Hz with a 5 V nominal amplitude. When a segment driver is in phase with the backplane signal the segment is OFF. An out of phase segment drive signal causes the segment to be ON or visible. This AC drive configuration results in negligible OC voltage across each LCD segment. This insures long LCD display life. The polarity segment driver is ON for negative analog inputs. If Vi and Vin are reversed this indicator would reverse. 1-1223 1/2 DIGIT A/D CONVERTER TC7106/7106A TC7107/7107A q} WF ote, 2805 280, X toso toso toso 8c 6 oF Vee AL 00s Nha ty isan GNNOD WIG TWNYALNI ayy I . . DOT TOULNOD |-4 vt ate 250, A } 49019 vy! indino volvuydno2 Woud > SYIAINGHOUMS OL eI SUNN 1 SNIL |-{SOIJUONNHE > SONYSNOWL volvudHol it Uh i j HOLY viva NotLoas Wi Lut LI paviuioid oore 3009430 300930 300930 pl inanogs 2] [ANanoas Z| fLNaRNOS Z . vouvuvainty ke 1 Ui TIL LULL st Se a3 m3 AMI 3 3u suanud LN3W93$ G97 nt asso eA 9 INI5 43g We u ~- INV 1d s9VE I 8 9 9 | ONNOYD TWUOIG TVNY3LNI YOOLLOL ail AVidstd 091 a Andlno ININDIS A + INdLNO LN3WD3S WAL 4350 HLL FST FigureS TC7106A Block Diagram 1-123TC7106/7106A TC7107/7107A On the TC7106A when the test pin is pulled to V+ all segments are turned ON. The display reads 1888. During this mode the LCD segments have a constant OC voltage impressed. Do not leave the disolay in this mode for mare than several minutes. LCD displays may be destroyed if operated with OC levels for extended periods. The display FONT and the segment drive assignment are shown in Figure 6. DISPLAY FONT GiCF4SE789 [ore TT tore te te oF =, ~ - i Li il (oo a 4350 ILC Fou Figure 6 Display FONT and Segment Assignment, In the TC7106A an internal digital ground is generated from a 6 valt zener diode and a large P channel source follower. This supply is made stiff to absorb the large capacitive currents when the backplane voltage is switched. Digital Section (TC7107A) ' Figure 7 shows the TC7107A. It is identical to the TC7106A except that the regulated supply and back plane drive have been eliminated and the segment drive is typi- cally 8 mA. The 1000 output (pin 19) sinks current from two LED segments, and has a 16 mA drive capability, The TC7107A is designed to drive common anode LEDs. In bath devices, the polarity indication is on for nega- tive analog inputs. If Vij and Vix, are reversed, this indication can be reversed also, if desired. The display font is the same as the TC7106A. System Timing The oscillator frequency is divided by 4 prior to clacking the internal decade counters. The three phase measure- ment cycle takes a total of 4000 counts or 16000 clock pulses. The 4000 count cycle is independent of input signal magnitude. Each phase of the measurement cycie has the following length: 1000 to 3000 Counts (4000 to 12000 Clock Pulses) For signals less than full-scale the auto-zero phase is assigned the unused reference integrate time period, * Auto-Zero Phase: % Te 3 1/2 DIGIT A/D CONVERTER * Signal Integrate: 1000 Counts (4000 Clock Pulses) This time period is fixed. The integration period is: 1. Ts; = 4000 Ea osc Where fogc is the extemally set clock frequency. + Reference Integrate: 0 to 2000 Counts (0 to 8000 Clock Pulses) The TC7106A/7107A are drop in replacements for the 7106/7107 parts. External component value changes are not required to benefit from the low drift internal reference. Clock Circuit Three clocking methods may be used: 1. An external oscillator connected to pin 40. 2. Acrystal between pins 39 and 40. 3. An A-C oscillator using all three pins. poe e eee CAYSTAL ie EXT sr ose TC71064 TCTIOTA TO TEST PIN ON TSCT106A TO GND PIN ON TSCT107A- a0 1, Fi0 Figure 3 Clock Circuits Component Value Selection Auto-Zero Capacitor Caz The Caz capacitor size has some influence on system noise. A 0.47 LF capacitor is recommended for 200 mV full- scale applications where 1 LSB is 100 pV. A 0.047 LF capacitor is adequate for 2.0 V full-scale applications. A mylar type dielectric capacitor is adequate. Reference Voltage Capacitor Cper The reference voltage used to ramp the integrator output voltage back to Zero during the reference integrate cycle is stored on Caer. A 0.1 pF capacitor is acceptable when Vix is tied to analog common. If a large common-mode voltage exists (Vaez # analog common) and the application requires a 200 mV full-scale increase Cag to 1.0 LF. Rollover errar willbe held to less than Q.5 count. A mylartype dielectric capacitor is adequate. 4-124Ni 3 1/2 DIGIT A/D CONVERTER TC7106/7106A TC7107/7107A ONNOUD Wild A jt VE 3805 280, Asat Yoso0 los0 980 dt ae 6c of u00s ONnoD IvAlDld I jo JOULNOD 31901} 4 pe fa 350, h A079 L___ Andino voLyuvunod Nous > SUSAIUC HOLIMS OL siiin t->] sta. [-|saauonnnt tsonvsndis yoLruvanoa Ul itl Li WoLv viva <I #NOILI3S } 008 Ui HY ayuDIG 3d0030 300930 300940 pL piarrogs cf pinawoas 2] fanarroas 2 Mt LUT Wg DAT Wy | SUBANO LN3ND3S 091 nf x IN|5 T 1Y5 GNNOUS IWUOIG WHUALNT @o8 Gl- AY1d510 G31 indilno AN3INOIS yuso A + ANd LNG INFNDZS TIAL LOLLZ9L wt Ny HOWNOS DOTYHY 4959 ILL FCM TCT107A Glock Diagram Figure 7 1-125TC7106/7106A TC7107/7107A 3 1/2 DIGIT A/D CONVERTER Integrating Capacitor Cint Cint should be selected to inaximize integrator output voltage swing without causing output saturation. Due to the TC710GA/7107A superior analog common temperature coeffictent specification, analog common will normally sup- ply the differential voltage reference. For this casea +2 V full- scale integrator output swing is satisfactory. For3 readings/ second (fogc = 48 kHz) a 0.22 LF value is suggested. Ifa different oscillator frequency is used Ciyr must be changed in inverse proportion to maintain the nominal 2 V integrator swing. An exact expression for Cir is: 1 Ves (4000) (-) (= C fosc Rint INT = Vint Where: fosc = Clock frequency at Pin 38 Ves = Full-scale input voltage Rint = Integrating resistor Vint = Desired full-scale integrator output swing ~ Cinr must have low dielectric absorption to minimize rollover error. An inexpensive polypropylene capacitor is recommended. INTEGRATING RESISTOR Rint The input buffer amplifier and integrator are designed with class A output stages. The output stage idling current is 100 uA. The integrator and buffer can supply 20 pA drive currents with negligible linearity errors. Rint is chosen to remain in the output stage linear drive region but not so large that printed circuit board leakage currents induce errors. For a 200 mV full-scale Aint is 47 kQ. A 2.0 V full-scale requires 470 kQ. Component Nominal Full-Scale Voltage Value 200.0 mV 2.000 V Caz 0.47 pF 0.047 pF Funr 47 KQ 470 kQ Cit 0.22 wr 0.22 uF Note: 1. fesc = 48 kHz (3 readings/sac) Oscillator Components Rose (Pin 40 to Pin 39) should be 100 kil. Cogc is selected fram the equation: e - 0-88 osc = RC For fosc of 48 KHz, Cogc is 100 pF nominally. Note thatfosc is divided by fourto generate the TC7106A internal control clock. The backplane drive signal is derived by dividing fosc by 800. To achieve maximum rejection of 60 Hz noise pickup, the signal integrate period should be a multiple of 60 Hz. Oscillator frequencies of 240 kHz, 120 kHz, 80 kHz, 60 kHz, 40 kHz, 33 1/3 kHz, etc. should be selected. Far 50 Hz rejection, oscillator frequencies of 200 kHz, 100 Khz, 66 2/3 kHz, 50 kHz, 40 kHz, etc. would be suitable. Note that 40 kHz (2.5 readings/secand) will reject both 50 and 60 Hz (also 400 and 440 Hz). Reference Voltage Selection A full-scale reading (2000 counts) requires the input signal be twice the reference voltage. Required Fuil-Scale Voltage* Vacs 200.0 mV 100.0 mV 2.000 V 1.000 V Ves = 2 Vege In same applications a scale factor other than unity may exist between a transducer output voltage and the required digital reading. Assume, for example, a pressure transducer output is 400 mV for 2000 Ib/in?. Rather than dividing the input vaitage by two the reference voltage should te set to 200 mV. This permits the transducer input to be used directly. The differential reference can also be used when a digital zero reading is required when Vix is not equal to zero. This is common in temperature measuring instrumentation. A compensating offset voltage can be applied between analog common and Vix. The transducer output is con- nected between Vin, and analog common, The intemal voltage reference potential avaitable at analog common will normally be used to supply the convert- ers reference. This potential is stable whenever the suocly potential is greater than approximately 7 V. In acoclicatiens where externally generated reference voltage is desired refer to Figure 9. 1-126 re we: \ee the 3 1/2 DIGIT A/D CONVERTER ve vt eo vr ve 4 5.8Y REF CENER 4 6.8 kO VREF be TCTIO6A TCTIO7A Me, A lz + 4 ~ TCTIO6A VREF Tc04 TC7T107A va 1.2V REF y-*~? REF COMMON (a) (b) 4350 (LL FIT Figura 9 External Reference Device Pin Functional Description Differential Signal Inputs (Vit (Pin 31), Vin (Pin 30)) The TC71064/7017A is designed with true differential inputs and accepts input signals within the input stage common mode voltage range (Vcm). The typical range is V* 1.0 to V-+1 V. Common-mode voltages are removed frant the system when the TC7106A/TC7107A operates from a battery ar floating power source (isolated from measured system) and Vix is connected to analog common (Vcom): See Figure 10. In systems where common-mode voltages exist in 86 dB common-mode rejection ratio minimizes error. Com- mon-meode voltages do, however, affect the integrator out- put level. Integrator output saturation must be prevented. A worse case condition exists if a large positive Voy exists in conjunction with a full-scale negative differential signal. The negative signal drives the integrator output positive along with Vew (Figure 11). For such applications the integrator TC7106/7106A TC7107/7107A output swing can be reduced below the recommended 2.0 V full-scale swing. The integrator output will swing within 0.3 V of V* or V~ without increasing linearity errors. INPUT. c, BUFFER Ce + Ay - 0 V, Vin > | | INTEGRATOR v vi ~z [Von -Vin| r Where: \ 4000 T, = INTEGRATION TIME = - iy osc C, = INTEGRATION CAPACITOR RA) = INTEGRATION RESISTOR aS ILL E19 Figure 11 Common-Made Voltage Reduces Available Integrator Swing. (Vcom # Vin) Differential Reference (VRee (Pin 36), Vaer (Pin 35)) The reference voltage can be generated anywhere within the V* to V~ power supply range. To prevent railover type errors being induced by large common-mode voltages Crer should be large campared to stray node capacitance. The TC7106A/TC7107A circuiis have significantly lower analog common temperature coefficient. This potential gives avery stable voltage suitable for use as a voltage reference. The temperature coefficient of analog common ts 20 pprvC typically. pw] SEGMENT DAIVE LCD DISPLAY 1234 J MEASURED Vv Gay V POL 8P SYSTEM |. een AZ INT asc, a vr - pn asc, J" _ +t v TC7T106A vo sgno ANALOG , ys OSC, COMMON YREFYREF Vv v ee Jolie POWER | | | SOURCE V av ISI 212 | Figure 10 Common-Mode Voltage Removed in Battery Operation with Vix, = Analog Common 1-127TC7106/7106A TC7107/7107A Analog Common (Pin 32) The analog common pin is set at a voltage potential approximately 3.0 V below V*. The potential is guaranteed to be between 2.7 V and 3.35 V belaw V*. Analog common is tied internally to the N channel FET capable of sinking 20 mA. This FET will hold the common line at 3.0 V should an external load attempt to pull the common line toward V~. Analog common source current is limited to 10 pA. Analog common is therefore easily pulled to a more negative voltage (i.e., below V* -3.0 V). The TC7106A connects the internal Vi, and Vix, inputs to analog common during the auto-zero cycle. During the reference integrate phase Vix, is connected to analog com- mon. If Vix is not externally connected to analog common, a common-mode voitage exists. This is rejected by the converters 86 dB common-mode rejection ratio. in battery operation analog common and Vix are usually connected removing common-mode voltage concerns. In systerns where Vin is connected to the power supply ground or to a given voltage, analog common should be connected to Vix; - The analog common pin serves to set the analog section reference or common paint. The TC7106A is spetifically designed to operate from a battery or in any measurement system where input signals are not referenced (float) with respect to the TC7106A power source. The analog common potential of V* -3.0 V gives a 6 V end of battery life voltage. The commen potential has a 0.001%/% voltage coefficient and a 15 Q output impedance, With sufficiently high total supply voltage (V* -V~ > 7.0 V) analog common is a very stable potential with excel- 3 1/2 DIGIT A/D CONVERTER lent temperature stabilitytypically 20 pprmvC. This poten- tial can be used to generate the reference voltage. An external voltage reference will be unnecessary in most cases because of the 50 pprvC maximum temperature coefficient. See Internal Voltage Reference discussion. Test (Pin 37) The test pin potential is 5 V less than V*. Test may be used as the negative pawer supply connection for extemal CMOS logic. The test pin is tied to the internally generated negative logic supply (Internal Logic Ground) through a 500Q resistor in the TC7106A. The test pin load should be no more than 1mA. If testis pulled ta V* all segments plus the minus sign will, be activated. Do not operate in this mode for more than several minutes with the TC7106A. With Test = V+ the LCD Segments are impressed with a DC voltage which will destroy the LCD. The test pin will sink about 10 mA when puiled to V*. . Internal Valtage Reference Stability The analog common voitage temperature stability has been significantly improved (Figure 12). The A version of the industry standard circuits allow users to upgrade old systems and design new systems without external voltage references. External R and C values da not need to be changed. Figure 13 shows analog common supplying the necessary voltage reference far the TC7106A/TC7107A. 200 @ 180+ No g MAXIMUM i & 180 F SPECIFIED Ho MaxIMuN 7 . gq 40r TYPICAL o = 120+ < kab g 1 NO MAXIMUM wo gg |. MAXIMUM SPECIFIED 2 UMIT Typtcat ! e 8 | w | on | & joe | TYPICAL | | a 1 1 | : 20 <sE I ' 3 We OGA IcL7t06 | | ICL7146 S350 1LL Fla ae v vr 24 kQ 4~ TC7106A TC71IO7A + VREF 1kQ VREF ANALOG ~ COMMON SET Voer = 1/2 Yew scale 4480 ILL FS : Figure 12 Analog CammonTemperature Coefficient Figura 13 Internal Voltage Reference Connectionmate 8 3 1/2 DIGIT A/D CONVERTER TC7106/7106A TC7107/7107A Power Supplies The TC7107A is designed to wark from +5V supplies. , However, if a negative supply is not available, it can be generated from the clock output with two diodes, two capaci- tors, and an inexpensive IC, (Figure 14) In selected appiicatians a negative supply is not re- quired. The conditions to use a single +5V supply are: ' * The input signal can be referenced to the center of the . Vv Vier | common-mode range of the converter. +1983 [38 i LED REF = Vine i | t The signal is less than +1.5V. + An external reference is used. DRIVE ae com 32 The TSC7660 DC to DC converter may be used to qerara generate 5 V from +5 V (Figure 15). vp, Lt vr Vin oo? TL - 21 epee enn v7 GNO a 26 > = ee NS as roe . Ww js sy osc, 3 | *4-172 DIGIT ADC ! Oscy H Thue OSs KT. asso F7 | an = : gr ~ Figure 15 Negative Power Supply Generation with TC7660 TSC7IO7A : . re only a 5 percent reduction. Maximum power dissipation is ry. only 7.7 mAx 2.5 Vx 24 = 462 mW, a reduction of 26%. An output voltage reduction of 1 volt (point C) reduces LED | current by 10% (7.3 mA) but power dissipation by 38%! (7.3 mA x 2.2 V x 24 =385 mW). 4380 ILL FIs Figure 14 Generating Negative Supply From +5 V TC7107 Power Dissipation Reduction The TC7107A sinks the LED display current and this causes heat to build up in the IC package. If the internal voltage reference is used, the changing chip temperature can cause the display to change reading. Sy reducing package power dissipation such variations can be reduced. By reducing the LED cormmon anode voltage the TC7107A package power dissipation is reduced. Figure 16 is a photograph of a curve-trace display showing the relationship between output current and output voltage for a typical TC7107CPL. Since a typical LED has 1.9 volts across it at 7 mA, and its common anode is 7 5 connected ta +5 V, the TC7107A output is at 3.2 V. (pointA Figure 16 TC7107A Output Current vs Output Voltage on Figure 15). Maximum power dissipation is 8.1 mA x 3.2 V x 24 segments = 622 mW. Notice, however, that once the TC7107A output voltage is above two volts, the LED currentis essentially constant as output voltage increases. Reducing the output voltage by 0.7 V (point 8 in Figure 16) results in 7.7 mA of LED current, 1-129TC7106/7106A TC7107/7107A Reduced power dissipation is very easy to obtain. Figure 17 shows two ways: eithera 5.1 ohm, 1/4 watt resistor ora 1 Amp diode placed in series with the display (but not in series with the TCG7107A). The resistor will reduce the TC7107A output voltage, when all 24 segments are ON, to point "C" of Figure 16. When segments tur off, the output voltage will increase. The diode, on the other hand, will result in a relatively steady output voltage, around point B. In addition to limiting maximum power dissipation, the resistor reduces the change in power dissipation as the display changes. This effect is caused by the fact that, as fewer segments are ON, each ON output drops more valtage and current. For the best case of six segments {a 111 display) to worst case (a 1888 display) the resistor will change about 230 mW, while a circuit without the resistor will change about 470 mW. Therefore, the resistor will reduce the effect of display dissipation on reference voltage drift by about 50%. The change in LED brightness caused by the resistor is almost unnoticeable as more segments turn off. If display brightness remaining steady is very important to the de- signer, a diode may be used instead of the resistor. *5V IN -SV > o- 2442 so 150.0 e Tk O47 = 109 ty uF O22 TPS ef HE TY TP2 at DISPLAY a le uF a | ? dh ritil= 40 30 TP 21 D 4G 1C71078 1 10 i 20 Pedr t iad bai ti i) bb ii & DISPLAY 3.10 14Ww e a i ion PIS 9G ne eee tse! 4350 ILL FID Figure 17 Diode or Resistor Limits Package Power Dissipation APPLICATIONS INFORMATION LIQUID CRYSTAL DISPLAY SOURCES Several LCD manufacturers supply standard LCD dis- plays to interface with the TC7106A 3 1/2 digit analog-to- digital converter. Manufacturer 3 1/2 DIGIT A/D CONVERTER Manufacturer Address/Phone Part Numbers! Crystaloid 5282 Hudson Dr.; C5335, 15535, Electronics Hudsan, OH 44236 T5135, SX440 218/655-2429 ANDO 770 Airport Blvd.,- FE 0801 Burlingame, CA 94010 FE 0203 415/347-9916 EPSON 3415 Kashikawa St, LD-B7098Z Torrance, CA 90505 LD-H7992AZ 214/534-0360 Hamlin, Inc. 612 . Lake St., 3902, 3933, 3903 Lake Mills, WI 53551 414/648-2361 Note: 1. Contact LCO manufacturer for full product listings specifications. Light Emitting Diode Display Sources Several LED manufacturers supply seven segment digits with and without decimal point annunciators for the TCTIO7A. Display Type Address Hewlett-Packard 640 Page Mill Ad. LED Components Palo Alto, CA 94304 And 770 Airpart Blvd. LED Burlingame, CA 94010 Decimal! Point and Annunciator Drive The test pin is connected to the internally-generated digital logic supply ground through a 500 Q resistor. The test pin may be used as the negative supply for external CMOS gate segment drivers. LCO display annunciators for decimal points, low battery indication, or function indication may be added without adding an additional supply. No more than 1 mA should be supplied by the test pin. The test pin potential is approximately 5 V below V*. Ratiomeiric Resistance Measurements The true differential input and differential reference make ratiometric reading possible. Typically in a ratiometric operation, an unknown resistance is measured with respect to a known standard resistance. No accurately defined reference voltage is needed. 1-1303 1/2 DIGIT A/D CONVERTER TC7106/7106A TC7107/7107A The unknown resistance is put in series with a known standard and a current passed through the pair. The voltage vr 1 | developed across the unknown is applied to the input and na 4049 ; the voltage across the knawn resistor is applied to the gr ' ; reference input. If the unknown equals the standard, the TC7106A \ display will read 1000. The displayed reading can be deter- 21 1 TOLCD mined from the following expression: BP 7 DECIMAL : POINT R Unk -- @- = . nknown GN Displayed Reading = _._ x 1000 rest} J pay 3 A Standard TO LCO bldg - . . BACK The display will overrange for R Unknown 2 2x R standard. yr \7 Wy 1 rd > Vv" gp +4 | Vier " t+} t Va ha i ; RstanoAano REF > Fq) TO LCD LOO DISPLAY sN DEAE tS DECIMAL Vin agin oN TC7106A D+ POINTS - SELECT _ RuNKNOWN TCTIO6GA H/| 1983 . > VIN TEST , 030 3 ANALOG [exo COMMON 41356 ILL F20 4350 UL F21 I Figure 18 Decimal Point Drive Using Test as Lagie Ground Figure 19 Law Parts Count Aatiometric Aesistance Measurement + | ew IN4343 aA tpF = 200 mV re yv ws 27 " 10 kn {i} [74 P vce | SY iz Fa] zane i uF TC7106A 29 i] Wy. = 4) y- wg | Le] aces ner c 35 28 ton 6.4 uF = Cs] 10 + Y-ner 7 ro] : 22) anatoc i 1HQ 10% 31] COMMON 40 {7 1 a ow VIN 20 ka 22 yF i iL ot 10% 30 COM Lt mn eT C1 s 3-10 pF VARIAGLE, 26 39 C2 2.132 pF VARIABLE saat ORIVE ' ! Cc 7 : ! ' | : LCD OISPLAY : i 43801 FZ Figure 20 3 1/2 Digit True RMS AC OMM 1-1313 1/2 DIGIT A/D CONVERTER j ' +] OV > | | QV I {1 | 160 kQ 300 kQ 100 ko vr v7 ve v7 ' IN a nN 4 IN4148 Ay Vin iyi SENSOR 50 ka IN -TCT7106A Vin TCT106A Veg =2 Vv R + v2 2S v REF 50 kQ ; REF + VREF VREF COMMON COMMON 4350 ILL F23 . 4380 ILL Fle : ay Figura 21. Temperature Sensor Figure 22 Positive Temperature Coefficient Resistor . . Temperature Sensor gv ~ 9g 2 CONSTANT SV 1 vr ve . VRer wan ae 4c ! REFO2 5 Sika s.tkaq | TOOT soxa TC7106A Vout YN AA Ro S+$Hj Vaer Re As ! Ves 22.00 V ans NC 2 NS 3 3 VIN TEMP va 4 Vout = / / 1.364 @ Vin TEMPERATURE 4 c 50 ka DEPENDENT $ 1.3% Ry 3 COMMON OUTPUT s | GNO vw 4- a 26 AISOILL F2S | Figure 23 Integrated Circuit Temperaturs Sensor 1-1323 1/2 DIGIT A/D CONVERTER | __TOPIN1 TO PIN i SET Vage= 100 mV SET Vagg= 100 mV - REF 40 REF AAA ook | 39 AAA 190 2] 37 100 pF ) Ry i | ae - a | TCTI06A TCT107A 30 | | 2 250 I 28 T t . 249 23 O DISPLAY 23 DISPLAY | 22 : 22 : } 21 TO BACKPLANE } 21} -- ------------- 4380 ILL Foe - _ 4350 1LL F27 | j Figure 24. TC7106A Using the Internal Reference. ..> Figure 25 TC7107A Internal Reference (200 mV Full-Scale, (200 mV Full-Seale, 3 RPS). 3 APS, Vix Tied to GNO for Single Ended Inputs). __ | | ye ; <7 7 a TO PIN 1 | q sl aaa" SET Vpge = 1 y 5 cE ae r 100 kK TO on : LoGic } 3a [+ ! Yeo To 377 100 pF i LoGic : GNO 36 D}-_, 24kQ i 4 95 S}p- VW: 34 Tr, | yr] 252 i TCT7106A nw BES 1maQ | C fr 32 pF ot i TC7106A no 0.01 pF JN : 3G Fp = TC7TIOTA 0.047 uA = : om OE Ov a : ies | ; Be a7 Praag ae _ | aa 25 O_O : cE oT ( C] 20 21 x B ? eosezs c{ 3 TO O1SPLAY OA 74010 _. 22 CO4077 OMA = OVERRANGE 2 UMA = UNOERRANGE i , 4380 LL F28 4380 UL 22% Figure 26 Circuit for Developing Underrange and Overrange Figure 27. TC7106A/TCT107A: Recommended Component Signals fram TC7106A4 Outputs. Values for 2.00 V Full-Scale 13 1/2 DIGIT A/D CONVERTER TC7106/7106A TC7107/7107A a OPIN A _. TOPINI 40 : AAA look go 100k) ser Vacs 100 mv 3a a7 100 pF a 19kQ 10k Moun 10s 38 y" 35 vy" | AT Tco04 x 1 uF) arTcos f 1.2 + ~ 32 or 2V * ae. Pt 0 sr 31 = O01 HF. IMA IN Tc7T107A 3" 0.01 Powe MMM 1MQ IN TC7107A 30}} ae 39 oa oF eee : = bare 27 EF ona pg - 27 | oa ye SET Vage= 100 m 3H oN - 24 2a 23 TO OISPLAY 23 TO DISPLAY 22 22 ) 21 ) 21 [re omy 4350 ILL F380 4350 ILL Fit Figure 28 TC7107A With a 1.2 V External Band-Gap Reference. Figure 29 TC7107A Operated from Single +5 V Supply An (Win Tied to Common.) External Reference Must Be Used in This Application, : i 1.138