83336-21 - PEREGRINE SEMICONDUCTOR

Page 1 of 12

Peregrine’s PE83336 is a high performance integer-N PLL

capable of frequency synthesis up to 3.0 GHz. The superior

phase noise performance of the PE83336 makes it ideal for

rugged military environments including: radio handsets,

radar, avionics, missiles, etc.

The PE83336 features a 10/11 dual modulus prescaler,

counters and a phase comparator as shown in Figure 1.

Counter values are programmable through either a serial or

parallel interface and can also be directly hard wired.

The PE83336 Phase Locked-Loop is optimized for stringent

military environments. It is manufactured on Peregrine’s

UltraCMOS® process, a patented variation of silicon-on-

insulator (SOI) technology on a sapphire substrate, offering

the performance of GaAs with the economy and integration

of conventional CMOS.

Product Specification

3000 MHz UltraCMOS® Integer-N PLL

For Low Phase Noise Applications

Military Operating Temperature Range

Product Description

PE83336

Features

 3.0 GHz operation

 ÷10/11 dual modulus prescaler

 Internal phase detector

 Serial, parallel or hardwired

programmable

 Ultra-low phase noise

 Available in 44-lead CQFJ

Figure 1. Block Diagram

F

in

F

in

Prescaler

10 / 11

20

Main

Counter

20

Secon-

dary

20-bit

Latch

20

Primary

20-bit

Latch

Pre_en

M(6:0)

A(3:0)

R(3:0)

16

20

R Counter

f

r

Phase

Detector

66

f

c

f

p

8

D(7:0)

13

Sdata PD_U

PD_D

Product Specification

PE83336

Page 2 of 12

Table 1. Pin Descriptions

Figure 2. Pin Configuration (Top View)

44-lead CQFJ

11

12

13

14

15

16

17

10

9

8

7

6 5 4 3 2 1 44 43 42 41 40

35

34

33

32

31

30

29

36

37

38

39

18 19 20 21 22 23 24 25 26 27 28

D

0

, M

0

D

1

, M

1

D

2

, M

2

D

3

, M

3

V

DD

V

DD

S_WR, D

4

, M

4

Sdata, D

5

, M

5

Sclk, D

6

, M

6

FSELS, D

7

, Pre_en

GND GND

f

p

V

DD

_f

p

D

out

V

DD

C

ext

V

DD

PD_D

PD_U

V

DD

_f

c

f

c

F

in

F

in

Hop_WR

A_WR

M1_WR

V

DD

Bmode

Smode, A

3

M2_WR, A

2

E_WR, A

1

FSELP, A

0

GND

R

3

R

2

R

1

R

0

V

DD

Enh

LD

fr

GND

Figure 3. Package Photo

Pin No.

(44-lead

CQFJ)

Name

Interface

Mode Type Description

1 VDD ALL (Note 1) Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended.

2 R0 Direct Input R Counter bit0 (LSB).

3 R1 Direct Input R Counter bit1.

4 R2 Direct Input R Counter bit2.

5 R3 Direct Input R Counter bit3.

6 GND ALL (Note 1) Ground.

7 D0 Parallel Input Parallel data bus bit0 (LSB).

M0 Direct Input M Counter bit0 (LSB).

8 D1 Parallel Input Parallel data bus bit1.

M1 Direct Input M Counter bit1.

9 D2 Parallel Input Parallel data bus bit2.

M2 Direct Input M Counter bit2.

10 D3 Parallel Input Parallel data bus bit3.

M3 Direct Input M Counter bit3.

11 VDD ALL (Note 1) Same as pin 1.

12 VDD ALL (Note 1) Same as pin 1.

13

S_WR Serial Input Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register

data are transferred to the secondary register on S_WR or Hop_WR rising edge.

D4 Parallel Input Parallel data bus bit4

M4 Direct Input M Counter bit4

Product Specification

PE83336

Page 3 of 12

Table 1. Pin Descriptions (continued)

Pin No.

(44-lead

CQFJ)

Name

Interface

Mode Type Description

14

Sdata Serial Input Binary serial data input. Input data entered MSB first.

D5 Parallel Input Parallel data bus bit5.

M5 Direct Input M Counter bit5.

15

Sclk Serial Input Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the

8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.

D6 Parallel Input Parallel data bus bit6.

M6 Direct Input M Counter bit6.

16

FSELS Serial Input Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for

programming of internal counters while in Serial Interface Mode.

D7 Parallel Input Parallel data bus bit7 (MSB).

Pre_en Direct Input Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.

17 GND ALL Ground.

18

FSELP Parallel Input Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for

programming of internal counters while in Parallel Interface Mode.

A0 Direct Input A Counter bit0 (LSB).

19

E_WR

Serial Input Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into

the enhancement register on the rising edge of Sclk.

Parallel Input Enhancement register write. D[7:0] are latched into the enhancement register on the rising

edge of E_WR.

A1 Direct Input A Counter bit1.

20

M2_WR Parallel Input M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of

M2_WR.

A2 Direct Input A Counter bit2.

21

Smode Serial,

Parallel Input Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode (Bmode=0,

Smode=0).

A3 Direct Input A Counter bit3 (MSB).

22 Bmode ALL Input Selects direct interface mode (Bmode=1).

23 VDD ALL (Note 1) Same as pin 1.

24 M1_WR Parallel Input M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of

M1_WR.

25 A_WR Parallel Input A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of

A_WR.

26 Hop_WR Serial,

Parallel Input Hop write. The contents of the primary register are latched into the secondary register on the

rising edge of Hop_WR.

27 Fin ALL Input Prescaler input from the VCO. 3.0 GHz max frequency.

28 Fin ALL Input Prescaler complementary input. A bypass capacitor should be placed as close as possible to

this pin and be connected in series with a 50 Ω resistor directly to the ground plane.

29 GND ALL Ground.

Product Specification

PE83336

Page 4 of 12

Table 1. Pin Descriptions (continued)

Note 1: All VDD pins are connected by diodes and must be supplied with the same positive voltage level.

V

DD-fp and VDD-fp are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp and

fc outputs.

Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.

30 fp ALL Output Monitor pin for main divider output. Switching activity can be disabled through enhancement

register programming or by floating or grounding VDD pin 31.

31 VDD-fp ALL (Note 1) VDD for fp. Can be left floating or connected to GND to disable the fp output.

32 Dout Serial,

Parallel Output Data Out. The MSEL signal and the raw prescaler output are available on Dout through

enhancement register programming.

33 VDD ALL (Note 1) Same as pin 1.

34 Cext ALL Output

Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor.

Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier

used for driving LD.

35 VDD ALL (Note 1) Same as pin 1.

36 PD_D ALL Output PD_D is pulse down when fp leads fc.

37 PD_U ALL PD_U is pulse down when fc leads fp.

38 VDD-fc ALL (Note 1) VDD for fc can be left floating or connected to GND to disable the fc output.

39 fc ALL Output Monitor pin for reference divider output. Switching activity can be disabled through

enhancement register programming or by floating or grounding VDD pin 38.

40 GND ALL Ground.

41 GND ALL Ground.

42 fr ALL Input Reference frequency input.

43 LD ALL Output Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high

impedance, otherwise LD is a logic low (“0”).

44 Enh Serial,

Parallel Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional.

N/A NC ALL No connection.

Pin No.

(44-lead

CQFJ)

Name

Interface

Mode Type Description

Product Specification

PE83336

Page 5 of 12

Table 2. Absolute Maximum Ratings

Note 1: Periodically sampled, not 100% tested. Tested per MIL-

STD-883, M3015 C2

Table 4. ESD Ratings

Electrostatic Discharge (ESD) Precautions

When handling this UltraCMOS® device, observe

the same precautions that you would use with

other ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the specified rating in Table 4.

Latch-Up Avoidance

Unlike conventional CMOS devices, UltraCMOS®

devices are immune to latch-up.

Table 3. Operating Ratings

Table 5. DC Characteristics: VDD = 3.0 V, -55° C ≤ TA ≤ 125° C, unless otherwise specified

Symbol Parameter/Conditions Min Max Units

VDD Supply voltage -0.3 4.0 V

VI Voltage on any input -0.3 VDD

+ 0.3 V

II DC into any input -10 +10 mA

IO DC into any output -10 +10 mA

Tstg Storage temperature

range -65 150 °C

Symbol Parameter/Conditions Min Max Units

VDD Supply voltage 2.85 3.15 V

TA Operating ambient

temperature range -55 125 °C

Symbol Parameter/Conditions Level Units

VESD ESD voltage (Human Body

Model) 1000 V

Symbol Parameter Conditions Min Typ Max Units

IDD

Operational supply current;

Prescaler disabled

Prescaler enabled

VDD = 2.85 to 3.15 V

10

20

28

mA

Digital Inputs: All except fr, R0, Fin, Fin

VIH High level input voltage VDD = 2.85 to 3.15 V 0.7 x VDD V

VIL Low level input voltage VDD = 2.85 to 3.15 V 0.3 x VDD V

IIH High level input current VIH = VDD = 3.15 V +70 µA

IIL Low level input current VIL = 0, VDD = 3.15 V -1 µA

Reference Divider input: fr

IIHR High level input current VIH = VDD = 3.15 V +100 µA

IILR Low level input current VIL = 0, VDD = 3.15 V -100 µA

R0 Input (Pull-up Resistor): R0

IIHRO High level input current VIH = VDD = 3.15 V +70 µA

IILRO Low level input current VIL = 0, VDD = 3.15 V -5 µA

Counter and phase detector outputs: fc, fp, PD_D, PD_U

VOLD Output voltage LOW Iout = 6mA 0.4 V

VOHD Output voltage HIGH Iout = -3mA VDD - 0.4 V

Lock detect outputs: Cext, LD

VOLC Output voltage LOW, Cext Iout = 100µA 0.4 V

VOHC Output voltage HIGH, Cext Iout = -100µA VDD - 0.4 V

VOLLD Output voltage LOW, LD Iout = 6mA 0.4 V

Product Specification

PE83336

Page 6 of 12

Table 6. AC Characteristics: VDD = 3.0 V, -55° C ≤ TA ≤ 125° C, unless otherwise specified

Note 1: Parameter is guaranteed through characterization only and is not tested.

Note 2: Running at low frequencies (< 10 MHz sinewave), the device will still be functional but may cause phase noise degradation. Inserting a low-

noise amplifier to square up the edges is recommended at lower input frequencies.

Note 3: CMOS logic levels may be used if DC coupled. For optimum phase noise performance, the reference input falling edge rate should be faster

than 80mV/ns.

Note 4: All devices are screened to phase noise limits listed in Table 7. The magnitude of the tester uncertainty precludes testing phase noise as

part of qualification testing. These parameters are also exempt from PDA requirements.

Note 5: Parameter is tested using 100pF load capacitance and is guaranteed through characterization only. Typical test delay is 12nS.

Symbol Parameter Conditions Min Typ Max Units

Control Interface and Latches (see Figures 4, 5, 6)

fClk Serial data clock frequency 10 MHz

tClkH Serial clock HIGH time 30 ns

tClkL Serial clock LOW time 30 ns

tDSU Sdata set-up time after Sclk rising edge, D[7:0] set-up

time to M1_WR, M2_WR, A_WR, E_WR rising edge 10 ns

tDHLD Sdata hold time after Sclk rising edge, D[7:0] hold time to

M1_WR, M2_WR, A_WR, E_WR rising edge 10 ns

tPW S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width 30 ns

tCWR Sclk rising edge to S_WR rising edge. S_WR, M1_WR,

M2_WR, A_WR falling edge to Hop_WR rising edge 30 ns

tCE Sclk falling edge to E_WR transition 30 ns

tWRC S_WR falling edge to Sclk rising edge. Hop_WR falling

edge to S_WR, M1_WR, M2_WR, A_WR rising edge 30 ns

tEC E_WR transition to Sclk rising edge 30 ns

tMDO MSEL data out delay after Fin rising edge CL = 12 pf 8 (Note 5) ns

Main Divider (Including Prescaler)

Fin Operating frequency 500 3000 MHz

PFin Input level range

External AC coupling -5 5 dBm

External AC coupling

85C < TA ≤ 125C 0 5 dBm

Main Divider (Prescaler Bypassed)

Fin Operating frequency 50 300 MHz

PFin Input level range

External AC coupling -5 5 dBm

External AC coupling

85C < TA ≤ 125C 0 5 dBm

Reference Divider

fr Operating frequency (Note 1) (Note 2) 100 MHz

Pfr Reference input power Single ended input -2 10 dBm

Vfr Input sensitivity External AC coupling

(Note 3) 0.5 VP-P

Phase Detector

fc Comparison frequency (Note 1) 20 MHz

SSB Phase Noise : Output Referred (Fin = 1918MHz, fr = 10 MHz, fc = 1MHz, LBW = 70 kHz)

PNOR Output Referred Phase Noise 100 Hz Offset:

VDD = 3.0V, T = 25°C -78 (Note 4) dBc/Hz

PNOR Output Referred Phase Noise 1000 Hz Offset:

VDD = 3.0V, T = 25°C -84 (Note 4) dBc/Hz

PNOR Output Referred Phase Noise 10000 Hz Offset:

VDD = 3.0V, T = 25°C -87 (Note 4) dBc/Hz

Product Specification

PE83336

Page 7 of 12

Functional Description

The PE83336 consists of a prescaler, counters, a

phase detector and control logic. The dual

modulus prescaler divides the VCO frequency by

either 10 or 11, depending on the value of the

modulus select. Counters “R” and “M” divide the

reference and prescaler output, respectively, by

integer values stored in a 20-bit register. An

additional counter (“A”) is used in the modulus

select logic. The phase-frequency detector

generates up and down frequency control signals.

The control logic includes a selectable chip

interface. Data can be written via serial bus,

parallel bus, or hardwired direct to the pins. There

are also various operational and test modes and

lock detect.

Figure 4. Functional Block Diagram

Control

Logic

R Counter

(6-bit)

Phase

Detector

f

c

PD_U

PD_D

R(5:0)

M(8:0)

A

(3:0)

D(7:0)

Sdata

Control

Pins

f

r

Modulus

Select

10/11

Prescaler

M Counter

(9-bit)

2k



Cext

f

p

F

in

F

in

Product Specification

PE83336

Page 8 of 12

Main Counter Chain

The main counter chain divides the RF input

frequency, Fin, by an integer derived from the user

defined values in the “M” and “A” counters. It is

composed of the 10/11 dual modulus prescaler,

modulus select logic, and 9-bit M counter. Setting

Pre_en “low” enables the 10/11 prescaler. Setting

Pre_en “high” allows Fin to bypass the prescaler

and powers down the prescaler.

The output from the main counter chain, fp, is

related to the VCO frequency, Fin, by the following

equation:

fp = Fin / [10 x (M + 1) + A] (1)

where A



M + 1, 1



M



511

When the loop is locked, Fin is related to the

reference frequency, fr, by the following equation:

Fin = [10 x (M + 1) + A] x (fr / (R+1)) (2)

where A



M + 1, 1



M



511

A consequence of the upper limit on A is that Fin

must be greater than or equal to 90 x (fr / (R+1)) to

obtain contiguous channels. Programming the M

Counter with the minimum value of “1” will result in

a minimum M Counter divide ratio of “2”.

When the prescaler is bypassed, the equation

becomes:

Fin = (M + 1) x (fr / (R+1)) (3)

where 1



M



511

In Direct Interface Mode, main counter inputs M7

and M8 are internally forced low.

Reference Counter

The reference counter chain divides the reference

frequency, fr, down to the phase detector

comparison frequency, fc.

The output frequency of the 6-bit R Counter is

related to the reference frequency by the following

equation:

fc = fr / (R + 1) (4)

where 0



R



63

Note that programming R equal to “0” will pass the

reference frequency, fr, directly to the phase

detector.

In Direct Interface Mode, R Counter inputs R4 and

R5 are internally forced low (“0”).

Register Programming

Parallel Interface Mode

Parallel Interface Mode is selected by setting the

Bmode input “low” and the Smode input “low”.

Parallel input data, D[7:0], are latched in a

parallel fashion into one of three, 8-bit primary

register sections on the rising edge of M1_WR,

M2_WR, or A_WR per the mapping shown in

Table 7 on page 9. The contents of the primary

register are transferred into a secondary register

on the rising edge of Hop_WR according to the

timing diagram shown in Figure 5. Data are

transferred to the counters as shown in Table 7

on page 9.

The secondary register acts as a buffer to allow

rapid changes to the VCO frequency. This

double buffering for “ping-pong” counter control

is programmed via the FSELP input. When

FSELP is “high”, the primary register contents

set the counter inputs. When FSELP is “low”, the

secondary register contents are utilized.

Parallel input data, D[7:0], are latched into the

enhancement register on the rising edge of

E_WR according to the timing diagram shown in

Figure 5. This data provides control bits as

shown in Table 8 on page 9 with bit functionality

enabled by asserting the Enh input “low”.

Serial Interface Mode

Serial Interface Mode is selected by setting the

Bmode input “low” and the Smode input “high”.

While the E_WR input is “low” and the S_WR

input is “low”, serial input data (Sdata input), B0

to B19, are clocked serially into the primary

register on the rising edge of Sclk, MSB (B0)

first. The contents from the primary register are

transferred into the secondary register on the

rising edge of either S_WR or Hop_WR

according to the timing diagram shown in

Figures 5-6. Data are transferred to the counters

as shown in Table 7 on page 9.

The double buffering provided by the primary

and secondary registers allows for “ping-pong”

counter control using the FSELS input. When

FSELS is “high”, the primary register contents

set the counter inputs. When FSELS is “low”, the

secondary register contents are utilized.

Product Specification

PE83336

Page 9 of 12

While the E_WR input is “high” and the S_WR input

is “low”, serial input data (Sdata input), B0 to B7, are

clocked serially into the enhancement register on

the rising edge of Sclk, MSB (B0) first. The

enhancement register is double buffered to prevent

inadvertent control changes during serial loading,

with buffer capture of the serially entered data

performed on the falling edge of E_WR according to

the timing diagram shown in Figure 6. After the

falling edge of E_WR, the data provide control bits

as shown in Table 8 with bit functionality enabled by

asserting the Enh input “low”.

Direct Interface Mode

Direct Interface Mode is selected by setting the

Bmode input “high”.

Counter control bits are set directly at the pins as

shown in Table 8. In Direct Interface Mode, main

counter inputs M7 and M8, and R Counter inputs

R4 and R5 are internally forced low (“0”).

MSB (first in) (last in) LSB

Table 7. Primary Register Programming

Table 8. Enhancement Register Programming

*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.

*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

MSB (first in) (last in) LSB

Interface

Mode Enh Bmode Smode R5 R4 M8 M7 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0

Parallel 1 0 0 M2_WR rising edge load M1_WR rising edge load A_WR rising edge load

D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Serial* 1 0 1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19

Direct 1 1 X 0 0 0 0 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0

Interface

Mode Enh Bmode Smode Reserved Reserved Reserved Power

down Counter

load MSEL

output Prescaler

output fc, fp OE

Parallel 0 X 0 E_WR rising edge load

D7 D6 D5 D4 D3 D2 D1 D0

Serial* 0 X 1 B0 B1 B2 B3 B4 B5 B6 B7

Product Specification

PE83336

Page 10 of 12

Figure 6. Serial Interface Mode Timing Diagram

Figure 5. Parallel Interface Mode Timing Diagram

tDHLD

tDSU

t

PW

t

CWR

t

WRC

tPW

D

M1_W R

M2_W R

A_WR

E_WR

Hop_WR



0:7

tDHLD

tDSU tClkH tClkL tCW R tPW tWRC

tEC tCE

E_WR

Sdata

Sclk

S_WR

Product Specification

PE83336

Page 11 of 12

PD_U and PD_D drive an active loop filter which

controls the VCO tune voltage. PD_U pulses

result in an increase in VCO frequency; PD_D

pulses result in a decrease in VCO frequency (for

a positive Kv VCO).

A lock detect output, LD is also provided, via the

pin Cext. Cext is the logical “NAND” of PD_U and

PD_D waveforms, which is driven through a series

2 kΩ resistor. Connecting Cext to an external

shunt capacitor provides low pass filtering of this

signal. Cext also drives the input of an internal

inverting comparator with an open drain output.

Thus LD is an “AND” function of PD_U and PD_D.

Enhancement Register

The functions of the enhancement register bits are shown below with all bits active “high”.

Table 9. Enhancement Register Bit Functionality

** Program to 0

Phase Detector

The phase detector is triggered by rising edges

from the main Counter (fp) and the reference

counter (fc). It has two outputs, PD_U, and PD_D.

If the divided VCO leads the divided reference in

phase or frequency (fp leads fc), PD_D pulses

“low”. If the divided reference leads the divided

VCO in phase or frequency (fc leads fp), PD_U

pulses “low”. The width of either pulse is directly

proportional to phase offset between the two input

signals, fp and fc.

The phase detector gain is equal to 2.7 V / 2 π,

which numerically yields 0.43 V / radian.

Bit Function Description

Bit 0 Reserved**

Bit 1 Reserved**

Bit 2 Reserved**

Bit 3 Power down Power down of all functions except programming interface.

Bit 4 Counter load Immediate and continuous load of counter programming as directed by the Bmode and

Smode inputs.

Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.

Bit 6 Prescaler output Drives the raw internal prescaler output onto the Dout output.

Bit 7 fp, fc OE f

p, fc outputs disabled.

Product Specification

PE83336

Page 12 of 12

Figure 7. Package Drawing

44-lead CQFJ

Table 10. Ordering Information

Order Code Part Marking Description Package Shipping Method

83336-21 PE83336 Packaged Part 44-lead CQFJ 15 units / Tray

83336-22 PE83336 Packaged Part 44-lead CQFJ 500 units / T&R

83336-00 PE83336EK CQFJ Evaluation Board with Software 44-lead CQFJ 1 / Box

Advance Information:

The product is in a formative or design stage. The datasheet contains design target

specifications for product development. Specifications and features may change in any manner without notice.

Preliminary Specification:

The datasheet contains preliminary data. Additional data may be added at a later

date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best

possible product.

Product Specification:

The datasheet contains final data. In the event Peregrine decides to

change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer

Notification Form).

The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use

of this information. Use shall be entirely at the user’s own risk.

No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.

Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,

or in other applications intended to support or sustain life, or in any application in which the failure of the

Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no

liability for damages, including consequential or incidental damages, arising out of the use of its products in

such applications.

The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE

are trademarks of Peregrine Semiconductor Corp.

Sales Contact and Information

For sales and contact information please visit www.psemi.com.