ANALOG DSP DEVICES Microcomputer Preliminary Technical Data ADSP-2186M FEAT URES Performance . 13.3 ns Instruction Cycle Time @ 2.5 Volts (internal), 75 MIPS Sustained Performance . Single-Cycle Instruction Execution . Single-Cycle Context Switch . 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle - Multifunction Instructions - Powerdown Mode Featuring Low CMOS Standby Power Dissipation with 200 CLKIN Cycle Recovery from Powerdown Condition Low Power Dissipation in Idle Mode Integration ADSP-2100 Family Code Compatible (easy to use algeb . 40K Bytes of On-Chip RAM, Configured as 8K We On-Chip Data Memory RAM . Dual Purpose Program Memory for Both Ii Independent ALU, Multiplier/Accui ax), with Instruction Set Extensions Program Memory RAM and 8K Words 1 Storage t Computational Units Conditional Instruction Execution 100-Lead LQFP System Interface Flexible I/O structure allows 2.5V or 3.3V operation; all inputs tolerate up to 3.GV regardless of mode - 16-Bit Internal DMA Port for High Speed Access to on-Chip Memory (Mode Selectable) 4 MByte Memory Interface for Storage of Data Tables & Program Overlays (Mode Selectable) - 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable) - I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable) Programmable Memory Strobe & Separate I/O Memory Space Permits Glueless System Design Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering . Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port . Six External Interrupts . 13 Programmable Flag Pins Provide Flexible System Signaling . UART Emulation through Software SPORT Reconfiguration - ICE-Port Emulator Interface Supports Debugging in Final Systems R EV PrA This information applies to a product under development. Its characteristics and One Technology Way hitp:/Awww.analag.com/dsp . specifications are subject to change without notice. Analog Devices assumes no P.O. Box 9106 Tel: 1-800-ANALOG-D obligation regarding future manufacturing unless otherwise agreed to in writing. Norwood MA 02062-9106 Fax: 1-781-461-3010 U.S.A. @Analog Devices Inc., 1999 MH 0816800 0066590 76 mmSeptember 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 General note This data sheet represents preliminary (x- grade) specifications for the ADSP-2186M 2.5V processor. GENERAL DESCRIPTION The ADSP-2186M is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2186M combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. The ADSP-2186M integrates 40K bytes of on-chip memory configured as 8K words (24-bit) of program RAM, and 8K words (16-bit) of data RAM. Power down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-2186M is available in 100-pin LQFP package. In addition, the ADSP-2186M supports new instructions, which include bit manipulationsbit set, bit clear, bit toggle, bit testnew ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory tran id global interrupt masking, for increased flexibility. | ADSP-2186M operates with a 13.3 ns Fabricated in a high speed, low power, CMQ igle processor cycle. instruction cycle time. Every instructio. The ADSP-2186Ms flexible ar perform multiple operatio - Generate the next . Fetch the next instruction - Perform one or two data m .- Update one or two data address pointers - Perform a computational operation This takes place while the processor continues to: - Receive and transmit data through the two serial ports - Receive and/or transmit data through the internal DMA port - Receive and/or transmit data through the byte DMA port . Decrement timer DEVELOPMENT SYSTEM The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, supports the ADSP-2186M. The System Builder provides a high level method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to program and debug. The Linker combines object files into an executable file. The Simulator provides an interactive instruction-level simulation with a reconfigurable user interface to display different portions of the hardware environment. 2? This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 A PROM Splitter generates PROM programmer compatible files. The C Compiler, based on the Free Software Foundations GNU C Compiler, generates ADSP-2186M assembly source code. The source code debugger allows programs to be corrected in the C environment. The Runtime Library includes over 100 ANSI-standard mathematical and DSP-specific functions. The EZ-KIT Lite is a hardware/software kit offering a complete development environment for the entire ADSP-21xx family: an ADSP-218x based evaluation board with PC monitor software plus Assembler, Linker, Simulator, and PROM Splitter software. The ADSP-218x EZ-KIT Lite is a low cost, easy to use hardware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features: 33 MHz ADSP-218x - Full 16-bit Stereo Audio I/O with AD1847 SoundPort Codec - RS-232 Interface to PC with Windows 3.1 Control Software EZ-ICE Connector for Emulator Control - DSP Demo Programs The ADSP-218x EZ-ICE Emulator aids in the hardware debugging of an ADSP-2186M system. The emulator consists of hardware, host computer resident software, andthe target board connector. The ADSP-2186M integrates on-chip emulation support with a1 CE-Port interface. This interface provides a simpler target board connection that requires hanical clearance considerations than other ADSP-2100 Family EZ-ICEs. The ADSP-2186 need. not be removed from the target system when using the EZ-ICE, nor are any adapt small footprint of the EZ-ICE . In-target operation - Up to 20 breakpoints - Single-step or full-speed operation: : - Registers and memory values can be examined and altered PC upload and download functions . Instruction-level emulation of program booting and execution - Complete assembly and disassembly of instructions - Csource-level debugging See Designing An EZ-ICE-Compatible Target System in the ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as well as the Designing an EZ-ICE compatible System section of this data sheet for the exact specifications of the EZ-ICE target board connector. Additional Information This data sheet provides a general overview of ADSP-2186M functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-2100 Family Users Manual. For more information about the development tools, refer to the ADSP-2100 Family Development Tools Data Sheet. R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 3 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 ARCHITECTURE OVERVIEW The ADSP-2186M instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-2186M assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. POWERDOWN CONTROL (i MEMORY FULL MEMORY MODE Fs | DATA ADDRESS Program Memory Data Memory PROGRAMMABLE | EXTERNAL | GENERATORS PROGRAM 1/0 || ADDRESS |i > [oaci][bace] SEQUENCER 8K x 24-bit 8K x 16-bit and BUS FLAGS 4 EXTERNAL { , DATA |< [ PROGRAM MEMORY ADDRESS BUS | || L | ! | q | | | DATA MEMORY ADDRESS BYTE DMA | L | | J | | CONTROLLER |! I PROGRAM MEM ORY DATA (a hoy [sy h OR | DATA MEMORY DATA A LO | | | EXTERNAL | \ v4 DATA |qg@1+- > | ARITHMETIC UNITS SERIAL PORTS TIMER ! BUS ! ] DMA |-<#__ | | ADSP-2100 BASE OL ror Jo ARCHITECTURE HOST MODE . BLOCK DIAGRAM Figure 1 is an overall block diagram of the ADSP-2186M. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control including multi-word and block floating-point representations. The internal result (R) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop counters and loop stacks, the ADSP-2186M executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one 4 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. Efficient data transfer is achieved with the use of five internal buses: .- Program Memory Address (PMA) Bus . Program Memory Data (PMD) Bus - Data Memory Address (DMA) Bus - Data Memory Data (DMD) Bus . Result (R) Bus The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permitting the ADSP-2186M to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSP-2186M can fetch an operand from program memory and the next instruction in the same cycle. the ADSP-2186M may be external systems. The IDMA port A port provides transparent, direct In lieu of the address and data bus for external memory connectio configured for 16-bit Internal DMA port IDMA port) conn: is made up of 16 data/address pins and five control pin access to the DSPs on-chip program and data RAM A port (BDMA port). The An interface to low cost byte-wide memory i ted egabytes of external RAM or ROM BDMA port is bidirectional and can direetly for off-chip storage of program o The byte memory and I/O me! peripherals with programmable wait buses with bus request/grant signals:(E ADSP-2186M to continue running fro processor to halt while buses are granted. ne execution mode (Go Mode) allows the y. Normal execution mode requires the The ADSP-2186M can respond to eleven interrupts. There can be up to six external interrupts (one edge-sensitive, two level-sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port, and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock. The ADSP-2186M provides up to 13 general-purpose flag pins. The data input and output pins on SPORT 1 can be alternatively configured as an input flag and an output flag. In addition, there are eight flags that are programmable as inputs or outputs, and three flags that are always outputs. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) decrements every n processor cycles, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 5 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 Serial Ports The ADSP-2186M incorporates two complete synchronous serial ports (SPORTO and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2186M SPORTs. For additional information on Serial Ports, refer to the ADSP-2100 Family Users Manual. - SPORTs are bidirectional and have a separate, double-buffered transmit and receive section. - SPORTs can use an external serial clock or generate their own serial clock internally. SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulse widths and timings. - SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and u-law companding according to CCITT recommendation G.711. - SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. - SPORTs can receive and transmit an entire circular buffe data word. An interrupt is generated after a data buffer SPORTO has a multichannel interface to selec 1 division multiplexed, serial bitstream. - SPORT1 can be configured to have.tw Flag Out signals. The internal i { data with only one overhead cycle per ve and transmit a 24 or 32 word, time- RQO and IRQ1) and the Flag In and nay still be used in this configuration. Pin Descriptions The ADSP-2186M will be avail QEP package. In order to maintain maximum functionality and reduce packs : t;some serial port, pro grammable flag, interrupt and external bus pins have dual, mu iplexed funetionality. The external bus pins are configured during RESET only, while serial port pins are softwafe configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics. Common Mode Pins Pin Name(s) #of | I/O | Function Pins RESET 1 I Processor Reset Input BR 1 I Bus Request Input BG 1 O Bus Grant Output BGH 1 O Bus Grant Hung Output DMS 1 O Data Memory Select Output PMS 1 O Program Memory Select Output IOMS 1 O Memory Select Output 6 This information applies to a product under development. Its characteristics and specifications are subject to change with = REV Prf out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.ADSP-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 Common Mode Pins (Continued) Pin Name(s) #of | I/O | Function Pins BMS 1 O Byte Memory Select Output CMS 1 O Combined Memory Select Output RD 1 O Memory Read Enable Output WR 1 O Memory Write Enable Output IRQ2 1 I Edge- or Level-Sensitive Interrupt Request! PF7 I/O | Programmable I/O Pin IRQLO 1 I Level-Sensitive Interrupt Requests! PF6 I/O | Programmable I/O Pin IRQL1 1 I Level-Sensitive Interrupt Requests! PFS I/O | Programmable I/O Pin IRQE 1 I Edge-Sensitive Int PF4 I/O | Programmable Mode D 1 only during RESET PF3 ing normal operation Mode C 1 d only during RESET PF2 normal operation Mode B 1 shecked only during RESET PFI Pin during normal operation Mode A 1 I Mode Select Input - Checked only during RESET PFO I/O | Programmable I/O Pin during normal operation CLKIN 2 I Clock or Quartz Crystal Input XTAL CLKOUT 1 O Processor Clock Output SPORTO 5 I/O | Serial Port I/O Pins SPORT 1 5 I/O | Serial Port I/O Pins IRQ1:0, FI, FO Edge- or Level-Sensitive Interrupts, Flag In, Flag Out PWD 1 I Powerdown Control Input PWDACK 1 O Powerdown Control Output FLO, FL1, FL2 3 O Output Flags VpDINT 2 I Internal VDD (2.5V) Power R EV . P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 7 out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 Common Mode Pins (Continued) Pin Name(s) #of | I/O | Function Pins VpDEXT 4 I External VDD (2.5V or 3.3V) Power GND 10 I Ground EZ-Port 9 I/O | For emulation use 1. Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag. 2. SPORT configuration determined by the DSP System Control Register. Software configurable Memory Interface Pins The ADSP-2186M processor can be used in one of two modes, Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. Fhe operating mode is determined by the state of the Mode C pin during RESET and cannot be:ehanged while the processor is running. Full Memory Mode Pins (Mode C = 0) | Pin Name #of | I/O Pins A13:0 D23:0 ins for Program, Data, Byte and I/O Spaces rim, Data, Byte and I/O Spaces (8 MSBs e Memory addresses) Host Mode Pins (Mode C = 1) Pin Name #of | I/O | Function Pins IAD15:0 16 I/O | IDMA Port Address/Data Bus AO 1 O Address Pin for External I/O, Program, Data, or Byte access! D23:8 16 I/O | Data I/O Pins for Program, Data Byte and I/O spaces IWR 1 I IDMA Write Enable IRD 1 I IDMA Read Enable TAL 1 I IDMA Address Latch Pin 1S 1 I IDMA Select IACK 1 O IDMA Port Acknowledge Configurable in Mode D; Open Drain 1. In Host Mode, external peripheral addresses can be decoded using the AO, CMS, PMS, DMS, and IOMS signals 8 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 Interrupts The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. The ADSP-2186M provides four dedicated external interrupt input pins, IRQ2, IRQLO, IRQL1, and IRQE (shared with the PF7:4 pins). In addition, SPORT1 may be reconfigured for IRQO, IRQ1, FLAG_IN and FLAG_OUT, for a total of six external interrupts. The ADSP-2186M also supports internal interrupts from the timer, the byte DMA port, the two serial ports, software, and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable (except power down and reset). The IRQ2, IRQO, and IRQ1 input pins can be programmed to be either level- or edge-sensitive. IRQLO and IRQL] are level-sensitive and IRQE is edge sensitive. The priorities and vector addresses of all interrupts are shown in Table 1. Table 1 Interrupt Priority & Interrupt Vector Addresses Source Of Interrupt Interrupt Vector Address (Hex) Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority) Power Down (Nonmaskable) 002C IRQ2 IRQLI IRQLO SPORTO Transmit SPORTO Receive IRQE BDMA Interrupt SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQO 0024 Timer 0028 (Lowest Priority) Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable. The ADSP-2186M masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers. The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQO, IRQ], and IRQ2 external interrupts to be either edge- or level-sensitive. The IRQE pin is an external edge sensitive interrupt and can be forced and cleared. The IRQLO and IRQL1 pins are external level sensitive interrupts. The IFC register is a write-only register used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are twelve levels deep to allow interrupt, loop, and subroutine nesting. The following instructions allow global R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 9 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 enable or disable servicing of the interrupts (including power down), regardless of the state of IMASK. Disabling the interrupts does not affect serial port autobuffering or DMA. ENA INTS; DIS INTS; When the processor is reset, interrupt servicing is enabled. LOW POWER OPERATION The ADSP-2186M has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are: . Power Down . Idle . slow Idle The CLKOUT pin may also be disabled to reduce external power dissipation. Power Down The ADSP-2186M processor has a low power featur dormant state through hardware or software contr to the ADSP-2100 Family Users Manual, SY the power-down feature. the processor enter a very low power a brief list of power-down features. Refer cechapter, for detailed information about Quick recovery from power dow. S executing instructions in as few as 200 CLKIN cycles. - Support for an ext t essor clock. The external clock can contin- ue running during power do " a owest power rating and 200 CLKIN cycle recovery. - support for crystal operation includes disabling the oscillator to save power (the processor automat- ically waits approximately 4096 CLKIN cycles for the crystal oscillator to start or stabilize), and let- ting the oscillator run to allow 200 CLKIN cycle start up. - Power down is initiated by either the power down pin (PWD) or the software power-down force bit.Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The power down interrupt also can be used as a non-maskable, edge sensitive in- terrupt. - Context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power down state. The RESET pin also can be used to terminate power down. - Power down acknowledge pin indicates when the processor has entered power down. Idle When the ADSP-2186M is in the Idle Mode, the processor waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA and autobuffer cycle steals still occur. 1 0 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 Slow Idle The IDLE instruction is enhanced on the ADSP-2186M to let the processors internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction. The format of the instruction is: IDLE (n); where n = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While it is in this state, the processors other internal clock signals, such as SCLK, CLKOUT, and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction. When the IDLE (n) instruction is used, it effectively slows down the processors internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-2186M will remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming normal operation. When the IDLE (n) instruction is used in systems that have an the serial clock rate may be faster than the processors redued conditions, interrupts must not be generated at a fas time the processor takes to come out of the idle stat senaily generated serial clock (SCLK), nal clock rate. Under these be serviced, due to the additional processor cycles). SYSTEM INTERFACE Figure 2 shows typical basic s the ADSP-2186M, two serial devices, a byte- emories (mode selectable). nect easily to slow peripheral devices. and one serial port. Host Memory Mode allows aceess to the full external data bus, but limits addres0OOsing to a single address bit (AO). Additional system peripherals can be added in this mode through the use of external hardware to generate and latch address signals. R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 1 1 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 Clock Signals FULL MEMORY MODE HOST MEMORY MODE ADSP-2186M NA ADSP-2186M 1/2x CLOCK CLKIN f 1/2x CLOCK CLKIN OR OR CRYSTAL XTAL 14 Aisa CRYSTAL XTAL ADDR13-0 [TZ | 1 <>] FL0-2 Das-16 [py A0-A21 +>] FL0-2 AO wae R02 pF 2 Piss EMOF ROZ 7 /- d MEMORY Re /PF7 opatazs-8 oo DATA23-0 KZ DATA ~<t] |ROE /PF4 by +] /ROE /PF4 +] |ROLO/PF5 one cS <> ]|RQLO/PF5 BMS BMS = cs BMs - +7 1RQL1 /PFS + ]/ROL1 /PFe wRe Ato-o wR | MODE D/PF3 a _| ADDR MODE D/PF3 wa RDB To <]}] MODE C/ et >| MODE cipF2 D pre RD 236 VO SPACE p MODE A/PFO DATA MODE A/PFO r| MODE B/PF1 (PERIPHERALS) +] MODE B/PFi cs 2048 LOCATIONS -_- Aiso SERIAL SERIAL DEVICE | A0PF OVERLAY DEVICE ee ata MEMORY TWO 8K PM SEGMENTS TWO 8K SERIAL SERIAL DM SEGMENTS DEVICE DEVICE SYSTEM INTERFACE OR WG ONT ROLLER The ADSP-2186M can t clocked: The CLKIN input cannot be halted;:chan lurifig operation, or operated below the specified frequency during normal operation. The only.exception is while the processor is in the power down state. For additional information, refer to Chapter 9, ADSP-2100 Family Users Manual for detailed information on this power down feature. If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the processors CLKIN input. When an external clock is used, the XTAL input must be left unconnected. The ADSP-2186M uses an input clock with a frequency equal to half the instruction rate; a 37.50 MHz input clock yields a 13 ns processor cycle (which is equivalent to 75 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled. Because the ADSP-2186M includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. 1 2? This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 A clock output (CLKOUT) signal is generated by the processor at the processors cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORTO Autobuffer Control Register. rH Figure 3 External Crystal Connections Reset The RESET signal initiates a master reset of the ADSP-2186M. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power up, the clock continues to run and does not require stabilization time The power-up sequence is defined as the total time required. after a valid Vpp is applied tc to the processor, and for the crystal oscillator circuit to stabilize hase- locked loop (PLL) to lock onto es that the PLL has locked but specification, tesp- The RESET input contains sq clears the MSTAT register. When RESET i is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes. Power Supplies The ADSP-2186M has separate power supply connections for the internal (Vpp nr) and external (VppExT) power supplies. The internal supply must meet the 2.5V requirement. The external supply can be connected to either a 2.5V or 3.3V supply. All external supply pins must be connected to the same supply. All input and I/O pins can tolerate input voltages up to 3.6V regardless of the external supply voltage. This feature provides maximum flexibility in mixing 2.5V and 3.3 volt components. R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 1 3 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 MODES OF OPERATION Setting Memory Mode Memory Mode selection for the ADSP-2186M is made during chip reset through the use of the Mode C pin. This pin is multiplexed with the DSPs PF2 pin, so care must be taken in how the mode selection is made. The two methods for selecting the value of Mode C are active and passive. Passive configuration involves the use a pull-up or pull-down resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as an output in the DSP application, a weak pull-up or pull-down, on the order of 40 kQ, can be used. This value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processors output driver. For minimum power consumption during powerdown, reconfigure PF2 to be an input, as the pull-up or pull-down will hold the pin in a known state, and will not switch. Active configuration involves the use of a three-statable external driver connected to the Mode C pin. A drivers output enable should be connected to the DSPs RESET signal such that it only drives the PF2 pin when RESET is active (low). When RESET is de-asserted, the driver should three-state, thus allowing full use of the PF2 pin as either an input or output minimize power consumption during powerdown, configure the programmable flag as an outp eft connected to a three-stated buffer. This ensures that the pin will be held at a constant:level;:and will not oscillate should the three-state driverslevel hover around the logic switching p: Table 2 ADSP-2186M Modes of O e MODED | MODEC d to load the first 32 program memory words from fe mfhory space. Program execution is held off until all 32 words n. loaded. Chip is configured in Full Memory Mode.! No Automatic boot operations occur. Program execution starts at external memory location 0. Chip is configured in Full Memory Mode. BDMA can still be used but the processor does not automatically use or wait for these operations. 0 1 0 0 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held offuntilall 32 words have been loaded. Chip is configured in Host Mode. [ACK has active pulldown. (REQUIRES ADDITIONAL HARDWARE). O 1 O 1 IDMA feature is used to load any internal memory as desired. Program execution is held off until internal prea location 0 is written to. Chip is configured in Host Mode. [ACK has active pulldown. 1 1 O O BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode; IACK requires external pulldown. (REQUIRES ADDITIONAL HARDWARE) 1 1 O 1 IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to. Chip is configured in Host Mode. IACK requires external pulldown. ! 1. Considered as standard operating settings. Using these configurations allows for easier design and better memory management. 1 4 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 TACK Configuration Mode D = 0 and in host mode: IACK is an active, driven signal and cannot be wire ORd. Mode D = 1 and in host mode: IACK is an open drain and requires an external pulldown, but multiple IACK pins can be wire ORd together. MEMORY ARCHITECTURE The ADSP-2186Mprovides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O. Refer to the following figures and tables for PM and DM memory allocations in the ADSP-2186M. Program Memory Program Memory (Full Memory Mode) is a 24-bit-wide space for storing both instruction opcodes and data. The ADSP-2186M has 8K words of Program Memory RAM on chip, and the capability of accessing up to two 8K external memory overlay spaces using the external data bus. External overlay access is limited not available in host mode due to Program Memory (Host Mode) allows access to all internal memo by a single external address line (AQ). External program e a restricted data bus that is 16-bits wide only. R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 1 5 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 PROGRAM MEMORY PROGRAM MEMORY MODE B=0 ADDRESS MODE B=1 ADDRESS Ox3FFF Ox3FFF 8K EXTERNAL PMOVLAY = 1,2 RESERVED Ox1 FFF Ox1FFF 8K 8K INTERNAL EXTERNAL 0x0000 0x0000 Figure 4 Program Memory Table 3 PMOVLAY bits PMOVLAY A12:0 0 Not Applicable 1 13 LSBs of Address Between 0x2000 and 0x3FFF 2 External Overlay 2 1 13 LSBs of Address Between 0x2000and 0x3FFF Data Memory Data Memory (Full Memory Mode) is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The ADSP-2186M has 8K words on Data Memory RAM on chip. Part of this space is used by 32 memory-mapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus. All internal accesses complete in one cycle. 1 6 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 Accesses to external memory are timed using the wait states specified by the DWAIT register and the waitstate mode bit. DATA MEMORY ADDR 32 MEMORY Ox3FFF MAPPED REGISTERS Ox3FEO Ox3FDF INTERNAL 8160 WORDS 0x2000 Ox1FFF EXTERNAL 8K DMOWLAY = 1,2 O0x0000 Figure 5 Data Mem Data Memory (Host Mode) allows access to all inte: ry. External overlay access is limited by a single external address line (AQ). ss Table 4 DMOVLAY bits DMOVLAY M. A12:0 0 Intertial ; a Not Applicable 1 External Overlay1 13 LSBs of Address Between 0x2000 and0Ox3FFF 2 External Overlay 2 1 13 LSBs of Address Between 0x2000and 0x3FFF Memory Mapped Registers (New to the ADSP-2186M) The ADSP-2186M has three memory mapped registers that differ from other ADSP-21xx Family DSPs. The slight modifications to these registers (Waitstate Control, Programmable Flag & Composite Select Control, and System Control) provide the ADSP-2186Ms waitstate and BMS control features. R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 1 7 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 WAITSTATE CONTROL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TT DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAITO DM(0x3FFE) Wait State Mode Select (ADSP-2186M) 0 = Normal mode (DWAIT, IOWAITO-3 = N wait states, ranging from 0 to 7) 1 = 2N+1 mode (DWAIT, IOWAITO-3 = 2N+1 wait states, ranging from 0 to 15) Figure 6 Waitstate Control Register ADSP-2186M WAITSTATE CONTROL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM(0x3FFE) DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAITO Wait State Mode Select (ADSP-2186M) 0 = Normal mode (DWAIT, IOWAITO-3 = N wait states, ranging from 0 to 7) 2N+1 mode (DWAIT, IOWAITO-3 = 2N+1 wait states, ranging from 0 to 15) a I Figure 7 SYSTEM CONTROL 15 14 13 12 11 #10 9 8 7 6 5 4 3 2 1 0 4 |DM(ox3FFF) 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 NT RESERVED, ALWAYS SPORTO Enable 0 = Disable 1 Enable SET TOO = ena (ADS P-2186M) PWAIT SPORT1 Enable Woe eee 0 = Disable alt stales 1 = Enable SPORT1 Gonfigure 0 = FI, FO, IRQO, IRQ1, SCLK 1= SPORT1 Disable BMS (ADSP-2186M) 0 = Enable BMS 1 = Disable BMS, except when memory strobes are three-stated Figure 8 System Control Register (ADSP-2186M) Note: Reserved bits are shown on a gray field. These bits should always be written with zeros. 1 8 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 I/O Space (Full Memory Mode) The ADSP-2186M supports an additional external memory space called I/O space. This space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers. I/O space supports 2048 locations of 16-bit wide data. The lower eleven bits of the external address bus are used; the upper three bits are undefined. Two instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated three-bit wait state registers, IOWAITO-3, which in combination with the waitstate mode bit, specify up to 15 wait states to be automatically generated for each of four regions. The wait states act on address ranges as shown in Table 5. Table 5 Wait States Address Range Wait State Register 0x000-0x1 FF IOWAITO and Wait State Mode Select bit 0x200-0x3FF IOWAIT1 and W. te Mode Select bit 0x400-O0xSFF State Mode Select bit 0x600-0x7FF Composite Memory Select (CMS) The ADSP-2186M has a program: select signals for memories mappe same timing as each of the ind combine their functionality. Each bit in the CMSSEL register, when set, causes:the CMS signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory, and use either DMS or PMS as the additional address bit. MS signal is generated to have the DMS, BMS, IOMS) but can The CMS pin functions like the other memory select signals with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. All enable bits default to 1 at reset, except the BMS bit. Byte Memory Select (BMS) The ADSP-2186Ms BMS disable feature combined with the CMS pin lets you use multiple memories in the byte memory space. For example, an EPROM could be attached to the BMS select, and an SRAM could be connected to CMS. Because at reset BMS is enabled, the EPROM would be used for booting. After booting, software could disable BMS and set the CMS signal to respond to BMS, enabling the SRAM. Byte Memory The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K x 8. R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 1 9 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 The byte memory space on the ADSP-2186M supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. This allows up to a4 meg x 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register and the waitstate mode bit. Byte Memory DMA (BDMA, Full Memory Mode) The Byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space while the processor is operating normally and steals only one DSP cycle per 8-, 16- or 24-bit word transferred. BDM Control Register The BDMA circuit supports fo : at s which are selected by the BT'YPE register field. The appropriate number of 8-bit accesses ar:done from the byte memory space to build the word size selected. Table 6 shows the data formats supported by the BDMA circuit. Table 6 Data Formats BT YPE Internal Memory Space | Word Size Alignment 00 Program Memory 24 Full Word 01 Data Memory 16 Full Word 10 Data Memory 8 MSBs 11 Data Memory 8 LSBs Unused bits in the 8-bit data memory formats are filled with Os. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register field selects the direction of the transfer. Finally, the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers. 20 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register. The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations. The source or destination of a BDMA transfer will always be on-chip program or data memory. When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses. The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the context of the processor, and start execution at address 0 when the BDMA accesses have completed. The BDMA overlay bits specify the OVLAY memory blocks to be The BMWAIT field, which has 4-bits on ADSP-2186M, transfers. essed for internal memory. ect up to 15 waitstates for BDMA Internal Memory DMA Port (IDMA Po: The IDMA Port provides an efficien 2186M. The port is used to access only one DSP cycle per word.' 1. Host starts IDMA transfer 2. Host checks IACK control line to see if the DSP'is busy 3. Host uses IS and IAL control lines to latch either the DMA starting address (IDMAA) or the PM/ DM OVLAY selection into the DSPs IDMA control registers. If bit 15 = 1, the value of bits 7:0 represent the IDMA overlay: bits 14:8 must be set to 0. If bit 15 = 0, the value of bits 13:0 represent the starting address of internal memory to be accessed and bit 14 reflects PM or DM for access. 4. Host uses IS and IRD (or IWR) to read (or write) DSP internal memory (PM or DM). 5. Host checks IACK line to see if the DSP has completed the previous IDMA operation. 6. Host ends IDMA transfer. The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written while the ADSP-2186M is operating at full speed. The DSP memory address is latched and then is automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access. IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location, the destination type specifies R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 2? 1 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 whether itis a DM or PM access. The falling edge of the IDMA address latch signal (IAL) or the missing edge of the IDMA select signal (IS) latches this value into the IDMAA register. Once the address is stored, data can then be either read from, or written to, the ADSP-2186Ms on- chip memory. Asserting the select line (IS) and the appropriate read or write line IRD and IWR respectively) signals the ADSP-2186M that a particular transaction is required. In either case, there is a one-processor-cycle delay for synchronization. The memory access consumes one additional processor cycle. Once an access has occurred, the latched address is automatically incremented, and another access can occur. Through the IDMAA register, the DSP can also specify the starting address and data format for DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-2186M to write the address onto the [ADO-14 bus into the IDMA Control Register. If bit 15 is set to0, IDMA latches the address. If bit 15 is set to 1, IDMA latches into the OVLAY register. This register, shown below, is memory mapped at address DM (Ox3FEO). Note that the latched address (DMAA) cannot be read back by the host. Refer to the following figures for more information on IDMA and DMA memory maps. Figure 10 IDMA Control/OVLAY Registers 2? This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 DMA DMA PROGRAM MEMORY DATA MEMORY OVLAY OVLAY ALWAYS ALWAYS ACCESSIBLE ACCESSIBLE AT ADDRESS AT ADDRESS O0x0000 - Ox1FFF 0x2000 - Ox3FFF NOTE: IDMA AND BDMA HAVE SEPARATE DMA CONTROL REGISTERS Figure 11 Direct Memory Access-PM and DM Memory Maps Bootstrap Loading (Booting) ding of the internal program memory A, B;.and C configuration bits. The ADSP-2186M has two mechanisms to allow autom, after reset. The method for booting is controlled b When the MODE pins specify BDMA booti when reset is released. The BDMA interface is set up d the BDIR, BMPAGE, BIAD program memory 24 bit words, and chip program memory to be loade to load in the remaining program code: to be held off until all 32 words are loaded into on: address 0. The ADSP-2100 Family development software (Revision 5.02 and later) fully supports the BDMA booting feature and can generate byte memory space compatible boot code. se 32 words a are used to set up the BDMA is also set to 1, which causes program execution chip program memory. Execution then begins at The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface. For BDMA accesses while in Host Mode, the addresses to boot memory must be constructed externally to the ADSP-2186M. The only memory address bit provided by the processor is AO. IDMA Port Booting The ADSP-2186M can also boot programs through its Internal DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the ADSP-2186M boots from the IDMA port. IDMA feature can load as much on-chip memory as desired. Program execution is held off until on-chip program memory location 0 is written to. Bus Request & Bus Grant The ADSP-2186M can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) signal. If the ADSP- R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 23 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 2186M is not performing an external memory access, then it responds to the active BR input in the following processor cycle by: - Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, . Asserting the bus grant (BG) signal, and - Halting program execution. If Go Mode is enabled, the ADSP-2186M will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2186M is performing an external memory access when the external device asserts the BR signal, then it will not three-state the memory interfaces or assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, re-enables the output drivers and continues program execution from the point where it stopped. _ The bus request feature operates at all times, including w is active. The BGH pin is asserted when the ADSP-21 access, but is stopped. The other device can released, the ADSP-2186M deasserts B' ocessor is booting and when RESET the external bus for a memory or BDMA Flag I/O Pins The ADSP-2186M ha from a pin configured as an input is synchronized to the ADSP-2186Ms clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset. In addition to the programmable flags, the ADSP-2186M has five fixed-mode flags, FLAG_IN, FLAG_OUT, FLO, FL1, and FL2. FLO-FL2 are dedicated output flags. FLAG_IN and FLAG_OUT are available as an alternate configuration of SPORT1. Note: Pins PFO, PF1, PF2 and PF3 are also used for device configuration during reset. Instruction Set Description The ADSP-2186M assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processors unique architecture, offers the following benefits: - Thealgebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AYO, resembles a simple equation. - Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. - Thesyntax isa superset ADSP-2100 Family assembly language and is completely source and object code compatible with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP-2186Ms interrupt vector and reset vector map. 24 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 - sixteen condition codes are available. For conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. Multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle. DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM The ADSP-2186M has on-chip emulation support and an ICE-Port, a special set of pins that interface to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICEs in-circuit probe, a 14-pin plug. Issuing the chip reset command during emulation causes the DSP to perform a full chip reset, including areset of its memory mode. Therefore, it is vital that the mode pins are set correctly PRIOR to issuing a chip reset command from the emulator user interface. If you are using a passive method of maintaining mode information (as discussed in Setting Memory Modes) then it does not matter that the mode information is latched by an emulator reset. However, if you are using the RESET pin asa method of setting the value of the mode pins, then you have to take into consideration the effects of an emulator reset. One method of ensuring that the values located on the m re'those desired is to construct a circuit like the one shown in Figure 12. This circuit forces high; regardless if it latched via the RESET or ERE! ERESET RESET AADSP-2186M MODE A/PFO PROGRAMMABLE |/O Figure 12 Mode A Pin/EZ-ICE Circuit See the ADSP-2100 Family EZ-Tools data sheet for complete information on ICE products. The ICE-Port interface consists of the following ADSP-2186M pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS, and ELOUT These ADSP-2186M pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down resistors. The traces for these signals between the ADSP-2186M and the connector must be kept as short as possible, no longer than 3 inches. The following pins are also used by the EZ-ICE: BR, BG, RESET, and GND The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-2186M in the target_ system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your system. The EZ-ICE connects to your target system via a ribbon cable and a 14-pin female plug. The female plug is plugged onto the 14-pin connector (a pin strip header) on the target board. R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 25 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 Target Board Connector for EZ-ICE Probe The EZ-ICE connector (a standard pin strip header) is shown in Figure 13. You must add this connector to your target board design if you intend to use the EZ-ICE. Be sure to allow enough room in your system to fit the EZ-ICE probe onto the 14-pin connector. Figure 13 The 14-pin, 2-row pin strip hea header. The pins must be 0,02 x 0.1 inches. The pin ICE probe plug. cationyou must remove Pin 7 from the t 10 20 inch in length. Pin spacing should be 0.1 h clearance on all sides to accept the EZ- ndo is 3M, McKenzie, and Samtec. Pin strip headers are available fr m ve Target Memory Interface For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed below. PM, DM, BM, IOM, & CM Design your Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM), and Composite Memory (CM) external interfaces to comply with worst case device timing requirements and switching characteristics as specified in this data sheet. The performance of the EZ- ICE may approach published worst case specification for some memory access timing requirements and switching characteristics. Note: If your target does not meet the worst case chip specification for memory access parameters, you may not be able to emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may have trouble manufacturing your system as DSP components statistically vary in switching characteristic and timing requirements within published limits. Restriction: All memory strobe signals on the ADSP-2186M (RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your target system must have 10 kQ pull-up resistors connected when the EZ-ICE is being used. The pull-up resistors are necessary because there are no internal pull-ups to guarantee their 26 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 state during prolonged three-state conditions resulting from typical EZ-ICE debugging sessions. These resistors may be removed at your option when the EZ-ICE is not being used. Target System Interface Signals When the EZ-ICE board is installed, the performance on some system signals change. Design your system to be compatible with the following system interface signal changes introduced by the EZ-ICE board: EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the RESET signal. EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the BR signal. EZ-ICE emulation ignores RESET and BR when single- stepping. EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted). EZ-ICE emulation ignores the state of target BR in certain modes. As a result, the target system may take control of the DSPs external memory bus only if bus grant (BG) is asserted by the EZ- ICE boards DSP. R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 27 out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADSP-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 ADSP-2186M-ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter K Grade B Grade Unit Min Max Min Max VpDINT 2.37 2.63 TBD TBD Vv VDDEXT 2.37 3.6 TBD TBD Vinpur! Vy = -0.3 Vin = 3.6 TBD TBD T AMB 0 +70 -40 +85 C 1. The ADSP-2186M is 3.3V tolerant (always accepts up to 3.6 Volt max Vj;;), but voltage compliance (on outputs, Vox) depends on the input Vppgxt:; because Voy (max)*VppextT (max). This applies to Bidirectional pins (D0D23, RFSO, RFS1, SCLKO, SCLK1, TFSO, TFS1, AlA13, PFOPF7) and Input only pins (CLKIN, RESET, BR, DRE ELECTRICAL CHARACTERISTICS 0), DR1, PWD). Parameter Unit Typ Max Vin Hi-Level Input Vok V Vin, Hi-Level CLKIN Voltag Vv V,,, Lo-Level Input Voltage! 3 0.7 Vv Vou, Hi-Level Output Voltage! * > @ Vppexr = min, 2.0 V Tou = 0.5 mA @ VopExt = 3.0V, 2.4 V Tou = 0.5 mA @ Voppexr = min, Vppexr-9.3 Vv Tox =100 wA Voz; Lo-Level Output Voltage! 4,5 @ Voppexr = min, 0.4 Vv Ip, =2 mA Ij, Hi-Level Input Current? @ Vopr = max, 10 HA Vin = 3.6V I,,, Lo-Level Input Current? @ Voppmwr = max, 10 UA Vin=0V 28 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV . P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 ELECTRICAL CHARACTERISTICS (Continued) K/B Grades Parameter Test Conditions Unit Min Typ Max Iozy, Three-State Leakage Current @ Vppexr = max, 10 HA Vin = 3.6V8 Ioz7, Three-State Leakage Current @ VppeExt = max, 10 WA VIN = 0 v8 Ipp. Supply Current (Idle)? @ Vopwr = 2.5, TBD mA tex = 15 ns Ipp, Supply Current (Idle)? @ Vopwr = 2.5, TBD mA tex = 13.3 ns Ipp, Supply Current (Dynamic)!? TBD mA Ipp, Supply Current (Dynamic)! TBD mA Ipp, Supply Current (Power TBD LA C;, Input Pin Capacitance* 6, 13 8 pF Co, Output Pin Capacitance?!214 | @ Vin=2.5 V, 8 pF fy = 1.0 MHz, T AMB=t29C nA & WN Re TN 8. 9. . Bidirectional pins: DO-D23, RFSO, RFS1, SCLKO, SCLK1, TFS0, TFS1, Al-A13, PFOPF7. . Input only pins: RESET, BR, DRO, DR1, PWD. . Input only pins: CLKIN, RESET, BR, DRO, DR1, PWD. . Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, AO, DT0, DT1, CLKOUT, FL2-0, BGH. . Although specified for TTL outputs, all ADSP-2186M outputs are CMOS-compatible and will drive to Vypprx7 and GND, assuming no DC loads. . Guaranteed but not tested. . Three-statable pins: AO-A13, DO-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0O, DT 1, SCLKO, SCLK1, TFSO, TFS1, RFSO, RSF1, PFOPF7. 0 V on BR. Idle refers to ADSP-2186M state of operation during execution of IDLE instruction. Deasserted pins are driven to either Vpp or GND. 10.Ipp measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 11.V{, = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section. 12.See Chapter 9 of the ADSP-2100 Family Users Manual for details 13. Applies to LQFP package type. 14.Output pin capacitance is the capacitive load for any three-stated output pin. R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 29 out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 ABSOLUTE MAXIMUM RATINGS! Parameter Value Min Max Internal Supply Voltage (Vpp nT) -0.3 V +3.0 V External Supply Voltage (Vpprxr) 0.3 V 4.6 V Input Voltage 0.5 V +4.6 V Output Voltage Swing? O5V Vppext + 0.5 V Operating Temperature Range (Ambient) 40 C +85 C Storage Temperature Range 65 C +150 C Lead Temperature (5 sec) LQFP +280 C trnanent damage to the device. These are stress ratings e those indicated in the operational sections of this ; forextended periods may affect device reliability. .1-A13, PFO-PF7) and Input only pins (CLKIN, 1. Stresses above those listed under Absolute Maximum Ratings only, and functional operation of the device at these or an specification is not implied. Exposure to absolute maxi 2. Applies to Bidirectional pins (DO0-D23, RFSO, RFS RESET, BR, DRO, DR1, PWD). 3. Applies to Output pins (BG, PMS, DMS ;PWDACK, AO, DTO, DT 1, CLKOUT, FL2-0, BGH). ESD SENSITIVITY. Caution: ESD (electrostatic disharge) sen device. Electro- static charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without WARNING! detection. Although the ADSP-2186M features proprietary ESD , oe protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. iil ol ESD SENSITIVE DEVICE 3 0 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 ADSP-2186M TIMING PARAMETERS GENERAL NOTES Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add up parameters to derive longer times. TIMING NOTES Switching characteristics specify how the processor changes its signals. You have no control over this timingcircuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. MEMORY TIMING SPECIFICATIONS The table below shows common memory devie timing parameters, for your convenience orresponding ADSP-2186M Memory Device Specificatio g Parameter Definition! Address setup to Write Start 3, xMS Setup before WR Low Address Setup to Write End AO-A13, xMS Setup before WR Deasserted Address Hold Time twra AO-A13, xMS Hold before WR Low Data Setup Time tow Data Setup before WR High Data Hold Time tox Data Hold after WR High OE to Data Valid tepp RD Low to Data Valid Address Access Time taa AO-A13, xMS to Data Valid 1. NOTE: xMS = PMS, DMS, BMS, CMS, or IOMS FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS tox is defined as 0.5texy. The ADSP-2186M uses an input clock with a frequency equal to half the instruction rate: a 37.50 MHz input clock (which is equivalent to 26 ns) yields a 13 ns processor cycle (equivalent to 75 MHz). tex values within the range of 0.5tc,] period should be substituted for all relevant timing parameters to obtain the specification value. R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 3 1 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 Example: texy = 0.5tcex 7 ns = 0.5 (15 ns) 7 ns = 0.5 ns EN VIRONMENTAL CONDITIONS! Rating Description Symbol Value Thermal Resistance (Case-to-Ambient) Oca A8 C/W Thermal Resistance (Junction-to-Ambient) Or 50 C/W Thermal Resistance (Junction-to-Case) Oic 2 C/W 1. Where the Ambient Temperature Rating (T aygp) is: Tamp = Tcasg ~ (PD x 8c) Tcasg = Case Temperature in C PD = Power Dissipation in W POWER DISSIPATION To determine total power dissipation in a specific application for each output: Cx Vpp2 xf C = load capacitance, f = output switching f followin g equation should be applied Example: In an application where exte: is calculated as follows:: nd no other outputs are active, power dissipation Assumptions: .- External data memory is ace ssed every h 50% of the address pins switching. . External data memory writes occur every other cycle with 50% of the data pins switching. . Each address and data pin has a 10 pF total load at the pin. The application operates at Vppgxt = 3.3 V and tex = 15 ns. Total Power Dissipation = PINT + (C x Vppxr xD) PINT = internal power dissipation from Power vs. Frequency graph (Figure 15). (Cx VppExT- x f) is calculated for each output: Parameters # of Pins xC x Vpp EXT xf PD Address, DMS 8 10 pF 3.32 V 33.3 MHz 29.0 mW Data Output, WR 9 10 pF 3.32 V 16.67 MHz 16.3 mW RD 1 10 pF 3.32 V 16.67 MHz 1.8 mW CLKOUT 1 10 pF 3.32 V 33.3 MHz 3.6 mW 50.7 mW 32 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 Total power dissipation for this example is PINT + 50.7 mW. Output Drive Currents Figure 14 shows typical I-V characteristics for the output drivers on the ADSP-2186M. The curves represent the current drive capability of the output drivers as a function of output voltage. 80 60 40 1 20 C Zz us TBD oc 5 0 oO uw oO oc D> -20 [e) n -40 -60 -80 0 5 1 1.5 2 2.5 3 3.5 4 SOURCE VOLTAGE -V R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 33 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 1,2,3 2186M POWER, INTERNAL 1: 3:4 POWER, IDLE 115 110 105 100 = = a) E = 9 ay Zz a a 85 7 oc c 80 ff = = 6 75 = 70 a 65 60 55 VALID FOR ALL TEMPERATURE GRADES. POWER, IDLE n MODES POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 2IDLE REFERS TO ADSP-2186M STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO 2 EITHER Vpp OR GND. ; 3TYPICAL POWER DISSIPATION AT 2.5V Vopnt Fi 4 AND 25C EXCEPT WHERE SPECIFIED. c 4\pp MEASUREMENT TAKEN WITH ALL [ra INSTRUCTIONS EXECUTING FROM INTERNAL = MEMORY. 50% OF THE INSTRUCTIONS ARE 9 MULTIFUNCTION (TYPES 1,4,5,12,13,14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 50.55 6065 70 75 80 1g - MHz Figure 15 :Power vs. Frequency 34 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 Capacitive Loading Figure 16 and Figure 17 show the capacitive loading characteristics of the ADSP-2186M. 30 T T = +85 Vpp = OV to 2.0V nN ao nN a TBD a RISE TIME (0.4V-2.4V) - ns a 0 50 100 150 200 250 300 CL - pF Figure 16 Typical Output Rise Time vs. Load Capacitance Max Ambient Operating Temp) NOMINAL be VALID OUTPUT DELAY OR HOLD DB ns B4 D6 0 50 100 150 200 250 C.D pF Figure 17 Typical Output Valid Delay or Hold vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature) TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output disable time (tpys) is the difference of typasuRED 20d tpgcay: as shown in the Output Enable/Disable diagram. The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage. R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 35 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 The decay time, tpgcay; is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the following equation: tDECAY = C ~O2N L from which tps = tMEASURED - DECAY is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. point, as shown in the Output Enable/Disa diagram. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving 3 6 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 Figure 19 Output Enable/Disable Figure 20 Equivalent Loading for AC Measurements (Including All Fixtures) R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 37 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 Clock Signals and Reset Parameter Min Max | Unit Clock Signals and Reset Timing Requirements: tex CLKIN Period 26.6 100 | ns tcKIh CLKIN Width Low 13 ns tex CLKIN Width High 13 ns Switching Characteristics: tcKL CLKOUT Width Low 0.5tcK -2 ns tcKH CLKOUT Width High 0.5tcK -2 ns tcKoH CLKIN High to CLKOUT High 0 13 | ns Control Signals Timing Requirements: tsp RESET Width Low 5tcx! ns tus Mode Setup Before RESET High 2 ns tw Mode Hold After RESET High 5 ns 1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time) A XXX = Figure 21 Clock Signals 38 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADSP-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 September 1999 Interrupts and Flags Parameter Min Max | Unit Interrupts and Flag Timing Requirements: tips IRQx, FI, or PFx Setup before CLKOUT Low! 23.4 0.25tcK + 10 ns tien IRQx, FI, or PFx Hold after CLKOUT High! * 3>4 0.25teK ns Switching Characteristics: trou Flag Output Hold after CLKOUT Low 0.5tcK - 5 ns trop Flag Output Delay from CLKOUT Low O.5tce, +4 | ns NOTES Te TROx and FI inputs meet typg and typy setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP- 2100 Family User's Manual for further information on interrupt servicing.) 7Edge-sensitive interrupts require pulse widths greater than 10ns; level-sensitive interrupts must be held low until serviced. TROx = IRQO, IRQ1, IRQ2, IRQLO, IRQL1, IRQLE. 4PFx = PFO, PF1, PF2, PF3, PF4, PF5, PF6, PF7. 5Flag Outputs = PFx, FLO, FL1, FL2, Flag out. ; Figure 22 Interrupts and Flags R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 39September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 Bus Request-Bus Grant Parameter Min Max | Unit Bus Request/Grant Timing Requirements: tay BR Hold after CLKOUT High! 0.25tcK + 2 ns tps BR Setup before CLKOUT Low! 0.25tcK + 10 ns Switching Characteristics: _ tsp CLKOUT High to xMS, RD, WR Disable 0.25tcK +8 | ns tsps xMS, RD, WR Disable to BG Low 0 ns tgp BG High to xMS, RD, WR Enable 0 ns tsac xMS, RD, WR Enable to CLKOUT High 0.25tc,K 3 ns tspBH xMS, RD, WR Disable to BGH Low 0 ns tsar BGH High to xMS, RD, WR Enable 0 ns NOTES 'BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family Users Manual for BR/BG cycle relationships. ?BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue. Figure 23 Bus Request-Bus Grant 40 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .A DS P-2 1 86 M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 Memory Read Parameter Min Max Unit Memory Read Timing Requirements: trop RD Low to Data Valid O0.5te,-5+Ww | ns taa AO-A13, xMS to Data Valid 0.75tcK -6+w | ns trpH Data Hold from RD High 0 ns Switching Characteristics: trp RD Pulse Width _ 0.5te, -34+Ww ns tase AO-A13, xMS Setup before RD Low 0.25tc,K - 3 ns trpa A0-A13, xMS Hold after RD Deasserted 0.25tc,x 3 ns trwR RD High to RD or WR Low 0.5tcK - 3 ns W = wait states x tox ee xX A Yi Figure 24 Memory Read REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADSP-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 Memory Write Parameter Min Max Unit Memory Write Switching Characteristics: _ tow Data Setup before WR High 0.5te,% 44+ w ns ton Data Hold after WR High 0.25tcK - 1 ns twp WR Pulse Width 0.5te, 3 +.w ns twpE WR Low._to Data Enabled _ 0 ns tasw A0-A13, xMS Setup before WR Low 0.25tcK 3 ns tppR Data Disable before WR or RD Low 0.25tcK 3 ns taw A0-A13, xMS, Setup before WR Deasserted 0.75tcK 5+w ns twra AO0-A13, xMS Hold after WR Deasserted 0.25tcx - 1 ns twwrR WR High to RD or WR Low 0.5tcK 3 ns W = wait states x tex xMS = PMS, DMS, CMS, IOMS, BMS Figure 25 Memory Write 4? This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 Serial Ports Parameter Min Max Unit Serial Ports Timing Requirements: tscK SCLK Period 26.67 ns tscs DR/TFS/RFS Setup before SCLK Low 4 ns tscH DR/TFS/RFS Hold after SCLK Low 7 ns tscp SCLKIN Width 12 ns Switching Characteristics: ns tec CLKOUT High to SCLKOUT 0.25tc,K 0.25tce, +6 | ns tscpE SCLK High to DT Enable 0 ns tscpv SCLK High to DT Valid 12 | ns try TFS/RFSOUT Hold after SCLK High 0 ns trp TFS/RFSOUT Delay from SCLK High 12 | ns tscpH DT Hold after SCLK High 0 ns trpr TFS (Alt) to DT Enable 0 ns trpv TFS (Alt) to DT Valid 12 | ns tscpp SCLK High to DT Disable 12 | ns trpv RFS (Multichannel, Frame Delay Zero) to DT ns Valid 12 | ns _ \, <____ ______ ___/ \ a ee | ee x - eo vl le. yt <+__> | e {xt xX b le > x N. ln >| x NX. + > Figure 26 Serial Ports R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 43 out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADSP-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 IDMA Address Latch Parameter Min Max Unit IDMA Address Latch Timing Requirements: traLp Duration of Address Latch! 10 ns trasu IAD15-0 Address Setup before Address Latch End? 5 ns tran IAD 15-0 Address Hold after Address Latch End? 2 ns trea TACK Low before Start of Address Latch * 0 ns traLs Start of Write or Read after Address Latch End? 3 3 ns tlaLD Address Latch Start after Address Latch End! 3 TBD ns NOTES Start of Address Latch = IS Low and IAL High. Start of Write or Read = TS Low and IWR Low or IRD Low. 3End of Address Latch =IS High or IAL Low. > le <+ XK < > + _ A K > +__ }>) << > Figure 27 IDMA Address Latch 44 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 IDMA Write, Short Write Cycle Parameter Min Max Unit IDMA Write, Short Write Cycle Timing Requirements: trxw TACK Low before Start of Write! 0 ns trwe Duration of Write! ? 10 ns trpsu IAD15-0 Data Setup before End of Write > 4 3 ns tipH IAD15-0 Data Hold after End of Write + 2 ns Switching Characteristics: trxew Start of Write to IACK High 10 | ns NOTES Start of Write = IS Low and IWR Low. End of Write =IS High or IWR High. 3If Write Pulse ends before [ACK Low, use specifications tipsy; typ. 4If Write Pulse ends after [ACK Low, use specifications trxsu: tiKH. _ Ty Figure 28 IDMA Write, Short Write Cycle R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 45 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 ID MA Write, Long Write Cycle Parameter Min Max | Unit IDMA Write, Long Write Cycle Timing Requirements: triew TACK Low before Start of Write! 0 ns tixsu IAD15-0 Data Setup before End of Write > 4 Stee +5 ns trey IAD15-0 Data Hold after End of Write > 4 0 ns Switching Characteristics: tieiw Start of Write to ACK Low* 1.5teK ns treuw Start of Write to [ACK High 10 | ns NOTES Start of Write = IS Low and IWR Low. If Write Pulse ends before [ACK Low, use specifications tyysu, typ. 31f Write Pulse ends after [ACK Low, use specifications tyxsu. treH. This is the earliest time for [ACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family Users Manual. _ UL XXX a | / Figure 29 IDMA Write, Long Write Cycle 46 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 IDMA Read, Long Read Cycle Parameter Min Max Unit IDMA Read, Long Read Cycle Timing Requirements: tree TACK Low before Start of Read! 0 ns Switching Characteristics: tiKHR TACK High after Start of Read! 10 | ns trxps IAD 15-0 Data Setup before IACK Low, 0.5tc, - 2 ns tixpH IAD15-0 Data Hold after End of Read? 0 ns trxpp IAD15-0 Data Disabled after End of Read? 10 | ns tIRDE IAD15-0 Previous Data Enabled after Start of Read 0 ns trrpv IAD 15-0 Previous Data Valid after Start of Read 10 | ns trrpH1 IAD15-0 Previous Data Hold after Start of Read (DM/PM1) 2tcK - 5 ns trrpH2 IAD15-0 Previous Data Hold after Start of Read (PM2)* ton - 5 ns NOTES Start of Read = IS Low and IRD Low. End of Read = IS High or IRD High. 3DM read or first half of PM read. 4Second half of PM read. A Figure 30 IDMA Read, Long Read Cycle R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 47 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.September 1999 ADS P-21 86M Preliminary Data Sheet For current information contact Analog Devices at (781) 461-3881 IDMA Read, Short Read Cycle Parameter Min Max | Unit IDMA Read, Short Read Cycle Timing Requirements: ter TACK Low before Start of Read! 0 ns trrp Duration of Read 10 ns Switching Characteristics: ns trKHR TACK High after Start of Read! 10 | ns tipi IAD15-0 Data Hold after End of Read 0 ns trepp IAD15-0 Data Disabled after End of Read 10 | ns tIRDE IAD15-0 Previous Data Enabled after Start of Read 0 ns trrpv TAD15-0 Previous Data Valid after Start of Read 10 | ns NOTES Start of Read = IS Low and IRD Low. End of Read = IS High or IRD High. >| > 4 K > Figure 31 IDMA Read, Short Read Cycle 48 This information applies to a product under development. Its characteristics and specifications are subject to change with- R EV P rA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. .ADSP-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 100-LEAD LQFP PACKAGE PINOUT [aq ON] Idd aNd dMd [Oo 3GONI] 24d [aaqoOnl] &4d o14 OavI/LV MOWdMd Hb [v3qON] 04d Lavl/ev ov > co > oO nN 1IxX3dqqa kd 21d ecd eed Led ocd aNd 61d sid Ztd glad A4/1AD3 D15 A5 / IAD4 D14 GND D13 A6 / IAD5 D12 A7/ |IAD6 GND A8 / IAD7 D11 A9 / IAD8 D10 A10/lIAD9 Dg A11/1AD10 VDDEXT At2/1AD11 GND ars imD2 ADSP-2186M 8 GND D7 / IWR CLKIN . D6 / IRD XTAL 100-Lead LQPF Pinout Ds / IAL VDDEXT . . D4/iIs CLKOUT Top View (pins down) GND VDDINT D3 / IACK WR D2/1AD15 R&D D1/1IAD14 BMS DO/ IAD13 DMS BG PMS EBG IOMS BR CMS FBR alsl0 S/S AG ESSLTARS OARS ARES 2 z 9 Q oag0 59 74 @54 z cr Ri ale ~ OZ 3 5 > ok 4 =a AG 23 33 > a REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change with- 49 out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 The ADSP-2186M package pinout appears in Table 7. Pin names in bold text replace the plain text named functions when Mode C = 1. A +sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. Table 7 ADSP-2186M Package Pinout LQFP Pin Name LQFP Pin Name LQFP Pin Name LQFP Pin Name Number Number Number Number 1 A4 /TAD3 26 IRQE + PF4 51 EBR 76 D16 2 A5/IAD4 27 IRQLO + PF5 52 BR V7 D17 3 GND 28 GND 53 EBG 78 D18 4 A6 / TADS 29 IRQLI + PF6 54 BG 79 D19 5 A7/TAD6 30 IRQ? + PF7 55 DO/TAD13 80 GND 6 A8 /IAD7 31 DTO 81 D20 7 A9/TAD8 32 TFSO 82 D21 8 Al10/TAD9 33 RESO 83 D22 9 All /TAD10 34 84 D23 10 Al2/TADI1 35 85 FL2 11 Al3 /TAD12 36 86 FLI 12 GND 87 FLO 13 CLKIN 38 D6/IRD 88 PF3 14 XTAL 39 RFS1 D7 /TIWR 89 PEF2 [Mode C] 15 VDDEXT 40 DRI 65 D8 90 VDDEXT 16 CLKOUT Al GND 66 GND 91 PWD 17 GND 42 SCLK1 67 VDDEXT 92 GND 18 VDDINT 43 ERESET 68 D9 93 PF1 [Mode B] 19 WR 44 RESET 69 D10 94 PEO [Mode A] 20 RD 45 EMS 70 D11 95 BGH 21 BMS 46 EE 71 GND 96 PWDACK 22 DMS 47 ECLK 72 D12 97 AO 23 PMS 48 ELOUT 73 D13 98 AITADO 24 IOMS 49 ELIN 74 D14 99 A2/TAD1 25 CMS 50 EINT 75 D15 100 A3 / TAD2 R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 50 out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.ADS P-21 86M Preliminary Data Sheet September 1999 For current information contact Analog Devices at (781) 461-3881 OUTLINE DIMENSIONS 0.638 (16.20) wa 0.630(16.00) TyP SQ 0.622 (15.80) 0.553 (14.05) 0.551 (14.00) Typ sq 0.549 (13.95) 0.063 (1.60) MAX 0.472 (12.00) BSC SQ meee 0} rye CAA 0.024 (0.60) Typ OO Ny e 3 SEATING PLANE TOP VIEW (PINS DOWN) HEMEREERCUGHGEGCUCEEE ER PRGA CRE A ein = INCHES (MILLIMETERS) MAX LEAD t 31 rors ae eves THATENHECHEHUEECHLCCULL a Tesco 0.020105 oor 27) 0.003 (0.077) iEAD PITCH Seon TYP LEAD WIDTH NOTE: THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.0032 (0.08) FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED Figure 32 100-Lead Metrie. Thin Plastic Quad Flatpack (Dimensions shown in millimeters and inches) ORDERING GUIDE Ambient . Package Part Number Temperature Instruction . ol Package Option Range Rate Description ADSP-2186MKST-300x | 0C to +70C 75 100-Lead LQFP_ | ST-100 1.In 1998, JEDEC re-evaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously labelled TQFP packages (1.6 mm thick) are now designated as LQFP. PRINTED IN USA R EV P rA This information applies to a product under development. Its characteristics and specifications are subject to change with- 5 1 . out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.