15004-520-XTP - ON SEMICONDUCTOR

July, 2017 − Rev. 3 1Publication Order Number:

AX−SFUS/D

AX-SFUS, AX-SFUS-API

Ultra-Low Power,

AT Command / API Controlled,

Sigfox) Compliant

Transceiver IC for Up-Link

and Down-Link

OVERVIEW

Circuit Description

AX−SFUS and AX−SFUS−API are ultra−low power

single chip solutions for a node on the Sigfox network with

both up− and down−link functionality. The AX−SFUS chip

is delivered fully ready for operation and contains all the

necessary firmware to transmit and receive data from the

Sigfox network in the US (SIGFOX RCZ2 region). It

connects to the customer product using a logic level RS232

UART. AT commands are used to send frames and configure

radio parameters.

The AX−SFUS−API variant is intended for customers

wishing to write their own application software based on the

AX−SF−LIB−1−GEVK library.

Features

Functionality and Ecosystem

•Sigfox up−link and down−link functionality controlled

by AT commands or API

•The AX−SFUS and AX−SF−API ICs are part of a

whole development and product ecosystem available

from ON Semiconductor for any Sigfox requirement.

Other parts of the ecosystem include

♦Ready to go development kit

DVK−SFEU−[API]−1−GEVK including a 2 year

Sigfox subscription

♦Sigfox Ready® certified reference design for the

AX−SFUS and AX−SFUS−API ICs

General Features

•QFN40 5 mm x 7 mm package

•Supply range 2.7 V* − 3.6 V

•−40°C to 85°C

•Temperature sensor

•Supply voltage measurements

*Includes the RF frontend module, circuit as in Figure 5. The

AX−SFUS chip alone is operational from 1.8 V to 3.6 V, a supply

voltage below 2.0 V is considered an extreme condition.

**Includes the RF frontend module, circuit as in Figure 5.

•8 GPIO pins

♦2 GPIO pins with selectable voltage measure

functionality, differential (1 V or 10 V range) or

single ended (1 V range) with 10 bit resolution

♦2 GPIO pins with selectable sigma delta DAC

output functionality

♦2 GPIO pins with selectable output clock

♦3 GPIO pins selectable as SPI master interface

♦RX/TX switching Control

Power Consumption**

•Ultra−low Power Consumption:

♦Charge required to send a Sigfox OOB packet at

24 dBm output power: 0.28 C

♦Deepsleep mode current: 100 nA

♦Sleep mode current: 1.3 mA

♦Standby mode current: 0.5 mA

♦Continuous radio RX−mode at 905.2 MHz :

34 mA

♦Continuous radio TX−mode at 902.2 MHz

230 mA @ 24 dBm

High Performance Narrow−band Sigfox RF Transceiver

•Receiver

♦Carrier frequency 905.2 MHz

♦Data−rate 600 bps FSK

♦Sensitivity

−128 dBm @ 600 bps, 905.2 MHz, GFSK

♦0 dBm maximum input power

•Transmitter

♦Carrier frequency 902.2 MHz

♦Data−rate 600 bps PSK

♦High efficiency, high linearity integrated power

amplifier

♦Maximum output power 24 dBm

Applications

Sigfox networks up−link and down−link.

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BLOCK DIAGRAM

Figure 1. Functional Block Diagram of the AX−SFUS / AX−SFUS−API

Communication

controller

CPU

Program

memory

(FLASH)

Sigfox identity (ID, PAC)

Sigfox compliant

RAMpower mode control

ADC

GPIO

UART

RF synthesis

DAC

AX−SFUS / AX−SFUS−API

TCXO

interface

Receive

CLKP

CLKN

ANTP

ANTN

UARTRX

UARTTX

GPIO[9:4,1:0]

VDD_IO

VDD_ANA

GND

dedicated

status

outputs

RADIO_LED

CPU_LED

TX_LED

RX_LED

VTCXO

RESET_N

CAL

FILT

application

(AX−SFUS only)

LNA

Transmit

ANTP1

TX_EN

RX_EN

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Table 1. PIN FUNCTION DESCRIPTIONS

Symbol Pin(s) Type Description

VDD_ANA 1 P Analog power output, decouple to neighboring GND

GND 2 P Ground, decouple to neighboring VDD_ANA

ANTP 3 A Differential receive input

ANTN 4 A Differential receive input

ANTP1 5 N Single ended transmit output

GND 6 P Ground, decouple to neighboring VDD_ANA

VDD_ANA 7 P Analog power output, decouple to neighboring GND

GND 8 P Ground

FILT 9 A Synthesizer filter

L2 10 A Must be connected to pin L1

L1 11 AMust be connected to pin L2

NC 12 N Do not connect

GPIO8 13 I/O/PU General purpose IO

GPIO7 14 I/O/PU General purpose IO, selectable SPI functionality (MISO)

GPIO6 15 I/O/PU General purpose IO, selectable SPI functionality (MOSI)

GPIO5 16 I/O/PU General purpose IO, selectable SPI functionality (SCK)

GPIO4 17 I/O/PU General purpose IO, selectable SD DAC functionality, selectable dock

functionality

CPU_LED 18 O CPU activity indicator

RADIO_LED 19 O Radio activity indicator

VTCXO 20 O TCXO power

GPIO9 21 I/O/PU General purpose IO, wakeup from deep sleep

UARTTX 22 O UART transmit

UARTRX 23 I/PU UART receive

RX_LED 24 O Receive activity indicator

TX_LED 25 O Transmit activity indicator

NC 26 PD Do not connect

RESET_N 27 I/PU Optional reset pin. Internal pull−up resistor is permanently enabled,

nevertheless it is recommended to connect this pin to VDD_IO if it is not used.

GND 28 P Ground

VDD_IO 29 P Unregulated power supply

GPIO0 30 I/O/A/PU General purpose IO, selectable ADC functionality, selectable SD DAC

functionality, selectable clock functionality

GPIO1 31 I/O/A/PU General purpose IO, selectable ADC functionality

TX_EN 32 O Transmitter Enable (to frontend)

NC 33 N Do not connect

NC 34 N Do not connect

RX_EN 35 O Receiver Enable (to frontend)

VDD_IO 36 P Unregulated power supply

CAL 37 A Connect to FILT as shown in the application diagram

NC 38 N Do not connect

CLKN 39 A TCXO interface

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Table 1. PIN FUNCTION DESCRIPTIONS

DescriptionTypePin(s)Symbol

CLKP 40 A TCXO interface

GND Center pad PGround on center pad of QFN, must be connected

A = analog input

I = digital input signal

O = digital output signal

PU = pull−up

I/O = digital input/output signal

N = not to be connected

P = power or ground

PD = pull−down

All digital inputs are Schmitt trigger inputs, digital input

and output levels are LVCMOS/LVTTL compatible. Pins

GPIO[3:0] must not be driven above VDD_IO, all other

digital inputs are 5 V tolerant. All GPIO pins and UARTRX

start up as input with pull−up. For explanations on how to

use the GPIO pins, see chapter “AT Commands”.

Table 2.

Pin Possible GPIO Modes

GPIO0 0, 1, Z, U, A, T

GPIO1 0, 1, Z, U, A

GPIO4 0, 1, Z, U, T

GPIO5 0, 1, Z, U

GPIO6 0, 1, Z, U

GPIO7 0, 1, Z, U

GPIO8 0, 1, Z, U

GPIO9 0, 1, Z, U

0 = pin drives

1 = not to be connected

Z = pin is high impedance input

U = pin is input with pull−up

A = pin is analog input

T = pin is driven by clock or DAC

Pinout Drawing

Figure 2. Pinout Drawing (Top View)

AX−SFEU / AX−SFEU−API

QFN40

9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29

VDD_ANA

ANTP

GND

ANTN

ANTP1

GND

VDD_ANA

FILT CLKP

CLKN

CAL

VDD_IO

GPIO0

VDD_IO

GND

RESET_N

GPIO1

TX_EN

RX_EN

GPIO8

GPIO7

GPIO6

GPIO5

GPIO4

CPU_LED

RADIO_LED

VTCXO

GPIO9

UARTTX

UARTRX

RXLED

TXLED

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SPECIFICATIONS

Table 3. ABSOLUTE MAXIMUM RATINGS

Symbol Description Condition Min Max Units

VDD_IO Supply voltage −0.5 5.5 V

IDD Supply current 200 mA

Ptot Total power consumption 800 mW

PiAbsolute maximum input power at receiver input ANTP and ANTN

pins in RX mode 10 dBm

II1 DC current into any pin except ANTP, ANTN, ANTP1 −10 10 mA

II2 DC current into pins ANTP, ANTN, ANTP1 −100 100 mA

IOOutput Current 40 mA

Via Input voltage ANTP, ANTN, ANTP1 pins −0.5 5.5 V

Input voltage digital pins −0.5 5.5 V

Ves Electrostatic handling HBM −2000 2000 V

Tamb Operating temperature −40 85 °C

Tstg Storage temperature −65 150 °C

TjJunction Temperature 150 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

1. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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DC Characteristics

Table 4. SUPPLIES

Conditions for all current and charge values unless otherwise specified are for the hardware configuration described in the AX−SFUS

Application Note: Sigfox Compliant Reference Design.

Symbol Description Condition Min Typ Max Units

TAMB Operational ambient temperature −40 27 85 °C

VDDIO I/O and voltage regulator supply

voltage AX−SFUS chip only 1.8* 3.0 3.6 V

VDDIO_mod I/O and voltage regulator supply

voltage AX−SFUS with RF frontend

module as in Figure 5

2.7 3.3 3.6 V

VDDIO_R1 I/O voltage ramp for reset activation;

Note 1 Ramp starts at VDD_IO ≤ 0.1 V 0.1 V/ms

VDDIO_R2 I/O voltage ramp for reset activation;

Note 1 Ramp starts at 0.1 V < VDD_IO < 0.7 V 3.3 V/ms

IDS Deep sleep mode current; Note 3 AT$P=2 350 nA

ISLP Sleep mode current; Note 3 AT$P=1 1.6 mA

ISTDBY Standby mode current

Notes 2, 3 0.5 mA

IRX_CONT Current consumption continuous

RX; Note 3 AT$TM=3,255 34 mA

QSFX_OOB_24 Charge to send a Sigfox out of band

message, 24 dBm; Note 3 AT$S0 0.25 C

QSFX_BIT_24 Charge to send a bit, 24 dBm;

Note 3 AT$SB=0 0.22 C

QSFX_BITDL_24 Charge to send a bit with downlink

receive, 24 dBm; Note 3 AT$SB=0,1 0.28 C

QSFX_LFR_24 Charge to send the longest possible

Sigfox frame (12 byte) , 24 dBm;

Note 3

AT$SF=00112233445566778899aabb 0.73 C

QSFX_LFRDL_24 Charge to send the longest possible

Sigfox frame (12 byte) with downlink

receive, 24 dBm; Note 3

AT$SF=00112233445566778899aabb,1 0.84 C

ITXMOD24AVG Modulated Transmitter Current;

Note 3 Pout=24 dBm; average 230 mA

*The device is operational from 1.8 V to 3.6 V. However, a supply voltage below 2.0 V is considered an extreme condition and operation can

lead to reduced output power and increased spurious emission.

1. If VDD_IO ramps cannot be guaranteed, an external reset circuit is recommended, see the AX8052 Application Note: Power On Reset

2. Internal 20 MHz oscillator, voltage conditioning and supervisory circuit running.

3. Includes Front End Module, TCXO.

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Typical Current Waveform

Figure 3. Typical Current Waveform for a Maximum Length Frame with Downlink Receive at 24 dBm Output Power

Typical Current Waveform − Maximum Length Frame with Downlink Receive, Pout = 24 dBm

Time [s]

2010 30 400

250

Current [mA]

200

150

100

Battery Life Examples

Scenario:

•2 AAA Alkaline batteries in series

•One OOB frame transmitter per day at Pout=24 dBm

•Four maximum length frames with downlink receive

per day at Pout=24 dBm

•Device in Sleep

•Neglecting battery self discharge

2 AAA alkaline capacity 1500 mAh * 3600 s/h 5400 C

Sleep charge per day 1.6 mA * 86400 s 0.14 C/day

OOB frame transmission 0.25 C/day

Frame transmission with downlink 4 * 0.84 C/day 3.36 C/day

Total Charge consumption 3.75 C/day

Battery life 3.9 Years

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Table 5. LOGIC

Symbol Description Condition Min Typ Max Units

Digital Inputs

VT+ Schmitt trigger low to high threshold point VDD_IO = 3.3 V 1.55 V

VT− Schmitt trigger high to low threshold point 1.25 V

VIL Input voltage, low 0.8 V

VIH Input voltage, high 2.0 V

VIPA Input voltage range, GPIO[3:0] −0.5 VDD_IO V

VIPBC Input voltage range, GPIO[9:4], UARTRX −0.5 5.5 V

ILInput leakage current −10 10 mA

RPU Programmable Pull−Up Resistance 65 kW

Digital Outputs

IOH Output Current, high

Ports GPIO[9:0], UARTTX, TXLED, RXLED,

TXLED, CPULED

VOH = 2.4 V 8 mA

IOL Output Current, low

GPIO[9:0], UARTTX, TXLED, RXLED, TXLED,

CPULED

VOL = 0.4 V 8 mA

IOZ Tri−state output leakage current −10 10 mA

AC Characteristics

Table 6. TCXO REFERENCE INPUT

Symbol Description Condition Min Typ Max Units

fTCXO TCXO frequency A passive network between the TCXO output

and the pins CLKP and CLKN is required.

For detailed TCXO network recommendations

depending on the TCXO output swing refer to

the AX5043 Application Note: Use with a

TCXO Reference Clock.

For TCXO recommendations see the

AX−SFUS Application Note: Sigfox Compliant

Reference Design

48 MHz

Table 7. TRANSMITTER

Conditions for transmitter specifications unless otherwise specified with the antenna network from AX−SFUS Application Note: Sigfox

Compliant Reference Design and at 902.2 MHz.

Symbol Description Condition Min Typ Max Units

SBR Signal bit rate 100 bps

PTX Highest Transmitter output power AT$CW=902200000,1,24 24 dBm

dTXtemp Transmitter power variation vs.

temperature −40°C to +85°C±0.5 dB

dTXVdd Transmitter power variation vs. VDD_IO 1.8 to 3.6 V ±0.5 dB

PTXharm2 Emission @ 2nd harmonic −51 dBc

PTXharm3 Emission @ 3rd harmonic −63

PTXharm4 Emission @ 4th harmonic −84

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Figure 4. Typical Spectrum with Harmonics at 24 dBm Output Power

Ref

−20 dBm

Att

5dB

1AV

CLRWR

3DB

RBW

1MHz

VBW

3MHz

SWT

10 s

Center

3.5 GHz

Span

5GHz

500 MHz/

−120

−110

−100

−90

−80

−70

−60

−50

−40

−30

−20

Marker 1 [T1 ]

−34.50 dBm

1.801282051 GHz

Marker 2 [T1 ]

−78.31 dBm

2.706730769 GHz

Marker 3 [T1 ]

−59.62 dBm

3.612179487 GHz

Marker 4 [T1 ]

−67.47 dBm

4.509615385 GHz

FCCP15H0

FCCP15H1

Table 8. RECEIVER

Conditions for transmitter specifications unless otherwise specified with the antenna network from AX−SFUS Application Note: Sigfox

Compliant Reference Design and at 869.525 MHz.

Symbol Description Condition Min Typ Max Units

SBR Signal bit rate 600 bps

ISBER868 AT$SB=x,1, AT$SF=x,1,

AT$TM=3,x PER < 0.1 −128 dBm

BLK905 Blocking at ±10 MHz

offset Channel/Blocker @ PER = 0.1, wanted signal

level is +3 dB above the typical sensitivity, the

blocker signal is CW

78 dB

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Table 9. ADC / TEMPERATURE SENSOR

Symbol Description Condition Min Typ Max Units

ADCRES ADC resolution 10 Bits

VADCREF ADC reference voltage 0.95 1 1.05 V

ZADC00 Input capacitance 2.5 pF

DNL Differential nonlinearity ±1 LSB

INL Integral nonlinearity ±1 LSB

OFF Offset 3 LSB

GAIN_ERR Gain error 0.8 %

ADC in Differential Mode

VABS_DIFF Absolute voltages & common mode voltage in

differential mode at each input 0 VDD_IO V

VFS_DIFF01 Full swing input for differential signals Gain x1 −500 500 mV

VFS_DIFF10 Gain x10 −50 50 mV

ADC in Single Ended Mode

VMID_SE Mid code input voltage in single ended mode 0.5 V

VIN_SE00 Input voltage in single ended mode 0 VDD_IO V

VFS_SE01 Full swing input for single ended signals Gain x1 0 1 V

Temperature Sensor

TRNG Temperature range AT$T? −40 85 °C

TERR_CAL Temperature error AT$T? −2 2°C

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COMMAND INTERFACE

General Information

The chapter “Command Interface” is a documentation of

the AT−Command set for devices which do not have an

API−interface. To see whether the device is capable of

receiving AT−Commands, please refer to chapter “Part

Numbers”. If the device has been shipped with the

API−Interface, please refer to the SW manual and

“apiexample” code delivered with AX−SF−LIB−1−GEVK

for an introduction on how to setup a project and how to use

the API−Interface.

Serial Parameters: 9600, 8, N, 1

The AX−SFUS uses the UART (pins UARTTX,

UARTRX) to communicate with a host and uses a bitrate of

9600 baud, no parity, 8 data bits and one stop bit.

Power Modes

Standby

After Power−Up and after finishing a SIGFOX

transmission, AX−SFUS enters Standby mode. In Standby

mode, AX−SFUS listens on the UART for commands from

the host. Also, OOB frames are transmitted whenever the

OOB timer fires. To conserve power, the AX−SFUS can be

put into Sleep or turned off (Deep Sleep) completely.

Sleep

The command AT$P=1 is used to put the AX−SFUS into

Sleep mode. In this mode, only the wakeup timer for

out−of−band messages is still running. To wake the

AX−SFUS up from Sleep mode toggle the serial UARTRX

pin, e.g. by sending a break (break is an RS232 framing

violation, i.e. at least 10 bit durations low). When an Out of

Band (OOB) message is due, AX−SFUS automatically

wakes up to transmit the message, and then returns to Sleep

mode.

Deep Sleep

In Deep Sleep mode, the AX−Sigfox is completely turned

off and only draws negligible leakage current. Deep Sleep

mode can be activated with AT$P=2. To wake−up from

Deep Sleep mode, GPIO9 is pulled to GND.

When using Deep Sleep mode, keep two things in mind:

Everything is turned of f, timers are not running at all and all

settings will be lost (use AT$WR to save settings to flash

before entering Deep Sleep mode). Out−of−band messages

will therefore not be sent. The pins states are frozen in Deep

Sleep mode. The user must ensure that this will not result in

condition which would draw a lot of current.

AT Commands

Numerical Syntax

hexdigit ::= [0−9A−Fa−f]

hexnum ::= “0x” hexdigit+

decnum ::= “0” | [1−9] [0−9]*

octnum ::= “0” [0−7]+

binnum ::= “0b” [01]+

bit ::= [01]

optnum ::= “−1”

frame ::= (hexdigit hexdigit)+

uint ::= hexnum | decnum | octnum | binnum

uint_opt ::= uint | optnum

Command Syntax

A command starts with ‘AT’ (everything is case

sensitive!), continues with the actual command followed by

parameters (if any) and ends with any kind of whitespace

(space, tab, newline etc.)

If incorrect syntax is detected (“parsing error”) all input

is ignored up until the next whitespace character.

Also note that any number can be entered in any format

(Hexadecimal, Decimal, Octal and binary) by adding the

corresponding prefix (‘0x’, ‘0’, ‘0b’). The only exception is

the ‘Send Frame’ command (AT$SF) which expects a list of

hexadecimal digits without any prefix.

Return Codes

A successful command execution is indicated by sending

‘OK’. If a command returns a value (e.g. by querying a

Examples

Bold text is sent to AX−SFUS.

AT$I=0

AXSEM AT Command Interface

Here, we execute command ‘I’ to query some general

information.

AT$SF=aabb1234

This sends a Sigfox frame containing { 0x00 : 0x11 : 0x22

: 0x33 : 0x44 }, then waits for a downlink response telegram,

which in this example contains { 0xAA : 0xBB : 0xCC :

0xDD }.

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AT$CB=0011223344,1

RX=AA BB CC DD

This sends a Sigfox frame containing { 0xAA : 0xBB : 0x12

: 0x34 } without waiting for a response telegram.

AT$CB=0xAA,1

The ‘CB’ command sends out a continuous pattern of bits,

in this case 0xAA = 0b10101010.

AT$P=1

This transitions the device into sleep mode. Out−of−band

transmissions will still be triggered. The UART is powered

down. The device can be woken up by a low level on the

UART signal, i.e. by sending break.

Table 10. COMMANDS

Command Name Description

AT Dummy Command Just returns ‘OK’ and does nothing else. Can be used to check

communication.

AT$SB=bit[,bit] Send Bit Send a bit status (0 or 1). Optional bit flag indicates if AX−SFUS

should receive a downlink frame.

AT$SF=frame[,bit] Send Frame Send payload data, 1 to 12 bytes. Optional bit flag indicates if

AX−SFUS should receive a downlink frame.

AT$SO Manually send out of band

message Send the out−of−band message.

AT$TR? Get the transmit repeat Returns the number of transmit repeats. Default: 2

AT$TR=? Get transmit range Returns the allowed range of transmit repeats.

AT$TR=uint Get transmit repeat Sets the transmit repeat.

ATSuint? Get Register Query a specific configuration register’s value. See chapter

“Registers” for a list of registers.

ATSuint=uint Set Register Change a configuration register.

ATSuint=? Get Register Range Returns the allowed range of transmit repeats.

AT$IF=uint Set TX Frequency Set the output carrier macro channel for Sigfox frames.

AT$IF? Get TX Frequency Get the currently chosen TX frequency.

AT$DR=uint Set RX Frequency Set the reception carrier macro channel for Sigfox frames.

AT$DR? Get RX Frequency Get the currently chosen RX frequency.

AT$CW=uint,bit[,uint_opt] Continuous Wave To run emission tests for Sigfox certification it is necessary to send a

continuous wave, i.e. just the base frequency without any modula-

tion. Parameters:

Name Range Description

Frequency 800000000− Continuous wave frequency in Hz.

999999999, 0 Use 902200000 for Sigfox or 0 to

keep previous frequency.

Mode 0, 1 Enable or disable carrier wave.

Power 24 dBm of signal | Default: 24

AT$CB=uint_opt,bit Test Mode: TX constant byte For emission testing it is useful to send a specific bit pattern. The

first parameter specifies the byte to send. Use ‘−1’ for a

(pseudo−)random pattern. Parameters:

Name Range Decsription

Pattern 0−255, −1 Byte to send. Use ‘−1’ for a

(pseudo−)random pattern.

Mode 0, 1 Enable or disable pattern test mode.

AT$RC Reset FCC Macrochannel This command resets the FCC Macrochannel. Subsequent transmit

operations (AT$SO, AT$SB, AT$SF) may pause up to 20 s to ensure

FCC compliance

AT$T? Get Temperature Measure internal temperature and return it in 1/10th of a degree

Celsius.

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Table 10. COMMANDS

Command DescriptionName

AT$V? Get Voltages Return current voltage and voltage measured during the last

transmission in mV.

AT$I=uint Information Display various product information:

0: Software Name & Version

Example Response: AX−Sigfox 1.1.1−FCC

1: Contact Details

Example Response: support@axsem.com

2: Silicon revision lower byte

Example Response: 8F

3: Silicon revision upper byte

Example Response: 51

4: Major Firmware Version

Example Response: 1

5: Minor Firmware Version

Example Response: 1

7: Firmware Variant (Frequency Band etc. (EU/US))

Example Response: FCC

9: SIGFOX Library Version

Example Response: UDL1−1.8.7

10: Device ID

Example Response: 00012345

11: PAC

Example Response: 0123456789ABCDEF

AT$P=uint Set Power Mode To conserve power, the AX−SFUS can be put to sleep manually.

Depending on power mode, you will be responsible for waking up the

AX−SFUS again!

0: software reset (settings will be reset to values in flash)

1: sleep (send a break to wake up)

2: deep sleep (toggle GPIO9 or RESET_N pin to wake up;

the AX−SFUS is not running and all settings will be reset!)

AT$WR Save Config Write all settings to flash (RX/TX frequencies, registers) so they

survive reset/deep sleep or loss of power.

Use AT$P=0 to reset the AX−SFUS and load settings from flash.

AT:Pn? Get GPIO Pin Return the setting of the GPIO Pin n; n can range from 0 to 9.

A character string is returned describing the mode of the pin,

followed by the actual value. If the pin is configured as analog pin,

then the voltage (range 0…1 V) is returned. The mode characters

have the following meaning:

Mode Description

0 Pin drives low

1 Pin drives high

Z Pin is high impedance input

U Pin is input with pull−up

A Pin is analog input (GPIO pin 0…3 only)

T Pin is driven by clock or DAC (GPIO pin 0 and 4 only)

The default mode after exiting reset is U on all GPIO pins.

AT:Pn=? Get GPIO Pin Range Print a list of possible modes for a pin. The table below lists the

response.

Pin Modes

P0 0, 1, Z, U, A, T

P1 0, 1, Z, U, A

P4 0, 1, Z, U, T

P5 0, 1, Z, U

P6 0, 1, Z, U

P7 0, 1, Z, U

P8 0, 1, Z, U

P9 0, 1, Z, U

AT:Pn=mode Set GPIO Pin Set the GPIO pin mode.

For a list of the modes see the command AT:Pn?

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Table 10. COMMANDS

Command DescriptionName

AT:ADC Pn[−Pn[ (1V|10V)]]? Get GPIO Pin Analog Voltage Measure the voltage applied to a GPIO pin. The command also

allows measurement of the voltage difference across two GPIO pins.

In differential mode, the full scale range may also be specified as 1 V

or 10 V. Note however that the pin input voltages must not exceed

the range 0..VDD_IO. The command returns the result as fraction of

the full scale range (1 V if none is specified). The GPIO pins

referenced should be initialized to analog mode before issuing this

command.

AT:SPI[(A|B|C|D)]=bytes SPI Transaction This command clocks out bytes on the SPI port. The clock frequency is

312.5 kHz. The command returns the bytes read on MISO during out-

put. Optionally the clocking mode may be specified (default is A):

Mode Clock Inversion Clock Phase

A normal normal

B normal alternate

C inverted normal

D inverted alternate

Note that SEL, if needed, is not generated by this command,

and must instead be driven using standard GPIO commands

(AT:Pn=0|1).

AT:CLK=freq,reffreq Set Clock Generator Output a square wave on the pin(s) set to T mode. The frequency of

the square wave is (freq / 216) × reffreq. Possible values for reffreq

are 20000000, 10000000, 5000000, 2500000, 1250000, 625000,

312500, 156250. Possible values if freq are 0…65535.

AT:CLK=OFF Turn off Clock Generator Switch off the clock generator

AT:CLK? Get Clock Generator Return the settings of the clock generator. Two numbers are

returned, freq and reffreq.

AT:DAC=value Set SD DAC Output a SD DAC value on the pin(s) set to T mode. Parameter

value may be in the range −32768…32767. The average output

voltage is (1/2 + value / 217) × VDD.

An external low pass filter is needed to get smooth output voltages.

The modulation frequency is 20 MHz. A possible low pass filter

choice is a simple RC low pass filter with R = 10 kW and C = 1 mF.

AT:DAC=OFF Turn off SD DAC Switch off the DAC

AT:DAC? Get SD DAC Return the DAC value

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Table 10. COMMANDS

Command DescriptionName

AT$TM=mode,config Activates the Sigfox Testmode Available test modes:

0. TX BPSK

Send only BPSK with Synchro Bit + Synchro frame +

PN sequence: No hopping centered on the TX_frequency.

Config bits 0 to 6 define the number of repetitions. Bit 7 of config

defines if a delay is applied of not in the loop

1. TX Protocol:

Tx mode with full protocol with Sigfox key: Send Sigfox protocol

frames with initiate downlink flag = True. Config defines the

number of repetitions.

2. RX Protocol:

This mode tests the complete downlink protocol in Downlink only.

Config defines the number of repetitions.

3. RX GFSK:

RX mode with known pattern with SB + SF + Pattern on

RX_frequency (internal comparison with received frame ⇔ known

pattern = AA AA B2 27 1F 20 41 84 32 68 C5 BA AE 79 E7 F6 DD

9B. Config defines the number of repetitions. Config defines the

number of repetitions.

4. RX Sensitivity:

Does uplink + downlink frame with Sigfox key and specific timings.

This test is specific to SIGFOX’s test equipments & softwares.

5. TX Synthesis:

Does one uplink frame on each Sigfox channel to measure

frequency synthesis step

AT$SE Starts AT$TM−3,255 indefinitely Convenience command for sensitivity tests

AT$SL[=frame] Send local loop Sends a local loop frame with optional payload of 1 to 12 bytes.

Default payload: 0x84, 0x32, 0x68, 0xC5, 0xBA, 0x53, 0xAE, 0x79,

0xE7, 0xF6, 0xDD, 0x9B.

AT$RL Receive local loop Starts listening for a local loop.

Table 11. REGISTERS

Number Name Description Default Range Units

300 Out Of Band

Period AX−SFUS sends periodic static

messages to indicate that they are

alive. Set to 0 to disable.

24 0−24 hours

400 Macrochannel

Mask The mask of Macrochannels to use. <000001FF>

<00000000>

<00000000>,1

410 Encryption Key

Configuration Set to zero for normal operation. Set

to one for use with the SIGFOX

Network Emulator Kit (SNEK)

00−1 0: private key

1: public key

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APPLICATION INFORMATION

Typical Application Diagrams

Typical AX−SFUS / AX−SFUS−API Application Diagram

Figure 5. Typical Application Diagram

For detailed application configuration and BOM see the

AX−SFUS Application Note: Sigfox Compliant Reference

Design.

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QFN40 PACKAGE INFORMATION

QFN40 7x5, 0.5P

CASE 485EG

ISSUE A

SEATING

NOTE 4

0.15 C

(A3)

E2 40X

40X

BOTTOM VIEW

DETAIL A

TOP VIEW

SIDE VIEW

DA B

0.15 C

ÉÉ

PIN ONE

REFERENCE

0.10 C

0.08 C

A0.10 B

0.05 C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSIONS: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30mm FROM TERMINAL

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.18 0.30

D7.00 BSC

D2 5.30 5.50

E5.00 BSC

3.50E2 3.30

e0.50 BSC

L0.30 0.50

L1 −−− 0.15

PLANE

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

e/2

NOTE 3

DIMENSIONS: MILLIMETERS

0.50

5.60

0.32

3.60

40X

0.60

40X

5.30

7.30

PITCH

PACKAGE

OUTLINE

RECOMMENDED

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

ÉÉ

ÇÇ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE

CONSTRUCTION

DETAIL B

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QFN40 Soldering Profile

Figure 6. QFN40 Soldering Profile

Preheat Reflow Cooling

TsMAX

TsMIN ts

T25°C to Peak

Temperature

Time

25°C

Table 12.

Profile Feature Pb−Free Process

Average Ramp−Up Rate 3°C/s max.

Preheat Preheat

Temperature Min TsMIN 150°C

Temperature Max TsMAX 200°C

Time (TsMIN to TsMAX) ts60 – 180 sec

T ime 25 °C to Peak Temperature T25°C to Peak 8 min max.

Reflow Phase

Liquidus Temperature TL217°C

Time over Liquidus Temperature tL60 – 150 s

Peak Temperature tp260°C

Time within 5°C of actual Peak Temperature Tp20 – 40 s

Cooling Phase

Ramp−down rate 6°C/s max.

1. All temperatures refer to the top side of the package, measured on the the package body surface.

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QFN40 Recommended Pad Layout

1. PCB land and solder masking recommendations

are shown in Figure 7.

Figure 7. PCB Land and Solder Mask Recommendations

A = Clearance from PCB thermal pad to solder mask opening, 0.0635 mm minimum

B = Clearance from edge of PCB thermal pad to PCB land, 0.2 mm minimum

C = Clearance from PCB land edge to solder mask opening to be as tight as possible

to ensure that some solder mask remains between PCB pads.

D = PCB land length = QFN solder pad length + 0.1 mm

E = PCB land width = QFN solder pad width + 0.1 mm

2. Thermal vias should be used on the PCB thermal

pad (middle ground pad) to improve thermal

conductivity from the device to a copper ground

plane area on the reverse side of the printed circuit

board. The number of vias depends on the package

thermal requirements, as determined by thermal

simulation or actual testing.

3. Increasing the number of vias through the printed

circuit board will improve the thermal

conductivity to the reverse side ground plane and

external heat sink. In general, adding more metal

through the PC board under the IC will improve

operational heat transfer, but will require careful

attention to uniform heating of the board during

assembly.

Assembly Process

Stencil Design & Solder Paste Application

1. Stainless steel stencils are recommended for solder

paste application.

2. A stencil thickness of 0.125 – 0.150 mm

(5 – 6 mils) is recommended for screening.

3. For the PCB thermal pad, solder paste should be

printed on the PCB by designing a stencil with an

array of smaller openings that sum to 50% of the

QFN exposed pad area. Solder paste should be

applied through an array of squares (or circles) as

shown in Figure 8.

4. The aperture opening for the signal pads should be

between 50−80% of the QFN pad area as shown in

Figure 9.

5. Optionally, for better solder paste release, the

aperture walls should be trapezoidal and the

corners rounded.

6. The fine pitch of the IC leads requires accurate

alignment of the stencil and the printed circuit

board. The stencil and printed circuit assembly

should be aligned to within + 1 mil prior to

application of the solder paste.

7. No−clean flux is recommended since flux from

underneath the thermal pad will be difficult to

clean if water−soluble flux is used.

Figure 8. Solder Paste Application on Exposed Pad

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Figure 9. Solder Paste Application on Pins

Minimum 50% coverage 62% coverage Maximum 80% coverage

Life Support Applications

This product is not designed for use in life support

appliances, devices, or in systems where malfunction of this

product can reasonably be expected to result in personal

injury. ON Semiconductor customers using or selling this

product for use in such applications do so at their own risk

and agree to fully indemnify ON Semiconductor for any

damages resulting from such improper use or sale.

Device Information

The following device information can be queried using

the AT−Commands AT$I=4, AT$I=5 for the APP version

and AT$I=2, AT$I=3 for the chip version.

Table 13. DEVICE VERSIONS

Product Part Number

APP Version Chip Version

[0] [1] [0] [1]

AX−SFUS AX−SFUS−1−01−XXXX10x01 0x01 0x8F 0x51

AX−SFUS−API AX−SFUS−API−1−01−XXXX10x01 0x01 0x8F 0x51

1. TB05 for Reel 500, TX30 for Reel 3000 reel

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coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

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Europe, Middle East and Africa Technical Support:

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AX−SFUS/D

Sigfox and Sigfox Ready are registered trademarks of Sigfox SARL.

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