AD7294-2BSUZ - ANALOG DEVICES

12-Bit Monitor and

Control System with Multichannel

ADC, DACs, Temperature Sensor, and Current Sense

Data Sheet

AD7294-2

Rev. 0 Document Feedback

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FEATURES

12-bit SAR ADC with 3 μs conversion time

4 uncommitted analog inputs

Differential/single-ended

VREF, 2 × VREF input ranges

2 high-side current sense inputs

5 V to 59.4 V operating range

0.75% maximum gain error

±200 mV input range

2 external diode temperature sensor inputs

−55°C to +150°C measurement range

±2°C accuracy

Series resistance cancellation

1 internal temperature sensor: ±2°C accuracy

Built-in monitoring features

Minimum/maximum recorder for each channel

Programmable alert thresholds

Programmable hysteresis

Four 12-bit, monotonic, 15 V DACs

5 V span, 0 V to 10 V offset

8 μs settling time

10 mA sink and source capability

Power-on reset (POR) to 0 V

Internal 2.5 V reference

2-wire, fast mode I2C interface

Temperature range: −40°C to +105°C

Package type: 64-lead TQFP

Pin compatible with the AD7294

APPLICATIONS

Cellular base stations

GSM, EDGE, UMTS, CDMA, TD-SCDMA, W-CDMA, WiMAX

Point-to-multipoint and other RF transmission systems

12 V, 24 V, 48 V automotive applications

Industrial controls

GENERAL DESCRIPTION

The AD7294-2 contains all the functions that are required for

general-purpose monitoring and control of current, voltage,

and temperature, integrated into a single-chip solution. The part

includes low voltage (±200 mV) analog input sense amplifiers

for current monitoring across shunt resistors, temperature sense

inputs, and four uncommitted analog input channels multiplexed

into a SAR analog-to-digital converter (ADC) with a 3 μs

conversion time. A high accuracy internal reference is provided

to drive both the digital-to-analog converters (DACs) and the

ADC. Four 12-bit DACs provide the outputs for voltage control.

The AD7294-2 also includes limit registers for alarm functions.

The part is designed for high voltage compliance: 59.4 V on the

current sense inputs and up to a 15 V DAC output voltage.

The AD7294-2 is a highly integrated solution that offers all the

functionality necessary for precise control of the power amplifier

in cellular base station applications. In these types of applications,

the DACs provide 12-bit resolution to control the bias currents

of the power transistors. Thermal diode-based temperature sensors

are incorporated to compensate for temperature effects. The ADC

monitors the high-side current and temperature. This functionality

is provided in a 64-lead TQFP, which operates over a temperature

range of −40°C to +105°C.

AD7294-2 Data Sheet

Rev. 0 | Page 2 of 44

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications ..................................................................................... 4

DAC Specifications....................................................................... 4

ADC Specifications ...................................................................... 5

General Specifications ................................................................. 7

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings ............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 12

Terminology .................................................................................... 17

DAC Terminology ...................................................................... 17

ADC Terminology ...................................................................... 17

Theory of Operation ...................................................................... 18

ADC Overview ........................................................................... 18

ADC Transfer Functions ........................................................... 18

Analog Inputs .............................................................................. 19

Current Sensor ............................................................................ 20

Analog Comparator Loop ......................................................... 22

Temperature Sensor ................................................................... 22

DAC Operation ........................................................................... 23

ADC and DAC Reference .......................................................... 24

VDRIVE Feature .............................................................................. 24

Address Pointer Register ........................................................... 25

Command Register .................................................................... 26

ADC Result Register .................................................................. 26

TSENSE1 and TSENSE2 Result Registers ......................................... 27

TSENSEINT Result Register .......................................................... 27

DACA, DACB, DACC, and DACD Value Registers ....................... 27

Alert Status Register A, Alert Status Register B, and Alert

Status Register C ......................................................................... 28

Channel Sequence Register ....................................................... 28

Configuration Register .............................................................. 29

Power-Down Register ................................................................ 30

DATALOW and DATAHIGH Registers .......................................... 30

Hysteresis Registers .................................................................... 30

Remote Channel TSENSE1 and TSENSE2 Offset Registers ........... 31

I2C Interface .................................................................................... 32

General I2C Timing .................................................................... 32

Serial Bus Address Byte ............................................................. 32

Interface Protocol ....................................................................... 33

Modes of Operation ....................................................................... 36

Command Mode ........................................................................ 36

Autocycle Mode .......................................................................... 37

Alerts and Limits Theory .............................................................. 38

ALERT_FLAG Bit ....................................................................... 38

Alert Status Registers ................................................................. 38

DATALOW and DATAHIGH Monitoring Features ...................... 38

Hysteresis ..................................................................................... 39

Applications Information .............................................................. 40

Base Station Power Amplifier Monitor and Control ............. 40

Gain Control of Power Amplifier ............................................. 41

Outline Dimensions ....................................................................... 42

Ordering Guide .......................................................................... 42

REVISION HISTORY

6/13—Revision 0: Initial Version

Data Sheet AD7294-2

Rev. 0 | Page 3 of 44

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

10936-001

LIMIT

REGISTERS

MUX

CONTROL LOGIC

I2C INT E RFACE

PROTOCOL

TEMP

SENSOR

HIGH-SIDE

CURRENT

SENSE

HIGH-SIDE

CURRENT

SENSE

REFOUT/

REFIN DAC

T1 T2

TO LOAD

RS1(+) RS2(+) RS2(–)RS1(–)

D1(+)

D2(+)

D1(–)

D2(–)

AVDD

AGND1

AGND7 DAC O UTV+ AB,

DAC OUT V + CD,

AD7294-2

REFOUT/

REFIN ADC

VPP1, VPP2

ALERT/

BUSY

DCAP

VREF

10.41

ISENSE1

OVERRANGE

ISENSE2

OVERRANGE

RSENSE

12-BIT

ADC

AS0AS1

AS2SCL

SDARESET

DGND (× 3)

VIN0

VIN1

VIN2

VIN3

12-BIT

DAC

100kΩ 200kΩ

12-BIT

DAC

100kΩ 200kΩ

12-BIT

DAC

100kΩ 200kΩ

12-BIT

DAC

100kΩ 200kΩ

OFFSET IN A

VOUTB

OFFSET IN B

VOUTC

OFFSET IN C

VOUTD

OFFSET IN D

VOUTA

2.5V

REF

AD7294-2 Data Sheet

Rev. 0 | Page 4 of 44

SPECIFICATIONS

DAC SPECIFICATIONS

AVDD = 4.5 V to 5.5 V, AGND1 to AGND7 = DGND = 0 V, internal 2.5 V reference; VDRIVE = 2.7 V to 5.5 V; TA = −40°C to +105°C, unless

otherwise noted. DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating; therefore, the DAC output span = 0 V

to 5 V.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ACCURACY1

Resolution 12 Bits

Relative Accuracy (INL) ±1 ±3 LSB

Differential Nonlinearity (DNL) ±0.3 ±1 LSB Guaranteed monotonic

Zero-Code Error 2.5 6 mV

Full-Scale Error 10 mV DAC OUTV+ = 5.5 V

Offset Error ±4 mV Measured in the linear region, TA = −40°C to +105°C

±2 mV Measured in the linear region, TA = 25°C

Offset Error Temperature

Coefficient

±5 ppm/°C

Gain Error ±0.025 ±0.155 % FSR

Gain Error Drift ±5 ppm/°C

DAC OUTPUT CHARACTERISTICS

Output Voltage Span 0 2 × VREF V 0 V to 5 V for a 2.5 V reference

Output Voltage Offset 0 10 V The output voltage span can be positioned in the 0 V to 15 V

range; if the OFFSET IN x pin is left floating, the offset =

2/3 × VREF, giving an output of 0 V to 2 × VREF

Offset Input Pin Range 0 5 V VOUT = 3 × VOFFSET − 2 × VREF + VDAC

DC Input Impedance2 75 kΩ 100 kΩ to VREF, and 200 kΩ to AGND; see Figure 45

Output Voltage Settling Time2 8 µs 1/4 to 3/4 change within 1/2 LSB, measured from last

SCL edge

Slew Rate

1.1

V/µs

Short-Circuit Current2 40 mA Full-scale current shorted to ground

Load Current2 ±10 mA Source and/or sink within 200 mV of supply

Capacitive Load Stability2 10 nF RL = ∞

DC Output Impedance2 1 Ω

REFERENCE

Reference Output Voltage 2.49 2.5 2.51 V ±0.2% maximum at 25°C, AVDD = 5 V

Reference Input Voltage Range 0 AVDD − 2 V

Input Current 400 480 µA VREF = 2.5 V

Input Capacitance2 20 pF

VREF Output Impedance2 5 Ω A buffer is required if the reference output is used to drive

external loads

Reference Temperature

Coefficient

10 25 ppm/°C

1 Linearity calculated using a reduced code range: Code 10 to Code 4095.

2 Guaranteed by design and characterization; not production tested.

Data Sheet AD7294-2

Rev. 0 | Page 5 of 44

ADC SPECIFICATIONS

AVDD = 4.5 V to 5.5 V, AGND1 to AGND7 = DGND = 0 V, internal or external 2.5 V reference; VDRIVE = 2.7 V to 5.5 V; VPPx = AVDD to 59.4 V;

TA = −40°C to +105°C, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

DC ACCURACY

Resolution 12 Bits

Integral Nonlinearity (INL)1 ±0.5 ±1 LSB Differential mode

±0.5 ±1.5 LSB Single-ended or pseudo differential mode

Differential Nonlinearity (DNL)1 ±0.5 ±0.99 LSB Differential, single-ended, and pseudo differential

modes

Single-Ended Mode

Offset Error ±1 ±7 LSB

Offset Error Match ±0.4 LSB

Gain Error ±0.5 ±4.5 LSB

Gain Error Match ±0.4 LSB

Differential Mode

Positive Gain Error ±1 LSB

Positive Gain Error Match ±0.5 LSB

Zero Code Error ±3 LSB

Zero Code Error Match ±0.5 LSB

Negative Gain Error ±1 LSB

Negative Gain Error Match ±0.5 LSB

CONVERSION RATE

Conversion Time2 3 μs

Autocycle Update Rate2 50 μs

Throughput Rate 22.22 kSPS fSCL = 400 kHz

ANALOG INPUT3

Single-Ended Input Range 0 VREF V 0 V to VREF mode

0 2 × VREF V 0 V to 2 × VREF mode

Pseudo Differential Input Range: VIN+ − VIN−4 0 VREF V 0 V to VREF mode

0 2 × VREF V 0 V to 2 × VREF mode

Fully Differential Input Range: VIN+ − VIN− −VREF +VREF V 0 V to VREF mode

−2 × VREF +2 × VREF V 0 V to 2 × VREF mode

Input Capacitance2 30 pF

DC Input Leakage Current ±1 µA

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)1 73 dB fIN = 10 kHz sine wave; differential mode

72 dB fIN = 10 kHz sine wave; single-ended and pseudo

differential modes

Signal-to-Noise and Distortion Ratio

(SINAD)1

72.5 dB fIN = 10 kHz sine wave; differential mode

71.5 dB fIN = 10 kHz sine wave; single-ended and pseudo

differential modes

Total Harmonic Distortion (THD)1 −81 dB fIN = 10 kHz sine wave; differential mode

−79 dB fIN = 10 kHz sine wave; single-ended and pseudo

differential modes

Spurious-Free Dynamic Range (SFDR)1 −81 dB fIN = 10 kHz sine wave; differential mode

−79 dB fIN = 10 kHz sine wave; single-ended and pseudo

differential modes

Channel-to-Channel Isolation2 −90 dB fIN = 0.5 Hz to 100 kHz

AD7294-2 Data Sheet

Rev. 0 | Page 6 of 44

Parameter Min Typ Max Unit Test Conditions/Comments

TEMPERATURE SENSOR—INTERNAL

Operating Range −40 +105 °C

Accuracy ±2 °C Internal temperature sensor, TA = −30°C to +90°C

±2.5 °C Internal temperature sensor, TA = −40°C to +105°C

Resolution

0.25

°C

LSB size

Update Rate 5 ms

TEMPERATURE SENSOR—EXTERNAL External transistor is 2N3906

Operating Range −55 +150 °C Limited by external diode

Accuracy ±2 °C TA = TDIODE = −40°C to +105°C

Resolution 0.25 °C LSB size

Low Level Output Current Source2 8 µA

Medium Level Output Current Source2 32 µA

High Level Output Current Source2 128 µA

Maximum Series Resistance (R

) for

External Diode2

kΩ

For <±0.5°C additional error, C

= 0 (see Figure 29)

Maximum Parallel Capacitance (CP) for

External Diode2

1 nF RS = 0 (see Figure 28)

CURRENT SENSE VPP = AVDD to 59.4 V

VPP Supply Range AVDD 59.4 V

Gain Error ±0.75 % FSR 2.5 V reference

Differential Input

±200

2.5 V reference

RS(+)/RS(−) Input Bias Current 25 32 µA

CMRR/PSRR2 110 dB Inputs shorted to VPP

Offset Error ±50 ±780 µV

Offset Drift 3 µV/°C

Amplifier Peak-to-Peak Noise2 400 µV Referred to input

VPP Supply Current 0.18 0.25 mA Per channel, VPP1 = VPP2 = 59.4 V

REFERENCE

Reference Output Voltage 2.49 2.5 2.51 V ±0.2% maximum at 25°C

Reference Input Voltage Range2 0.1 4.1 V

DC Leakage Current ±2 μA

VREF Output Impedance2 5 Ω A buffer is required if the reference output is used

to drive external loads

Input Capacitance2 20 pF

Reference Temperature Coefficient 10 25 ppm/°C

1 See the Terminology section for more information.

2 Guaranteed by design and characterization; not production tested.

3 VIN+ and VIN− must remain within AGND/AVDD. (The analog input pins are VIN3 to VIN0.)

4 VIN− = 0 V for specified performance. For full input range on VIN−, see Figure 36.

Data Sheet AD7294-2

Rev. 0 | Page 7 of 44

GENERAL SPECIFICATIONS

AVDD = 4.5 V to 5.5 V, AGND1 to AGND7 = DGND = 0 V, internal or external 2.5 V reference; VDRIVE = 2.7 V to 5.5 V; VPPx = AVDD to

59.4 V; DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating; therefore, DAC output span = 0 V to 5 V;

TA = −40°C to +105°C, unless otherwise noted.

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

Input High Voltage VIH 0.7 VDRIVE V SDA, SCL only

Input Low Voltage VIL 0.3 VDRIVE V SDA, SCL only

Input Leakage Current IIN ±1 µA

Input Hysteresis1 VHYST 0.05 VDRIVE V

Input Capacitance1 CIN 8 pF

Glitch Rejection1 50 ns Input filtering suppresses noise spikes of

less than 50 ns

Maximum External Capacitance of

I2C Address Pins When Floating1

30 pF Tristate input

LOGIC OUTPUTS

SDA, ALERT SDA and ALERT/BUSY are open-drain

outputs

Output Low Voltage VOL 0.4 V ISINK = 3 mA

0.6 V ISINK = 6 mA

Floating-State Leakage Current1 ±1 µA

Floating-State Output

Capacitance1

8 pF

ISENSE OVERRANGE ISENSEx OVERRANGE are push-pull outputs

Output High Voltage VOH VDRIVE − 0.2 V ISOURCE = 200 µA for push-pull outputs

Output Low Voltage

0.2

SINK

= 200 µA for push-pull outputs

Overrange Setpoint1 VFS VFS × 1.2 mV VFS = ±VREF ADC/12.5

POWER REQUIREMENTS

VPP1, VPP2 AVDD 59.4 V

AVDD 4.5 5.5 V

DAC OUTV+ xx 4.5 16.5 V

VDRIVE 2.7 5.5 V

IDD 5.3 7.5 mA AVDD + VDRIVE; DAC outputs unloaded

DAC OUTV+ xx, IDD 0.6 1.2 mA At midscale output voltage, DAC outputs

unloaded

Power Dissipation 70 110 mW

Power-Down

IDD 4.4 5.5 mA AVDD and VDRIVE; ADC, DACs, and

temperature sensor powered down

DAC OUTV+ x, I

µA

Power Dissipation 70 mW

1 Guaranteed by design and characterization; not production tested.

AD7294-2 Data Sheet

Rev. 0 | Page 8 of 44

TIMING CHARACTERISTICS

I2C Serial Interface

AVDD = 4.5 V to 5.5 V, AGND1 to AGND7 = DGND = 0 V, internal or external 2.5 V reference; VDRIVE = 2.7 V to 5.5 V; VPPx = AV DD to

59.4 V; DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V;

TA = −40°C to +105°C, unless otherwise noted.

Table 4.

Parameter

Limit at T

MIN

, T

MAX

Unit

Symbol

Description

fSCL 400 kHz max SCL clock frequency

t1 2.5 µs min SCL cycle time

t2 0.6 µs min tHIGH SCL high time

t3 1.3 µs min tLOW SCL low time

t4 0.6 µs min tHD,STA Start/repeated start condition hold time

t5 100 ns min tSU,DAT Data setup time

t6 0.9 µs max tHD,DAT Data hold time

0 µs min tHD,DAT Data hold time

t7 0.6 µs min tSU,STA Setup time for repeated start

t8 0.6 µs min tSU,STO Stop condition setup time

t9 1.3 µs min tBUF Bus free time between a stop and a start condition

t102 300 ns max tR Rise time of SCL and SDA when receiving

0 ns min tR Rise time of SCL and SDA when receiving (CMOS compatible)

t112 300 ns max tF Fall time of SDA when transmitting

20 × (VDRIVE/5.5 V) ns min tF Fall time of SCL and SDA when transmitting

0 ns min tF Fall time of SDA when receiving (CMOS compatible)

300 ns max tF Fall time of SCL and SDA when receiving

400

pF max

Capacitive load for each bus line

1 See Figure 2.

2 tR and tF are measured between 0.3 VDD and 0.7 VDD.

3 Cb is the total capacitance in pF of one bus line.

Timing and Circuit Diagrams

Figure 2. I2C-Compatible Serial Interface Timing Diagram

Figure 3. Load Circuit for Digital Output

START

CONDITION REPEATED

START

CONDITION

STOP

CONDITION

t9t3

t11 t4

t10

t4t5t7

t6t8

SDA

SCL

10936-002

50pF

TO OUTPUT PIN VOH (MIN) OR

VOL (MAX)

200µA

IOL

IOH

10936-003

Data Sheet AD7294-2

Rev. 0 | Page 9 of 44

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.1

Table 5.

Parameter Rating

VPPx to AGND −0.3 V to +65 V

AVDD to AGND −0.3 V to +7 V

DAC OUTV+ AB to AGND −0.3 V to +17 V

DAC OUTV+ CD to AGND −0.3 V to +17 V

VDRIVE to OPGND −0.3 V to +7 V

Digital Inputs to OPGND −0.3 V to VDRIVE + 0.3 V

RESET to OPGND −0.3 V to +7 V

SDA/SCL to OPGND −0.3 V to +7 V

Digital Outputs to OPGND −0.3 V to VDRIVE + 0.3 V

RS(+)/RS(−) to VPPx VPPx − 0.3 V to VPPx + 0.3 V

REFOUT/REFIN ADC to AGND −0.3 V to AVDD + 0.3 V

REFOUT/REFIN DAC to AGND −0.3 V to AVDD + 0.3 V

OPGND to AGND −0.3 V to +0.3 V

OPGND to DGND −0.3 V to +0.3 V

AGND to DGND −0.3 V to +0.3 V

VOUTx to AGND −0.3 V to DAC OUTV+ xx + 0.3 V

Analog Inputs to AGND −0.3 V to AVDD + 0.3 V

Operating Temperature Range −40°C to +105°C

Storage Temperature Range −65°C to +150°C

Junction Temperature (TJ MAX) 150°C

ESD, Human Body Model 1 kV

Reflow Soldering Peak

Temperature

260°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

To conform with IPC-2221 industrial standards, it is advisable

to use conformal coating on the high voltage pins.

THERMAL RESISTANCE

Table 6. Thermal Resistance

Package Type θJA θ

JC Unit

64-Lead TQFP 54 16 °C/W

ESD CAUTION

1 Transient currents of up to 100 mA do not cause SCR latch-up.

AD7294-2 Data Sheet

Rev. 0 | Page 10 of 44

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

2, 61 RS2(−), RS1(−) Connection for External Shunt Resistor.

3, 60 RS2(+), RS1(+) Connection for External Shunt Resistor.

1, 4, 5, 8,

16, 17, 25,

32, 33, 57

59, 64

NC This pin has no internal connection.

14 FACTORY TEST

Factory Test Pin. To maintain pin compatibility with the AD7294, this pin can tolerate being connected to

voltages of up to 5.5 V.

56 AVDD Analog Supply Pin. The operating range is 4.5 V to 5.5 V. This pin provides the supply voltage for all the

analog circuitry on the AD7294-2. This supply should be decoupled to AGND with one 10 μF tantalum

capacitor and a 0.1 μF ceramic capacitor.

6, 7, 13,

24, 34,

55, 58

AGND1 to AGND7 Analog Ground. Ground reference point for all analog circuitry on the AD7294-2. Refer all analog input

signals and any external reference signal to this AGND voltage. Connect all seven of these AGND pins to

the AGND plane of the system. Note that AGND5 is a DAC ground reference point and should be used as

a star ground for circuitry being driven by the DAC outputs. Ideally, the AGND and DGND voltages should

be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

9, 12 D2(−), D1(−) Temperature Sensor Analog Inputs. These pins are connected to the external temperature sensing

transistor. See Figure 43 and Figure 44.

10, 11 D2(+), D1(+) Temperature Sensor Analog Inputs. These pins are connected to the external temperature sensing

transistor. See Figure 43 and Figure 44.

15 REFOUT/REFIN DAC DAC Reference Output/Input Pin. The REFOUT/REFIN DAC pin is common to all four DAC channels. On

power-up, the default configuration of this pin is as an external reference (REFIN). Enable the internal

reference by writing to the power-down register; see Table 27. Decoupling capacitors (220 nF

recommended) are connected to this pin to decouple the reference buffer. If the output is buffered, the

on-chip reference can be taken from this pin and applied externally to the rest of a system. A maximum

external reference voltage of AVDD − 2 V can be supplied to the REFOUT portion of the REFOUT/REFIN DAC pin.

AGND3

FACTORY TEST

REF

OUT

/REF

DAC

DGND

SENSE

1 OVE R RANGE

SENSE

2 OVE R RANGE

RESET

DGND

DRIVE

OPGND

SCL

SDA

AS0

AS1

AS2

ALERT/BUSY

AGND5

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

RS1(–)

RS1(+)

AGND6

AGND7

DCAP

REF

OUT

/REF

ADC

RS2(–)

RS2(+)

AGND1

AGND2

D2(–)

D2(+)

D1(+)

D1(–)

PIN 1

INDICATOR

NOTES

1. NC = NO INTE RN

L CONNECTI ON.

AD7294-2

TQFP

TOP VIEW

(Not to Scale)

DAC OUT GND CD

OFFSET IN A

OFFSET IN B

OFFSET IN C

OFFSET IN D

OUT

DAC OUT GNDAB

DAC OUTV+AB

AGND4

DAC OUTV+ CD

10936-005

Data Sheet AD7294-2

Rev. 0 | Page 11 of 44

Pin No. Mnemonic Description

18, 23,

26, 31

OFFSET IN A to

OFFSET IN D

DAC Analog Offset Input Pins. These pins set the desired output range for each DAC channel. The DACs

have an output voltage span of 5 V, which can be shifted from 0 V to 5 V to a maximum output voltage of

10 V to 15 V by supplying an offset voltage to these pins. These pins can be left floating, in which case

decouple them to AGND with a 100 nF capacitor.

19, 22,

27, 30

VOUTA to VOUTD Buffered Analog DAC Outputs for Channel A to Channel D. Each DAC analog output is driven from an

output amplifier that can be offset using the OFFSET IN x pin. The DAC has a maximum output voltage

span of 5 V that can be level shifted to a maximum output voltage level of 15 V. Each output is capable of

sourcing and sinking 10 mA and driving a 10 nF load.

20, 29 DAC OUT GND AB,

DAC OUT GND CD

Analog Ground. Analog ground pins for the DAC output amplifiers on VOUTA and VOUTB, and VOUTC and

VOUTD, respectively.

21, 28 DAC OUTV+ AB,

DAC OUTV+ CD

Analog Supply. Analog supply pins for the DAC output amplifiers on VOUTA and VOUTB, and VOUTC and

VOUTD, respectively. The operating range is 4.5 V to 16.5 V.

35 ALERT/BUSY

Digital Output. Selectable as an alert or busy output function in the configuration register. This is an

open-drain output. An external pull-up resistor is required.

When configured as an alert, this pin acts as an out-of-range indicator and becomes active when the

conversion result violates the DATAHIGH or DATALOW register values. See the Alert Status Registers section.

When configured as a busy output, this pin becomes active when a conversion is in progress.

38, 37, 36 AS0, AS1, AS2 Digital Logic Inputs. Together, the logic state of these inputs selects a unique I2C address for the AD7294-2.

See Table 34 for more information.

39 SDA Digital Input/Output. Serial bus bidirectional data; external pull-up resistor required.

40 SCL Serial I2C Bus Clock. The data transfer rate in I2C mode is compatible with both 100 kHz and 400 kHz

operating modes. Open-drain input; external pull-up resistor required.

41 OPGND Dedicated Ground Pin for I2C Interface.

42 VDRIVE Logic Power Supply. The voltage supplied at this pin determines at what voltage the interface operates.

Decouple this pin to DGND. The voltage range on this pin is 2.7 V to 5.5 V; it may be different from the

voltage level at AVDD but should never exceed it by more than 0.3 V. To set the input and output

thresholds, connect this pin to the supply to which the I2C bus is pulled.

43, 47, 48 DGND Digital Ground. This pin is the ground for all digital circuitry.

44 RESET Reset. Taking RESET low performs a reset of the I2C interface logic. The logic input threshold of the pin is

set by VDRIVE (Pin 42). To maintain pin compatibility with the AD7294, this pin can tolerate being connected to

voltages of up to 5.5 V.

46, 45 ISENSE1 OVERRANGE,

ISENSE2 OVERRANGE

Fault Comparator Outputs. These pins connect to the high-side current sense amplifiers.

49, 50,

51, 52

VIN3 to VIN0 Uncommitted ADC Analog Inputs. These pins are programmable as four single-ended channels or two

true differential analog input channel pairs. See Table 2 and Table 10 for more information.

53 REFOUT/REFIN ADC ADC Reference Output/Input Pin. The REFOUT/REFIN ADC pin provides the reference source for the ADC.

On power-up, the default configuration of this pin is as an external reference (REFIN). Enable the internal

reference by writing to the power-down register (see Table 27). Connect decoupling capacitors (220 nF

recommended) to this pin to decouple the reference buffer. If the output is buffered, the on-chip

reference can be taken from this pin and applied externally to the rest of a system. A maximum external

reference voltage of 2.5 V can be supplied to the REFOUT portion of this pin.

54 DCAP External Decoupling Capacitor Input for Internal Temperature Sensor. Decouple this pin to AGND using

a 0.1 μF capacitor. In normal operation, the voltage is typically 1.25 V.

62, 63 VPP1, VPP2 Current Sensor Supply Pins. Power supply pins for the high-side current sense amplifiers. The operating

range is from AVDD to 59.4 V. Decouple these supplies to AGND. Refer to the Current Sense Filtering section

for more information about using these pins.

AD7294-2 Data Sheet

Rev. 0 | Page 12 of 44

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. Signal-to-Noise Ratio, Single-Ended Input, VREF Range

Figure 6. Signal-to-Noise Ratio, Single-Ended Input, 2 × VREF Range

Figure 7. Signal-to-Noise Ratio, Differential Input, VREF Range

Figure 8. Signal-to-Noise Ratio, Differential Input, 2 × VREF Range

Figure 9. ADC INL, Single-Ended Input, VREF Range

Figure 10. ADC DNL, Single-Ended Input, VREF Range

10936-105

–20

–40

–60

–80

–100

–120

–140 010000

8000

6000

40002000

AMPLITUDE (dB)

FRE QUENCY ( kHz )

AVDD = 5V, VDRIVE = 5V

VREF RANGE

SAMPLE

= 20kSPS

SIGNAL

= 10303Hz

SINGLE-ENDED

10936-106

–20

–40

–60

–80

–100

–120

–140 01000080006000

40002000

AMPLITUDE (dB)

FRE QUENCY ( kHz )

AVDD = 5V, VDRIVE = 5V

2 × VREF RANG E

SAMPLE

= 20kSPS

SIGNAL

= 10303Hz

SINGLE-ENDED

10936-107

–20

–40

–60

–80

–100

–120

–140 0100008000600040002000

AMPLITUDE (dB)

FRE QUENCY ( kHz )

AVDD = 5V, VDRIVE = 5V

VREF RANGE

SAMPLE

= 20kSPS

SIGNAL

= 10303Hz

DIFFERENTIAL

10936-108

–20

–40

–60

–80

–100

–120

–140 0100008000600040002000

AMPLITUDE (dB)

FRE QUENCY ( kHz )

AVDD = 5V, VDRIVE = 5V

2 × VREF RANG E

SAMPLE

= 20kSPS

SIGNAL

= 10303Hz

DIFFERENTIAL

10936-109

1.00

0.50

0.75

0.25

–0.25

–0.50

–0.75

–1.00 04095

30002000

1000500

INL (LSB)

CODE

= 5V, V

DRIVE

= 5V

REF

RANGE

350025001500

10936-110

1.00

0.75

0.50

0.25

–0.25

–0.50

–0.75

–1.00 04095

300020001000500

DNL ( LSB)

CODE

= 5V, V

DRIVE

= 5V

REF

RANGE

3500

25001500

Data Sheet AD7294-2

Rev. 0 | Page 13 of 44

Figure 11. ADC INL, Single-Ended Input, 2 × VREF Range

Figure 12. ADC DNL, Single-Ended Input, 2 × VREF Range

Figure 13. ADC INL, Differential Input, VREF Range

Figure 14. ADC INL, Differential Input, VREF Range

Figure 15. ADC DNL, Differential Input, 2 × VREF Range

Figure 16. ADC DNL, Differential Input, 2 × VREF Range

10936-111

1.00

0.50

0.75

0.25

–0.25

–0.50

–0.75

–1.00 04095

3000

2000

1000500

INL (LSB)

CODE

= 5V, V

DRIVE

= 5V

2 × V

REF

RANGE

35002500

1500

10936-112

1.00

0.75

0.50

0.25

–0.25

–0.50

–0.75

–1.00 04095

3000

20001000500

DNL ( LSB)

CODE

= 5V, V

DRIVE

= 5V

2 × V

REF

RANGE

35002500

1500

10936-113

1.00

0.50

0.75

0.25

–0.25

–0.50

–0.75

–1.00 04095

30002000

1000500

INL (LSB)

CODE

= 5V, V

DRIVE

= 5V

REF

RANGE

3500

25001500

10936-115

1.00

0.50

0.75

0.25

–0.25

–0.50

–0.75

–1.00 04095

300020001000500

INL (LSB)

CODE

= 5V, V

DRIVE

= 5V

2 × V

REF

RANGE

3500

25001500

10936-114

1.00

0.75

0.50

0.25

–0.25

–0.50

–0.75

–1.00 04095

3000

20001000

500

DNL ( LSB)

CODE

= 5V, V

DRIVE

= 5V

2 × V

REF

RANGE

350025001500

10936-116

1.00

0.75

0.50

0.25

–0.25

–0.50

–0.75

–1.00 04095

300020001000500

DNL ( LSB)

CODE

= 5V, V

DRIVE

= 5V

2 × V

REF

RANGE

3500

25001500

AD7294-2 Data Sheet

Rev. 0 | Page 14 of 44

Figure 17. ADC INL vs. Reference Voltage

Figure 18. ADC DNL vs. Reference Voltage

Figure 19. DAC INL

Figure 20. DAC DNL

Figure 21. 0.1 Hz to 10 Hz DAC Output Noise, Input Code = 0x800

Figure 22. Settling Time for a ¼ to ¾ Output Voltage Step

–1.5

–1.0

–0.5

INL (LSB)

0.5

1.0

1.5

012 3

REFERENCE VOLTAGE (V)

456

MAX INL

MIN INL

= 5V

DRIVE

= 5V

10936-117

DNL (LSB)

012 3

REFERENCE VOLTAGE (V)

456

MAX DNL

MIN DNL

10936-118

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

= 5V

DRIVE

= 5V

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

256

512

768

1024

INL ERRO R ( LSB)

CODE

1280

1536

1792

2048

2304

2560

2816

3072

3328

3584

3840

10936-119

–0.6

–0.4

–0.2

0.2

0.4

0.6

256

512

768

1024

1280

1536

1792

2048

2304

2560

2816

3072

3328

3584

3840

DNL ERRO R ( LSB)

CODE

10936-120

10936-121

CH1 20µV M1.00s A CH4 1.02V

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0510 15

4914

3813

2712

1611

DAC OUTPUT VOLTAGE (V)

TIME (µs)

0nF

1nF

10nF

10936-122

Data Sheet AD7294-2

Rev. 0 | Page 15 of 44

Figure 23. Zoomed-In Settling Time for a ¼ to ¾ Output Voltage Step

Figure 24. DAC Sinking Current at Input Code = 0x000, (VOUT = 0 V)

Figure 25. DAC Sourcing Current at Input Code = 0xFFF, (VOUT = AVDD)

Figure 26. DAC Output Voltage vs. Load Current, Input Code = 0x800

Figure 27. Response of Temperature Sensor to a Step Function

Figure 28. Temperature Error vs. Capacitance from Dx(+) to Dx(−)

3.750

3.752

3.754

3.756

3.758

3.760

0 5 10 151 6 11 162 7 12 173 8 13 184 9 14 19 20

DAC OUT P UT VO LTAGE (V)

TIME (µs)

10936-123

0nF

1nF

10nF

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0 5 10 15 20 25 30 35 40

OUT

(V)

SINK CURRE NT (mA)

10936-124

–1.0

–0.9

–0.8

–0.7

–0.6

–0.5

–0.4

–0.3

–0.2

–0.1

0 5 10 15 20 25 30 35 40

VOUT (V)

SOURCE CURRE NT (mA)

10936-125

–100

–80

–60

–40

–20

100

–50 –40 –30 –20 –10 010 20 30 40 50

CHANGE IN OUTPUT V OLTAGE (mV)

LO AD CURRE NT (mA)

10936-126

–0.1 00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

TEMPERAT URE RE ADING ( °C)

TIME (Seconds)

10936-127

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

00.5 1.0 1.5 2.0 2.5

ERRO R ( °C)

CAPACITANCE FROM Dx( + ) TO Dx(–) ( nF)

10936-128

AD7294-2 Data Sheet

Rev. 0 | Page 16 of 44

Figure 29. Temperature Error vs. Series Resistance

Figure 30. Frequency Response of the High-Side Current Sensor

Figure 31. ISENSE Power Supply Rejection Ratio (PSRR) vs. Supply Ripple

Frequency Without VPP Supply Decoupling Capacitors for a 500 mV Ripple

–1.0

–0.9

–0.8

–0.7

–0.6

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

02 4 6 8 10 12 14 16

ERRO R ( °C)

SERIES RESISTANCE (kΩ)

10936-129

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

100 1k 10k 100k 1M 10M 100M

AMPLITUDE (dB)

FREQUENCY (Hz)

10936-130

–120

–110

–100

–90

–80

–70

–60

–50

1k 10k 100k 1M 10M

PSRR ( dB)

FREQUENCY (Hz)

10936-131

Data Sheet AD7294-2

Rev. 0 | Page 17 of 44

TERMINOLOGY

DAC TERMINOLOGY

Relative Accuracy

A measure of the maximum deviation, in LSBs, from a straight

line passing through the endpoints of the DAC transfer function.

Differential Nonlinearity (DNL)

The difference between the measured change and the ideal 1 LSB

change between any two adjacent codes. A specified differential

nonlinearity of ±1 LSB maximum ensures monotonicity. This

DAC is guaranteed monotonic by design.

Zero Code Error

A measure of the output error when zero code (0x0000) is

loaded to the DAC register. Ideally, the output should be 0 V.

The zero code error is always positive in the AD7294-2 because

the output of the DAC cannot go below 0 V. Zero code error is

expressed in mV.

Full-Scale Error

A measure of the output error when full-scale code (0xFFFF) is

loaded to the DAC register. Ideally, the output should be VDD −

1 LSB. Full-scale error is expressed in mV.

Gain Error

A measure of the span error of the DAC. It is the deviation in

slope of the DAC transfer characteristic from ideal, expressed

as a percent of the full-scale range (% FSR).

Gain Error Drift

A measure of the change in gain error with changes in tem-

perature. It is expressed in (ppm of full-scale range)/°C.

ADC TERMINOLOGY

Signal-to-Noise-and-Distortion Ratio (SINAD)

The measured ratio of signal-to-noise and distortion at the

output of the ADC. The signal is the rms amplitude of the

fundamental. Noise is the sum of all nonfundamental signals

up to half the sampling frequency (fS/2), excluding dc. The

ratio is dependent on the number of quantization levels in the

digitization process; the more levels, the smaller the quantization

noise. The theoretical signal-to-noise-and-distortion ratio for

an ideal N-bit converter with a sine wave input is given by

Signal-to-Noise-and-Distortion = (6.02 N + 1.76) dB

Thus, the SINAD is 74 dB for an ideal 12-bit converter.

Total Harmonic Distortion (THD)

The ratio of the rms sum of harmonics to the fundamental. For

the AD7294-2, THD is defined as

THD 2

log20

)

dB( ++

where V1 is the rms amplitude of the fundamental and V2, V3,

V4, V5, and V6 are the rms amplitudes of the second through

sixth harmonics.

Integral Nonlinearity (INL)

The maximum deviation from a straight line passing through

the endpoints of the ADC transfer function. The endpoints are

zero scale, a point 1 LSB below the first code transition, and full

scale, a point 1 LSB above the last code transition.

Differential Nonlinearity (DNL)

The difference between the measured change and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Offset Error

The deviation of the first code transition (00…000) to

(00…001) from the ideal—that is, AGND + 1 LSB.

Offset Error Match

The difference in offset error between any two channels.

Gain Error

The deviation of the last code transition (111 … 110 to

111 … 111) from the ideal (that is, REFIN − 1 LSB) after the

offset error has been adjusted out.

Gain Error Match

The difference in gain error between any two channels.

AD7294-2 Data Sheet

Rev. 0 | Page 18 of 44

THEORY OF OPERATION

ADC OVERVIEW

The AD7294-2 provides the user with a 9-channel multiplexer,

an on-chip track-and-hold, and a successive approximation ADC

based on four capacitive DACs. The analog input range for the

part can be selected as a 0 V to VREF input or a 2 × VREF input,

configured with either single-ended or differential analog inputs.

An on-chip 2.5 V reference can be disabled when an external

reference is preferred. If the internal ADC reference is to be used

elsewhere in a system, the output must first be buffered.

The various monitored and uncommitted input signals are multi-

plexed into the ADC. The AD7294-2 has four uncommitted analog

input channels, VIN0 to VIN3. These four channels allow single-

ended, differential, and pseudo differential mode measurements

of various system signals.

ADC TRANSFER FUNCTIONS

The designed code transitions occur at successive integer LSB

values (1 LSB, 2 LSB, and so on). In single-ended mode, the

LSB size is VREF/4096 when the 0 V to VREF range is used, and

2 × VREF/4096 when the 0 V to 2 × VREF range is used. The ideal

transfer characteristic for the ADC, when outputting straight

binary coding, is shown in Figure 32.

Figure 32. Single-Ended Transfer Characteristics

In differential mode, the LSB size is 2 × VREF/4096 when the 0 V

to VREF range is used, and 4 × VREF/4096 when the 0 V to 2 × VREF

range is used. The ideal transfer characteristic for the ADC, when

outputting twos complement coding, is shown in Figure 33

(with the 2 × VREF range).

Figure 33. Differential Transfer Characteristics with VREF ± VREF Input Range

For VIN0 to VIN3 in single-ended mode, the output code is

straight binary, where

VIN = 0 V, D OUT = x000, VIN = VREF − 1 LSB, and DOUT = 0xFFF

In differential mode, the code is twos complement, where

VIN+ − VIN− = 0 V, a n d D OUT = 0x00

VIN+ − VIN− = VREF − 1 LSB, and DOUT = 00x7FF

VIN+ − VIN− = −VREF, and DOUT = 0x800

Channel 5 and Channel 6 (current sensor inputs) are twos

complement, where

VIN+ − VIN− = 0 m V, and DOUT = 0x000

VIN+ − VIN− = VREF/12.5 − 1 LSB, and DOUT = 0x7FF

VIN+ − VIN− = −VREF/12.5, and DOUT = 0x800

Channel 7 to Channel 9 (temperature sensor inputs) are twos

complement with the LSB equal to 0.25°C, where

TIN = 0°C, and DOUT = 0x000

TIN = +255.75°C, and DOUT = 0x7FF

TIN = −256°C, and DOUT = 0x800

000...000

111...111

1LS B = V

REF

/4096

1LSB V

REF

– 1LS B

ANALOG INPUT

ADC CODE

000...001

000...010

111...110

111...000

011...111

NOTE

1. V

REF

IS EIT HER V

REF

OR 2 × V

REF

10936-016

100...000

011...111

1LSB = 2 × V

REF

/4096

REF

– 1LSB–V

REF

+ 1LS B V

REF

– 1LSB

ANALO G INP UT

ADC CODE

100...001

100...010

011...110

000...001

000...000

111...111

10936-017

Data Sheet AD7294-2

Rev. 0 | Page 19 of 44

ANALOG INPUTS

The AD7294-2 has four analog inputs, VIN3 to VIN0. Depending

on the configuration register setup, they can be configured as

two single-ended inputs, two pseudo differential channels, or

two fully differential channels (see the Register Settings section).

Single-Ended Mode

The AD7294-2 can have four single-ended analog input channels.

In applications where the signal source has high impedance, it is

recommended that the analog input be buffered before it is applied

to the ADC. The analog input range can be programmed to either

of the following modes: 0 V to VREF or 0 V to 2 × VREF. In 2 × VREF

mode, the input is effectively divided by 2 before the conversion

takes place. Note that the voltage, with respect to GND on the

ADC analog input pins, cannot exceed AVDD.

If the analog input signal to be sampled is bipolar, the internal

reference of the ADC can be used to externally bias up this

signal so that it is correctly formatted for the ADC. Figure 34

shows a typical connection diagram when operating the ADC

in single-ended mode.

Figure 34. Single-Ended Mode Connection Diagram

Differential Mode

The AD7294-2 can have two differential analog input pairs.

Differential signals have some benefits over single-ended

signals, including noise immunity based on the common-

mode rejection of the device and improvements in distortion

performance. Figure 35 defines the fully differential analog

input of the AD7294-2.

Figure 35. Differential Input Definition

The amplitude of the differential signal is the difference between

the signals applied to VIN+ and VIN− in each differential pair

(VIN+ − VIN−). The resulting converted data is stored in twos

complement format in the result register.

Simultaneously drive VIN0 and VIN1 by two signals, each of

amplitude VREF (or 2 × VREF, depending on the range chosen), that

are 180° out of phase.

Assuming that the 0 V to VREF range is selected, the amplitude

of the differential signal is, therefore, −VREF to +VREF peak-to-

peak (2 × VREF), regardless of the common-mode voltage (VCM).

The common-mode voltage is the average of the two signals.

(VIN+ + VIN−)/2

The common-mode voltage is, therefore, the voltage on which

the two inputs are centered.

The result is that the span of each input is VCM ± VREF/2. This

common-mode voltage must be set up externally, and its range

varies with the reference value, VREF. As the value of VREF

increases, the common-mode range decreases. When driving the

inputs with an amplifier, the actual common-mode range is

determined by the output voltage swing of the amplifier.

The common-mode voltage must be within this common-mode

range to guarantee the functionality of the AD7294-2.

When a conversion takes place, the common-mode voltage is

rejected, resulting in a virtually noise-free signal of amplitude

−VREF to +VREF, corresponding to the digital output codes of

−2048 to +2047 in twos complement format.

If the 2 × VREF range is used, the input signal amplitude extends

from −2 × VREF (VIN+ = 0 V, V IN− = VREF) to +2 × VREF (VIN− = 0 V,

VIN+ = VREF).

Driving Differential Inputs

The differential modes that are available on VIN0 to VIN3 (see

Table 10) require that VIN+ and VIN− be driven simultaneously

with two equal signals that are 180° out of phase. The common-

mode voltage on which the analog input is centered must be set

up externally. The common-mode range is determined by VREF,

the power supply, and the particular amplifier used to drive the

analog inputs. Differential modes of operation with either an ac

or dc input provide the best THD performance over a wide

frequency range. Because not all applications have a signal that

is preconditioned for differential operation, there is often a need

to perform a single-ended-to-differential conversion.

Using an Op Amp Pair

An op amp pair can be used to directly couple a differential signal

to one of the analog input pairs of the AD7294-2. The circuit

configuration that is illustrated in Figure 38 shows how a dual

op amp can be used to convert a single-ended bipolar signal into

a differential unipolar input signal.

The voltage applied to Point A sets up the common-mode voltage.

As shown in Figure 38, Point A connects to the reference, but any

value in the common-mode range can be the input at Point A to

set up the common-mode voltage. The AD8022 is a suitable dual

op amp that can be used in this configuration to provide

differential drive to the AD7294-2.

+1.25V

–1.25V

REF

OUT

ADC

AD7294-2

+2.5V

0.47µF

ADDITIONAL PINS OMITTED FOR CLARITY.

10936-018

IN+

AD7294-2

IN–

REF

p-p

REF

p-p

COMMON-MODE

VOLTAGE

ADDITIONAL PINS OMITTED FOR CLARITY.

10936-019

AD7294-2 Data Sheet

Rev. 0 | Page 20 of 44

Care is required when choosing the op amp because the selection

depends on the required power supply and system performance

objectives. The driver circuit in Figure 38 is optimized for dc

coupling applications that require best distortion performance.

The differential op amp driver circuit shown in Figure 38 is

configured to convert and level shift a single-ended, ground

referenced (bipolar) signal to a differential signal that is centered

at the VREF level of the ADC.

Pseudo Differential Mode

The four uncommitted analog input channels can be configured

as two pseudo differential pairs. Two uncommitted inputs, VIN0

and VIN1, are a pseudo differential pair, as are VIN2 and VIN3. In

this mode, VIN+ is connected to the signal source, which can have

a maximum amplitude of VREF (or 2 × VREF, depending on the

range that is chosen) to make use of the full dynamic range of

the part. A dc input is applied to VIN−. The voltage applied to this

input provides an offset from ground or a pseudo ground for the

VIN+ input. The channel specified as VIN+ is determined by the

ADC channel allocation. The differential mode must be selected

to operate in the pseudo differential mode. The resulting converted

pseudo differential data is stored in twos complement format in the

result register.

For VIN0, the governing equation for the pseudo differential

mode is

VOUT = 2(VIN+ − VIN−) − VREF_ADC

where VIN+ is the single-ended signal and VIN− is a dc voltage.

The benefit of pseudo differential inputs is that they separate

the analog input signal ground from the ADC ground, allowing

dc common-mode voltages to be cancelled.

Figure 36 shows the typical voltage range for VIN− while in

pseudo differential mode, and Figure 37 shows a connection

diagram for pseudo differential mode.

Figure 36. VIN− Input Range vs. VREF in Pseudo Differential Mode

Figure 37. Pseudo Differential Mode Connection Diagram

CURRENT SENSOR

Two bidirectional high-side current sense amplifiers are

provided that can accurately amplify differential current shunt

voltages in the presence of high common-mode voltages from

AVDD up to 59.4 V. Each amplifier can accept a ±200 mV

differential input. Both current sense amplifiers have a fixed

gain of 12.5 and use an internal 2.5 V reference.

An analog comparator is also provided with each amplifier for

fault detection. The threshold is defined as

1.2 × Full-Scale Voltage Range

Figure 38. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal into a Differential Unipolar Signal

2.5

2.0

1.0

0.5

–0.5

VIN– (V)

VREF (V)

10936-137

1.5

1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5

AVDD = 5V

VDRIVE = 5V

DC INP UT

VOLTAGE

REF

p-p

REF

OUT

/REF

ADC

IN+

AD7294-2

IN–

0.47µF

ADDITIONAL PINS OMITTED FOR CLARITY.

10936-026

20kΩ

220kΩ

2 × V

REF

p-p

27Ω

V+

V–

V+

V–

GND

2.5V

3.75V

1.25V

2.5V

3.75V

1.25V REF

OUT

ADC

IN+

AD7294-2

IN–

440Ω

220Ω

0.47µF

ADDITIONAL PINS OMITTED FOR CLARITY.

220Ω

10kΩ

10936-023

Data Sheet AD7294-2

Rev. 0 | Page 21 of 44

When this limit is reached, the output is latched onto a dedicated

pin. This output remains high until the latch is cleared by writing

to the appropriate register.

Figure 39. High-Side Current Sense

The AD7294-2 current sense comprises two main blocks:

a differential and an instrumentation amplifier. A load current

flowing through the external shunt resistor produces a voltage

at the input terminals of the AD7294-2. Resistors R1 and R2

connect the input terminals to the differential amplifier (A1).

A1 nulls the voltage that appears across its own input terminals

by adjusting the current through R1 and R2 with Transistors Q1

and Q2. Common-mode feedback maintains the sum of these

currents at approximately 50 μA. When the input signal to the

AD7294-2 is zero, the currents in R1 and R2 are equal. When the

differential signal is nonzero, the current increases through one

of the resistors and decreases in the other. The current difference is

proportional to the size and polarity of the input signal.

The differential currents through Q1 and Q2 are converted into

a differential voltage by R3 and R4. A2 is configured as an instru-

mentation amplifier, buffering this voltage and providing additional

gain. Therefore, for an input voltage of ±200 mV at the pins, an

output span of ±2.5 V is generated.

The current sensors on the AD7294-2 are designed to remove

any flicker noise and offset that are present in the sensed signal.

This is achieved by using a chopping technique that is transparent

to the user. The VSENSE signal is first converted by the AD7294-2,

the analog inputs to the amplifiers are then swapped, and the

differential voltage is once again converted by the AD7294-2.

The two conversion results enable the digital removal of any

offset or noise. Switches on the amplifier inputs enable this

chopping technique to be implemented. The process typically

requires 6 μs, in total, to return a final result.

Choosing RSENSE

The resistor values used in conjunction with the current sense

amplifiers are determined by the specific application requirements

in terms of voltage, current, and power. Small resistors minimize

power dissipation, have low inductance to prevent any induced

voltage spikes, and provide good tolerance, which reduces current

variations. The final values chosen are a compromise between

low power dissipation and good accuracy. Low value resistors

have less power dissipated in them, but higher value resistors may

be required to use the full input range of the ADC, thus achieving

maximum SNR performance.

When the sense current is known, the voltage range of the

AD7294-2 current sensor (200 mV) is divided by the maximum

sense current to yield a suitable shunt value. If the power dissi-

pation in the shunt resistor is too large, the size of the shunt

resistor can be reduced; in this case, less of the ADC input range

is used. Using less of the ADC input range produces conversion

results that are more susceptible to noise and offset errors because

offset errors are fixed and are, thus, more significant when

smaller input ranges are used.

RSENSE must be able to dissipate the I2R losses. If the power dis-

sipation rating of the resistor is exceeded, its value may drift or

the resistor may be damaged, resulting in an open circuit. This

open circuit can cause a differential voltage across the terminals

of the AD7294-2 in excess of the absolute maximum ratings.

Additional protection is afforded to the current sensors on the

AD7294-2 by the recommended current limiting resistors,

RF1 and RF2, as shown in Figure 40. The AD7294-2 can handle

a maximum continuous current of 30 mA; thus, an RF2 of 1 kΩ

provides adequate protection for the AD7294-2.

If ISENSE has a large high frequency component, take care to choose

a resistor with low inductance. Low inductance metal film resistors

are best suited for these applications.

Current Sense Filtering

In some applications, it may be desirable to use external filtering to

reduce the input bandwidth of the amplifier (see Figure 40).

The −3 dB differential bandwidth of this filter is equal to

BWDM = 1/(4 × π × RC)

Note that the maximum series resistance on the RS(+) and

RS(−) inputs (see Figure 39) is limited to a maximum of 1 kΩ

due to back-to-back ESD protection diodes from RS(+) and

RS(−) to VPPx. Also, note that if RF1 and RF2 are in series with

R1 and R2 (see Figure 39), the gain of the amplifier is affected. Any

mismatch between RF1 and RF2 can introduce an offset error.

Figure 40. Current Sense Filtering (RSx Can Be Either RS1 or RS2)

For certain RF applications, the optimum value for RF1 and RF2

is 1 kΩ, whereas CF can range from 1 μF to 10 μF. There is an

additional decoupling capacitor for the VPPx supply. Its value is

application dependent, but for initial evaluation, values in the

range of 1 nF to 100 nF are recommended.

AD7294-2

TO 59.4V

RSx(+)

SENSE

LOAD

RSx(–)

40kΩ R2

40kΩ

100kΩ R4

100kΩ

Q1 Q2

OUT

TO MUX

10936-029

10936-098

RF1 RF2

AD7294-2

VPP RSENSE ILOAD

RSx(–)RSx(+)

10nF

VPPx

AD7294-2 Data Sheet

Rev. 0 | Page 22 of 44

Kelvin Sense Resistor Connection

When using a low value sense resistor for high current

measurement, the problem of parasitic series resistance can

arise. The lead resistance can be a substantial fraction of the

rated resistance, making the total resistance a function of lead

length. Avoid this problem by using a Kelvin sense connection.

This type of connection separates the current path through the

resistor and the voltage drop across the resistor. Figure 41 shows

the correct way to connect the sense resistor between the RS(+)

and RS(−) pins of the AD7294-2.

Figure 41. Kelvin Sense Connections (RSx Can Be Either RS1 or RS2)

ANALOG COMPARATOR LOOP

The AD7294-2 contains two setpoint comparators that are used

for independent analog control. This circuitry enables users to

quickly detect if the sensed voltage across the shunt resistor has

increased above the preset (VREF × 1.2)/12.5. If this increase occurs,

the ISENSEx OVERRANGE pin is set to a high logic level, enabling

appropriate action to be taken to prevent any damage to the

external circuitry.

The setpoint threshold level is fixed internally in the AD7294-2,

and the current sense amplifier saturates above this level. The

comparator is also triggered if a voltage of less than AVDD is

applied to the RSENSE resistor or the VPPx pin.

TEMPERATURE SENSOR

The AD7294-2 contains one local and two remote temperature

sensors. The temperature sensors continuously monitor the

three temperature inputs, and new readings are automatically

available every 5 ms.

The on-chip, band gap temperature sensor measures the temper-

ature of the system. Diodes are used in conjunction with the two

remote temperature sensors to monitor the temperature of other

critical board components.

The temperature sensor module on the AD7294-2 is based

on the three-current principle (see Figure 42), where three

currents are passed through a diode and the forward voltage

drop is measured at each diode, allowing the temperature to be

calculated free of errors caused by series resistance.

Figure 42. Internal and Remote Temperature Sensors

Each input integrates, in turn, over a period of several hundred

microseconds (µs). This integration takes place continuously in

the background, leaving the user free to perform conversions on

the other channels. When the integration is complete, a signal

passes to the control logic to initiate a conversion automatically.

If the ADC is in command mode, the temperature conversion is

performed as soon as the next conversion is completed. In auto-

cycle mode, the conversion is inserted into an appropriate place

in the current sequence (see the Register Settings section for

further details. If the ADC is idle, the conversion takes place

immediately.

Three registers store the result of the last conversion on each

temperature channel; these can be read at any time. In addition,

in command mode, one or both of the two external channel

registers can be read out as part of the output sequence.

Remote Sensing Diode

The AD7294-2 is designed to work with discrete transistors,

2N3904 and 2N3906. If an alternative transistor is used, the

AD7294-2 operates as specified, provided that the conditions

explained in the following sections are adhered to.

Ideality Factor

The ideality factor of the transistor, nf, is a measure of the deviation

of the thermal diode from ideal behavior. The AD7294-2 is

trimmed for an nf value of 1.008. Use the following equation to

calculate the error introduced at a Temperature T (°C) when

using a transistor whose nf does not equal 1.008:

ΔT = (nf − 1.008) × (273.15 K + T)

To factor in this error, the user can write the ∆T value to the

offset register. The AD7294-2 automatically adds it to, or

subtracts it from, the temperature measurement.

Base Emitter Voltage

The AD7294-2 operates as specified if the base emitter voltage is

greater than 0.25 V at 8 µA at the highest operating temperature,

and less than 0.95 V at 128 µA for the lowest operating tem-

perature.

SENSE RESISTOR

CURRENT

FLOW FROM

SUPPLY

CURRENT

FLOW TO

LOAD

KELVIN

SENSE

TRACES

AD7294-2

RSx(+) RSx(–)

10936-031

LIMIT

REGISTERS

TEMP

SENSOR

T1 T2

ALERT

D2+

D2–

D1+

D1–

AD7294-2

DCAP

REMOTE

SENSING

TRANSISTORS

16 × I II-BIAS

MUX

BIAS DIO DE

TO ADC

4 × I

= 65kHz

LPF

10936-032

Data Sheet AD7294-2

Rev. 0 | Page 23 of 44

hFE Variation

Use a transistor with little variation in hFE (~50 to 150). Little

variation in hFE indicates tight control of the VBE characteristics.

For RF applications, the use of high Q capacitors, functioning as

a filter, protects the integrity of the measurement. Connect these

capacitors, such as Johanson Technology 10 pF, high Q capacitors,

Reference Code 500R07S100JV4T, between the base and the

emitter, as close to the external device as possible. However, large

capacitances affect the accuracy of the temperature measurement;

thus, the recommended maximum capacitor value is 100 pF. In

most cases, a capacitor is not required; the selection of any capa-

citor is dependent on the noise frequency level.

Figure 43. Measuring Temperature Using an NPN Transistor

Figure 44. Measuring Temperature Using a PNP Transistor

Series Resistance Cancellation

The AD7294-2 is designed to automatically cancel out the effect

of parasitic, base, and collector resistance on the temperature

reading. This feature provides a more accurate result, without

the need for any user characterization of the parasitic resistance.

The AD7294-2 can compensate for up to 10 kΩ in a process

that is transparent to the user.

DAC OPERATION

The AD7294-2 contains four 12-bit DACs that provide digital

control with 12 bits of resolution and a 2.5 V internal reference.

The DAC core is a thin film 12-bit string DAC with a 5 V output

span and an output buffer that can drive the high voltage output

stage. The DAC has a span of 0 V to 5 V with a 2.5 V reference

input. The output range of the DAC, which is controlled by the

offset input, can be positioned from 0 V to 15 V.

Resistor String

The resistor string structure is shown in Figure 45. It consists of

a string of 2n resistors, each of Value R. The code loaded to the

DAC register determines at which node on the string the voltage

is tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string

to the amplifier. This architecture is inherently monotonic,

voltage out, and low glitch. It is also linear because all of the

resistors are of equal value.

Figure 45. Resistor String Structure

Output Amplifiers

The purpose of Op Amp A1 is to buffer the DAC output range

from 0 V to VREF. A second amplifier, Op Amp A2, is configured

such that when an offset is applied to OFFSET IN x, its output

voltage is 3× the offset voltage minus 2× the DAC voltage.

VOUT = 3 × VOFFSET – 2 × VDAC

The DAC word is digitally inverted on chip such that

VOUT = 3 × VOFFSET + 2 × (VDAC − VREF)

and VDAC =























REF

where:

VDAC is the output of the DAC before digital inversion.

D is the decimal equivalent of the binary code that is loaded to the

DAC register.

n is the bit resolution of the DAC.

An example of the offset function is given in Table 8.

Table 8. Offset Voltage Function Example

Offset

Voltage (V) VOUT with 0x000 (V) VOUT with 0xFFF (LSB)

1.67 0 5 V − 1

3.33 5 10 V − 1

5.00 10 15 V − 1

The user has the option of leaving the offset pin open, in which

case the voltage on the noninverting input of Op Amp A2 is set

by the resistor divider, giving

VOUT = 2 × VDAC

10936-099

2N3904

NPN

AD7294-2

D+

D–

10pF

10936-100

10pF

2N3906

PNP

AD7294-2

D+

D–

RTO OUTPUT

AMPLIFIERS

10936-028

AD7294-2 Data Sheet

Rev. 0 | Page 24 of 44

This configuration generates the 5 V output span from a 2.5 V

reference. Digitally inverting the DAC allows the circuit to

operate as a generic DAC when no offset is applied. If the offset

pin is not driven, it is best practice to place a 100 nF capacitor

between the pin and ground to improve both the settling time

and the noise performance of the DAC.

Note that a significant amount of power can be dissipated in the

DAC outputs.

ADC AND DAC REFERENCE

The AD7294-2 has two independent, internal, high performance

2.5 V references, one for the ADC and the other for the four

on-chip DACs. If the application requires an external reference,

it can be applied to the REFOUT/REFIN DAC pin and/or to the

REFOUT/REFIN ADC pin. Buffer the internal reference before

it is used by external circuitry. Decouple both the REFOUT/REFIN

DAC pin and the REFOUT/REFIN ADC pin to AGND, using a

220 nF capacitor. On power-up, the AD7294-2 is configured for

use with an external reference. To enable the internal references,

write a zero to both the D4 and D5 bits in the power-down register

(see the Register Settings section). Both the ADC and DAC

references require a minimum of 60 μs to power up and settle to

12-bit performance when a 220 nF decoupling capacitor is used.

The AD7294-2 can also operate with an external reference.

Suitable reference sources for the AD7294-2 include the AD780,

AD1582, ADR431, REF193, and ADR391. In addition, choosing

a reference with an output trim adjustment, such as the ADR441,

allows a system designer to trim system errors by setting a

reference voltage to a voltage other than the nominal.

Long-term drift is a measure of how much the reference drifts

over time. A reference with a low long-term drift specification

ensures that the overall solution remains stable during its entire

lifetime. If an external reference is used, select a low temperature

coefficient specification to reduce the temperature dependence

of the system output voltage on ambient conditions.

VDRIVE FEATURE

The AD7294-2 also has a VDRIVE feature to control the voltage at

which the I2C interface operates. The VDRIVE pin is connected to

the supply to which the I2C bus is pulled. This pin sets the input

and output threshold levels for the digital logic pins and the

ISENSEx OVERRANGE pins. The VDRIVE feature allows the AD7294-2

to easily interface to both 3 V and 5 V processors.

For example, if the AD7294-2 is operated with a VDD of 5 V, the

VDRIVE pin can be powered from a 3 V supply, allowing a large

dynamic range with low voltage digital processors. Thus, the

AD7294-2 can be used with the 2 × VREF input range with a VDD

of 5 V, yet it remains capable of interfacing to 3 V digital parts.

Decouple the VDRIVE pin to DGND with a 100 nF capacitor and

a 1 μF capacitor.

Data Sheet AD7294-2

Rev. 0 | Page 25 of 44

The AD7294-2 contains internal registers (see Figure 46) that

store conversion results, high and low conversion limits, and

information to configure and control the device.

Figure 46. Register Structure

Each data register has an address to which the address pointer

remainder of the addresses have both read and write access.

ADDRESS POINTER REGISTER

The address pointer register is an 8-bit register in which the

six LSBs are used as pointer bits to store an address that points

to one of the AD7294-2 data registers (see Table 9).

Table 9. Register Addresses

Address

Access

0x00 Command register W

0x01 ADC result register R

DACA value W

0x02 TSENSE1 result R

DACB value W

0x03 TSENSE2 result R

DACC value W

0x04

SENSE

INT result

DACD value W

0x05 Alert Status Register A R/W

0x06 Alert Status Register B R/W

0x07 Alert Status Register C R/W

0x08

Channel sequence register

R/W

0x09 Configuration register R/W

0x0A Power-down register R/W

0x0B DATALOW Register VIN0 R/W

0x0C DATAHIGH Register VIN0 R/W

0x0D Hysteresis Register VIN0 R/W

0x0E DATALOW Register VIN1 R/W

0x0F DATAHIGH Register VIN1 R/W

0x10 Hysteresis Register VIN1 R/W

0x11 DATALOW Register VIN2 R/W

0x12 DATAHIGH Register VIN2 R/W

0x13 Hysteresis Register VIN2 R/W

0x14 DATALOW Register VIN3 R/W

0x15 DATAHIGH Register VIN3 R/W

0x16 Hysteresis Register VIN3 R/W

0x17 DATALOW Register ISENSE1 R/W

0x18 DATAHIGH Register ISENSE1 R/W

0x19

Hysteresis Register I

SENSE

R/W

0x1A DATALOW Register ISENSE2 R/W

0x1B DATAHIGH Register ISENSE2 R/W

0x1C Hysteresis Register ISENSE2 R/W

0x1D DATALOW Register TSENSE1 R/W

0x1E DATAHIGH Register TSENSE1 R/W

0x1F Hysteresis Register TSENSE1 R/W

0x20 DATALOW Register TSENSE2 R/W

0x21 DATAHIGH Register TSENSE2 R/W

0x22 Hysteresis Register TSENSE2 R/W

0x23 DATALOW Register TSENSEINT R/W

0x24 DATAHIGH Register TSENSEINT R/W

0x25 Hysteresis Register TSENSEINT R/W

0x26 TSENSE1 offset register R/W

0x27 TSENSE2 offset register R/W

0x40 Factory test mode N/A

0x41 Factory test mode N/A

ADDRESS

POINTER

SERIAL BUS INTE RFACE SDA

SCL

DATA

COMMAND

ADC RESULT

DAC

REGISTERS

TSENSE RESULT

REGISTERS × 3

TSENSE OFFSET

REGISTERS × 2

ALE RT ST ATUS

REGISTERS × 3

CONFIGURATION

POWER-DOWN

HYSTERESIS

REGISTERS × 9

DATAHIGH/

DATALOW

REGISTERS × 1 8

CHANNEL

SEQUENCE

10936-039

AD7294-2 Data Sheet

Rev. 0 | Page 26 of 44

COMMAND REGISTER

A write to the command register (Address 0x00) puts the part

into command mode. In command mode, the part cycles through

the selected channels from LSB (Bit D0) to MSB (Bit D7) on each

subsequent read (see Table 11). A channel is selected for conversion

if a 1 is written to the desired bit in the command register. On

power-up, all bits in the command register are set to 0. If the

external TSENSE channels are selected in the command register

byte, it is not actually requesting a conversion. The result of the

last automatic conversion is output as part of the sequence (see

the Modes of Operation section).

If a command mode conversion is required while the autocycle

mode is active, it is necessary to disable the autocycle mode

before proceeding to the command mode (see the Autocycle

Mode section for more details).

ADC RESULT REGISTER

The ADC result register (Address 0x01) is a 16-bit, read only

inputs and the two ISENSE channels are stored in the result

Bit D14 to Bit D12 are the channel allocation bits, each of which

identifies the ADC channel that corresponds to the subsequent

result (see the ADC Channel Allocation section). Bit D11 to Bit D0

contain the most recent ADC result.

Bit D15 is reserved as an ALERT_FLAG bit. Table 12 lists the

contents of the first byte that is read from the AD7294-2 results

ADC Channel Allocation

The three channel address bits indicate which channel the result

in the result register represents. Table 10 describes the channel ID

bits (S.E. indicates single-ended, and DIFF indicates differential).

Table 10. ADC Channel Allocation

Function

Channel ID

CHID2 CHID1 CHID0

VIN0 (S.E.) or

VIN0 − VIN1 (DIFF)

0 0 0

VIN1 (S.E.) or

VIN1 − VIN0 (DIFF)

0 0 1

VIN2 (S.E.) or

VIN2 − VIN3 (DIFF)

0 1 0

VIN3 (S.E.) or

VIN3 − VIN2 (DIFF)

0 1 1

ISENSE1 1 0 0

ISENSE2 1 0 1

TSENSE1 1 1 0

TSENSE2 1 1 1

Table 11. Command Register1

MSB LSB

Bits D7 D6 D5 D4 D3 D2 D1 D0

Channel

Name

Read out last

result from

TSENSE2

Read out last

result from

TSENSE1

ISENSE2 ISENSE1 VIN3 (S.E.)

VIN3 − VIN2

(DIFF)

VIN2 (S.E.)

VIN2 − VIN3

(DIFF)

VIN1 (S.E.)

VIN1 − VIN0

(DIFF)

VIN0 (S.E.)

VIN0 − VIN1

(DIFF)

1 S.E. indicates single-ended, and DIFF indicates differential.

Table 12. ADC Result Register (First Read)

MSB LSB

D15

D14

D13

D12

D11

D10

ALERT_FLAG CHID2 CHID1 CHID0 B11 B10 B9 B8

Table 13. ADC Result Register (Second Read)

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

Data Sheet AD7294-2

Rev. 0 | Page 27 of 44

TSENSE1 AND TSENSE2 RESULT REGISTERS

The TSENSE1 result register (Address 0x02) and TSENSE2 result register

(Address 0x03) are 16-bit, read only registers. The MSB, Bit D15,

is the ALERT_FLAG bit; Bits[D14:D12] contain the three ADC

channel allocation bits. Bit D11 is reserved for flagging diode open

circuits. Bits[D10:D0] store the temperature reading from the

ADC in an 11-bit, twos complement format (see Table 14 and

Table 15). Conversions take place approximately every 5 ms.

Table 14. TSENSEx Result Register (First Read)

MSB LSB

D15 D14 D13 D12 D11 D10 D9 D8

ALERT_FLAG CHID2 CHID1 CHID0 B11 B10 B9 B8

Table 15. TSENSEx Result Register (Second Read)

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

TSENSEINT RESULT REGISTER

The TSENSEINT result register (Address 0x04) is a 16-bit, read

only register used to store the ADC data generated from the

internal temperature sensor. Similar to the TSENSE1 and TSENSE2

result registers, this register stores the temperature readings from

the ADC in an 11-bit, twos complement format (D10 to D0) and

uses the MSB as a general alert flag. Bits[D14:D11] are not used

and are set to zero. Conversions take place approximately every 5

ms. The temperature data format in Table 18 applies to the

internal temperature sensor data.

Temperature Value Format

The temperature reading from the ADC is stored in an 11-bit

twos complement format, D10 to D0, to accommodate both

positive and negative temperature measurements. The temper-

ature data format is provided in Table 18.

DACA, DACB, DACC, AND DACD VALUE REGISTERS

Writing to Address 0x01 to Address 0x04 sets the DACA, DACB,

DACC, and DACD output voltage codes, respectively. Bits[D11:D0]

in the write result register are the data bits sent to DACA. Note

that Bits[D15:D12] are ignored.

Table 16. DAC Register (First Write)1

MSB LSB

D15 D14 D13 D12 D11 D10 D9 D8

X X X X B11 B10 B9 B8

1 X is don’t care.

Table 17. DAC Register (Second Write)

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

Table 18. TSENSEINT Data Format

Input D10 (MSB) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB)

Value (°C) −256 +128 +64 +32 +16 +8 +4 +2 +1 +0.5 +0.25

AD7294-2 Data Sheet

Rev. 0 | Page 28 of 44

ALERT STATUS REGISTER A, ALERT STATUS

Alert Status Register A (Address 0x05), Alert Status Register B

(Address 0x06), and Alert Status Register C (Address 0x07) are

8-bit, read/write registers that provide information about an alert

event. If a conversion results in activation of the ALERT/BUSY

pin or the ALERT_FLAG bit in the ADC result register or the

TSENSEx result registers, the alert status registers can be read to

gain more information. To clear the full content of any alert

status registers, write a code of 0xFF (all 1s) to the relevant register.

Alternatively, write to the respective alert bit in the selected

alert status register to clear the alert that is associated with that

bit.

The entire contents of all the alert status registers can be cleared

by writing a 1 to Bit D1 and Bit D2 in the configuration register,

as shown in Table 24. However, this operation then enables the

ALERT/BUSY pin for subsequent conversions. See the Alerts

and Limits Theory section for more information.

CHANNEL SEQUENCE REGISTER

The channel sequence register (Address 0x08) is an 8-bit,

read/write register that allows the user to sequence the ADC

conversions to be performed in autocycle mode. Table 22 shows

the contents of the channel sequence register. See the Modes of

Operation section for more information.

Table 19. Alert Status Register A

Alert Bit D7 D6 D5 D4 D3 D2 D1 D0

Function

high alert

low alert

high alert

low alert

high alert

low alert

high alert

low alert

Table 20. Alert Status Register B

Alert Bit D7 D6 D5 D4 D3 D2 D1 D0

Function Reserved Reserved ISENSE2

overrange

ISENSE1

overrange

ISENSE2

high alert

ISENSE2

low alert

ISENSE1

high alert

ISENSE1

low alert

Table 21. Alert Status Register C

Alert Bit D7 D6 D5 D4 D3 D2 D1 D0

Function Open diode

flag

Overtemp

alert

TSENSEINT

high alert

TSENSEINT

low alert

TSENSE2

high alert

TSENSE2

low alert

TSENSE1

high alert

TSENSE1

low alert

Table 22. Channel Sequence Register

Channel Bit D7 D6 D5 D4 D3 D2 D1 D0

Function

Reserved

SENSE

Data Sheet AD7294-2

Rev. 0 | Page 29 of 44

CONFIGURATION REGISTER

The configuration register (Address 0x09) is a 16-bit, read/write

functions of the configuration register are outlined in Table 23

and Table 24. On power-up, the configuration register is reset

to 0x0000.

Sample Delay and Bit Trial Delay

It is recommended that no I2C bus activity occur when a con-

version is taking place; however, this may not be possible, for

example, when operating in autocycle mode. Bit D14 and Bit D13

in the configuration register are used to delay critical sample

intervals and bit trials from occurring while there is activity

on the I2C bus. On power-up, Bit D14 (noise-delayed sampling),

Bit D13 (noise-delayed bit trials), and Bit D3 (I2C filters) are

enabled (set to 0). This configuration is appropriate for low

frequency applications because the bit trials are prevented from

occurring when there is activity on the I2C bus, thereby ensuring

good dc linearity performance. For high frequency input signals,

it may be desirable to have a known sampling point; thus, the

noise-delayed sampling can be disabled by writing 1 to Bit D14 in

the configuration register. This ensures that the sampling instance

is fixed relative to SDA, resulting in improved SNR performance.

If noise-delay samplings extend longer than 1 µs, the current

conversion terminates. This termination can occur if there are

edges on SDA that are outside the I2C specification. When noise-

delayed sampling is enabled, the rise and fall times must meet

the I2C-specified standard. When Bit D13 is enabled, the

conversion time may vary.

The default configuration for Bit D3 (enabled) is recommended

for normal operation because it ensures that the I2C requirements

for tOf (minimum)and tSP are met. The I2C filters reject glitches

of less than 50 ns. If this function is disabled, the conversion results

are more susceptible to noise from the I2C bus.

Table 23. Configuration Register Bit Function Descriptions, Bits[D15:D8]

Channel

Bit D15 D14 D13 D12 D11 D10 D9 D8

Function Reserved Noise-delayed

sampling. Use

to delay critical

sample intervals

from occurring

when there is

activity on the

I2C bus.

Noise-delayed

bit trials. Use to

delay critical bit

trials from taking

place when there

is activity on the

I2C bus.

Autocycle

mode

Pseudo

differential

mode for

VIN2/VIN3

Pseudo

differential

mode for

VIN0/VIN1

Differential

mode for

VIN2/VIN3

Differential

mode for

VIN0/VIN1

Setting

Enabled = 0

Enabled = 1

Disabled = 1 Disabled = 1 Disabled = 0 Disabled = 0 Disabled = 0 Disabled = 0 Disabled = 0

Table 24. Configuration Register Bit Function Descriptions, Bits[D7:D0]

Channel

Bit D7 D6 D5 D4 D3 D2 D1 D0

Function 2 × VREF range

for VIN3

2 × VREF range

for VIN2

2 × VREF range

for VIN1

2 × VREF range

for VIN0

I2C filters ALERT pin BUSY pin (D2 = 0),

clear alerts (D2 = 1)

Select ALERT

pin polarity

(active high/

active low)

Setting Enabled = 1

Disabled = 0

Enabled = 1

Disabled = 0

Enabled = 1

Disabled = 0

Enabled = 1

Disabled = 0

Enabled = 0

Disabled = 1

Enabled

D2 = 1

D1 = 0

Disabled

D2 = 0

Enabled

D1 = 1 + D0 = 0

Disabled D1 = 0

Active high = 1

Active low = 0

Table 25. ALERT/BUSY Pin Function Descriptions

D2 D1 ALERT/BUSY Pin Function Descriptions

Pin does not provide any interrupt signal.

0 1 Configures pin as a busy output.

1 0 Configures pin as an alert output.

1 1 Resets the ALERT/BUSY output pin, the ALERT_FLAG bit in the conversion result register, and the entire alert status register (if any

is active). 11 is written to Bits[D2:D1] in the configuration register to reset the ALERT/BUSY pin, the ALERT_FLAG bit, and the alert status

register. Following this write, the content of the configuration register read 10 for Bit D2 and Bit D1, respectively, when read back.

Table 26. ADC Input Mode Examples

D11 D10 D9 D8 Description

All channels single-ended

0 0 0 1 Differential mode on VIN0/VIN1

0 1 0 1 Pseudo differential mode on VIN0/VIN1

AD7294-2 Data Sheet

Rev. 0 | Page 30 of 44

POWER-DOWN REGISTER

The power-down register (Address 0x0A) is an 8-bit, read/write

On power-up, the default value for the power-down register is 0x70.

The content of the power-down register is listed in Table 27.

Table 27. Power-Down Register Bit Descriptions

Bit Description

D7 Powers down the ADC and DAC reference buffers and the

temperature sensor. Sets the DAC outputs to high impedance

and disables the ISENSE1 and ISENSE2 alerts.

D6 Reserved.

D5 Powers down the ADC reference buffer. To allow for an

external reference, set to 1 at power-up.

D4 Powers down the DAC reference buffer. To allow for an

external reference, set to 1 at power-up.

Powers down the temperature sensor.

D2 Disables the ISENSE1 alerts.

D1 Disables the ISENSE2 alerts.

D0 Sets the DAC outputs to high impedance.

DATALOW AND DATAHIGH REGISTERS

VIN0 to VIN3 Channels

The DATALOW and DATAHIGH registers (Address 0x0B and

Address 0x0C, VIN0; Address 0x0E and Address 0x0F, VIN1;

Address 0x11 and Address 0x12, VIN2; Address 0x14 and

Address 0x15, VIN3), one pair for each VINx channel, are 16-bit,

read/write registers (see Table 29 and Table 30). General alert

is flagged by the MSB, Bit D15. Bits[D14:D12] are not used in

the register and are set to 0. The remaining 12 bits set the low and

high limits for the relevant channel. For single-ended mode, the

default values for VIN0 to VIN3 are 0x000 (DATALOW) and 0xFFF

(DATAHIGH) in binary format. For differential mode, the default

values for VIN0 to VIN3 are 0x800 (DATALOW) and 0x7FF

(DATAHIGH) in twos complement format. Note that, if the part is

configured in either single-ended or differential mode and the

mode is changed, the limits in the DATALOW and DATAHIGH

registers must be reprogrammed.

TSENSE1, TSENSE2, and TSENSEINT Channels

Channel 7 to Channel 9 (Address 0x1D and Address 0x1E,

TSENSE1; Address 0x20 and Address 0x21, TSENSE2; and

Address 0x23 and Address 0x24, TSENSEINT) default to 0x400

(DATALOW) and 0x3FF (DATAHIGH) as the limits because they

are in 11-bit, twos complement format.

Table 28. Default Values for DATALOW and DATAHIGH

Registers

ADC

Channel

Single-Ended

Differential

DATALOW DATAHIGH DATALOW DATAHIGH

VIN0 0x000 0xFFF 0x800 0x7FF

VIN1 0x000 0xFFF 0x800 0x7FF

VIN2 0x000 0xFFF 0x800 0x7FF

VIN3 0x000 0xFFF 0x800 0x7FF

SENSE

N/A

0x800

0x7FF

ISENSE2 N/A N/A 0x800 0x7FF

TSENSE1 N/A N/A 0x400 0x3FF

TSENSE2 N/A N/A 0x400 0x3FF

TSENSEINT N/A N/A 0x400 0x3FF

Table 29. DATALOW, DATAHIGH Register (First Read/Write)

MSB LSB

D15 D14 D13 D12 D11 D10 D9 D8

ALERT_FLAG 0 0 0 B11 B10 B9 B8

Table 30. DATALOW, DATAHIGH Register (Second Read/Write)

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

HYSTERESIS REGISTERS

Each hysteresis register (Address 0x0D, VIN0; Address 0x10, VIN1;

Address 0x13, VIN2; Address 0x16, VIN3; Address 0x19, ISENSE1;

Address 0x1C, ISENSE2; Address 0x1F, TSENSE1; Address 0x22,

TSENSE2; Address 0x25, TSENSEINT) is a 16-bit, read/write register

in which only the 12 LSBs of the register are used. The MSB signals

the alert event. If 0xFFF is written to the hysteresis register, the

hysteresis register enters the minimum/maximum mode (see

the Alerts and Limits Theory section).

Table 31. Hysteresis Register (First Read/Write)

MSB LSB

D15

D14

D13

D12

D11

D10

ALERT_FLAG 0 0 0 B11 B10 B9 B8

Table 32. Hysteresis Register (Second Read/Write)

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

Data Sheet AD7294-2

Rev. 0 | Page 31 of 44

REMOTE CHANNEL TSENSE1 AND TSENSE2 OFFSET

REGISTERS

The TSENSE1 offset register (Address 0x26) and TSENSE2 offset

offset to the temperature. These 8-bit, read/write registers store

data in a twos complement format. The data is subtracted from

the temperature readings taken by the TSENSE1 and TSENSE2

temperature sensors. The offset is implemented before the

values are stored in the TSENSE1 and TSENSE2 result registers.

The offset registers can be used to compensate for transistors

with different ideality factors because the TSENSEx results are based

on the 2N3906 transistor ideality factor. Different transistors

with different ideality factors result in different offsets within the

region of interest, which can be compensated for by using this

Table 33. TSENSE1, TSENSE2 Offset Register Data Format

Input

MSB

D7 D6 D5 D4 D3 D2 D1

LSB

Value (°C) −32 +16 +8 +4 +2 +1 +0.5 +0.25

AD7294-2 Data Sheet

Rev. 0 | Page 32 of 44

I2C INTERFACE

GENERAL I2C TIMING

Figure 47 shows the timing for general read and write operations

using an I2C-compliant interface. The I2C bus uses open-drain

drivers; therefore, when no device is driving the bus, both SCL

and SDA are high. This is known as idle state. When the bus is

idle, the master initiates a data transfer by establishing a start

condition, defined as a high-to-low transition on the serial data

line (SDA) while the serial clock line (SCL) remains high. This

indicates that a data stream follows. The master device is

responsible for generating the clock.

Data is sent over the serial bus in groups of nine bits: eight bits

of data from the transmitter followed by an acknowledge bit (ACK)

from the receiver. Data transitions on the SDA line must occur

during the low period of the clock signal and remain stable

during the high period. The receiver should pull the SDA line

low during the acknowledge bit to signal that the preceding byte

has been received correctly. If this is not the case, cancel the

transaction.

The first byte that the master sends must consist of a 7-bit slave

address, followed by a data direction bit. Each device on the bus

has a unique slave address; therefore, the first byte sets up

communication with a single slave device for the duration of the

transaction.

The transaction can be used either to write to a slave device

(data direction bit = 0) or to read data from it (data direction

bit = 1). In the case of a read transaction, it is often necessary

first to write to the slave device (in a separate write transaction)

to tell it from which register to read. Reading and writing

cannot be combined in one transaction.

When the transaction is complete, the master can keep control

of the bus, initiating a new transaction by generating another

start bit (high-to-low transition on SDA while SCL is high). This

is known as a repeated start (Sr). Alternatively, the bus can be

relinquished by releasing the SCL line followed by releasing the

SDA line. This low-to-high transition on SDA while SCL is high

is known as a stop bit (P), and it leaves the I2C bus in its idle state

(that is, no current is consumed by the bus).

The example in Figure 47 shows a simple write transaction with

an AD7294-2 as the slave device. In this example, the AD7294-2

SERIAL BUS ADDRESS BYTE

The first byte the user writes to the device is the slave address

byte. Similar to all I2C-compatible devices, the AD7294-2 has

a 7-bit serial address. The five LSBs are user-programmable via

the three, three-state input pins, as shown in Table 34.

Table 34 shows that the ASx pins are sometimes left floating.

Note that, in such cases, the stray capacitance on the pin must

be less than 30 pF to allow correct detection of the floating state;

therefore, any PCB trace must be kept as short as possible.

Table 34. Slave Address Control Using Three-State Input Pins1

AS2 AS1 AS0 Slave Address (A6 to A0)

L L L 0x61

L L H 0x62

L L NC 0x63

L H L 0x64

L H H 0x65

L H NC 0x66

L NC L 0x67

L NC H 0x68

L NC NC 0x69

H L L 0x6A

H L H 0x6B

H L NC 0x6C

H H L 0x6D

H H H 0x6E

H H NC 0x6F

H NC L 0x70

H NC H 0x71

H NC NC 0x72

NC L L 0x73

NC L H 0x74

NC L NC 0x75

NC H L 0x76

NC H H 0x77

NC H NC 0x78

NC NC L 0x79

NC NC H 0x7A

NC NC NC 0x7B

1 H = tie the pin to VDRIVE, L = tie the pin to DGND, NC = pin left floating.

Figure 47. General I2C Timing

P7 P6 P5 P4 P3 P2 P1 P0

START

BY M ASTE R ACK. BY

AD7294-2

SLAVE ADDRESS BYT E ACK. BY

AD7294-2

SCL

REGI ST E R ADDRESS STOP BY

MASTER

USER PROG RAMM ABL E 5 LSBs

R/W

A6 A5 A4 A3 A2 A1 A0

10936-040

Data Sheet AD7294-2

Rev. 0 | Page 33 of 44

INTERFACE PROTOCOL

The AD7294-2 uses the following I2C protocols.

Writing a Single Byte of Data to an 8-Bit Register

The alert status registers (Address 0x05 to Address 0x07), the

power-down register (Address 0x0A), the channel sequence

(Address 0x26 and Address 0x27), and the command register

(Address 0x00) are 8-bit registers. Therefore, only one byte of

data can be written to each. In this operation, the master device

sends a byte of data to the slave device (see Figure 48).

To write data to the register, use the following command sequence:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by a zero

for the direction bit, indicating a write operation.

3. The addressed slave device asserts an acknowledge on SDA.

4. The master sends a register address.

5. The slave asserts an acknowledge on SDA.

6. The master sends a data byte.

7. The slave asserts an acknowledge on SDA.

8. The master asserts a stop condition to end the transaction.

Figure 48. Single Byte Write Sequence

SDA

1 1 9

P0P1P2P3P4P5P6P7

R/W

A4 A3 A2 A1 A0

SCL

1 9

SDA (CO NTI NUE D)

SCL ( CONT INUED)

START BY

MASTER ACK. BY

AD7294-2 ACK. BY

AD7294-2

FRAME 1

SLAVE ADDRESS BYTE FRAME 2

ADDRESS P OI NTER REGIS TER BYTE

SSLAV E ADDRE S S 0 A REG POINTER ADATA A P

FRAME 3

DATA BYTE

ACK. BY

AD7294-2 STOP BY

MASTER

D0D1D2D3D4D5D6D7

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDITION

SR = REP E ATED S TART

P = STOP CONDITION

A = ACKNOWL E DGE

A = NO ACKNOW LEDG E

10936-061

AD7294-2 Data Sheet

Rev. 0 | Page 34 of 44

Writing Two Bytes of Data to a 16-Bit Register

The limit and hysteresis registers (Address 0x0B to Address 0x25),

the result registers (Address 0x01 to Address 0x04), and the

configuration register (Address 0x09) are 16-bit registers.

Therefore, two bytes of data are required to write a value to any

one of these registers (see Figure 49). Use the following sequence

to write the two bytes of data to one of these registers:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master sends a register address.

5. The slave asserts an acknowledge on SDA.

6. The master sends the first data byte (most significant).

7. The slave asserts an acknowledge on SDA.

8. The master sends the second data byte (least significant).

9. The slave asserts an acknowledge on SDA.

10. The master asserts a stop condition on SDA to end the

transaction.

Writing to Multiple Registers

Use the following sequence to write to multiple address registers:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device (the AD7294-2) asserts an

acknowledge on SDA.

4. The master sends a register address; for example, the Alert

Status Register A register address.

5. The slave asserts an acknowledge on SDA.

6. The master sends the data byte.

7. The slave asserts an acknowledge on SDA.

8. The master sends a second register address; for example,

the configuration register.

9. The slave asserts an acknowledge on SDA.

10. The master sends the first data byte to the second register

address.

11. The slave asserts an acknowledge on SDA.

12. The master sends the second data byte.

13. The slave asserts an acknowledge on SDA.

14. The master asserts a stop condition on SDA to end the

transaction.

The previous examples describe writing to two registers only

(Alert Status Register A and the configuration register).

However, the AD7294-2 can read from multiple registers

following one write operation, as shown in Figure 50.

Figure 49. Writing Two Bytes of Data to a 16-Bit Register

Figure 50. Writing to Multiple Registers

10936-059

SSLAV E ADDRE S S 0AREG POINTER ADATA[15:8] A PDATA[7:0] A

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDITION

SR = REP E ATED START

P = STOP CONDITION

A = ACKNOWLE DGE

A = NO ACKNOWLEDGE

10936-054

SSL AV E ADDRE S S 0APOINT TO CONFIG REG ( ADDR 0x09)

DATA[15:8]

DATA[7:0] APO INT TO P D RE G (ADDR 0X0A)

DATA[7:0]A A

...

FROM MASTER TO SL AVE

FROM SLAVE TO MASTER

S = START CONDITION

SR = REP E ATED S TART

P = STOP CONDITION

A = ACKNOWL E DGE

A = NO ACKNOW LEDG E

Data Sheet AD7294-2

Rev. 0 | Page 35 of 44

Reading Data from an 8-Bit Register

Reading the contents from any of the 8-bit registers is a single-

byte read operation, as shown in Figure 51. In this protocol, the

first part of the transaction writes to the register pointer. When

the register address has been set up, any number of reads can be

performed from that particular register address without having

to write to the address pointer register again. When the required

number of reads is completed, the master should not acknowledge

the final byte. This tells the slave to stop transmitting, allowing

a stop condition to be asserted by the master. Additional reads

from this register can be performed in a future transaction

without the need to rewrite to the register pointer.

If a read from a different address is required, the relevant register

address must be written to the address pointer register. Again,

any number of reads from this register can then be performed.

In the next example, the master device receives two bytes from

a slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

read bit (high).

3. The addressed slave device asserts an acknowledge

on SDA.

4. The master receives a data byte.

5. The master asserts an acknowledge on SDA.

6. The master receives another 8-bit data byte.

7. The master asserts a no acknowledge on SDA to inform

the slave that the data transfer is complete.

8. The master asserts a stop condition on SDA to end the

transaction.

Reading Two Bytes of Data from a 16-Bit Register

In this example, the master device reads three lots of two-byte

data from a slave device (see Figure 52). However, any number

of lots consisting of two bytes can be read. This protocol assumes

that the particular register address has been set up by a single-

byte write operation to the address pointer register (see the

previous read example).

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

read bit (high).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master receives the data byte.

5. The master asserts an acknowledge on SDA.

6. The master receives a second data byte.

7. The master asserts an acknowledge on SDA.

8. The master receives a data byte.

9. The master asserts an acknowledge on SDA.

10. The master receives a second data byte.

11. The master asserts an acknowledge on SDA.

12. The master receives a data byte.

13. The master asserts an acknowledge on SDA.

14. The master receives a second data byte.

15. The master asserts a no acknowledge on SDA to notify the

slave that the data transfer is complete.

16. The master asserts a stop condition on SDA to end the

transaction.

Figure 51. Reading Two Single Bytes of Data from a Selected Register

Figure 52. Reading Three Lots of Two Bytes of Data from the Conversion Result Register

10936-055

S 0 A A A

REG POINTER

...

SR 1 A

SL AV E ADDRE S S SL AV E ADDRE S S

DATA[7:0]

FROM MASTER TO SL AVE

FROM SLAVE TO MASTER

S = START CONDITION

SR = REP E ATED S TART

P = STOP CONDITION

A = ACKNOWL E DGE

A = NO ACKNOW LEDG E

10936-060

S A

...

1 A

A A A

SL AV E ADDRE S S

DATA[7:0]

DATA[7:0] DATA[7:0]

DATA[15:8]

DATA[15:8] DATA[15:8]

FROM MASTER TO SL AVE

FROM SLAVE TO MASTER

S = START CONDITION

SR = REP E ATED S TART

P = STOP CONDITION

A = ACKNOWL E DGE

A = NO ACKNOW LEDG E

AD7294-2 Data Sheet

Rev. 0 | Page 36 of 44

MODES OF OPERATION

There are two different methods of initiating a conversion on

the AD7294-2: command mode and autocycle mode.

COMMAND MODE

In command mode, the AD7294-2 ADC converts on demand

on either a single channel or a sequence of channels. To enter

this mode, the required combination of channels is written into

the command register (Address 0x00). The first conversion

takes place at the end of this write operation, in time for the

result to be read out in the next read operation. While this

result is being read out, the next conversion in the sequence

takes place, and so on.

To exit the command mode, the master does not acknowledge the

final byte of data. This stops the AD7294-2 from transmitting,

allowing the master to assert a stop condition on the bus. When

switching to read mode, therefore, it is important that, after

writing to the command register, a repeated start (Sr) signal be

used rather than a stop (P) followed by a start (S). Otherwise, the

device exits command mode after the first conversion.

After writing to the command register, the register pointer is

returned to its previous value. If a new pointer value is required

(typically for the ADC result register, Address 0x01), it can be

written immediately following the command byte. This extra

write operation does not affect the conversion sequence because

the second conversion is triggered only at the start of the first

read operation.

The maximum throughput that can be achieved using this

mode with a 400 kHz I2C clock is (400 kHz/18) = 22.2 kSPS.

Figure 53 shows the command mode converting on a sequence

of channels including VIN0, VIN1, and ISENSE1.

The conversion sequence is as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device (AD7294-2) asserts an

acknowledge on SDA.

4. The master sends the command register address (0x00).

The slave asserts an acknowledge on SDA.

5. The master sends Data Byte 0x13, which selects the VIN0,

VIN1, and ISENSE1 channels.

6. The slave asserts an acknowledge on SDA.

7. The master sends the ADC result register address (0x01).

The slave asserts an acknowledge on SDA.

8. The master sends the 7-bit slave address followed by the

write bit (high).

9. The slave (AD7294-2) asserts an acknowledge on SDA.

10. The master receives a data byte, which contains the

ALERT_FLAG bit, the channel ID bits, and the four MSBs

of the conversion result for the VIN0 channel. The master

then asserts an acknowledge on SDA.

11. The master receives the second data byte, which contains

the eight LSBs of the converted result for the VIN0 channel.

The master then asserts an acknowledge on SDA.

12. Step 10 and Step 11 are repeated for the VIN1 channel and

the ISENSE1 channel.

13. When the master receives the results from all the selected

channels, the slave again converts and outputs the result for

the first channel in the selected sequence. Step 10 to Step 12

are repeated.

14. The master asserts a no acknowledge on SDA and a stop

condition on SDA to end the conversion and exit

command mode.

If no read occurs in a 5 ms period, the AD7294-2 automatically

exits command mode. To change the conversion sequence,

write a new sequence to the command register.

Figure 53. Command Mode Operation

10936-056

S A

......

0A ACOMM AND = 0x13

0[11:8]

POINT TO ADC RE S ULT RE G

(ADDR 0x01) SR 1 A

ACH ID (000)ALERT?

...

CH ID (001)ALERT? A

...

SENSE

1[11:8]

A A

...

0[7:0]

...........

= POSITION OF A CONVERSION START

SLAV E ADDRE S S

POINT TO COMMAND RE G (ADDR 0x00)

1[7:0]

0[7:0] V

1[11:8]

0[11:8]

SLAV E ADDRE S S

SENSE

1[7:0]

SENSE

1[7:0]

ALERT? CH I D ( 100) ALERT? CH I D ( 000)

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDITION

SR = REP E ATED S TART

P = STOP CONDITION

A = ACKNOWL E DGE

A = NO ACKNOW LEDG E

Data Sheet AD7294-2

Rev. 0 | Page 37 of 44

AUTOCYCLE MODE

The AD7294-2 can be configured to convert continuously on a

programmable sequence of channels, making it the ideal mode

of operation for system monitoring. These conversions occur in

the background approximately every 50 µs and are transparent

to the master. Typically, this mode is used to automatically monitor

a selection of channels with either the limit registers programmed

to signal an out-of-range condition via the alert function or the

minimum/maximum recorders tracking the variation over time

of a particular channel. Reads and writes can be performed at

any time (the ADC result register, Address 0x01, contains the

most recent conversion result).

On power-up, the autocycle mode is disabled. To enable it,

write to Bit D12 in the configuration register (Address 0x09)

and select the desired channels for conversion in the channel

sequence register (Address 0x08).

If a command mode conversion is required while the autocycle

mode is active, it is necessary to disable the autocycle mode before

proceeding to the command mode. This is achieved either by

clearing Bit D12 of the configuration register or by writing 0x00

to the channel sequence register. When the command mode

conversion is complete, the user must exit command mode by

issuing a stop condition before reenabling autocycle mode.

When switching from autocycle mode to command mode,

the temperature sensor must be given sufficient time to settle

and complete a new temperature integration cycle. Therefore,

temperature sensor conversions performed within the first

500 ms after switching from autocycle mode to command

mode may trigger false temperature high and low alarms. It is

recommended that the temperature sensor alarms be disabled for

the first 500 ms after mode switching by writing 0x400 to the

DATALOW register TSENSEx and 0x3FF to the DATAHIGH register

TSENSEx. Reconfigure the temperature sensor alerts to the desired

alarm level when the 500 ms period has elapsed. Alternatively,

ignore any temperature alerts triggered during the first 500 ms

after mode switching.

AD7294-2 Data Sheet

Rev. 0 | Page 38 of 44

ALERTS AND LIMITS THEORY

ALERT_FLAG BIT

The ALERT_FLAG bit indicates whether the conversion result

being read or any other channel result has violated the limit

registers associated with it. If an alert occurs and the ALERT_

FLAG bit is set, the master can read the alert status register to

obtain more information on where the alert occurred.

ALERT STATUS REGISTERS

The alert status registers are 8-bit, read/write registers that provide

information on an alert event. If a conversion results in activa-

tion of the ALERT/BUSY pin or the ALERT_FLAG bit in the

ADC result register or TSENSE result registers, the alert status

alert register structure).

Figure 54. Alert Status Register Structure

Alert Status Register A (see Table 19) consists of four channels with

two status bits per channel, one bit corresponding to each of the

DATALOW and DATAHIGH limits. This register stores the alert

event data for VIN3 to VIN0, which are the standard voltage

inputs. When the contents of this register are read, any bit with

a status of 1 indicates a violation of its associated limit; that is,

it identifies the channel and whether the violation occurred

on the upper or lower limit. If a second alert event occurs on

another channel before the contents of the alert register are

read, the bit corresponding to the second alert event is also set.

Alert Status Register B (see Table 20) consists of three channels,

also with two status bits per channel, representing the specified

DATALOW and DATAHIGH limits. Bits[D3:D0] correspond to the

low and high limit alerts for the current sense inputs.

Bit D4 and Bit D5 represent the ISENSE1 OVERRANGE and ISENSE2

OVERRANGE values of VREF/10.41. During power-up, it is

possible for the fault outputs to be triggered, depending on which

supply comes up first. It is recommended that these bits be cleared

on power-up as part of the initialization routine by writing a 1 to

both D4 and D5.

The AD7294-2 internal circuitry can generate an alert if either

the D1(±) or the D2(±) input pins for the external temperature

sensor are open circuit. The most significant bit (MSB) of Alert

Status Register C (see Table 21) alerts the user when an open

diode flag occurs on the external temperature sensors. If the

internal temperature sensor detects an AD7294-2 die temperature

of greater than 150°C, the overtemperature alert bit (Bit D6 in

Alert Status Register C) is set, and the DAC outputs are set to a

high impedance state. The remaining six bits in Address 0x06

store alert event data for TSENSEINT, TSENSE2, and TSENSE1 with two

status bits per channel, one corresponding to each of the DATAHIGH

and DATALOW limits.

To clear the full contents of any alert register, write a code of

0xFF (all 1s) to the relevant registers. Alternatively, the user can

write to the respective alert bit in the selected alert register to

clear the alert that is associated with that bit. The entire

contents of all the alert status registers can be cleared by writing

a 1 to Bit D2 and Bit D1 in the configuration register, as shown

in Table 24. However, this operation then enables the

ALERT/BUSY pin for subsequent conversions.

DATALOW AND DATAHIGH MONITORING FEATURES

If the result moves outside the lower or upper limit set by the

user, the AD7294-2 signals an alert using hardware (via the

ALERT/BUSY pin), software (via the ALERT_FLAG bit), or

both, depending on the configuration.

The DATALOW register stores the lower limit that activates the

ALERT/BUSY output pin and/or the ALERT_FLAG bit in the

conversion result register. If the conversion result is less than the

value in the DATALOW register, an alert occurs. The DATAHIGH

output pin and/or the ALERT_FLAG bit in the conversion result

DATAHIGH register, an alert occurs.

An alert associated with either the DATALOW or DATAHIGH register

is cleared automatically when the monitored signal is back in range;

that is, the conversion result is between the limits. The contents of

the alert register are updated after each conversion. A conversion is

performed every 50 µs in autocycle mode; as a result, the contents

of the alert register may change every 50 µs. If the ALERT pin

signals an alert event and the content of the alert register is not

read before the next conversion is complete, the contents of the

returns between the specified limits. In such circumstances, the

ALERT pin no longer signals the occurrence of an alert event.

10936-057

ALERT

STATUS

ALERT

STATUS

ALERT

STATUS

VIN3 HIGH AL E RT

VIN3 LOW ALERT

VIN2 HIGH AL E RT

VIN2 LOW ALERT

VIN1 HIGH AL E RT

VIN1 LOW ALERT

VIN0 HIGH AL E RT

VIN0 LOW ALERT

RESERVED

ISENSE2 O V E RRANGE*

ISENSE2 HI GH ALE RT

ISENSE1 O V E RRANGE*

ISENSE2 L OW ALERT

ISENSE1 L OW ALERT

ISENSE1 HI GH ALE RT

OPEN DIODE FLAG*

OVERTEMP ALERT*

TSENSEI NT HIGH ALE RT

TSENSE2 HI GH ALE RT

TSENSEINT LOW ALERT

TSENSE2 L OW ALERT

TSENSE1 L OW ALERT

TSENSE1 HI GH ALE RT

ALERT

FLAG

OR ALERT/BUSY

CONFIGURATION

D2 = 1, D1 = 0

*THESE BITS ARE ALWAYS ACTIVE. ALL OTHER BITS

CAN BE PRO GRAMM E D TO BE ACTIV E OR NOT,

AS REQ UIRED.

Data Sheet AD7294-2

Rev. 0 | Page 39 of 44

The hysteresis register can be used to avoid flicker on the ALERT/

BUSY pin. If the hysteresis function is enabled, the conversion

result must return to a value of at least N LSBs above the DATALOW

or N LSBs below the DATAHIGH register value for the ALERT/BUSY

output pin and ALERT_FLAG bit to be reset. The value of N is

taken from the 12-bit hysteresis register associated with that

channel. By setting the hysteresis register to a code that is close to

the maximum output code for the ADC (for example, 0x77D),

the DATALOW or DATAHIGH alerts are not cleared automatically

by the AD7294-2.

Bit D11 of DATALOW or DATAHIGH Register TSENSEx is the diode

open circuit flag. If this bit is set to 0, it indicates the presence of an

open circuit between the Dx(+) and Dx(−) pins. An alert that is

triggered on either ISENSE OVERRANGE pin remains until it is

cleared by a write to the alert status register. The contents of the

DATALOW and DATAHIGH registers are reset to their default values

on power-up (see Table 28).

HYSTERESIS

The hysteresis value determines the reset point for the ALERT/

BUSY pin and/or ALERT_FLAG bit if a violation of the limits

occurs. The hysteresis register stores the hysteresis value, N,

when using the limit registers. Each pair of limit registers has a

dedicated hysteresis register. For example, if a hysteresis value of

8 LSBs is required on the upper and lower limits of VIN0, the

16-bit word, 0000 0000 0000 1000, should be written to Hysteresis

hysteresis registers contain a value of 8 LSBs for nontemperature

result registers and 8°C, or 32 LSBs, for the TSENSE registers. If

a different hysteresis value is required, that value must be written

to the hysteresis register for the channel in question.

The advantage of having hysteresis registers associated with

each of the limit registers is that hysteresis prevents chatter on

the alert bits associated with each ADC channel. Figure 55

shows the limit checking operation.

Using the Limit Registers to Store Minimum/Maximum

Conversion Results

If 0xFFF is written to the hysteresis register for a particular channel,

the DATALOW and DATAHIGH registers for that channel no longer

act as limit registers, as previously described, but, instead, act as

storage registers for the maximum and minimum conversion

results. This function is useful when an alert signal is not required

in an application, but it is still required to monitor the minimum

and maximum conversion values over time. Note that on power-

up, the contents of the DATAHIGH register for each channel are set

to the maximum code, whereas the contents of the DATALOW

registers are set to the minimum code by default.

Figure 55. Limit Checking

HIGH LIMIT

LOW LIMIT

HIGH LIMIT – HYSTERESIS

LOW LIMIT + HYSTERESIS

TIME

INPUT SIGNAL

ALERT SIGNAL

10936-067

AD7294-2 Data Sheet

Rev. 0 | Page 40 of 44

APPLICATIONS INFORMATION

The AD7294-2 contains all the functions that are required for

general-purpose monitoring and control of current, voltage,

and temperature. With its 59.4 V maximum common-mode

range, the device is useful in industrial and automotive applications

where current sensing in the presence of a high common-mode

voltage is required. For example, the part is ideally suited for

monitoring and controlling a power amplifier in a cellular base

station.

BASE STATION POWER AMPLIFIER MONITOR AND

CONTROL

The AD7294-2 is used in a power amplifier signal chain to

achieve the optimal bias condition for the LDMOS transistor.

The main factors influencing the bias conditions are tempera-

ture, supply voltage, gate voltage drift, and general processing

parameters. The overall performance of a power amplifier

configuration is determined by the inherent trade-offs required

in efficiency, gain, and linearity. The high level of integration

offered by the AD7294-2 allows the use of a single chip to

dynamically control the drain bias current to maintain a constant

value over temperature and time, thus significantly improving

the overall performance of the power amplifier. The AD7294-2

incorporates the functionality of eight discrete components,

bringing considerable board area savings over alternative solutions.

The circuit in Figure 56 is a typical system connection diagram

for the AD7294-2. The device monitors and controls the overall

performance of two final stage amplifiers. The gain control and

phase adjustment of the driver stage are incorporated in the

application and are carried out by the two available uncommitted

outputs of the AD7294-2. Both high-side current senses measure

the amount of current on the respective final stage amplifiers.

The comparator outputs, the ISENSE1 OVERRANGE and ISENSE2

OVERRANGE pins, are the controlling signals for the switches

on the RF inputs of the LDMOS power FETs. If the high-side

current sense reads a value above a specified limit compared

with the setpoint, the RF IN signal is switched off by the

comparator.

By measuring the transmitted power (Tx) and the received power

(Rx), the device can dynamically change the drivers and PA

signal to optimize performance. This application requires a

logarithmic detector/controller, such as the Analog Devices

AD8317 or AD8362.

Figure 56. Typical HPA Monitor and Control Application

COMPARATORS

AND REG IST E RS

MUX

TEMP

SENSOR

HIGH SI DE

CURRENT

SENSE

HIGH SI DE

CURRENT

SENSE

T1 T2

VOUTA

VOUTB

VOUTC

FILTER

RF CHOKE

RF OUT

LDMOS

RS1(+) RS2(+) RS2(–)RS1(–)

D1+

D2+

D2–

D1–

SETPOINT

240mV

ISENSE1

OVERRANGE

ISENSE2

OVERRANGE

GAIN

CONTROL

RSENSE

VDD

LDMOS

RF OUT

12-BIT

ADC

VIN0

VIN1

VIN2

VIN3

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC VOUTDGAIN

CONTROL

RF CHOKE

Tx POWER

MONITOR

Rx PO WER

MONITOR

POWER

RF CUTOFF

POWER

AD7294-2*

RF IN

*ADDITIONAL PINS OMITTED FOR CLARITY.

REF

10936-036

Data Sheet AD7294-2

Rev. 0 | Page 41 of 44

GAIN CONTROL OF POWER AMPLIFIER

In gain control mode, a setpoint voltage that is proportional in

decibels (dB) to the desired output power is applied to a power

detector such as the AD8362. A sample of the output power from

the power amplifier (PA), through a directional coupler and

attenuator (or by other means), is fed to the input of the AD8362.

The VOUT pin is connected to the gain control terminal of the

PA (see Figure 57). Based on the defined relationship between

VOUT and the RF input signal, the AD8362 adjusts the voltage on

VOUT (VOUT is now an error amplifier output) until the level

at the RF input corresponds to the applied VSET. The AD7294-2

completes a feedback loop that tracks the output of the AD8362

and adjusts the VSET input of the AD8362 accordingly.

The VOUT pin of the AD8362 is applied to the gain control

terminal of the power amplifier. For this output power control

loop to be stable, a ground referenced capacitor must be connected

to the CLPF pin of the AD8362. This capacitor integrates the

error signal (which is actually a current) that is present when the

loop is not balanced. In a system where a variable gain amplifier

(VGA) or variable voltage attenuator (VVA) feeds the power

amplifier, only one AD8362 is required. In such a case, the gain

on one of the parts (VVA, PA) is fixed, and VOUTx feeds the

control input of the other.

Figure 57. Setpoint Controller Operation

1nF C7

0.1nF

1:4

AD8362

AD7294-2

LPF

ENVELOPE OF

TRANSMITTED

SIGNAL

DIRECTIONAL

COUPLER

ATTENUATOR

POWER

AMPLIFIER RF IN

OUT

VOUT

VSET

INLO

INHI

10936-037

AD7294-2 Data Sheet

Rev. 0 | Page 42 of 44

OUTLINE DIMENSIONS

Figure 58. 64-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-64-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD7294-2BSUZ −40°C to +105°C 64-Lead Thin Plastic Quad Flat Package [TQFP] SU-64-1

AD7294-2BSUZ-RL −40°C to +105°C 64-Lead Thin Plastic Quad Flat Package [TQFP] SU-64-1

1 Z = RoHS Compliant Part.

COMPLIANT TO JEDEC S TANDARDS MS-026-ABD

1.20

MAX

16 32

0.40

BSC

LEAD P IT CH

0.75

0.60

0.45

9.20

9.00 SQ

8.80

7.20

7.00 SQ

6.80

0.23

0.18

0.13

TOP VIEW

(PINS DO WN)

PIN 1

VIEW A

1.05

1.00

0.95

0.20

0.09

0.08 MAX

COPLANARITY

SEATING

PLANE

0° M IN

7°

3.5°

0°

0.15

0.05

VIEW A

ROTAT E D 90° CCW

012108-A

Data Sheet AD7294-2

Rev. 0 | Page 43 of 44

NOTES

AD7294-2 Data Sheet

Rev. 0 | Page 44 of 44

NOTES

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D10936-0-6/13(0)