CAT28C16A 16K-Bit CMOS PARALLEL E2PROM FEATURES Fast Read Access Times: 200 ns End of Write Detection: DATA Polling Low Power CMOS Dissipation: Hardware Write Protection -Active: 25 mA Max. -Standby: 100 A Max. CMOS and TTL Compatible I/O 10,000 Program/Erase Cycles Simple Write Operation: 10 Year Data Retention -On-Chip Address and Data Latches -Self-Timed Write Cycle with Auto-Clear Commercial, Industrial and Automotive Temperature Ranges Fast Write Cycle Time: 10ms Max DESCRIPTION The CAT28C16A is a fast, low power, 5V-only CMOS Parallel E2PROM organized as 2K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling signals the start and end of the self-timed write cycle. Additionally, the CAT28C16A features hardware write protection. The CAT28C16A is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 10,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 24-pin DIP and SOIC or 32-pin PLCC packages. BLOCK DIAGRAM A4-A10 ADDR. BUFFER & LATCHES ROW DECODER VCC INADVERTENT WRITE PROTECTION HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC 2,048 x 8 E2PROM ARRAY I/O BUFFERS TIMER DATA POLLING I/O0-I/O7 A0-A3 ADDR. BUFFER & LATCHES COLUMN DECODER 5089 FHD F02 (c) 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 25033-00 2/98 CAT28C16A PIN CONFIGURATION WE OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 WE OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 4 3 2 1 32 31 30 5 29 6 28 7 27 8 26 9 25 TOP VIEW 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 A6 A5 A4 A3 A2 A1 A0 NC I/O0 PIN FUNCTIONS Pin Name VCC WE NC 1 2 3 4 5 6 7 8 9 10 11 12 A8 A9 NC NC OE A10 CE I/O7 I/O6 I/O5 14 13 A8 A9 I/O3 I/O4 22 21 20 19 18 17 16 15 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS VCC NC NC 24 23 VSS NC 1 2 3 4 5 6 7 8 9 10 11 12 PLCC Package (N) I/O1 I/O2 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS SOIC Package (J,K) A7 NC DIP Package (P) 5089 FHD F01 Function A0-A10 Address Inputs I/O0-I/O7 Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable VCC 5V Supply VSS Ground NC No Connect MODE SELECTION Mode CE WE OE Read L H Byte Write (WE Controlled) L Byte Write (CE Controlled) I/O Power L DOUT ACTIVE H DIN ACTIVE L H DIN ACTIVE Standby, and Write Inhibit H X X High-Z STANDBY Read and Write Inhibit X H H High-Z ACTIVE CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 5V Symbol Test Max. Units Conditions CI/O(1) Input/Output Capacitance 10 pF VI/O = 0V CIN(1) Input Capacitance 6 pF VIN = 0V Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 25033-00 2/98 2 CAT28C16A ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. -55C to +125C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... -65C to +150C Voltage on Any Pin with Respect to Ground(2) ........... -2.0V to +VCC + 2.0V VCC with Respect to Ground ............... -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND (1) TDR(1) VZAP (1) ILTH(1)(4) Parameter Units Test Method 10,000 Cycles/Byte MIL-STD-883, Test Method 1033 10 Years MIL-STD-883, Test Method 1008 ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 Latch-Up 100 mA Endurance Min. Data Retention Max. JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS VCC = 5V 10%, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC VCC Current (Operating, TTL) 35 mA CE = OE = VIL, f = 1/tRC min, All I/O's Open ICCC(5) VCC Current (Operating, CMOS) 25 mA CE = OE = VILC, f = 1/tRC min, All I/O's Open ISB VCC Current (Standby, TTL) 1 mA CE = VIH, All I/O's Open ISBC(6) VCC Current (Standby, CMOS) 100 A CE = VIHC, All I/O's Open ILI Input Leakage Current -10 10 A VIN = GND to VCC ILO Output Leakage Current -10 10 A VOUT = GND to VCC, CE = VIH VIH(6) High Level Input Voltage 2 VCC +0.3 V VIL(5) Low Level Input Voltage -0.3 0.8 V VOH High Level Output Voltage 2.4 VOL Low Level Output Voltage VWI Write Inhibit Voltage 0.4 3.0 V IOH = -400A V IOL = 2.1mA V Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC +1V. (5) VILC = -0.3V to +0.3V. (6) VIHC = VCC -0.3V to VCC +0.3V. Doc. No. 25033-00 2/98 3 CAT28C16A A.C. CHARACTERISTICS, Read Cycle VCC = 5V 10%, unless otherwise specified. 28C16A-20 Symbol Parameter Min. Max. 200 Units tRC Read Cycle Time tCE CE Access Time 200 ns tAA Address Access Time 200 ns tOE OE Access Time 80 ns tLZ(1) CE Low to Active Output 0 ns tOLZ(1) OE Low to Active Output 0 ns tHZ(1)(2) CE High to High-Z Output 55 ns tOHZ(1)(2) OE High to High-Z Output 55 ns tOH(1) Output Hold from Address Change 0 ns ns Figure 1. A.C. Testing Input/Output Waveform(3) 2.4 V 2.0 V INPUT PULSE LEVELS REFERENCE POINTS 0.8 V 0.45 V 5089 FHD F03 Figure 2. A.C. Testing Load Circuit (example) 1.3V 1N914 3.3K DEVICE UNDER TEST OUT CL = 100 pF CL INCLUDES JIG CAPACITANCE 5089 FHD F04 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. (3) Input rise and fall times (10% and 90%) < 10 ns. Doc. No. 25033-00 2/98 4 CAT28C16A A.C. CHARACTERISTICS, Write Cycle VCC = 5V 10%, unless otherwise specified. 28C16A-20 Symbol Parameter Min. Max. Units 10 ms tWC Write Cycle Time tAS Address Setup Time 10 ns tAH Address Hold Time 100 ns tCS CE Setup Time 0 ns tCH CE Hold Time 0 ns tCW(2) CE Pulse Time 150 ns tOES OE Setup Time 15 ns tOEH OE Hold Time 15 ns tWP(2) WE Pulse Width 150 ns tDS Data Setup Time 50 ns tDH Data Hold Time 10 ns tDL Data Latch Time 50 ns tINIT(1) Write Inhibit Period After Power-up 5 20 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) A write pulse of less than 20ns duration will not initiate a write cycle. Doc. No. 25033-00 2/98 5 CAT28C16A DEVICE OPERATION low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. Read Data stored in the CAT28C16A is transferred to the data bus when WE is held high, and both OE and CE are held Figure 3. Read Cycle tRC ADDRESS tCE CE tOE OE VIH tLZ WE tOHZ tOLZ HIGH-Z DATA OUT tHZ tOH DATA VALID DATA VALID tAA 28C16A F05 Figure 4. Byte Write Cycle [WE Controlled] tWC ADDRESS tAS tAH tCH tCS CE OE tOES tWP tOEH WE tDL DATA OUT DATA IN HIGH-Z DATA VALID tDS tDH 5089 FHD F06 Doc. No. 25033-00 2/98 6 CAT28C16A Byte Write DATA Polling A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms. DATA polling is provided to indicate the completion of a byte write cycle. Once a byte write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0-I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self-timed byte write cycle, all I/O's will output true data during a read cycle. Figure 5. Byte Write Cycle [CE Controlled] tWC ADDRESS tAS tAH tDL tCW CE tOEH OE tCS tOES tCH WE HIGH-Z DATA OUT DATA IN DATA VALID tDS tDH 5089 FHD F07 Figure 6. DATA Polling ADDRESS CE WE tOEH tOES tOE OE tWC I/O7 DIN = X DOUT = X DOUT = X 28C16A F08 Doc. No. 25033-00 2/98 7 CAT28C16A HARDWARE DATA PROTECTION teristics), provides a 5 to 20 ms delay before a write sequence, after VCC has reached 3.0V min. The following is a list of hardware data protection features that are incorporated into the CAT28C16A. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high. (1) VCC sense provides for write protection when VCC falls below 3.0V min. (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. (2) A power on delay mechanism, tINIT (see AC charac- ORDERING INFORMATION Prefix Device # CAT 28C16A Optional Company ID Product Number Suffix N I Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) A = Automotive (-40 to +105C)* Package P: PDIP N: PLCC J: SOIC (JEDEC) K: SOIC (EIAJ) T -20 Tape & Reel T: 500/Reel Speed 20: 200ns 28C16A F09 * -40C to +125C is available upon request Notes: (1) The device used in the above example is a CAT28C16ANI-20T (PLCC, Industrial temperature, 200 ns Access Time, Tape & Reel). Doc. No. 25033-00 2/98 8