PRELIMINARY
128K x 36 Synchronous Flow-Through 3.3V Cache RAM
f
ax
id
:
1111
CY7C1345
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Au
g
ust 24
,
1998
Features
• Supports 117-MHz microprocessor cache systems with
zero wai t states
• 128K by 36 com m on I/ O
• Low St andby Power (1.65 mW, L version)
• Fast clock-to-output times
—7.5 ns (117-MHz version)
• Two-bit wrap-around co unter supporting either
interleaved or linear burst sequence
• Separate processor and controller address strobes pro-
vide direct interf ace w it h the processor and external
cache control ler
• Synchronous sel f-ti me d writ e
• Asynchronous out put enable
•3.3V I/Os
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
Functional Descripti on
The CY7 C1345 is a 3 .3V 128K by 36 syn chronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue lo gic. Maximum access delay from cloc k rise is
7.5 ns (1 17-MHz v ers ion). A 2-b it on-chi p counter cap tures the
firs t address in a burst and increm ents the address automati-
cally for the rest of the burst access.
The CY7C1345 allows either interleaved or linear burst se-
quences, selected by the M O DE input pin. A HIGH s elects an
interlea ved bu rst sequence , while a LO W selects a linear burst
sequence. Burst accesses can be initi ated with the proc essor
address str obe (ADSP) or the c ache c ontrol ler a ddress s trobe
(ADSC) input s. Addres s advancement is controlled by the ad-
dress advancement (ADV) input.
A synchr onous self -timed write mechani sm is pro vided to si m-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selecti on and output three-state control.
Selection Guid e
7C1345–117 7C1345–100 7C1345–90 7C1345–50
Maximum Access Time (ns) 7.5 8.0 8.5 11.0
Maximum Oper ating Current (mA) 350 325 300 250
Maxim um Standby Current (mA) 2.0 2.0 2.0 2.0
Pentium is a registered trademark of Intel Corporation.
CLK
ADV
ADSC
A[16:0]
GW
BWE
BWS0
CE1
CE3
CE2
OE
ZZ
BURST
COUNTER
DQ[31:24],DP3
BYTEWRITE
REGISTERS
ADDRESS
REGISTER
DQ
INPUT
REGISTERS
128K X 36
MEMORY
ARRAY
CLK
Q0
Q1
Q
D
CE
CE
CLR
SLEEP
CONTROL
DQ[23:16],DP2
BYTEWRITE
REGISTERS
D Q
DQ
DQ[15:8],DP1
BYTEWRITE
REGISTERS
DQ[7:0],DP0
BYTEWRITE
REGISTERS
D Q
ENABLE
REGISTER
DQ
CE
CLK
36 36
17
15
15
17
(A0,A1)2
MODE
ADSP
Logic Block Diagram
DQ[31:0]
BWS1
BWS2
BWS3
DP[3:0]
CY7C1345
PRELIMINARY
2
Pin Configuration
100-Lead TQFP
A5
A4
A3
A2
A1
A0
DNU
DNU
VSS
VDD
DNU
A10
A11
A12
A13
A14
A16
DP1
DQ14
VDDQ
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
VDDQ
DQ9
DQ8
VSS
NC
VDD
DQ7
DQ6
VDDQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VDDQ
DQ1
DQ0
DP0
DP2
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
VSSQ
VDD
NC
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
DP3
A6
A7
CE1
CE2
BWS3
BWS2
BWS1
BWS0
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSP
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
BYTE0
BYTE2
A15
ADV
ADSC
ZZ
MODE
DNU
BYTE1
DQ15
BYTE3
VSS
CY7C1345
PRELIMINARY
3
Pin Descriptions
TQFP Pin
Number Name I/O Description
85 ADSC Input-
Synchronous Addr ess Strobe from Controller, sampled on the risi ng edge of CLK. When asserted
LO W, A[15:0] is captured in the address r egisters. A[1:0] are also loaded into t he burst
counter. When ADSP and ADSC are both asserted, only ADSP is re c o gnized.
84 ADSP Input-
Synchronous Addr ess Strobe fr om Processor, sampled on the rising edge of CLK. W hen asserted
LO W, A[15:0] is captured in the address r egisters. A[1:0] are also loaded into t he burst
counter. When ADSP and ADSC are bot h asserted, only ADSP is r ecogniz ed . ASDP
is ignored when CE1 is deasserted HIGH.
36, 37 A[1:0] Input-
Synchronous A1, A0 Address Inputs. These inputs feed the on-chip burst counter as the LSBs as
well as being used to access a particular memory locat ion in the memory arr ay.
49 −44,
81–82,
99–100,
32–35
A[16:2] Input-
Synchronous Addr ess Inputs used in conj unction with A[1:0] to select one of the 64K address loca-
tions. Sampled at the rising edge of the CLK, if CE 1, CE2, and CE3 are sampled a ctive ,
and ADSP or ADSC is active LOW .
96–93 BW[3:0] Input-
Synchronous Byt e Write Select Inputs , acti ve LOW. Qual ifi ed wit h BWE to conduct b yte writes.
Sampled on the rising edge. BW0 controls DQ[7:0] and DP0, BW1 controls DQ[15:8] and
DP1, BW2 controls DQ[23:16] and DP2, and BW3 controls DQ[31:24] and DP3. See Write
Cycle Descri ptions table for fu rthere det ails .
83 ADV Input-
Synchronous Adv ance Input used to adv ance the on-chi p address counter . When LO W the internal
burs t c ounter is adv an ced in a b urst se quenc e. The b urst s equence i s se lected using
the MODE input.
87 BWE Input-
Synchronous Byt e Write Ena b le Inp ut, ac tiv e LOW. Sampl ed on the ri sing edge of CLK. T his si gnal
must be asserted LOW t o conduct a byte writ e.
88 GW Input-
Synchronous Glob al Writ e Input, active LOW. Sampled on the ris ing edge of CLK. This si gnal is
used to conduct a global write, independent of the state of BWE and BW[3:0]. Global
writes override byt e writes.
89 CLK Input-Clock Clock Input. Used to captur e all synchronous inputs to the device.
98 CE1Input-
Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE2 and CE3 to select/deselect the device. CE1 gates ADSP.
97 CE2Input-
Synchronous Chi p Enable 2 Input, active HIG H. Sampled on the ri sing edge of CLK. Used in con-
junction with CE1 and CE3 to sele ct/deselect the device.
92 CE3Input-
Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE1 and CE2 to select/deselect the de vice.
86 OE Input-
Asynchronous Output Enable, asynchronous input, active LOW . Controls the direction of the I/O pins.
When LOW, the I/O pi ns behave as out puts. When deas serted HIGH, I/O pins are
three- stated, and act as i nput data pins.
64 ZZ Input-
Asynchronous Snooze input. Active HIGH asynchronous. When HIGH, the de vice enters a low-power
standb y mode in which all other inputs are ignored, but the dat a in the memory arra y
is maint ained.Lea ving ZZ fl oating or NC will default the device into an active state.
31 MODE -Mode input. Sel ects the burst order of t he device . Tied HIGH selects the int erl eaved
burst order. Pulled LOW s elects the lin ear burst order. When left flo ating or NC, de-
faults to interleaved burst order.
30–28,
25–22,
19–18,
13–12,
9–6, 3–1,
80–78,
75–72,
69–68,
63–62,
59–56,
53–51
DQ[31:0],
DP[3:0] I/O-
Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on- chip data register t hat is
triggered b y the ri sing edge of CLK. As o utputs , t he y d elive r t he dat a con tained in t he
memory locati on specified by A[16:0] during the pr evious c lock rise of t he read cycle.
The direction of the pins is controlled by OE in conjunction with the inte rnal cont rol
logic . W hen OE is asserted LOW, the pin s behave as outputs. When HIGH, DQ[31:0]
and DP[3:0] ar e placed in a thre e-state condit ion. The outputs ar e automatically
three-stated when a Write cycle is detected.
15, 4 1, 65,
91 VDD Power Supply Power supply inputs t o the cor e of the device. Should be connected to 3.3V power
supply.
CY7C1345
PRELIMINARY
4
Functional Description
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses pre-
sented are loaded into the address register and the burst
count er/con trol logic and deli v ered t o the RAM cor e. The write
inputs (GW, BWE, and BW[3:0]) are ignored during this first
clock cycle. I f t he write inputs are asser ted active (see Write
Cycle Descriptions table for appropriate states that indi cate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW0 controls DQ[7:0], BW1 controls
DQ[15:8], BW2 controls DQ[23:16], and BW3 controls DQ[31:24].
All I/Os are three-stated during a byte write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasser ted and the I/Os must be three-stated prior to the
presentation of data to DQ[31:0]. As a safety precaution, the
data li nes are three-stated once a write cycle i s detected, re-
gardless of the state of OE.
Single Write Accesses Initiated by ADSC
This writ e acc ess is i nitiat ed when the f oll owing c ondi tion s are
satisfied at clock rise: (1) CE1, C E 2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH , and (4) the write in put signals (GW, BWE, and BW[3:0])
indi cate a writ e access. A DSC is i gnor ed if A DSP is active LO W.
The addr ess es presen ted are loa ded int o the addr ess regist er
and the burst counter/control logic and delivered to the RAM
core. The information presented to DQ[31:0] will be written into
the spe cified add res s lo cation. Byte wri tes are all owed. Durin g
byte writes, BW0 contr ols DQ[7:0], BW1 contr ols DQ[15:8], BW2
controls DQ[23:16], and BWS3 controls DQ[31:24]. All I /Os are
thr ee-stat ed when a write i s detec ted, even a byte write . Since
thi s is a common I/O device , the as ynchrono us OE input signal
mu st be deass erte d and the I /Os mus t be thr ee-st ated prio r to
the p resentati on of dat a to DQ[31:0]. As a safety precaution, the
data li nes are three-stated once a write cycle i s detected, re-
gardless of the state of OE.
Single Read Accesses
A single read access is initi ated when the following conditi ons
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all as-
serted active, and (2) ADSP or ADSC i s asserted LOW (if the
access is initiated by ADSC, the write i nputs m ust be deas sert-
ed during this first cycle). The address presented to the ad-
dress inputs is latched into the address register and the burst
counter/control logic and present ed to the memory core. If the
OE input is asserted LO W , the req uested data will be av ai lable
at the data outputs a maximum to tCDV after clock rise. ADSP
is ignored if CE1 is HIGH.
Burst Se quences
The CY7C1338 provides an on-chip 2-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0],
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LO W on MODE wi ll se lect a line ar b urst sequenc e. A HIG H on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause t he device to default to a inter leaved
bu rst sequence .
17, 4 0, 67,
90 VSS Ground G round for the I/O ci rcuitry of the device. Should be connected to ground of t he
system.
5, 10, 14,
21, 2 6, 55,
60, 71, 76
VSSQ Ground G round for the device. Should be connected to ground of t he system.
4, 11, 20,
27, 5 4, 61,
70, 77
VDDQ I/O Po wer
Supply Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
1,16, 30,
50–51, 66,
80
NC -No connects.
38, 3 9, 42,
43 DNU -Do not use pins. Should be left unconnected or tied LOW.
Pin Descriptions (c ontinued)
TQFP Pin
Number Name I/O Description
Table 1. Counter Implementation for the Intel
P entium®/ 80486 Processor’s Sequence.
First
Address Second
Address Third
Address Fourth
Address
AX + 1 , AxAX + 1, AxAX + 1, AxAX + 1, Ax
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Table 2. Counter Implementation for a Linear Sequence.
First
Address Second
Address Third
Address Fourth
Address
AX + 1, AxAX + 1, A xAX + 1, AxAX + 1, A x
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
CY7C1345
PRELIMINARY
5
Sleep Mode
The ZZ in put pin is a n asynchronous inp ut. Asserting ZZ HIGH
places the SRAM i n a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Ac-
cesses pending when entering the “sleep” mode are not con-
sidered valid nor is the completion of the operation guaran-
teed. The device must be deselected prior to entering the
“s le ep” mod e. C E 1, CE2, CE3, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LO W. Lea ving ZZ unc onnected defaults the de vice into an ac-
tive state.
Cycle Description Table[1, 2, 3]
Cycle Description ADD
Used CE1CE3CE2ZZ ADSP ADSP ADV WE OE CLK DQ
Deselected Cyc le, P o wer-do wn None H X X L X L X X X L-H High-Z
Deselected Cyc le, P o wer-do wn None L X L L L X X X X L-H High-Z
Deselected Cyc le, P o wer-do wn None L H X L L X X X X L-H High-Z
Deselected Cyc le, P o wer-do wn None L X L L H L X X X L-H High-Z
Deselected Cyc le, P o wer-do wn None X X X L H L X X X L-H High-Z
Snooze M ode, P ower-down None X X X H X X X X X X High-Z
Read Cycle, Begin Burst External L L H L L X X X L L-H Q
Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z
Write Cycl e, Begin Burst External L L H L H L X L X L-H D
Read Cycle, Begin Burst External L L H L H L X H L L-H Q
Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z
Write Cycl e, Continue Burst Ne xt X X X L H H L L X L-H D
Write Cycl e, Continue Burst Ne xt H X X L X H L L X L-H D
Read Cycle, Sus pend Burst Current X X X L H H H H L L-H Q
Read Cycle, Sus pend Burst Current X X X L H H H H H L-H High-Z
Read Cycle, Sus pend Burst Current H X X L X H H H L L-H Q
Read Cycle, Sus pend Burst Current H X X L X H H H H L-H High-Z
Write Cycl e, Suspend Burst Current X X X L H H H L X L-H D
Write Cycl e, Suspend Burst Current H X X L X H H L X L-H D
Notes:
1. X=Don't Care, 1=Logic HIGH, 0=Logic LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a don't care for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.
CY7C1345
PRELIMINARY
6
Maximum Ratings
(Above whi ch the useful life may be impa ir ed. For user guide-
li nes, not tested.)
Storage Temperat ure ... .. ................. .......... .– 65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
DC Voltage Appli ed to Outputs
in High Z State[5]....................................–0.5V to VDD + 0.5V
DC Input Voltage[5]................................–0.5V to VDD + 0.5 V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage ...... ...................... .... .. ........ >2001V
(per MIL- STD-883, Met hod 3015)
Latch-Up Current. .. ......... ...... .. .. ................. .......... ... >200 mA
Notes:
4. When a write cycle is detected, all I/Os are three-stated, ev en during byte writes.
5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
6. TA is the “instant on” c ase tempe ra ture.
Write Cycle Descriptions[1, 2, 3, 4]
Function GW BWE BW3BW2BW1BW0
Read 11XXXX
Read 101111
Write Byt e 0,DP0101110
Write Byt e 1,DP1101101
Write Byt es 1, 0,DP0,DP1101100
Write Byt e 2,DP2101011
Write Byt es 2, 0,DP2,DP0101010
Write Byt es 2, 1,DP2,DP1101001
Write Byt es 2, 1, 0,DP2,DP1,DP0101000
Write Byt e 3,DP3100111
Write Byt es 3, 0,DP3,DP0100110
Write Byt es 3, 1,DP3,DP0100101
Write Byt es 3, 1, 0,DP3,DP1,DP0100100
Write Byt es 3, 2,DP3,DP2100011
Write Byt es 3, 2, 0,DP3,DP2,DP0100010
Write Byt es 3, 2, 1,DP3,DP2,DP1100001
Write All Bytes 100000
Write All Bytes 0 XXXXX
Operating Range
Range Ambient
Temperature[6] VDD VDDQ
Com’l 0°C to +70 °C 3.135V to 3.6V 2.375V to VDD
CY7C1345
PRELIMINARY
7
Electrica l Characteristics Over t he Operating Range
P arameter Des cripti on Test Condi ti ons Min. Max. Unit
VOH Output HI GH Volt age VDDQ = 3.3V, VDD = Min., IOH=–4.0 mA 2.4 V
VDDQ = 2.5V, VDD = Min., IOH=–2.0 mA 1.7 V
VOL Output LOW Voltage VDDQ = 3.3V, VDD = Min., IOL=8.0 mA 0.4 V
VDDQ = 2.5V, VDD = Min., IOL=2.0 m A 0.7 V
VIH Input HIGH Voltage 1.7 VDD +
0.3V V
VIL Input LOW Vol tage[5] –0.3 0.8 V
IXInput Load Current
(except ZZ and MODE) GND ≤ VI ≤ VDDQ −11µA
Input Current of MODE Input = VSS –30 µA
Input = VDDQ 5µA
Input Current of ZZ Input = VSS –5 µA
Input = VDDQ 30 µA
IOZ Output Leakage Current GND ≤ VI ≤ VDD, Output Disabl ed –5 5 µA
IOS Output Short Circuit Curre nt[7] VDD=Max., VOUT=GND –300 mA
IDD VDD Operating Supply Current VDD=Max., IOUT=0 mA ,
f=fMAX =1/t CYC 8.5- ns cycle, 117 MHz 35 0 mA
10-ns cy cle, 100 MHz 32 5 mA
11-ns cy cle, 90 MHz 30 0 mA
20-ns cy cle, 50 MHz 25 0 mA
ISB1 Automat ic CE Power-Down
Current—TTL Inputs switching Max. VDD, Devi ce D ese lec te d,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
8.5-ns cycle, 117 MHz 12 5 mA
10-ns cy cle, 100 MHz 11 0 mA
11-ns cy cle, 90 MHz 10 0 mA
20-ns cy cle, 50 MHz 75 m A
ISB2 Automat ic CE Power-Down
Current — CMOS Inputs stati c Ma x. VDD, Devi ce D ese le cte d,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0
Std version - All speeds 10 mA
L version - All spe eds 2 m A
Max. VDD, Device Deselected,
VIN ≥ VDDQ– 0.3V or VIN ≤ 0.3V,
f=fMAX, inputs switching
ISB3 Automat ic CE Power-Down
Current—CM OS Inputs switching,
F=Max
8.5-ns cycle, 117 MHz 95 mA
10-ns cy cle, 100 MHz 85 mA
11-ns cy cle, 90 MHz 70 m A
20-ns cy cle, 50 MHz 60 m A
ISB4 Automatic CE Power-Down Current
— CMOS Inputs st atic, F=Max Ma x. VDD, Device Deselected,
VIN ≥ VDD –0.3V or VIN ≤ 0.3V,
f=fMAX, inputs static
8.5-ns cycle, 117 MHz 60 mA
10-ns cy cle, 100 MHz 50 mA
11-ns cy cle, 90 MHz 40 m A
20-ns cy cle, 50 MHz 35 m A
Notes:
7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C1345
PRELIMINARY
8
ZZ Mode Elec trical Characteristics
Parameter Description Test Conditions Min Max Unit
ICCZZ Sn ooze mo de
standby curr ent ZZ > VDD − 0.2V 3 mA
ICCZZ (L Version) Snooze m ode
standby curr ent ZZ > VDD − 0.2V 800 µA
tZZS Device operation to
ZZ ZZ > VDD − 0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2 V 2t CYC ns
Capacitance[8]
Parameter Desc ription Test Condi tions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 5.0V 5.0 pF
CI/O I/O Capacitance 8.0 pF
Note:
8. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
3.0V
GND
90%
10% 90%
10%
≤3.0 ns ≤3.0 ns
OUTPUT
R1=317Ω
R2=351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
ALL INPUT PULSES
OUTPUT
RL=50Ω
Z0=50Ω
VL=1.5V
3.3V
CY7C1345
PRELIMINARY
9
Switching Charac teris t ics Ov er the Operating Range[9]
Parameter Description
-117 -100 -90 -50
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC Clo ck Cy cle T im e 8. 5 10 11 20 ns
tCH Clock HIGH 3.0 4.0 4.5 4.5 ns
tCL Clock LOW 3.0 4.0 4.5 4.5 ns
tAS Address Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tAH Address Hold After CLK R ise 0.5 0.5 0.5 0.5 ns
tCDV Data Out put Valid After CLK Rise 7.5 8.0 8.5 11.0 ns
tDOH Data Output Hold After CLK Rise 2.0 2.0 2.0 2.0 n s
tADS ADSP, ADSC Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tWES BWS[1:0], GW,BWE Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tWEH BWS[1:0], GW,BWE Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tADVS ADV Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tDS Data Input Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns
tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tCES Chip Enable Set-Up 2.0 2.0 2.0 2.0 ns
tCEH Ch ip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
tCHZ Clock to High-Z[10,11] 3.5 3.5 3.5 3.5 ns
tCLZ Clock to Low- Z[10,11] 0000ns
tEOHZ OE HIGH t o Output High-Z[10,12] 3.5 3.5 3.5 3.5 ns
tEOLZ OE LOW to Output Low-Z[10,12] 0000ns
tEOV OE LOW to O utput Valid 3.5 3. 5 3.5 3.5 ns
Note:
9. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and loa d capaci tance. Show n in ( a) and ( b) of A C test l oads .
10. tCHZ, tCLZ, tEOHZ, and tEOLZ are specifi ed with a load capacit ance of 5 pF as in part (b) of A C Test Loads. Transition i s measur ed ± 200 mV from st eady-stat e v oltage .
11. At any given voltage and temperature, tCHZ (max) is l ess than tCLZ (min).
12. This parameter is sampled and not 100% tested.
CY7C1345
PRELIMINARY
10
Timing Diagram s
In/Out
A
tAH
tAS
= DON’T CARE = UNDEFINED
WE is t he combination of BWE, BW S[1:0], and GW to define a write cycle (see Write Cycle Definition table).
tCLZ
tCHZ
CE is the co mb ination of CE2 and CE3. All chip sel ects need to be active in order to select
the device. RAx stands for Read Addr ess X, WAx stands f or Wri te Address X, Dx stands for Data-i n X,
tDOH
CLK
ADD
WE
CE1
Data
BCD
ADSP
ADSC
ADV
CE
OE
Q(A) Q(B) Q
(B+1) Q
(B+2) Q
(B+3) Q(B) D(C) D
(C+1) D
(C+2) D
(C+3) Q(D)
tCYC
tCH tCL
tADS tADH
tADS tADH
tADVH
tADVS
tCEH
tCEH
tCES
tCES
tWEH
tWES
tCDV
Read/Writ e Timing
Device originally
deselected
ADSP ignored
with CE1 HIGH
tEOHZ
Qx stands for Data-out X.
CY7C1345
PRELIMINARY
11
Timing Diagram s (co nti nued)
In/Out
A
tAS
= DON’T CARE = UNDEFINED
WE is t he combination of BWE, BW S[1:0], and GW to define a write cycle (see Write Cycle Definition table).
tCLZ
tCHZ
CE is the co mb ination of CE2 and CE3. All chip sel ects need to be active in order to select
the device. RAx stands for Read Addr ess X, WAx stands f or Wri te Address X, Dx stands for Data-i n X,
tDOH
CLK
ADD
WE
CE1
Data
B
ADSP
ADSC
ADV
CE
OE
Q(A) Q(B) Q(D) D(C)
D (E) D (F) D (G)
tCYC
tCH tCL
tADS tADH
tCEH
tCES
tWEH
tWES
tCDV
Pipeli ne Timing
Device originally
deselected
ADSP ignored
with CE1 HIGH
Qx stands for Data-out X.
CD
Q(C)
EFGH
D (H)
CY7C1345
PRELIMINARY
12
Timing Diagram s (co nti nued)
OE
three-state
I/Os
tEOHZ tEOV
tEOLZ
OE Switch ing Waveforms
CY7C1345
PRELIMINARY
13
Note:
13. Device must be deselected when entering ZZ mode. See Cycle Description for all possible signal conditions to deselect the de vice.
14. I/Os ar e in three-state when exiting ZZ sleep mode.
Timing Diagram s (continued)
ADSP
CLK
ADSC
CE1
CE3
LOW
HIGH
ZZ tZZS
tZZREC
ICC ICC(active)
Three-state
I/Os
ZZ Mode Timing [13,14]
CE2
ICCZZ
HIGH
CY7C1345
PRELIMINARY
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semic onductor product. Nor does it conv ey or imply any license under patent or oth er rights. Cypr ess Semi condu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o res ult in significant injury to the user. The in clusion of Cypress
Semiconductor products in life-support systems appli cation implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Document #: 38-00725
Orde ring Information
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
117 CY7C1345–117AC A101 100-Lead Thin Quad Flat Pack Comm ercial
100 CY7C1345–100AC A101 100-Lead Thin Quad Flat Pack Comm ercial
90 CY7C1345–90AC A101 100-Lead Thin Quad Flat Pack Comm ercial
50 CY7C1345–50AC A101 100-Lead Thin Quad Flat Pack Comm ercial
Package Di ag ra m
100-Pin Thin Plas ti c Qua d Flat pack (14 x 20 x 1.4 mm) A101
51-85050-A
