AK4620BVF - AKM Semiconductor, Inc.

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

- 1 -

GENERAL DESCRIPTION

The AK4620B is a high performance 24-bit CODEC that supports up to 192kHz record and playback. The

on-board analog-to-digital converter has a high dynamic range due to AKM’s Enhanced Dual-Bit

architecture. Th e DAC utilizes AKM’s Advanced Multi-Bit architecture that achieves low out-of-band noise

and high jitter tolerance through the use of Switched Capacitor Filter (SCF) technology. The AK4620B has

an input Programmable Gain Amplifier and is ideal for Pro Audio sound cards, Digital Audio Workstations,

DVD-R, hard disk, CD-R recording/playback systems, and musical instrument recording.

FEATURES

• 24-bit 2-channel ADC

- Selectable Single-ended or Differential Input

- High Performance Linear Phase Dig ital Anti-Alias Filter

Passband: 0 ~ 20.25 kHz (@fs=44.1kHz)

Ripple: ± 0.005dB

Stopband Attenuation: 100dB

- S/(N+D): 90dB (single-ended)

100dB (differential)

- S/N: 110dB (single-ended)

113dB (differential)

- Digital High-pass Filter for Offset Cancellation

- Input PGA: 0dB to +18d B, 0.5dB/step (for single-en ded input)

- Input Digital Attenuator: 0dB to – 63dB, 0.5dB/step

- Overflow Flag

- Audio Interface Format: MSB justified or I2S

• 24-bit 2-channel DAC

- 24-bit 8 times Oversampling Linear Phase Digital Filter

Ripple: ±0.005dB

Stopband Attenuation: 75dB

- Switched-cap Low Pass Filter

- Differential Outputs

- S/(N+D): 97dB

- S/N: 115dB

- De-emphasis for 32kHz, 44.1kHz, 48kHz Sampling

- Output Digital Attenuator: Li near 255 steps

- Soft Mute

- Zero Detection Function

- Audio interface format: MSB justified, LSB justified, I2S, or DSD

• High Jitter Tolerance

• Sampling Rate: Up to 216kHz

• µP Interface: 3-wire Serial Interface

• Master Clock

- 128fs/192fs/256fs/384fs/512fs/768fs/1024fs

• Pow er Supply: 5V ± 5%(Analog), 3V~3.6V with 5V tolerant I/O(Digital)

• Small 30-pin VSOP package

• Ta: -10 to 70 °C

24-Bit 192kHz Audio CODEC with IPGA

AK4620B

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

- 2 -

 Block Diagram

A

INL+

VCOM

A

OUTL+

A

OUTL-

A

OUTR-

A

OUTR+

CSN/

DIF CCLK

/

CKS1 CDTI/

CKS0

SDTI

SDTO

BICK

LRCK

DGND

VT

VD

A

DC

DAC

HPF

DATT

SMUTE

A

udio I/F

Controller

Control Regist er I/F

PDN

MCLK

OVFL/DZFL

VREF VA

A

GND

OVFR/DZF

R

A

INL-/NC

A

INR+

A

INR-/NC

A

DMODE

DFS0

DEM0

P/S

DATT

OVF

Figure 1. Block Diagram

• Compatibility with AK4528 / AK4524

Function AK4524 AK4528 AK4620B

Max fs 96kHz 108kHz 216kHz

ADC Inputs Single-ended Differential Single-ended Differential

Input analog PGA 0dB ~ +18dB

0.5dB/step - 0 ~ +18dB

0.5dB/step -

Input digital ATT Mute, -72dB ~ 0dB

Pseudo-log step Mute, -72dB ~ 0dB

Pseudo-log step Mute,-63.5dB ~ 0dB

0.5dB/step Mute,-63.5dB ~ 0dB

0.5dB/step

ADC S/(N+D) 90dB 94dB 90dB 100dB

ADC DR, S/N 100dB 108dB 110dB 113dB

ADC Digital Filter SA 75dB 75dB 100dB

ADC Overflow detection - - X

DAC S/(N+D) 94dB 94dB 97dB

DAC DR, S/N 110dB 110dB 115dB

Output digital Attenuator Mute, -72dB ~ 0dB

Pseudo-log step Mute, -72dB ~ 0dB

Pseudo-log step Mute, -48dB ~ 0dB

Linear 256 steps Mute, -48dB ~ 0dB

Linear 256 steps

DAC DSD mode - - X

DAC Zero-data detection - - X

X’tal Os cil la ting Circu it X - -

Master Mode X - -

Parallel Mode - X X

X: Avai lable, -: N OT availa b le

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

- 3 -

 Ordering Guide

AK4620BVF -10∼+70°C 30pin VSOP (0.65mm pitch)

AKD4620B Evaluation Board

 Pin Layout

6

5

4

3

2

1

VCOM

A

INR+

A

INL+

A

IN

R

-/NC

A

INL-/N C

VREF

A

GND 7

VA 8

Top

View

10

9

P/S

MCLK

LRCK/DSDR 11

BICK/DCLK 12

13

14

SDTO

SDTI/DSDL

A

OUTR+

A

OUT

R

-

A

OUTL+

A

OUTL-

DGND

VD

VT

A

DMODE

DEM0

PDN

DFS0

CSN/DIF

25

26

27

28

29

30

24

23

21

22

20

19

18

17

CCLK/CKS1

CDTI/CKS0

15

OVFR/DZFR 16 OVFL/DZFL

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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PIN/FUNCTION

No. Pin Name I/O Function

1 VCOM O Common Voltage Output Pin, VA/2

Bias voltage of ADC inputs and DAC output s.

2 AINR+ I Rch Positive Input Pin

I Rch Negative Input Pin (whe n ADMODE pin=“H”)

3 AINR- I No Connect pin (when ADMODE pin=“L”)

No internal bonding. This pin should be open.

4 AINL+ I Lch Positive Input Pin

I Lch Negative Input Pin (when ADMODE pin=“H”)

5 AINL- I No Connect pin (when ADMODE pin=“L”)

No internal bonding. This pin should be open.

6 VREF I Voltage Reference Input Pin, VA

Used as a voltage reference by ADC & DAC. VREF is connected externally to filtered

VA.

7 AGND - Analog Ground Pin

8 VA - Analog Power Supply Pin, 4.75 ∼ 5.25V

9 P/S I Parallel/Serial Mode Select Pin

“L”: Serial Mode, “H”: Parallel Mode

Do not change this pin during PDN pin = “H”.

10 MCLK I Master Clock Input Pin

LRCK I Input/Output Channel Clock Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)

11 DSDR I DSD Rch Data Input Pin (when D/P bit=“1” in Serial Mode)

BICK I Audio Serial Data Clock Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)

12 D C LK I DSD Clock Pin (when D/P bit=“1” in Serial Mode)

13 SDTO O Audio Serial Data Output Pin

SDTI I Audio Serial Data Input Pi n (in Parallel mode or when D/P bit=“0” in Serial Mode)

14 DSDL I DSD Lch Data Input Pin (when D/P bit=“1” in Serial Mode)

OVFR O Rch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)

15 D ZFR O Rch Zero Dete ction Flag Pin (when ZOS bit=“1” in Serial Mode)

OVFL O Lch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)

16 DZFL O Lch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)

CDTI I Control Data Input Pin (in Serial Mode)

17 CKS0 I Master Clock Select Pin (in Parallel Mode)

CCLK I Control Data Clock Pin (in Serial Mode)

18 CKS1 I Master Clock Select Pin (in Parallel Mode)

CSN I Chip Select Pin in Serial Mode (in Serial Mode)

19 DIF I

Digital Audio Interface Select Pin (in Parallel Mode)

“L”: 24bit MSB justified, “H”: I2S compatible

20 DFS 0 I Double Speed Sa mpling Mode Pi n

21 PDN I Power-Down Mode Pin

“L”: Power down reset and initialize the control register, “H”: Power up

22 DEM0 I De-emphasis Control Pin

23 ADMODE I Analog Input Mode Sel ect Pin

“L”: Single-ended Input & IPGA Enable

“H”: Differential Input & IPGA Bypass

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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PIN/FUNCTION (Continued)

24 VT - Input Buffer Tolerant Pin, 3.0 ∼ 5.25V

25 VD - Digital Power Supply Pin, 3.0 ∼ 3.6V

26 DGND - Digital Ground Pin

27 AOUTL- O Lch Negative Analog Output Pin

28 AOUTL+ O Lch Positive Analog Output Pin

29 AOUTR- O Rch Negative Analog Output Pin

30 AOUTR+ O Rch Positive Analog Output Pin

Note. Do not allow digital input pins (P/S, MCLK, LRCK/DSDR, BICK/DCLK, SDTI/DSDL, CDTI/CKS0,

CCLK/CKS1, CSN/DIF, DFS0, PDN, DEM0 and ADMODE pins) to float.

 Handling of Unused Pin

The unused I/O pin should be processed appropriately as below.

Classification Pin Name Setting

AINL+, AINL-/NC, AINR+, AINR+NC These pins should be open when ADMODE pin = “L”.

AINL+, AINL-/NC AINL+ pin is connected to AINL-/NC pin when

ADMODE pin = “H”.

Analog Input

AINR+, AINR-/NC AINR+ pin is connected to AINR-/NC pin when

ADMODE pin = “H”.

Analog Output AOUTL+, AOUTL-, AOUTR+,

AOUTR- These pins should be open.

Digital Input DEM0 This pin should be connect ed to DVSS.

Digital Output OVFL/DZFL, OVFR/DZFR These pins should be open.

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

- 6 -

ABSOLUTE MAXIMUM RATINGS

(AGND, DGND=0V;Not e 1)

Parameter Symbol min max Units

Power Supplies:

Analog

Digital

Input Tolerant

|AGND – DGND| (Note 2)

VA

VD

VT

∆GND

-0.3

-

6.0

0.3

V

Input Current, Any Pin Except Supplies IIN - ±10 mA

Analog Input Voltage (Note 3) VINA -0.3 VA+0.3 V

Digital Input Voltage (Note 4) VIND -0.3 VT+0.3 V

Ambient Temperature (powered applied) Ta -10 70 °C

Storage Temperature Tstg -65 150 °C

Note 1. All voltages with respect to ground.

Note 2. AGND and DGND must be connected to the same analog ground plane.

Note 3. AINL+, AINL-/NC, AINR+ and AINR-/NC pins

Note 4. P/S, MCLK, LRCK/DSDR, B ICK/DCLK, SDTI/DSDL, CDTI/CKS0, CCLK/CKS1, CSN/DIF, DFS0, PDN,

DEM0 and ADMODE pins.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPE RATIN G CONDITIONS

(AGND, DGND=0V;Not e 1)

Parameter Symbol min typ max Units

Power Supplies

(Note 5)

Analog

Digital

Input Tolerant

VA

VD

VT

4.75

3.0

VD

5.0

3.3

5.0

5.25

3.6

5.25

V

Voltage Refer e nce VREF 3.0 - VA V

Note 5. The power up sequence among VA, VD and VT is not critical.

*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

- 7 -

ANALOG CHARACTERISTICS (ADC: Single-ended Input)

(Ta=25°C; VA=5V, VD=3.3V, VT=5V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency =1kHz; 24bit

Data; Measure ment frequency= 20Hz ∼ 20kHz at fs=44.1kHz, 40Hz ∼ 40kHz at fs= 96kHz, 40Hz ∼ 40kHz at fs=192kHz;

unless otherwise specified)

Parameter min typ max Units

Input PGA Characteristics:

Input Voltage (Note 6) 2.77 3.07 3.37 Vpp

Input Resistance (Note 7) 0.7 5.1 - kΩ

Step Size 0.2 0.5 0.8 dB

Gain Control Range 0 18 dB

ADC Analog Input Characteristics: IPGA=0dB

Resolution 24 Bits

fs=44.1kHz

BW=20kHz -1dBFS

-60dBFS 80

- 90

47

dB

fs=96kHz

BW=40kHz -1dBFS

-60dBFS -

- 90

44

dB

S/(N+D)

fs=192kHz

BW=40kHz -1dBFS

-60dBFS -

- 90

44

dB

Dynami c Range (-60dBFS with A-weighted) - 110 dB

S/N (A-weighted) 101 110 dB

Interchannel Isolat ion 90 105 dB

Interchannel Gain Mismatch 0.2 0.5 dB

Gain Drift 150 - ppm/°C

Power Supply Rejection (Note 8) - 50 dB

ANALOG CHARACTERISTICS (ADC: Differential Input)

(Ta=25°C; VA=5V, VD=3.3V, VT=5V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency =1kHz; 24bit

Data; Measure ment frequency= 20Hz ∼ 20kHz at fs=44.1kHz, 40Hz ∼ 40kHz at fs= 96kHz, 40Hz ∼ 40kHz at fs=192kHz;

unless otherwise specified)

Parameter min typ max Units

ADC Analog Input Characteristics:

Resolution 24 Bits

Input Voltage (Note 9) ±2.62 ±2.82 ±3.02 Vpp

Input Resistance fs=44.1kHz 8 14 - kΩ

fs=48kHz - 13 - kΩ

fs=96kHz - 13 - kΩ

fs=192kHz - 13 - kΩ

fs=44.1kHz

BW=20kHz -1dBFS

-60dBFS 90

- 100

50

dB

fs=96kHz

BW=40kHz -1dBFS

-60dBFS -

- 100

46

dB

S/(N+D)

fs=192kHz

BW=40kHz -1dBFS

-60dBFS -

- 100

46

dB

Dynamic Range (-60dBFS with A-weighted) - 113 dB

S/N (A-weighted) 103 113 dB

Interchannel Isolat ion 90 120 dB

Interchannel Gain Mismatch 0.1 0.5 dB

Gain Drift 20 - ppm/°C

Power Supply Rejection (Note 8) - 50 dB

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

- 8 -

Note 6. Full scale (0dB ) of the input voltage at PGA=0dB.

This voltage is proportional to VREF. Vin(ty p) = 3.07Vpp x VR EF/5.

Note 7. These values becom e smaller when a gain of IPGA is large.

IPGA=0dB; typ. 5.1kΩ, IPGA=+18dB; typ. 1.18kΩ

Note 8. PSR is applied to VA, VD, VT with 1kHz, 50mVpp. VREF pin is held a constant voltage.

Note 9. Full scale (0dB) of the input voltage at 0dB. This voltage is proportional to VREF.

Vin (typ) = ±2.82Vpp x VREF/5.

ANALOG CHARACTERISTICS (DAC)

(Ta=25°C; VA=5V, VD=3.3V, VT=5V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency =1kHz; 24bit

Data; Measure ment frequency= 20Hz ∼ 20kHz at fs=44.1kHz, 40Hz ∼ 40kHz at fs= 96kHz, 40Hz ∼ 40kHz at fs=192kHz;

unless otherwise specified)

DAC Analog Output Characteristics:

Parameter min typ max Units

Resolution 24 Bits

Dynamic Characteristics fs=44.1kHz

BW=20kHz 0dBFS

−60dBFS 87

- 97

52

dB

fs=96kHz

BW=40kHz 0dBFS

−60dBFS -

- 97

49

dB

S/(N+D)

fs=192kHz

BW=40kHz 0dBFS

−60dBFS -

- 97

49

dB

Dynamic Range (−60dBFS with A-weighted) (Note 10, Note 11) - 115 dB

S/N (A-weighted) (Note 11, Note 12) 107 115 dB

Interchannel Isolat ion (1kHz) 90 110 dB

DC Accuracy

Interchannel Gain Mismatch 0.15 0.3 dB

Gain Drift (Note 13) 20 - ppm/°C

Output Voltage (Note 14) ±2.6 ±2.8 ±3.0 Vpp

Load Capacitance 25 pF

Load Resistance (Note 15) 3 kΩ

Note 10. 100dB at 16bit data and 114dB at 20bit data.

Note 11. By Figure 19. External LPF Circuit Example 2 for PCM.

Note 12. S/N does not depend on input bit length.

Note 13. The voltage on VREF is held +5V externally.

Note 14. Full-scale voltage(0dB). Output voltage scales with the voltage of VREF.

AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = 5.6Vpp x VREF/5.

Note 15. For AC-load.

Parameter min typ max Units

Power Supplies

Power Supply Current

Normal Operation (PDN pin = “H” )

VA: ADC Single-ended Mode

ADC Differential Mode

60

55 90

83 mA

mA

VD+VT (fs=44.1kHz)

(fs=96kHz)

(fs=192kHz)

11

21

27

-

41

mA

Power-down mode (PDN pin = “L”) (Note 16)

VA

VD+VT

10

10 100

100

µA

Note 16. All digit al input pins are held VT or DGND.

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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ADC FILTER CHARACTERIST ICS (fs=44 .1kHz)

(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; Normal Speed Mode)

Parameter Symbol min typ max Units

ADC Digital Filter (Decimation LPF):

Passband (Note 17)

−0.005dB

−0.02dB

−0.06dB

−6.0dB

PB

0

-

20.25

20.4

22.05

19.8

-

kHz

Stopband (Note 17) SB 24.3 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 100 dB

Group Delay (Note 18) GD 43.2 1/fs

Group Delay Distortion ∆GD 0 µs

ADC Digital Filter (HPF):

Frequency Response (Note 17) −3dB

−0.1dB FR

0.9

6.0

Hz

ADC FILTER CHARACTERISTICS (fs=96kHz)

(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; Double Speed Mode)

Parameter Symbol min typ max Units

ADC Digital Filter (Decimation LPF):

Passband (Note 17)

−0.005dB

−0.02dB

−0.06dB

−6.0dB

PB

0

-

44.08

44.5

48.0

43.0

-

kHz

Stopband (Note 17) SB 53.0 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 100 dB

Group Delay (Note 18) GD 43.1 1/fs

Group Delay Distortion ∆GD 0 µs

ADC Digital Filter (HPF):

Frequency Response (Note 17) −3dB

−0.1dB FR

2.0

13.0

Hz

FILTE R CHAR ACTERIST I CS (fs=19 2kH z )

(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; Quad Speed Mode)

Parameter Symbol min typ max Units

ADC Digital Filter (Decimation LPF):

Passband (Note 17)

−0.005dB

−0.02dB

−0.06dB

−6.0dB

PB

0

-

88.18

89.0

96.0

86.0

-

kHz

Stopband (Note 17) SB 106.0 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 100 dB

Group Delay (Note 18) GD 38.2 1/fs

Group Delay Distortion ∆GD 0 µs

ADC Digital Filter (HPF):

Frequency Response (Note 17) −3dB

−0.1dB FR

4.0

26.0

Hz

Note 17. The passband and stopband frequencies scale with fs. The refere nce frequency of these responses is 1kHz.

Note 18. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the

setting of 24bit data both channels to the ADC output re gister for ADC.

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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DAC SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF;

SLOW = “0”)

Parameter Symbol min typ max Units

Digital Filter

Passband ±0.01dB (Note 19)

-6.0dB PB

0

-

22.05 20.0

- kHz

kHz

Stopband (Note 19) SB 24.1 kHz

Passband Ripple PR ± 0.005 dB

Stopband Attenuation SA 75 dB

Group Delay (Note 20) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 20.0kHz - ± 0.2 - dB

DAC SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)

(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 96kHz ; Double Speed Mode; DEM = OFF; SLOW

= “0”)

Parameter Symbol min typ max Units

Digital Filter

Passband ±0.01dB (Note 19)

-6.0dB PB

0

-

48.0 43.5

- kHz

kHz

Stopband (Note 19) SB 52.5 kHz

Passband Ripple PR ± 0.005 dB

Stopband Attenuation SA 75 dB

Group Delay (Note 20) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 40.0kHz - ± 0.3 - dB

DAC SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)

(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 192kHz; Quad Spe ed Mode; DEM = OF F; SLOW

= “0”)

Parameter symbol min typ max Units

Digital Filter

Passband ±0.01dB (Note 19)

-6.0dB PB

0

-

96.0 87.0

- kHz

kHz

Stopband (Note 19) SB 105 kHz

Passband Ripple PR ± 0.005 dB

Stopband Attenuation SA 75 dB

Group Delay (Note 20) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 80.0kHz - +0/-1 - dB

Note 19. The passband and stopband frequencies scale with fs.

For example, PB = 0.4535×fs (@±0.01dB), SB = 0.546×fs.

Note 20. Delay time caused by digital filtering. This time is from setting the 16/20/24bit data of both channels to input

register to the output of analog signa l.

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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DAC SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF;

SLOW = “1”)

Parameter Symbol min typ max Units

Digital Filter

Passband ±0.04dB (Note 21)

-3.0dB PB

0

-

18.2 8.1

- kHz

kHz

Stopband (Note 21) SB 39.2 kHz

Passband Ripple PR ± 0.005 dB

Stopband Attenuation SA 72 dB

Group Delay (Note 20) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 20.0kHz - +0/-5 - dB

DAC SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)

(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 96kHz ; Double Speed Mode; DEM = OFF; SLOW

= “1”)

Parameter Symbol min typ max Units

Digital Filter

Passband ±0.04dB (Note 21)

-3.0dB PB

0

-

39.6 17.7

- kHz

kHz

Stopband (Note 21) SB 85.3 kHz

Passband Ripple PR ± 0.005 dB

Stopband Attenuation SA 72 dB

Group Delay (Note 20) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 40.0kHz - +0/-4 - dB

DAC SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 1 92kHz)

(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 192kHz; Quad Spe ed Mode; DEM = OF F; SLOW

= “1”)

Parameter Symbol min typ max Units

Digital Filter

Passband ±0.04dB (Note 21)

-3.0dB PB

0

-

79.1 35.5

- kHz

kHz

Stopband (Note 21) SB 171 kHz

Passband Ripple PR ± 0.005 dB

Stopband Attenuation SA 72 dB

Group Delay (Note 20) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 80.0kHz - +0/-5 - dB

Note 21. The passband and stopband frequencies scale with fs.

For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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DIGITAL CHARACTERISTICS

(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V)

Parameter Symbol min typ max Units

High-Level Input Voltage

Low-Level Input Voltage VIH

VIL 70%VD

- -

- VT

30%VD V

V

High-Level Output Voltage (Iout=-100µA)

Low-Level Output Voltage (Iout=100µA) VOH

VOL VD-0.5

- -

0.5 V

V

Input Leakage Current Iin - - ±10 µA

SWITCHING CHARACTERISTICS

(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; CL=20pF)

Parameter Symbol min typ max Units

Master Clock Timing

Frequency

Pulse Width Low

Pulse Width High

fCLK

tCLKL

tCLKH

8.192

0.4/fCLK

55.296

MHz

ns

LRCK Frequency (Note 22)

Normal Speed Mode (DFS0=“0”, DFS1=”0”)

Double Speed Mode (DFS0=“1”, DFS1=”0”)

Quad Speed Mode (DFS0=“0”, DFS1=”1”)

Duty Cycl e

fsn

fsd

fsq

32

54

108

45

54

108

216

55

kHz

%

PCM Audio Interface Timing

BICK Period

Normal Speed Mode

Double Speed Mode

Quad Speed Mode

BICK Pulse Width Low

Pulse Width High

LRCK Edge to BICK “↑” (Note 23)

BICK “↑” to LRCK Edge (Note 23)

LRCK to SDTO (MSB) (Except I2S mode)

BICK “↓” to SDTO

SDTI Hold Time

SDTI Setup Time

tBCK

tBCKL

tBCKH

tLRB

tBLR

tLRS

tBSD

tSDH

tSDS

1/128fsn

1/64fsd

1/64fsq

33

20

ns

DSD Audio Interface Timing

DCLK Period

DCLK Pulse Width Low

Pulse Width High

DCLK Edge to DSDL/R (Note 24)

tDCK

tDCKL

tDCKH

tDDD

1/64fs

160

-20

20

ns

Note 22. When the normal/double/quad speed modes are switched, the AK4620B should be reset by PDN pin or RSTN

bit.

Note 23. BICK rising edge must not occur at the same time as LRC K edge.

Note 24. DSD data transm itting device must meet this time.

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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Parameter Symbol min typ max Units

Contr o l Interfac e Tim ing

CCLK Period

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN “H” Time

CSN “↓” to CCLK “↑”

CCLK “↑” to CSN “↑”

tCCK

tCCKL

tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

200

80

50

150

50

ns

Reset Timing

PDN Pulse Width (Note 25)

RSTAD “↑” to SDTO valid (Note 26)

tPD

tPDV

150

516

ns

1/fs

Note 25. The AK4620B can be reset by bringing PDN pin “L”.

Note 26. These cycles are the number of LRCK rising from RSTAD bit.

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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 Timing Diagram

1/fCLK

tCLKL

VIH

tCLKH

MCLK VIL

1/fs

LRCK VIH

VIL

tBCK

tBCKL

VIH

tBCKH

BICK VIL

Clock Timing

LRCK

BICK

SDTO

SDTI

tBLR tLRB

tLRS tBSD

tSDS tSDH

VIH

VIL

VIH

VIL

50%VD

VIH

VIL

Audio Interface Timing (PCM m ode)

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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VIH

DCLK VIL

tDDD

VIH

DSDL

DSDR VIL

tDCKHtDCKL

tDCK

Audio Serial Interface Timi ng (DSD Normal Mode, DCK B bit = “0”)

VIH

DCLK VIL

tDDD

VIH

DSDL

DSDR VIL

tDCKHtDCKL

tDCK

tDDD

Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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tCSS

CSN

VIH

CCLK VIL

VIH

CDTI VIL

VIH

VIL

C1 C0 R/W A4

tCCKL tCCKH

tCDS tCDH

WRITE Command Input Timing

CSN

VIH

CCLK VIL

VIH

CDTI VIL

VIH

VIL

D3 D2 D1 D0

tCSW

tCSH

WRITE Data Input Tim ing

tPD

PDN VIL

Power Down & Reset Timing

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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OPERATION OVERVIEW

 D/A Conversion Mode

In serial mode, the AK4620B can digitize either PCM data or DSD data. The P/D bit controls PCM/DSD mode. When

DSD m ode, DSD data input occurs on DCLK, DS DL and DSDR pins. The ADC and IPGA are in power down mode. In

PCM mode, PCM data input occurs on BICK, SDTI and LRCK pins. When PCM/DSD mode changes (D/P bit), the

AK4620B should be reset by setting RSTAD and RSTDA bits to “0” or by grounding the PDN pin. It takes from 2/fs to

3/fs to change the mode. In parallel mode, AK4620B can only process PCM data.

D/P bit DAC mode ADC mode

0 PCM PCM

1 DSD Power down

Table 1. DSD/PCM Mode Control

 System Clock Input

1. PCM Mode

AK4620B requires MC LK, BICK and LRCK external clocks. MCLK should be sync hronized with LRCK but the phase

is not critic al. External clocks (MCLK, BIC K and LRCK) should alw ays be present whenever t he AK4620B is i n normal

operation mode (PDN pin = “H” and either the ADC and DAC is in normal operation mode). If these cl ocks are not

provided, the AK4620B may draw excess current due to dynamic refresh of internal logic. If the external clocks are not

present, the AK4620B should be in the power-down mode (PDN pin = “L” or power down both the ADC and DAC by the

register). After e xiting reset (PDN pin = “L” Æ “ H”) at power-up etc., the AK4620B is in power-down mode until MCLK

and LRCK are provided.

As the AK4620B includes the phase detect circuit for LRCK, the AK4620B is reset automatically when the

synchronization is out of phas e by changing the clock frequencies.

1-1. Serial mode (P/S pin= “L”)

As shown in Table 2, Ta ble 3 and Table 4, select the MCLK frequency by setting CMODE, CKS0-1 and DFS0-1

(DFS0 bit and DFS0 pin are internally ORd). These registers are changed when RSTAD bit = RSTDA bit = “0”.

DFS1 bit OR of DFS0 bit /

DFS0 pin Mode Sampling Rate

0 0 Normal speed 32kHz-54kHz

Default

0 1 Double speed 54kHz-108kHz

1 0 Quad speed 108kHz-216kHz

1 1 N/A -

Table 2. Sampli ng speed in serial m ode

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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CMODE bit CKS1 bit CKS0 bit MCLK

Normal Speed

(DFS1-0 = “00”)

MCLK

Double Speed

(DFS1-0 = “01”)

MCLK

Quad Speed

(DFS1-0 = “10”)

0 0 0 256fs N/A N/A Default

0 0 1 512fs 256fs 128fs

0 1 0 1024fs 512fs 256fs

0 1 1 N/A Auto Setting Mode (*) N/A

1 0 0 384fs N/A N/A

1 0 1 768fs 384fs 192fs

Table 3. Master clock frequency in serial mode (“*”: refer to Table 4)

The Auto Setti ng Mode detects MCLK/LRC K ratio and selects Norma l/Double/Quad speed mode autom atically.

MCLK/LRCK ratio Mode Sampling Rate

512 or 768 Normal speed 32kHz-54kHz

256 or 384 Double speed 54kHz-108kHz

128 or 192 Quad speed 108kHz-216kHz

Table 4. Auto Setting Mode in serial mode (DFS1-0 = “01”, CMODE bit = “0”, CKS1-0 bit = “11”)

1-2. Parallel mode (P/S pin= “H”)

As shown in Table 5, Table 6 and Table 7, select the MCLK frequency with the CKS0-1 and DFS0 pins. These

pins should be changed when the PDN pin = “L”.

DFS0 pin Mode Sampling Rate

L Normal speed 32kHz-54kHz

H Double speed 54kHz-108kHz

Table 5. Sampli ng speed in parallel mode

CKS1 pin CKS0 pin MCLK

Normal Speed

(DFS0 pin = “L”)

MCLK

Double Speed

(DFS0 pin = “H”)

L L 256fs N/A

L H 512fs 256fs

H L 384fs Auto Setting Mode (*)

H H 1024fs 512fs

Table 6. Master clock fre quency in parallel mode (“*”; refer to Table 7.)

The Auto Setti ng Mode detects MCLK/LRC K ratio and selects Norma l/Double/Quad speed mode autom atically.

MCLK/LRCK ratio Mode Sampling Rate

512 or 768 Normal speed 32kHz-54kHz

256 or 384 Double speed 54kHz-108kHz

128 or 192 Quad speed 108kHz-216kHz

Table 7. Auto Setting Mode in parallel mode (DFS0 pin = “H”, CKS1 pin = “H”, CKS0 pin = “L”)

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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MCLK (Normal speed) fs=44.1kHz fs=48kHz MCLK (Double speed) fs=88.2kHz fs=96kHz

256fs 11.2896MHz 12.288MHz N/A N/A N/A

512fs 22.5792MHz 24.576MHz 256fs 22.5792MHz 24.576MHz

1024fs 45.1584MHz 49.152MHz 512fs 45.1584MHz 49.152MHz

384fs 16.9344MHz 18.432MHz N/A N/A N/A

768fs 33.8688MHz 36.864MHz 384fs 33.8688MHz 36.864MHz

MCLK (Quad speed) fs=176.4kHz fs=192kHz

128fs 22.5792MHz 24.576MHz

256fs 45.1584MHz 49.152MHz

192fs 33.8688MHz 36.864MHz

Table 8. Master clock frequency example

2. DSD Mode

The external clocks, which are required to operate the AK4620B, are MCLK and DCLK. The master clock (MCLK)

should be synchronized with DSD clock (DCLK) but the phase is not critical. The frequency of MCLK is set by DCKS

bit.

All external cloc ks (MCLK , DCLK) must be pre sent whenever the AK4620B i s in the norma l opera t ion m ode (P DN pin

= “H”). If these cl ocks are not provided, the AK4620B may draw excess current bec ause the device utilizes dynamically

refreshed logi c. The AK4620B should be reset by PDN pin = “L” aft er these clocks are provide d. If the external clocks are

not present, the AK4620B should be in the power-down mode (PDN pin = “L”). After exiting reset (PDN pin = “↑”) at

power-up etc., the AK4620B is in the power-down mode until MCLK is provided.

 Audio Serial Interface Format

1. PCM Mode

Five serial m odes a re supported and se lected by the DIF2-0 bi ts i n Serial Mode (two m odes by DIF pin in Parallel Mode )

as shown in Table 9 and Table 10. In all modes the serial data has MSB first, 2’s complement format. The SDTO is

clocked out on the falling edge of BICK and the SDTI is latched on the rising edge. Mode2 can be used for 20 and 16

MSB justified formats by zeroing the unused LSBs.

Mode DIF2 DIF1 DIF0 SDTO SDTI LRCK BICK

0 0 0 0 24bit, MSB justified 16bit, LSB justified H/L ≥ 48fs

1 0 0 1 24bit, MSB justified 20bit, LSB justified H/L ≥ 48fs

2 0 1 0 24bit, MSB justified 24bit, MSB justified H/L ≥ 48fs Default

3 0 1 1 24bit, I2S 24bit, I2S L/H ≥ 48fs

4 1 0 0 24bit, MSB justified 24bit, LSB justified H/L ≥ 48fs

Table 9. Audio data format (Serial Mode)

Mode DIF pin SDTO SDTI LRCK BICK

2 L 24bit, MSB justified 24bit, MSB justified H/L ≥ 48fs

3 H 24bit, I2S 24bit, I2S L/H ≥ 48fs

Table 10. Audio data format (Parallel Mode)

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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LRCK

BICK(64fs)

SDTO

(

o

)

0 1 2 1917 18 20 31 0 1 2 19 17 18 20 31 0

23

1

22 423 22 7 6 4 23

SDTI(i) 114 012 11 1 14 012 11

SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB

Lch Data Rch Data

Don’t Care Don’t Care

7 6 21 5 3

1315

30

21

3 3

53

15 13 2 2

Figure 2. Mode 0 Timing

LRCK

BICK(64fs)

SDTO

(

o

)

0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0

23

1

22 023 22 12 11 10 0 23

SDTI(i) 118 019 8 7 1 18 019 8 7

SDT O-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB

Lch Data Rch Data

Don’t Care Don’t Care

12 11 10

Figure 3. Mode 1 Timing

LRCK

BICK(64fs)

SDTO

(

o

)

0 1 2 18 19 20 21 22 0 1 2 18 19 20 22 21 0 1

SDTI(i)

23 24 25 23 24 25

23 22 4 23 22 5

45

4

122 023 3 2 1 22 0 23 3 2

23:MSB, 0:LSB Lch Data Rch Data

Don’t Ca re Don’t Care

5

5 4

1 0 32103 2 23

Figure 4. Mode 2 Timing

LRCK

BICK(64fs)

SDTO

(

o

)

0 1 2 3 19 20 21 22 0 1 2 3 19 20 22 21 0 1

SDTI(i)

23 24 25 23 24 25

23 22 4 23 22 5

45

4

122 023 3 2 1 22 0 23 3 2

23:MSB, 0:LSB Lch Data Rch Data

Don’t Care Don’t Care

5

5 4

1 0 32 103 2

Figure 5. Mode 3 Timing

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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LRCK

BICK(64fs)

SDTO

(

o

)

0 1 2 8 9 10 20 21 31 0 1 2 8 9 10 20 21 31 0

23

1

22 023 22 16 15 14 0 23

SDTI(i) 122 023 12 11 1 22 023 12 11

23:MSB, 0:LSB Lch Data Rch Data

Don’t Care Don’t Care

16 15 14

Figure 6. Mode 4 Timing

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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2. DSD Mode

In DSD mode, DIF0-2 is i gnored. The frequenc y of DCLK is fixed at 64fs. The DC KB bit inve rts the polari ty of DCLK.

DCLK (64fs)

DCKB=1

DCLK (64fs)

DCKB=0

DSDL,DSDR

Normal

DSDL,DSDR

Phase M odulation

D1

D0 D1 D2

D0 D2 D3

D1 D2 D3

Figure 7. DSD Mode Timing

 D/A conversion mode switching timing

RSTDA bit

D/A Data

D/A Mode

≥4/fs

≥0

PCM Data DSD Data

PCM Mode DSD Mode

Figure 8. D/A Mode Switching Timing (PCM to DSD)

RSTDA bit

D/A Data

D/A Mode

≥4/fs

DSD Data PCM Data

DSD Mode PCM Mode

Figure 9. D/A Mode Switching Mode Timing (DSD to PCM)

Caution: In DSD mode, the signal level ranges from 25% to 75%. Peak levels of DSD signal above this range are not

recommended by the SACD format book (Scarlet Book).

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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 Input Volume

The AK4620B includes two channel-independent analog volumes (IPGA), each with 32 levels in 0.5dB increments.

These are located in front of the ADC while digital volume controls (IATT) with 128 levels (including MUTE) are

located aft er the ADC. Control of both of these volume set tings is handled by the sam e register address. When the MSB of

the register is “1”, the IPGA changes and when the MSB = “0” t he IATT changes.

The IPGA is an analog volume control that improves the S/N ratio compared with digital volume controls (Table 11).

Level changes only occur during zero-crossings to minimize switching noise. Channel independent zero-crossing

detection is used. If there are no zero-crossings, then the level will change after a time-out. The time-out period scales

with fs. The periods of 256/fs, 512/fs, 1024/fs and 2048/fs are selected by ZTM1-0 bits in normal speed mode. If a new

value is written to the IPGA register before the IPGA changes at the zero crossing or time-out, the previous value

becomes invalid. The timer (channel independent) for time-out is reset and the timer restarts for the new IPGA value.

ZCEI bits in the control register enable zero-crossing detection.

The IATT is a log volume that is linear-interpol ated internally. When changing the level, the transition between ATT

values has 29 levels and is done by soft changes, eliminating any switching noise.

Input Gain Setting

0dB +6dB +18dB

fs=44.1kHz, A-weight 110dB 108dB 101dB

Table 11. IPGA+ADC S/N (typ.)

ZTM1 ZTM0 Normal speed Double speed Quad speed

0 0 256/fs 512/fs 1024/fs

0 1 512/fs 1024/fs 2048/fs

1 0 1024/fs 2048/fs 4096/fs

1 1 2048/fs 4096/fs 8192/fs

Default

Table 12. LRCK cycles for timeout period

 Output Volume

The AK4620B includes channel independent digital output volumes (ATT) with 256 levels at linear steps including

MUTE. These volumes are in front of the DAC and can attenuate the input data from 0dB to −48dB and mute. When

changing level s, t ransit i ons are e xec uted vi a soft change s, e liminat ing any swi t chi ng noise . The t ransit i on t i m e of 1 level

and all 256 levels is shown in Table 13.

Transition Time

Sampling Speed 1 Level 255 to 0

Normal Speed Mode 4LRCK 1020LRCK

Double Speed Mode 8LRCK 2040LRCK

Quad Speed Mode 16LRCK 4080LRCK

Table 13. ATT Transition Tim e

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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 Overflow Detection

The ADC has a cha nnel independent overflow detecti on function. This function is enable d in the parallel c ontrol mode, or

when the ZOS bit = ZOE bit = “0”in seri al control mode. OVF L/R pins go to “H” i f each Lch/Rch analog i nput overflows

(exceeds -0.3dBFS). The output of each OVFL/R pin has sam e group delay a s ADC against analog input. OVFL/R pin is

“L” for 516/fs (=10.8ms @fs=48kHz) after PDN pin = “↑”, and then overflow detection is enabled.

 Zero detection

The DAC has a cha nnel-independent zero detect function. The zero detect funct ion is enabled when the ZOS bi t = “1” and

the ZOE bit = “0”in se rial control mode. When the input data at both channels is conti nuously zero for 8192 LRCK cycles,

the DZF pin of each c hannel goe s t o “H”. The DZF pin of each c hannel immedi ate ly goes to “L” i f the input data of each

channe l is n ot zero aft er DZF “H”. If the RSTDA bit is “0 ”, the DZF pins of both channels go to “H”. DZF pins of both

channels go to “L” at 4~5/fs after the RSTDA bit becomes “1”. Zero detect function can be disabled by the ZOE bit. In

this case, the DZF pins of both channels are always “L”. The DZFB bit can invert the polarity of the DZF pin.

 Digital High Pass Filter

The ADC has a digital high pass fil ter for DC offset cancellation. The cut-off frequency of the HPF is 0.9Hz at

fs=44.1kHz. The digital high pass filter cutoff frequency scales with the sampling rate (fs). In parallel mode, the HPF is

always enable d. In se rial mode, t he HPF ca n control each channel by HPLN/HPRN bits.

 De-emphasis Filter

The DAC includes a digital de-emphasis fi lter (tc=50/15µs) via an inte grated IIR filter. This filter corresponds to three

frequencies (32kHz, 44.1kHz, 48kHz). This sett ing is done via control register (DEM1-0 bits). This filter is always OFF

in double and quad speed m odes. The DEM0 pin and DEM0 bi t are OR’d in serial cont rol mode. In parallel control m ode,

the DEM1 bi t is fixed to “ 0” and onl y t he DEM0 pin can be c ontrolled (44.1kHz or OFF). When in DSD mode, DEM1-0

bits are ignored. The setting value is held even if PCM mode and DSD mode are switched.

No DEM1 DEM0 Mode

0 0 0 44.1kHz

1 0 1 OFF

2 1 0 48kHz

3 1 1 32kHz

Default

Table 14. De-emphasis control (Normal Speed Mode)

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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 ADC Single-ended/Differential Input Mode

The ADC has a selec table single-ended or di fferential input m ode. This mode can be selecte d by ADMODE pin, AML bit

and AMR bit. (See Table 15 and Table 16) In differential input mode, the IPGA is powered-down and bypassed. IATT

can be controlled in differential mode.

ADMODE pin Lch Rch

L Single-ended Single-ended

H Differential Differential

Table 15. ADC Input Mode in parallel mode

ADMODE pin AML bit AMR bit Lch Rch

0 0 Single-ended Single-ended

0 1 Single-ended Differential

1 0 Differential Single-ended

L

1 1 Differential Differential

H X X Differential Differential

Table 16. ADC Input Mode in serial mode (X: Don’t care)

 Soft Mute Operation

Soft mute operation i s performed in the digital domain of the DAC input . When the SMUTE bit goes to “1”, the output

signal is attenuated by −∞ during ATT_DATA × ATT transition time (Tab le 12 ) from the curren t A TT lev e l. When

SMUTE bit is ret urned to “0”, the m ute is ca ncelled and the out put attenuat ion gradually changes to the ATT l evel during

ATT_DATA × ATT transition time. If soft mute is cancelled before attenuating to −∞ after startin g th e operation, the

attenuation i s discont inued and ret urns to ATT level by the sam e cy cle. The soft m ute is effecti ve for changi ng the signal

source without stopping the signal transmission.

SM UTE bit

A

ttenuation

D ZF pin

ATT_Level

-∞

A

OUT

8192/fs

GD GD

(1)

(2)

(3)

(4)

(1)

(2)

Notes:

(1) ATT_DATA × ATT transition time (Table 12). For example, this time is 1020LRCK cycles (1020/fs)

at ATT_DATA=255 in Normal Speed Mode.

(2) Analog output corresponding to digital input has group delay (GD).

(3) If the soft mute is cancelled before attenuating −∞ after starting the operation, the attenuation is discontinued

and returned to ATT level by the same cycle.

(4) When the input data at each channel is continuously zero for 8192 LRCK cycles, DZF pin of each channel goes

to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF pin “H”.

Figure 10. Soft Mute and Zero Detection

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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 Power Down & Reset

The ADC and DAC of AK4620B are placed in power-down mode by bringing the PDN pin = “L”. Each digital filter is

also reset at the same time. The internal register values are initialized by bringing PDN pin to “L”. This reset should

always be done after power-up. As both control registers of the ADC and the DAC go to the reset state (RSTAD bit =

RSTDA bit = “0”), each register should be cleared after performing the reset. In the case of the ADC, an analog

initiali zation cy cle sta rts afte r exiting the power-down or reset state. The output data (SDTO) is a vailable a fter 516 cycl es

of LRCK cloc k. This i niti ali zati on cy cle doe s not affec t the DAC operat ion. P ower down m ode can be also cont roll ed by

the register s (PWAD b it, PWDA bit).

Pow er Suppl

y

RSTAD(register

)

RSTDA(register

)

PWAD(register)

PW DA(register)

PWVR(register)

A

DC Internal State

IATT

SD TO

OATT

A

OU

T

DAC Internal State

External Mute

Examp le

External clocks

The cl ocks can be stopped

.

PD Reset INITA Normal PD INITA Normal

00H 00H

→ XXH XXH 00H 00H → XXH XXH

“0” “0”FI Output FI Output

PD Reset PD Normal Normal

FFH (1) FFH → XXH XXH XXH(2) XXH → YYH YYH

VCOM Hi-z FADE Output FAD E

MCLK, LRCK, BICK

PDN pin

****

FFH

Hi-z

• INITA: Initializing period of ADC analog section (516/fs).

• PD: Power down state. The contents of all registers are held.

• XXH, YYH: The current value in ATT registers.

• FI: Fade in. After exiting power down and reset state, ATT value fades in.

• FADE: After exiting power down and reset state, ATT value fades in/out.

(1) When RSTDA is “L” and OATT value is writte n to “XXH”, OATT value change s from FFH

to XXH according to fade operation.

(2) When PWDA is “L” a nd OATT value is wri tten to “YYH”, OA TT value changes from XXH

to YYH according to fade operation.

• AOUT: Some pop noise may occur at “*”.

Figure 11. Reset & Power down sequence in serial mode

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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In parallel mode, both ADC and DAC are powered up with releasing internal reset state when PDN pin is set to “H”.

When PDN pin i s “L” , IATT i s se t to “00H (M ute)”. Aft er exi ting powe r down mode, IATTs fade i n to “80H (0dB )”. At

that time, ADC s output “0” during first 516/fs cycles. DAC does not have the initialization cycle and the operation of

fade-in.

Power Supply

A

DC Internal State

SDTO

A

OUT

DAC Internal State

External Mute

Example

External clocks

The clocks can be stopped.

PD INITA Normal PD INITA Normal

“0” “0”Output Output

PD PDNormal Normal

Hi-Z Hi-Z Output

MCLK, LRCK, BICK

PDN pin

*

MCLK, LRCK, BICK

Output

**

IATT 00H 00HÆ80H 80H 00H 00HÆ80H 80H

FI FI

• INITA: Initializing period of ADC analog section (516/fs).

• PD: Power down state.

• FI: Fade in. After exiting power down and reset state, ATT value fades in.

• AOUT: Some pop noise may occur at “*”.

Figure 12. Reset & Power Down Sequence in parallel mode

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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 Serial Control Interface

The internal registers may be written to the 3-wire µP interface pins: CSN, CCLK, CDTI. The data on this interface

consists of Chip address (2bi ts, C0/1) Read/Write (1 bit), Register address (MSB first, 5 bi ts) and Control data (MSB first,

8 bits). Address and dat a is clocked in on the rising edge of CCLK. Data is latched out after the 16th risi ng edge of CCLK,

following a hi gh-to-low t ransition of C SN. Opera tion of the control serial port may be complet ely a synchronous with the

audio sample rat e. The maxi mum clock spee d of the CC LK is 5MHz. The chip address is fixed t o “10”. The access to the

chip address except for “10” is invalid. PDN pin = “L” resets the registers to their default values.

Function Parallel mode Serial mode

ADC Single-ended/Different ial Input mode X X

Overflow detection X X

Zero detection - X

Soft Mute - X

Input Volume - X

Output Vo l u me - X

HPF OFF - X

DSD mode - X

16/20/24 bit LSB justified format of DAC - X

MCLK = 256fs @ Quad Speed - X

De-emphasis: 32kHz, 48kHz - X

Table 17. Function List (X: available, -: not available)

CSN

CCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

CDTI C1 C0

A

2

A

3

A

1

A

0

A

4 D7D6D5D4D3D2D1D0 R/W

C1- C0: Chi p Addres s (Fi xed t o “10”)

R/W : READ/W R ITE (Fixed to “1”:W R ITE)

A

4-A0: Register Address

D7-D0: Control data

Figure 13. Control I/F Timing

* READ command is not supported.

* The control data can not be written when the CC LK rising edge is 15tim es or less or 17times or m ore during CSN is “L”.

ASAHI KASEI [AK4620B]

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 Register Map

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Power Down Control SLOW DZFB ZOE ZOS 0 PWVR PWAD PWDA

01H Reset Control D/P DCKS DCKB 0 AML AMR RSTAD RSTDA

02H Clock and Format Control DIF2 DIF1 DIF0 CMODE CKS1 CKS0 DFS1 DFS0

03H Deem and Volume Control SMUTE HPRN HPLN ZCEI ZTM1 ZTM0 DEM1 DEM0

04H Lch IPGA Control IPGL7 IPGL6 IPGL5 IPGL4 IPGL3 IPGL2 IPGL1 IPGL0

05H Rch IPGA Control IPGR7 IPGR6 IPGR5 IPGR4 IPGR3 IPGR2 IPGR1 IPGR0

06H Lch ATT Control ATTL7 ATTL6 ATTL5 ATTL4 ATTL3 ATTL2 ATTL1 ATTL0

07H Rch ATT Control ATTR7 ATTR6 ATTR5 ATTR4 ATTR3 ATTR2 ATTR1 ATTR0

Note: Data should not be written to addresses 08H through 1FH.

PDN pin = “L” resets the registe rs to their default values.

 Control Register Setup Sequence

When the PDN pin goes “L” to “H” upon power-up etc., the AK4620B will be ready for normal operation by the next

sequence. In this case, all control registers are set to default values and the AK4620B is in the reset state.

(1) Set the clock mode and the audio data interface mode.

(2) Cancel the reset state by setting RSTAD bit or RSTDA bit to “1”. Refer to Reset Contorl Register (01H).

(3) ADC output and DAC output should be m uted externally until canceling each reset state.

The clock mode shoul d be cha nged a ft er set ting RS TAD bit a nd RSTDA bit t o “0”. At t hat t ime, ADC out puts and DA C

outputs should be muted externally.

ASAHI KASEI [AK4620B]

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 Register Definitions

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Power Down Control SLOW DZFB ZOE ZOS 0 PWVR PWAD PWDA

DEFAULT 0 0 0 0 0 1 1 1

PWDA: DAC power down

0: Power down

1: Power up (Default)

“0” powers down only the DAC section and then the AOUTs go to Hi-Z immediately. The contents of all

registers are not initialized and enabled to write to the registers. After exiting power down mode, the OATTs

fade in/out the set ting value of the cont rol register (06H & 07H). The analog output should be muted externa lly

as some pop noise may occur when entering and exiting this mode.

PWAD: ADC power down

0: Power down

1: Power up (Default)

“0” powers down only the A DC and then the SDTO goes “L” i mmedia tely. The IPGAs al so go “00H”, but the

contents of all registers are not initialized and enabled to write to the registers. After exiting power down

mode, the IPG As fade in t he set ting value of the control registe r (04H & 05H). At that time, the ADC s output

“0” during first 516 LRCK cycles.

PWVR: Vref power down

0: Power down

1: Power up (Default)

“0” powers all sect ions down and the n both ADC and DAC do not ope rate. The contents of al l re gister values

are not initialized and enabled to write to the registers. When PWAD and PWDA bits go to “0” and PWVR bit

goes to “1”, only the VREF section can be powered up.

ZOS: Zero-detection/ Overflow-detection control for #15 and 16 pins.

0: Overflow detection for ADC input (Default)

1: Zero detecti on for DAC input.

ZOE: Zero-detection / Overflow-detection Disable

0: Enable ( De f ault)

1: Disable. Outputs “L”.

DZFB: Inverting Enable of DZF

0: DZF goes “H” at Zero Detection (Default)

1: DZF goes “L” at Zero Detection

SLOW: DAC Slow Roll-off Filter Enable

0: Sharp Roll-off Filter (Default)

1: Slow Roll-off Filter

ASAHI KASEI [AK4620B]

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

01H Reset Control D/P DCKS DCKB 0 AML AMR RSTAD RSTDA

DEFAULT 0 0 0 0 0 0 0 0

RSTDA: DAC reset

0: Reset (Default)

1: Normal Operation

“0” resets the i nte rnal timing and t he AOUTs go t o VCOM volta ge immedia t el y. The conte nts of all regi st ers

are not ini tialized and enabled to write to the regist ers. After exiting the power down m ode, the OATTs fade in

the setting values of the control register (06H & 07H). The analog outputs should be muted externally since

pop noise may occur when entering to and exiting from this mode.

RSTAD: ADC reset

0: Reset (Default)

1: Normal Operation

“0” resets the internal timing and then SDTO goes to “L” immediately. The IPGAs also go “00H”, but the

contents of all registers are not initialized and enabled to write to the register. After exiting the power down

mode, the IPG As fade in t he set ting value of the control registe r (04H & 05H). At that time, the ADC s output

“0” during first 516 LRCK cycles.

AML, AMR: defa ult “0” (see Table 16)

DCKB: Polarity of DCLK (DS D Only)

0: DSD data is available upon DCLK falling edge. (Default)

1: DSD data is available upon DCLK rising edge.

DCKS: Master Clock Frequency Select at DSD mode (DSD only)

0: 512fs (Default)

1: 768fs

D/P: DSD/PCM Mode Select

0: PCM mode (Default)

1: DSD mode

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

02H Clock and Format Control DIF2 DIF1 DIF0 CMODE CKS1 CKS0 DFS1 DFS0

DEFAULT 0 1 0 0 0 0 0 0

DFS1-0: Sampl ing Speed Control (see Table 2)

Default: Normal speed

CMODE, CKS1-0: Master Clock Frequency Select (see Table 3)

Default: 256fs

DIF2-0: Audio data interface modes (see Table 9)

000: Mode 0

001: Mode 1

010: Mode 2 (Default)

011: Mode 3

100: Mode 4

Default: 24bit MSB justified for both ADC and DAC

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

03H Deem and Volume Control SMUTE HPRN HPLN ZCEI ZTM1 ZTM0 DEM1 DEM0

DEFAULT 0 0 0 1 1 0 0 1

DEM1-0: De-empha sis response (see Table 3)

00: 44.1kHz

01: OFF (Default)

10: 48kHz

11: 32kHz

ZTM1-0: Zero-crossing timeout period select (see Table 11)

Default: 1024fs

ZCEI: ADC IPGA Zero crossing enable

0: Input PGA gain changes occur immediately

1: Input PGA gain changes occur only on zero-crossing or after timeout. (Default)

HPLN/RN: Left/Right channel Digital High Pass Filter Disable

0: Enable (Default)

1: Disable

SMUTE: DAC Input Soft Mute control

0: Normal operation (Default)

1: DAC outputs soft-muted

The soft mute is independent of the output ATT and performed digitally.

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

04H Lch IPGA Control IPGL7 IPGL6 IPGL5 IPGL4 IPGL3 IPGL2 IPGL1 IPGL0

05H Rch IPGA Control IPGR7 IPGR6 IPGR5 IPGR4 IPGR3 IPGR2 IPGR1 IPGR0

DEFAULT 1 0 0 0 0 0 0 0

IPGL/R7-0: ADC Input Gain Level

Refer to Table 10

Default: 80H (0dB)

The AK4620B includes two channel-independent analog volumes (IPGA), each with 32 levels in 0.5dB increments.

These are located in front of the ADC while digital volume controls (IATT) with 128 levels (including MUTE) are

located after the ADC. Control of both of these volume settings is handled by the same register address (04H for L-ch,

05H for R-ch). When the MSB of the re gister i s “1”, t he IPGA c hanges and whe n the MSB = “0” the IATT changes. 80H

is the crossover point of the IPGA and DATT, and both IPGA/IATT are set to 0dB.

The IPGAs are set to “00H” when the PDN pin goes “L”. After returning to “H”, the IPGAs fade in the default value,

“80H” by 531(1/ fs) cycl es. The IPGAs are set t o “00H” when PWAD goes “0” . After ret urning to “1” , the IPGAs fa de in

the current value, but the ADC out put is “0” during t he first 516(1/fs) cyc les. The IPAGs are set to “00H” when RSTAD

goes “0”. After ret urning to “1”, the IPGAs fade i n to the current value, but the ADC outputs “0” during the fi rst 516(1/fs)

cycles. IATTs can be controlled in differential mode.

Data Analog

Volume (dB) Digit al

ATT (dB) Total Gain (dB) St ep width

(dB)

FFH ~ A5H +18 0 +18 -

A4H +18 0 +18 -

A3H +17.5 0 +17.5 0.5

: : : : :

82H +1.0 0 +1.0 0.5

81H +0.5 0 +0.5 0.5

80H 0 0 0 0.5

IPGA

Analog volume with 0.5dB/step

7FH 0 -0.5 -0.5 0.5

7EH 0 -1.0 -1.0 0.5

: : : : :

02H 0 -63.0 -63.0 0.5

01H 0 -63.5 -63.5 0.5

00H 0 MUTE MUTE

IATT

Digital volume with 0.5dB/step.

Soft-changes between each level.

Table 10. IPGA code table

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

06H Lch OATT Control ATTL7 ATTL6 ATTL5 ATTL4 ATTL3 ATTL2 ATTL1 ATTL0

07H Rch OATT Control ATTR7 ATTR6 ATTR5 ATTR4 ATTR3 ATTR2 ATTR1 ATTR0

DEFAULT 1 1 1 1 1 1 1 1

ATT7-0: Attenuation Level

ATT = 20 log10 (ATT_DATA / 255) [dB]

FFH : 0dB (Default)

00H : Mu te

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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SYSTEM DESIGN

Figure 14 & Fi gure 15 shows the system connect ion diagram. An evaluation board (AKD4620B) is available, which

demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.

+

4.75 ∼ 5.25V

A

nalog S up p l y

10u

0.1u

0.1u0.1u

Rch Out

Lch Out

3.0 ∼ 5.25V

Digital Supply

Mode

Setting/

uP

Audio

DSP

Rch

LPF

Lch

LPF

VCOM

A

INR+

VREF

A

GND

VA

P/S

MCLK

LRCK

BICK

SDTO

SDTI CDTI/CKS0

CCLK/CKS1

CSN/DIF

DFS0

ADMODE

VT

VD

DGND

AOUTL-

AOUTL+

AOUTR-

AOUTR+

PDN

DEM0

1

2

3

5

6

7

8

9

11

12

13

14 17

18

19

20

21

22

23

26

27

28

29

30

A

K4620B

+

10

24

25

4

A

INR-

A

INL+

A

INL-

Rch

Input

Buffer

Lch

Input

Buffer

OVFR/DZFR OVFL/DZFL

15 16

3.0 ∼ 3.6V

Digital Supply

33p

330

Notes:

- AGND and DGND must be connected to the same analog ground plane.

- When AOUT+/- drives some capacitive load, some resistance should be added in series between AOUT+/- and

capacitive load.

- All digital input pins must not be left floating.

- When OVFR/DZFR pin and OVFL/DZFL pi n are used, a 330Ω resi stor and a 33pF capac itor should be a dded to

OVFR/DZFR pin and OVFL/DZFL pin to avoid the coupling from SDTO pin.

Figure 14. Typical Connection Diagram (Differential mode)

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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4.75 ∼ 5.25V

A

nalog Supply +

10u

0.1u

0.1u0.1u

Rch Out

Lch Out

3.0 ∼ 5.25V

Digital Supply

Mode

Setting/

uP

Audio

DSP

Rch

LPF

Lch

LPF

VCOM

A

INR+

VREF

A

GND

VA

P/S

MCLK

LRCK

BICK

SDTO

SDTI CDTI/CKS0

CCLK/CKS1

CSN/DIF

DFS0

ADMODE

VT

VD

DGND

AOUTL-

AOUTL+

AOUTR-

AOUTR+

PDN

DEM0

1

2

3

5

6

7

8

9

11

12

13

14 17

18

19

20

21

22

23

26

27

28

29

30

A

K4620B

+

10

24

25

4

NC

A

INL+

NC

OVFR/DZFR OVFL/DZFL

15 16

3.0 ∼ 3.6V

Digital Supply

33p

330

Notes:

- AGND and DGND must be connected to the same analog ground plane.

- When AOUT+/- drives some capacitive load, some resistor should be added in series between AOUT+/ - and

capacitive load.

- All digital input pins must not be left floating.

- When OVFR/DZFR pin and OVFL/DZFL pi n are used, a 330Ω resi stor and a 33pF capac itor should be a dded to

OVFR/DZFR pin and OVFL/DZFL pin to avoid the coupling from SDTO pin.

Figure 15. Typical Connection Diagram (Single-ended mode)

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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1

Analog Ground Digital Ground

System

Controller

2

3

4

5

6

7

8

9

10

11

12

30

29

28

27

26

25

24

23

22

21

20

19

13

14

18

17

VCOM

A

INR+

A

INR-/NC

A

INL+

A

INL-/NC

VREF

A

GND

VA

P/S

MCLK

LRCK

BICK

AOUTR+

AOUTR-

AOUTL+

AOUTL-

DGND

VD

VT

ADMODE

DEM0

PDN

DFS0

CSN/DIF

AK4620B

SDTO

SDTI

CCLK/CKS1

CDTI/CKS0

15 16

OVFR/DZFR OVFL/DZFL

Figure 16. Ground Layout

1. Grounding and Power Supply Decoupling

The AK4620B requires careful attention to power supply and grounding layout. To minim ize coupling from digit al noise,

decoupling capac itors should be connected to V A, VD and VT respectively . VA is supplied from the analog suppl y in the

system, and VD and VT are supplied from the digita l supply in the system. Power lines of VA, VD and VT should be

distributed separately from t he point with low impedance of regulator etc. The power up sequence is not critical among

VA, VD and VT. AGND and DGND must be connected to one analog ground plane. Decoupling capacitors

should be as near to the AK4620B as possible, with the small value cerami c capacitor being the nearest.

2. Voltage Reference

The differential voltage between VREF and A GND sets the analog input/output range. VREF pin is normally connected

to VA with a 0.1µF ceramic capacitor. VCOM is the signal ground of this chip. A 10µF electroly tic capacitor in parallel

with a 0.1µF cerami c capacitor atta ched to VCOM pin e liminates the effects of high frequency noise. No load curre nt may

be drawn from VC OM pin. All signa ls, especiall y clocks, should be kept away from the VREF and VCOM pins in order

to avoid unwanted coupling into the AK4620B.

3. ADC Outpu t

The ADC output data format is 2’s compl ement. The DC offset, including the ADC’s own DC offset, is removed by t he

internal HPF. The AK4620B sa mples the anal og inputs at 128fs. The digital filter rejects noi se above the stopband except

for multiples of 128fs.

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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4. Analog Inputs

4-1. Single-ended Input (ADMODE pin = “L”)

The IPGA inputs are single-ended. The input resistance of IPGA is typical ly 5.1kΩ at IPGA=0dB and typically

1.18kΩ at IPGA=+18dB. The input signal is typically AC coupled through a capacitor. The cut-off frequency is fc =

(1/2πRC). The input signal range scales with the VREF voltage and is nominally 3.07Vpp (VREF=5V) centered

around the internal common voltage (about VA/2). In single-ended mode, the AK4620B includes an anti-aliasing

filter (RC filter) to attenuate noise around 128fs.

4-2. Full-Differential Input (ADMODE pin = “H”)

The AK4620B can accept i nput voltages from AGND to VA. The input signal range scal es with the VREF voltage and

is nomi nally 2.82Vpp (VREF = 5V), centered a round the interna l com mon vol tage (a bout VA/2). Fi gure 17 shows an

input buffer circuit example. This is a fully differential input buffer circuit with an inverted amplifier (gain: −10dB).

The capacitor of 10nF between AINL+/− (AINR+/−) decreases the clock feedthrough noise of the modulator, and

composes a 1st order LPF (fc=360kHz) wi th a 22Ω resi stor before the capa cit or. This circ uit also has a 1st order LPF

(fc=370kHz) composed of op-amp. The evaluation board should be referred about the detail.

AIN+

AIN-

AK4620B

Analog In 4.7k

4.7k

VP+

VP-

NJM5532

47µ3k

470p

910

22

47µ3k

470p

910

22

Bias

10n

9.3Vpp

2.82Vpp

Bias

10µ0.1µBias

10k

VA

VA = 5V

VP+ = 15V

VP- = -15V

Figure 17. Input Buffer example in differential mode

ASAHI KASEI [AK4620B]

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5. Analog Outputs

The analog out puts are fully differential and 2.8Vpp (ty p. VREF = 5V), centered around VCOM . The different ial outputs

are summed externally: Vout = (AOUT+)-(AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output

range is 5.6Vpp (typ. VREF = 5V). The bi as voltage of the externa l summi ng circuit is supplied exte rnally. The input data

format is 2’s complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for

800000H(@24bit). The ideal AOUT is 0V for 000000H(@24bit).

The internal switched-capacitor filter and the external LPF attenuate the noise generated by the delta-sigma modulator

beyond the audio passband. Figure 18 shows an example of exte rnal LPF circuit summing the different ial outputs by an

op-amp. Figure 19 shows an example of differential outputs and LPF circuit example by t hree op-amps.

4.7k 4.7k

200

4.7k 200

4.7k 330p

+Vop

330p

-Vop

AOUT-

AOUT+

2.2n Analog

Out

AK4620B

Figure 18. External LPF Circuit Example 1 for PCM (fc = 136kHz, Q=0.694)

Frequency Response Gain

20kHz −0.01dB

40kHz −0.06dB

80kHz −0.59dB

Table 18. Filter Response of External LPF Circuit Example 1 for PCM

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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330

100u 180

AOUTL-

10k

3.9n

1.2k

680

3.3n

6

4

3

2 7 10u

0.1u

10u

NJM5534D

330

100u 180

AOUTL+

10k

3.9n

1.2k

680

3.3n

6

4

3

2 7 10u

0.1u

10u

NJM5534D 0.1u +

NJM5534D

0.1u 10u

100

4

3

2

1.0n

620

560

7

+

++

-

+

-

+

-

+

1.0n

Lch

-15

+15

6

560

Figure 19. External LPF Circuit Example 2 for PC M

1

st Stage 2nd Stage Total

Cut-off Frequency 182kHz 284kHz -

Q 0.637 - -

Gain +3.9dB -0.88dB +3.02dB

20kHz -0.025 -0.021 -0.046dB

40kHz -0.106 -0.085 -0.191dB

Frequency

Response 80kHz -0.517 -0.331 -0.848dB

Table 19. Filter Response of External LPF Circuit Example 2 for PCM

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

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It is recom mende d by SACD form at book (Scarl et Book) t hat the filte r response at S ACD play back is an a nalog low pass

filter with a cut-off frequency of maximum 50kHz and a slope of mini mum 30dB/Oct. The AK4620B can achieve this

filter response by combination of the internal filte r (Table 20) and an external filter (Figure 20).

Frequency Gain

20kHz −0.4dB

50kHz −2.8dB

100kHz −15.5dB

Table 20. Internal Filter Response at DSD mode

1.8k 4.3k

1.0k

1.8k 1.0k

4.3k 270p

+Vop

270p

-Vop

AOUT-

AOUT+

3300p Analog

Out

2.0k

2200p

-

+

2.8Vpp

6.34Vpp

2.8Vpp

Figure 20. External 3rd order LPF Circuit Example for DSD

Frequency Gain

20kHz −0.05dB

50kHz −0.51dB

100kHz −16.8dB

DC gain = 1.07dB

Table 21. 3rd order LPF (Figure 20) Response

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

- 41 -

PACKAGE

D e ta il A

NO TE: Dimension "*" does not include mold flash.

0.22±0.1 0.65

*9.7±0.1 1.5MAX

A

115

16

30

30pin VS OP (Unit: m m )

5.6±0.1

7.6±0.2

0.45±0.2

-0.0 5

+0.10

0.3

0.15

0.12 M

0.08

1.2±0.10

0.10 +0.10

-0.05

 Material & Lead finish

Package molding compound: Epoxy

Lead frame material: Cu

Lead frame surface treatment: Solder (Pb Free) plate

ASAHI KASEI [AK4620B]

MS0401-E-00 2005/07

- 42 -

MARKING

AKM

A

K4620BVF

XXXBYYYYC

XXXBYYYYC Date code identifier

XXXB : Lot number (X : Digit number, B : Alpha character)

YYYYC : Assembly date (Y : Digit number, C : Alpha character)

Revision History

Date (YY/MM/DD) Revision Reason Page Contents

05/07/08 00 First Edition

IMPORTANT NOTICE

• These products and their specifications are subject to change without notice. Before considering any use or

application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor

concerning their current status.

• AKM a ssumes no liabilit y for in fringem ent of a ny pa tent , in tellect ual prope rty , or other right in the a pplicat ion or

use of any information contained herein.

• Any export of these products, or devices or systems containing them, may require an export license or other

official approval under the law and regulations of the country of export pertaining to customs and tariffs,

currency exchange, or strategic materials.

• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or

other hazard related device or sy stem, and AKM assumes n o responsibility relat ing to any such use, except w ith

the express written consent of the Representative Director of AKM. As used here:

a. A hazard related device or system is one designed or intended for life support or maintenance of safety or

for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or

perform may reasonably be expected to result in loss of life or in significant injury or damage to person or

property.

b. A critical component is one whose failure to function or perform may reasonably be expected to result,

whet her d irectl y or indire ctly, i n t he loss of t he safety or effectiveness of the device or sy stem cont aining it,

and which must therefore meet very high standards of performance and reliability.

• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise

places the product with a thi rd party to notify that party in advance of the above content and conditio ns, and th e

buyer or di stributor agre es to assume an y a nd all responsi bility and liabi lity for and hold AKM harmless fr om any

and all claims arising from the use of said product in the absence of such notification.