Am29240 - Advanced Micro Devices

This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended

to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication #: 17787 Rev. C Amendment: /0

Issue Date: August 1995. WWW: 11/7/94

Advanced

Micro

Devices

Am29240 , Am29245 , and Am29243

High-Performance RISC Microcontrollers

ADVANCE INFORMATION

 

DISTINCTIVE CHARACTERISTICS

All three microcontrollers in the Am29240 microcon-

troller series have the following characteristics:

Completely integrated system for embedded

applications

Full 32-bit architecture

4-Kbyte, two-way set-associative instruction

cache

4-Gbyte virtual address space, 304-Mbyte

physical space implemented

Glueless system interfaces with on-chip wait

state control

36 VAX million instructions per second (MIPS)

sustained at 25 MHz

Four banks of ROM, each separately

programmable for 8-, 16-, or 32-bit interface

Four banks of DRAM, each separately

programmable for 16- or 32-bit interface

Single-cycle ROM burst-mode and DRAM

page-mode access

6-port peripheral interface adapter

16-line programmable I/O port

Bidirectional parallel port controller

Interrupt controller

Fully pipelined integer unit

Three-address instruction architecture

192 general purpose registers

Traceable Cache technology instruction and

data cache tracing

IEEE Std 1149.1-1990 (JTAG) compliant

Standard Test Access Port and

Boundary Scan Architecture

Binary compatibility with all 29K family

microprocessors and microcontrollers

Fully static system-clock capabilities

CMOS technology/TTL compatible

196-pin Plastic Quad Flat Pack (PQFP) package*

5-V power supply*

Note: * The new Am29240EH, Am29245EH, and Am29243EH

microcontrollers are packaged as 208-pin PQFPs and use a 3.3-V

power supply with 5-V-tolerant I/O. Before beginning a new design,

check with your field representative for schedule and availability of the

Am29240EH microcontroller series, described in Amendment 1 (order

#17787/1).

Am29240 Microcontroller

The Am29240 microcontroller has the following addi-

tional features:

2-Kbyte, two-way set-associative data cache

Single-cycle 32-bit multiplier for faster integer

math; two-cycle Multiply Accumulate (MAC)

function

16-entry on-chip Memory Management Unit

(MMU) with one Translation Look-Aside Buffer

4-channel double-buffered DMA controller with

queued reload

Two serial ports (UARTs)

Bidirectional bit serializer/deserializer

20- and 25-MHz operating frequencies

Scalable Clocking feature with full- and

double-speed internal clock

Am29245 Microcontroller

The low-cost Am29245 microcontroller is similar to the

Am29240 microcontroller, without the data cache and

32-bit multiplier. It includes the following features:

16-entry on-chip MMU with one TLB

Bidirectional bit serializer/deserializer

Two-channel DMA controller

One serial port (UART)

16-MHz operating frequency

Am29243 Microcontroller

The Am29243 data microcontroller is similar to the

Am29240 microcontroller , without the video interface. It

includes the following features:

2-Kbyte, two-way set-associative data cache

Single-cycle 32-bit multiplier for faster integer

math; two-cycle MAC

32-entry on-chip MMU with dual TLBs

4-channel, double-buffered DMA controller with

queued reload

Two serial ports (UARTs)

20- and 25-MHz operating frequencies

Scalable Clocking feature with full- and

double-speed internal clock

DRAM parity

AMD A D V A N C E I N F O R M A T I O N

2 Am29240 Microcontroller Series

TABLE OF CONTENTS

DISTINCTIVE CHARACTERISTICS 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Am29240 MICROCONTROLLER BLOCK DIAGRAM 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Am29245 MICROCONTROLLER BLOCK DIAGRAM 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Am29243 MICROCONTROLLER BLOCK DIAGRAM 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CUSTOMER SERVICE 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GENERAL DESCRIPTION 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Am29240 MICROCONTROLLER 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Am29245 MICROCONTROLLER 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Am29243 MICROCONTROLLER 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29K FAMILY DEVELOPMENT SUPPORT PRODUCTS 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

THIRD-PARTY DEVELOPMENT SUPPOR T PRODUCTS 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ORDERING INFORMATION 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RELATED AMD PRODUCTS 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

KEY FEATURES AND BENEFITS 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PERFORMANCE OVERVIEW 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN INFORMATION 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN DESCRIPTIONS 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CONNECTION DIAGRAM 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LOGIC SYMBOLS 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ABSOLUTE MAXIMUM RATINGS 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OPERATING RANGES 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC CHARACTERISTICS over COMMERCIAL Operating Ranges 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CAP ACITANCE 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SWITCHING WAVEFORMS 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SWITCHING TEST CIRCUIT 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

THERMAL CHARACTERISTICS 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PHYSICAL DIMENSIONS 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PQB 196 PLASTIC QUAD FLAT PACK, TRIMMED AND FORMED 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SOLDER LAND RECOMMENDATIONS 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMDA D V A N C E I N F O R M A T I O N

3

Am29240 Microcontroller Series

Am29240 MICROCONTROLLER BLOCK DIAGRAM

Interrupts, T raps

DRAM

Space

ROM

Memory

Serial Ports

Parallel Port

Controller 4-Channel DMA

Controller

Programmable

Interrupt

DRAM Controller

Timer/Counter

I/O Port

Controller

Serializer/

Deserializer

ROM

Controller

PIA

Controller

Am29000 CPU

Peripherals

62432

PIA

Chip Selects Address

Bus Instruction/Data

Bus

4

4 6 16 6

4/4

ROM

Chip Selects

Serial

Data

Printer/Scanner

Video

I/O

611

Parallel Port

Control/Status

Lines

Dual

2K DCache

32x32 Multiply

MMU

4K ICache

4 DREQ

58

Clock/

Lines

Control

JTAG

4

STAT

MEMCLK 4 DACK

GREQ/GACK/TDMA



RAS/CAS

Am29245 MICROCONTROLLER BLOCK DIAGRAM

Interrupts, T raps

DRAM

Space

ROM

Memory

Serial Port

Parallel Port

Controller 2-Channel DMA

Controller

Programmable

Interrupt

DRAM Controller

Timer/Counter

I/O Port

Controller

Serializer/

Deserializer

ROM

Controller

PIA

Controller

Am29000 CPU

Peripherals

62432

PIA

Chip Selects Address

Bus Instruction/Data

Bus

4

4 4 16 6

4/4

ROM

Chip Selects

Serial

Data

Printer/Scanner

Video

I/O

67

Parallel Port

Control/Status

Lines

Single

MMU

4K ICache

2 DREQ

58

Clock/

Lines

Control

JTAG

4

STAT

MEMCLK 2 DACK

GREQ/GACK/TDMA

RAS/CAS

AMD A D V A N C E I N F O R M A T I O N

4Am29240 Microcontroller Series

Am29243 MICROCONTROLLER BLOCK DIAGRAM

Interrupts, T raps

DRAM

Space

ROM

Memory

Serial Ports

Parallel Port

Controller 4-Channel DMA

Controller

Programmable

Interrupt

DRAM Controller

Timer/Counter

I/O Port

Controller

ROM

Controller

PIA

Controller

Am29000 CPU

Peripherals

62432

PIA

Chip Selects Address

Bus Instruction/Data

Bus

4

5 6 16 6

4/4

ROM

Chip Selects

Serial

Data I/O

611

Parallel Port

Control/Status

Lines

Dual

2K DCache

32x32 Multiply

MMU

4K ICache

4 DREQ

8

Clock/

Lines

Control

4

STAT

MEMCLK

JTAG

4 DACK

GREQ/GACK/TDMA

36

32

RAS/CAS

CUSTOMER SERVICE

AMD’s customer service network includes U.S. of fices,

international offices, and a customer training center . Ex-

pert technical assistance is available from AMD’s world-

wide staff of field application engineers and factory

support staff.

Hotline, E-mail, and Bulletin Board Support

For answers to technical questions, AMD provides a

toll-free number for direct access to our engineering

support staff. For overseas customers, the easiest way

to reach the engineering support staff with your ques-

tions is via fax with a short description of your question.

AMD 29K family customers also receive technical sup-

port through electronic mail. This worldwide service is

available to 29K family product users via the international

Internet e-mail service. Also available is the AMD bulletin

board service, which provides the latest 29K family prod-

uct information, including technical information and data

on upcoming product releases.

Engineering Support Staff

(800) 292-9263, ext. 2 toll-free for U.S.

0031-11-1163 toll-free for Japan

(512) 602-4118 direct dial worldwide

44-(0)256-811101 U.K. and Europe hotline

(512) 602-5031 fax

epd.support@amd.com e-mail

Bulletin Board

(800) 292-9263, ext. 1 toll-free for U.S.

(512) 602-7604 direct dial worldwide

Product Information

A simple phone call gets you free printed publications,

such as data books, user’s manuals, data sheets, ap-

plication notes, the Fusion29K Partner Solutions Cata-

log and Newsletter, and other literature. Internationally ,

contact your local AMD sales office for complete 29K

family literature. For electronic copies of the most cur-

rent product information and publications on the 29K

family, visit AMD’s worldwide web site on the Internet.

Literature Request

(800) 292-9263, ext. 3 toll-free for U.S.

(512) 602-5651 direct dial worldwide

(512) 602-7639 fax for U.S.

(800) 222-9323, option 2 AMD Facts-On-Demand

fax information service

toll-free for U.S.

http://www.amd.com worldwide web

AMDA D V A N C E I N F O R M A T I O N

5

Am29240 Microcontroller Series

GENERAL DESCRIPTION

The Am29240 microcontroller series is an enhanced

bus-compatible extension of the Am29200 RISC mi-

crocontroller family, with two to four times the perfor-

mance. The Am29240 microcontroller series includes

the Am29240 microcontroller, the low-cost Am29245

microcontroller , and the Am29243 data microcontroller.

The on-chip caches, MMU, faster integer math, and ex-

tended DMA addressing capability of the Am29240 mi-

crocontroller series allow the embedded systems

designer to provide increasing levels of performance

and software compatibility throughout a range of prod-

ucts (see Table 1 on page 7).

Based on a static low-voltage design, these CMOS-

technology devices offer a complete set of system pe-

ripherals and interfaces commonly used in embedded

applications. Compared to CISC processors, the

Am29240 microcontroller series offers better perfor-

mance, more efficient use of low-cost memories, lower

system cost, and complete design flexibility for the de-

signer. Coupled with hardware and software develop-

ment tools from AMD and the AMD Fusion29K

partners, the Am29240 microcontroller series provides

the embedded product designer with the cost and per-

formance edge required by today’s marketplace.

Am29240 Microcontroller

For general-purpose embedded applications, such as

mass-storage controllers, communications, digital sig-

nal processing, networking, industrial control, pen-

based systems, and multimedia, the Am29240

microcontroller provides a high-performance solution

with a low total-system cost. The memory interface of

the Am29240 microcontroller provides even faster di-

rect memory access than the Am29200 microcontroller .

This performance improvement minimizes the effect of

memory latency, allowing designers to use low-cost

memory with simpler memory designs. On-chip instruc-

tion and data caches provide even better performance

for time-critical code.

Other on-chip functions include: a ROM controller,

DRAM controller, peripheral interface adapter control-

ler , DMA controller, programmable I/O port, parallel port

controller, serial ports, and an interrupt controller . For a

complete description of the technical features, on-chip

peripherals, programming interface, and instruction set,

please refer to the

Am29240, Am29245, and Am29243

RISC Microcontrollers User’s Manual

(order #17741).

Am29245 Microcontroller

The low-cost Am29245 microcontroller is designed for

embedded applications in which cost and space

constraints, along with increased performance require-

ments, are primary considerations.

The Am29245 microcontroller also provides an easy up-

grade path for Am29200, Am29202, and Am29205

microcontroller-based products.

Am29243 Microcontroller

With DRAM parity support and a full MMU, the

Am29243 data microcontroller is recommended for

communications applications that require high-speed

data movement and fast protocol processing in a fault-

tolerant environment.

Both the Am29243 and Am29240 microcontrollers sup-

port fly-by DMA at 100 Mbytes/s for LANs and switching

applications, and a two-cycle Multiply Accumulate func-

tion for DSP applications. The low power requirements

make either microcontroller a good choice for field-

deployed devices.

29K Family

Development Support Products

Contact your local AMD representative for information

on the complete set of development support tools. The

following software and hardware development products

are available on several hosts:

Optimizing compilers for common high-level

languages

Assembler and utility packages

Source- and assembly-level software debuggers

Target-resident development monitors

Simulators

Execution boards

Third-Party

Development Support Products

The Fusion29K Program of Partnerships for Application

Solutions provides the user with a vast array of products

designed to meet critical time-to-market needs. Prod-

ucts/solutions available from the AMD Fusion29K part-

ners include the following:

Silicon products

Software generation and debug tools

Hardware development tools

Board-level products

Laser-printer solutions

Multiuser, kernel, and real-time operating systems

Graphics solutions

Networking and communication solutions

Manufacturing support

Custom software consulting, support, and training

AMD A D V A N C E I N F O R M A T I O N

6Am29240 Microcontroller Series

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the elements below.

Am29240 –25 C

TEMPERATURE RANGE

C = Commercial (TC = 0°C to +85°C)

PACKAGE TYPE

K = 196-Lead Plastic Quad Flat Pack (PQB 196)

SPEED OPTION

DEVICE NUMBER/DESCRIPTION

Am29240 RISC Microcontroller

Am29245 RISC Microcontroller

Am29243 RISC Data Microcontroller

Valid Combinations

Valid Combinations lists configurations

planned to be supported in volume. Consult

the local AMD sales office to confirm

availability of specific valid combinations, to

check on newly released combinations, and

to obtain additional data on AMD standard

military grade products.

Valid Combinations

–25 = 25 MHz

–20 = 20 MHz

–16 = 16 MHz

K\W

PROCESSING

\W = Trimmed and Formed (PQB 196)

Am29240–20 KC\W

Am29243–20

Am29245–16 KC\W

Am29240–25

KC\W

Am29243–25

RELATED AMD PRODUCTS

29K Family Devices

Product Description

Am29000R32-bit RISC microprocessor

Am29005Low-cost 32-bit RISC microprocessor with no MMU and no branch target cache

Am2903032-bit RISC microprocessor with 8-Kbyte instruction cache

Am2903532-bit RISC microprocessor with 4-Kbyte instruction cache

Am2904032-bit RISC microprocessor with 8-Kbyte instruction cache and 4-Kbyte data cache

Am2905032-bit RISC microprocessor with on-chip floating point

Am2920032-bit RISC microcontroller

Am29202Low-cost 32-bit RISC microcontroller with IEEE-1284-compliant parallel interface

Am29205Low-cost 32-bit RISC microcontroller

AMDA D V A N C E I N F O R M A T I O N

7

Am29240 Microcontroller Series

Table 1. Product Comparison—Am29200 Microcontroller Family

FEATURE Am29205

Controller Am29202

Controller Am29200

Controller Am29245

Controller Am29240

Controller Am29243

Controller

Instruction Cache — — — 4 Kbytes 4 Kbytes 4 Kbytes

Data Cache — — — — 2 Kbytes 2 Kbytes

Cache Associativity — — — 2-way 2-way 2-way

Integer Multiplier Software Software Software Software 32 x 32-bit 32 x 32-bit

Memory Management

Unit (MMU) — — — 1 TLB

16 Entry 1 TLB

16 Entry 2 TLBs

32 Entry

Data Bus Width

Internal

External 32 bits

16 bits 32 bits

32 bits 32 bits

32 bits

ROM Interface

Banks

Width

ROM Size (Max/Bank)

Boot-Up ROM Width

Burst-Mode Access

3

8, 16 bits

4 Mbytes

16 bits

Not Supported

4

8, 16, 32 bits

4 Mbytes

8, 16, 32 bits

Not Supported

4

8, 16, 32 bits

16 Mbytes

8, 16, 32 bits

Supported

4

8, 16, 32 bits

16 Mbytes

8, 16, 32 bits

Supported

4

8, 16, 32 bits

16 Mbytes

8, 16, 32 bits

Supported

4

8, 16, 32 bits

16 Mbytes

8, 16, 32 bits

Supported

DRAM Interface

Banks

Width

Size: 32-Bit Mode

Size: 16-Bit Mode

Video DRAM

Access Cycles

Initial/Burst

DRAM Parity

4

16 bits only

—

8 Mbytes/bank

Not Supported

3/2

No

4

16, 32 bits

16 Mbytes/bank

8 Mbytes/bank

Not Supported

3/2

No

4

16, 32 bits

16 Mbytes/bank

8 Mbytes/bank

Supported

3/2

No

4

16, 32 bits

16 Mbytes/bank

8 Mbytes/bank

Supported

3/1

No

4

16, 32 bits

16 Mbytes/bank

8 Mbytes/bank

Supported

3/1

No

4

16, 32 bits

16 Mbytes/bank

8 Mbytes/bank

Not Supported

3/1

Yes

On-Chip DMA

Width (ext. peripherals)

Total Number of Channels

Externally Controlled

External Master Access

External Master Burst

External Terminate Signal

8, 16 bits

2

1

No

8, 16, 32 bits

2

1

No

8, 16, 32 bits

2

Yes

No

Yes

8, 16, 32 bits

2

Yes

8, 16, 32 bits

4

Yes

8, 16, 32 bits

4

Yes

Scalable Clocking Double-

Frequency CPU Option No No No No Yes Yes

Low-Voltage Operation No No No Yes Yes Yes

Peripheral Interface

Adapter (PIA)

PIA Ports

Data Width

Min. Cycles Access

2

8, 16 bits

3

2

8, 16, 32 bits

3

6

8, 16, 32 bits

3

6

8, 16, 32 bits

1

6

8, 16, 32 bits

1

6

8, 16, 32 bits

1

Programmable I/O Port

(PIO)

Signals

Signals programmable

for interrupt generation

8

12

8

16

8

16

8

16

8

16

8

Serial Ports

Ports

DSR/DTR 1 Port

PIO signals 1 Port

Supported 1 Port

Supported 2 Ports

1 Port Supported 2 Ports

1 Port Supported

Interrupt Controller

External Interrupt Pins

External T rap and Warn

Pins

2

0

2

0

4

3

4

3

4

3

4

3

Parallel Port Controller

32-Bit T ransfer

IEEE-1284 Interface

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

JTAG Debug Support No Yes Yes Yes Yes Yes

Serializer/Deserializer Yes Yes Yes Yes Yes No

Pin Count and Package 100 PQFP 132 PQFP 168 PQFP 196 PQFP 196 PQFP 196 PQFP

Operating Voltage

VCC

I/O Tolerance 5 V

5 V 5 V

5 V

Processor Clock Rate 12, 16 MHz 12, 16, 20 MHz 16, 20 MHz 16 MHz 20, 25 MHz 20, 25 MHz

AMD A D V A N C E I N F O R M A T I O N

8Am29240 Microcontroller Series

KEY FEATURES AND BENEFITS

The Am29240 microcontroller series extends the line of

RISC microcontrollers based on 29K family architec-

ture, providing performance upgrades to the Am29205

and Am29200 microcontrollers. The RISC microcontrol-

ler product line allows users to benefit from the very high

performance of the 29K family architecture, while also

capitalizing on the very low system cost made possible

by integrating processor and peripherals.

The Am29240 microcontroller series expands the price/

performance range of systems that can be built with the

29K family. The Am29240 microcontroller series is fully

software compatible with the Am29000, Am29005,

Am29030, Am29035, Am29040, and Am29050 micro-

processors, as well as the Am29200 and Am29205 mi-

crocontrollers. It can be used in existing 29K family

microcontroller applications without software modifica-

tions.

On-Chip Caches

The Am29240 microcontroller series incorporates a

4-Kbyte, two-way instruction cache that supplies most

processor instructions without wait states at the proces-

sor frequency. For best performance, the instruction

cache supports critical-word-first reloading with fetch-

through, so that the processor receives the required

instruction and the pipeline restarts with minimum delay.

The instruction cache has a valid bit per word to mini-

mize the reload overhead. All cache array elements are

visible to software for testing and preload.

The Am29240 and Am29243 microcontrollers incorpo-

rate a 2-Kbyte, two-way set-associative data cache. The

data cache appears in the execute stage of the proces-

sor pipeline, so that loaded data is available immediate-

ly to the next instruction. This provides the maximum

performance for loads without requiring load schedul-

ing. The data cache performs critical-word-first, wrap-

around, and burst-mode refill with load-through. This

minimizes the time the processor waits on external data

as well as minimizing the reload time. The data cache

uses a write-through policy with a two-entry write buffer .

Byte, half-word, and word reads and writes are sup-

ported. All cache array elements are visible to software

for testing and preload.

Single-Cycle Multiplier

The Am29240 and Am29243 microcontrollers incorpo-

rate a full combinatorial multiplier that accepts two

32-bit input operands and produces a 32-bit result in a

single cycle. The multiplier can produce a 64-bit result

in two cycles. The multiplier permits maximum perfor-

mance without requiring instruction scheduling, since

the latency of the multiply is the same as the latency of

other integer operations. High-performance multiplica-

tion benefits imaging, signal processing, and state

modeling applications.

Complete Set of Common Peripherals

The Am29240 microcontroller series minimizes system

cost by incorporating a complete set of system facilities

commonly found in embedded applications, eliminating

the cost of additional components. The on-chip func-

tions include: a ROM controller, a DRAM controller, a pe-

ripheral interface adapter, a DMA controller, a

programmable I/O port, a parallel port, up to two serial

ports, and an interrupt controller. A video interface is

also included in the Am29240 and Am29245 microcon-

trollers for printer, scanner, and other imaging applica-

tions. These facilities allow many simple systems to be

built using only the Am29240 microcontroller series, ex-

ternal ROM, and/or DRAM memory.

ROM Controller

The ROM controller supports four individual banks of

ROM or other static memory, each with its own timing

characteristics. Each ROM bank may be a different size

and may be either 8, 16, or 32 bits wide. The ROM banks

can appear as a contiguous memory area of up to 64

Mbytes in size. The ROM controller also supports byte,

half-word, and word writes to the ROM memory space

for devices such as flash EPROMs and SRAMs.

DRAM Controller

The DRAM controller supports four separate banks of

dynamic memory. Each bank may be a different size and

may be either 16 or 32 bits wide. The DRAM banks can

appear as a contiguous memory area of up to 64 Mbytes

in size. The DRAM controller supports three-cycle ac-

cesses, with single-cycle page-mode and burst-mode

accesses.

Peripheral Interface Adapter

The Peripheral Interface Adapter (PIA) permits glueless

interfacing to as many as six external peripheral chips.

The PIA allows for additional system features imple-

mented by external peripheral chips.

DMA Controller

The DMA controller provides up to four channels for

transferring data between the DRAM and internal or ex-

ternal peripherals. The DMA channels are double buff-

ered to relax constraints on reload time.

I/O Port

The I/O port permits direct access to 16 individually pro-

grammable external input/output signals. Eight of these

signals can be configured to cause interrupts.

Parallel Port

The parallel port implements a bidirectional IBM PC-

compatible parallel interface to a host processor.

Serial Port

The serial port implements up to two full-duplex UARTs.

AMDA D V A N C E I N F O R M A T I O N

9

Am29240 Microcontroller Series

Serializer/Deserializer

The serializer/deserializer (video interface) on the

Am29240 and Am29245 microcontrollers permits direct

connection to a number of laser-marking engines, video

displays, or raster input devices such as scanners.

Interrupt Controller

The interrupt controller generates and reports the status

of interrupts caused by on-chip peripherals.

Wide Range of Price/Performance Points

To reduce design costs and time-to-market, the product

designer can use the Am29200 microcontroller family

and one basic system design as the foundation for an

entire product line. From this design, numerous imple-

mentations of the product at various levels of price and

performance may be derived with minimum time, effort,

and cost.

The Am29240 RISC microcontroller series supports this

capability through various combinations of on-chip

caches, programmable memory widths, programmable

wait states, burst-mode and page-mode access sup-

port, bus compatibility , and 29K family software compat-

ibility . A system can be upgraded using various memory

architectures without hardware and software redesign.

Within the Am29240 microcontroller series, the external

interfaces and the processor operate at frequencies in

the range of 16 to 25 MHz. Using the Scalable Clocking

feature on the Am29240 and Am29243 microcon-

trollers, the internal processor core can operate either at

the interface frequency or twice this frequency. For ex-

ample, the processor can operate at 25 MHz while the

interface operates at 12.5 MHz.

The ROM controller accommodates memories that are

either 8, 16, or 32 bits wide, and the DRAM controller ac-

commodates dynamic memories that are either 16 or 32

bits wide. This unique feature provides a flexible inter-

face to low-cost memory, as well as a convenient, flex-

ible upgrade path. For example, a system can start with

a 16-bit memory design and can subsequently improve

performance by migrating to a 32-bit memory design.

One particular advantage is the ability to add memory in

half-megabyte increments. This provides significant

cost savings for applications that do not require larger

memory upgrades.

The Am29200, Am29202, Am29205, Am29240,

Am29245, and Am29243 microcontrollers allow users

to address an extremely wide range of cost performance

points, with higher performance and lower cost than ex-

isting designs based on CISC microprocessors.

Glueless System Interfaces

The Am29240 microcontroller series also minimizes

system cost by providing a glueless attachment to exter-

nal ROMs, DRAMs, and other peripheral components.

Processor outputs have edge-rate control that allows

them to drive a wide range of load capacitances with low

noise and ringing. This eliminates the cost of external

logic and buffering.

Bus and Software Compatibility

Compatibility within a processor family is critical for

achieving a rational, easy upgrade path. Processors in

the Am29240 microcontroller series are all members of

a bus-compatible family of RISC microcontrollers. All

members of this family—the Am29205, Am29202,

Am29200, Am29240, Am29245, and Am29243 micro-

controllers—allow improvements in price, performance,

and system capabilities without requiring that users re-

design their system hardware or software. Bus compati-

bility ensures a convenient upgrade path for future

systems.

The Am29240 microcontroller series is available in a

196-pin plastic quad flat-pack (PQFP) package. The

Am29240 microcontroller series is signal-compatible

with the Am29200 and the Am29205 microcontrollers.

Moreover, the Am29240 microcontroller series is

binary compatible with existing RISC microcontrollers

and other members of the 29K family (the Am29000,

Am29005, Am29030, Am29035, Am29040, and

Am29050 microprocessors, as well as the Am29200,

Am29202, and Am29205 microcontrollers). The

Am29240 microcontroller series provides a migration

path to low-cost, high-performance, highly integrated

systems from other 29K family members, without re-

quiring expensive rewrites of application software.

Complete Development and

Support Environment

A complete development and support environment is vi-

tal for reducing a product’s time-to-market. Advanced

Micro Devices has created a standard development en-

vironment for the 29K family of processors. In addition,

the Fusion29K third-party support organization provides

the most comprehensive customer/partner program in

the embedded processor market.

Advanced Micro Devices offers a complete set of hard-

ware and software tools for design, integration, debug-

ging, and benchmarking. These tools, which are

available now for the 29K family, include the following:

Software development kit that includes the

High C 29K optimizing C compiler with assem-

bler, linker , ANSI library functions, 29K family archi-

tectural simulator, and MiniMON29K debug

monitor

XRAY29K source-level debugger

A complete family of demonstration and develop-

ment boards

AMD A D V A N C E I N F O R M A T I O N

10 Am29240 Microcontroller Series

In addition, Advanced Micro Devices has developed a

standard host interface (HIF) specification for operating

system services, the Universal Debugger Interface

(UDI) for seamless connection of debuggers to ICEs

and target hardware, and extensions for the UNIX com-

mon object file format (COFF).

This support is augmented by an engineering hotline, an

on-line bulletin board, and field application engineers.

Debugging and Testing

The Am29240 microcontroller series provides debug-

ging and testing features at both the software and

hardware levels.

Software debugging is facilitated by the instruction

trace facility and instruction breakpoints. Instruction

tracing is accomplished by forcing the processor to trap

after each instruction has been executed. Instruction

breakpoints are implemented by the HALT instruction

or by a software trap.

The processor provides several additional features to

assist system debugging and testing:

The Test/Development Interface is composed of a

group of pins that indicate the state of the processor

and control the operation of the processor.

A Traceable Cache feature permits a hardware-

development system to track accesses to the on-

chip caches, permitting a high level of visibility into

processor operation.

An IEEE Std 1149.1-1990 (JTAG) compliant Stan-

dard T est Access Port and Boundary-Scan Architec-

ture. The Test Access Port provides a scan interface

for testing processor and system hardware in a pro-

duction environment, and contains extensions that

allow a hardware-development system to control

and observe the processor without interposing hard-

ware between the processor and system.

PERFORMANCE OVERVIEW

The Am29240 microcontroller series offers a significant

margin of performance over CISC microprocessors in

existing embedded designs, since the majority of pro-

cessor features were defined for the maximum achiev-

able performance at very low cost. This section

describes the features of the Am29240 microcontroller

series from the point of view of system performance.

Instruction Timing

The Am29240 microcontroller series uses an arithmetic/

logic unit, a field shift unit, and a prioritizer to execute

most instructions. Each of these is organized to operate

on 32-bit operands and provide a 32-bit result. All opera-

tions are performed in a single cycle.

The performance degradation of load and store opera-

tions is minimized in the Am29240 microcontroller

series by overlapping them with instruction execution,

by taking advantage of pipelining, by an on-chip data

cache, and by organizing the flow of external data into

the processor so that the impact of external accesses is

minimized.

Pipelining

Instruction operations are overlapped with instruction

fetch, instruction decode and operand fetch, instruction

execution, and result write-back to the Register File.

Pipeline forwarding logic detects pipeline dependencies

and routes data as required, avoiding delays that might

arise from these dependencies. Pipeline interlocks are

implemented by processor hardware. Except for a few

special cases, it is not necessary to rearrange programs

to avoid pipeline dependencies, although this is some-

times desirable for performance.

On-Chip Instruction and Data Caches

On-chip instruction and data caches satisfy most pro-

cessor fetches without wait states, even when the pro-

cessor operates at twice the system frequency. The

caches are pipelined for best performance. The reload

policies minimize the amount of time spent waiting for

reload, while optimizing the benefit of locality of

reference.

Burst-Mode and Page-Mode Memories

The Am29240 microcontroller series directly supports

burst-mode memories. The burst-mode memory sup-

plies instructions at the maximum bandwidth, without

the complexity of an external cache or the performance

degradation due to cache misses.

The processor can also use the page-mode capability of

common DRAMs to improve the access time in cases

where page-mode accesses can be used. This is partic-

ularly useful in very low-cost systems with 16-bit-wide

DRAMs, where the DRAM must be accessed twice for

each 32-bit operand.

Instruction Set Overview

All 29K family members employ a three-address instruc-

tion set architecture. The compiler or assembly-lan-

guage programmer is given complete freedom to

allocate register usage. There are 192 general-purpose

registers, allowing the retention of intermediate calcula-

tions and avoiding needless data destruction. Instruc-

tion operands may be contained in any of the

general-purpose registers, and the results may be

stored into any of the general-purpose registers.

The Am29240 microcontroller series instruction set con-

tains 117 instructions that are divided into nine classes.

These classes are integer arithmetic, compare, logical,

shift, data movement, constant, floating point, branch,

and miscellaneous. The floating-point instructions are

not executed directly , but are emulated by trap handlers.

AMDA D V A N C E I N F O R M A T I O N

11

Am29240 Microcontroller Series

All directly implemented instructions are capable of

executing in one processor cycle, with the exception of

interrupt returns, loads, and stores.

Data Formats

The Am29240 microcontroller series defines a word as

32 bits of data, a half-word as 16 bits, and a byte as 8

bits. The hardware provides direct support for word-

integer (signed and unsigned), word-logical, word-Bool-

ean, half-word integer (signed and unsigned), and char-

acter data (signed and unsigned).

Word-Boolean data is based on the value contained in

the most significant bit of the word. The values TRUE

and FALSE are represented by the most significant bit

values 1 and 0, respectively.

Other data formats, such as character strings, are sup-

ported by instruction sequences. Floating-point formats

(single and double precision) are defined for the proces-

sor; however, there is no direct hardware support for

these formats in the Am29240 microcontroller series.

Protection

The Am29240 microcontroller series offers two mutually

exclusive modes of execution—the User and Supervi-

sor modes—that restrict or permit accesses to certain

processor registers and external storage locations.

The register file may be configured to restrict accesses

to Supervisor-mode programs on a bank-by-bank basis.

Memory Management Unit

The Am29240 microcontroller series provides a

memory-management unit (MMU) for translating virtual

addresses into physical addresses. The page size for

translation ranges from 1 Kbyte to 16 Mbytes in powers

of 4. The Am29245 and Am29240 microcontrollers each

have a single, 16-entry TLB. The Am29243 microcon-

troller has dual 16-entry TLBs, each capable of mapping

pages of different size.

Interrupts and Traps

When a member of the Am29240 microcontroller series

takes an interrupt or trap, it does not automatically save

its current state information in memory . This lightweight

interrupt and trap facility greatly improves the perfor-

mance of temporary interruptions such as simple

operating-system calls that require no saving of state in-

formation.

In cases where the processor state must be saved, the

saving and restoring of state information is under the

control of software. The methods and data structures

used to handle interrupts—and the amount of state

saved—may be tailored to the needs of a particular

system.

Interrupts and traps are dispatched through a 256-entry

vector table that directs the processor to a routine that

handles a given interrupt or trap. The vector table may

be relocated in memory by the modification of a proces-

sor register. There may be multiple vector tables in the

system, though only one is active at any given time.

The vector table is a table of pointers to the interrupt and

trap handlers, and requires only 1 Kbyte of memory. The

processor performs a vector fetch every time an inter-

rupt or trap is taken. The vector fetch requires at least

three cycles, in addition to the number of cycles required

for the basic memory access.

PIN DESCRIPTIONS

A23–A0

Address Bus (output, synchronous)

The Address Bus supplies the byte address for all ac-

cesses, except for DRAM accesses. For DRAM ac-

cesses, multiplexed row and column addresses are

provided on A14–A1. A2–A0 are also used to provide a

clock to an optional burst-mode EPROM.

BOOTW

Boot ROM Width (input, asynchronous)

This input configures the width of ROM Bank 0, so the

ROM can be accessed before the ROM configuration

has been set by the system initialization software. The

BOOTW signal is sampled during and after a processor

reset. If BOOTW is High before and after reset (tied

High), the boot ROM is 32 bits wide. If BOOTW is Low

before and after reset (tied Low), the boot ROM is 16 bits

wide. If BOOTW is Low before reset and High after reset

(tied to RESET), the boot ROM is 8 bits wide. This signal

has special hardening against metastable states, allow-

ing it to be driven with a slow-rise-time signal and permit-

ting it to be tied to RESET.

BURST

Burst-Mode Access (output, synchronous)

This signal is asserted to perform sequential accesses

from a burst-mode device.

CAS3–CAS0

Column Address Strobes, Byte 3–0

(output, synchronous)

A High-to-Low transition on these signals causes the

DRAM selected by RAS3–RAS0 to latch the column ad-

dress and complete the access. To support byte and

half-word writes, column address strobes are provided

for individual DRAM bytes. CAS3 is the column address

strobe for the DRAMs, in all banks, attached to

ID31–ID24. CAS2 is for the DRAMs attached to

ID23–ID16, and so on. These signals are also used in

other special DRAM cycles.

AMD A D V A N C E I N F O R M A T I O N

12 Am29240 Microcontroller Series

CNTL1–CNTL0

CPU Control

(input, asynchronous, internal pull-ups)

These inputs specify the processor mode: Load Test

Instruction, Step, Halt, or Normal.

DACKD–DACKA

DMA Acknowledge D through A

(output, synchronous)

These signals acknowledge an external transfer on a

DMA channel. DMA acknowledgments are not dedi-

cated to a particular DMA channel—each channel spec-

ifies which acknowledge line, if any , it is using. Only one

channel at a time can use either DACKD, DACKC,

DACKB, or DACKA, and the same channel uses the re-

spective DREQD–DREQA signal for transfer requests.

DMA transfers can occur to and from internal peripher-

als independent of these acknowledgments. The

DACKD and DACKC signals are supported on the

Am29240 and Am29243 microcontrollers only.

DREQD–DREQA

DMA Request D through A

(input, asynchronous, pull-up resistors)

These inputs request an external transfer on a DMA

channel. DMA requests are not dedicated to a particular

channel—each channel specifies which request line, if

any , it is using. Only one channel at a time can use either

DREQD, DREQC, DREQB, or DREQA. This channel ac-

knowledges a transfer using the respective DACKD–

DACKA signal. These requests are individually program-

mable to be either level- or edge-sensitive for either po-

larity of level or edge. DMA transfers can occur to and

from internal peripherals independent of these requests.

The DMA request/acknowledge pairs DREQA/DACKA

and DREQB/DACKB correspond to the Am29200 micro-

controller signals DREQ0/DACK0 and DREQ1/DACK1,

respectively. The pin placement reflects this correspon-

dence, and a processor reset dedicates these request/

acknowledge pairs to DMA channels 0 and 1,

respectively. This permits backward-compatible up-

grade to an Am29200 microcontroller . The DREQD and

DREQC signals are supported on the Am29240 and

Am29243 microcontrollers only.

DSRA

Data Set Ready, Port A (output, synchronous)

This indicates to the host that the serial port is ready to

transmit or receive data on Serial Port A.

DTRA

Data Terminal Ready, Port A

(input, asynchronous)

This indicates to the processor that the host is ready to

transmit or receive data on Serial Port A.

GACK

External Memory Grant Acknowledge

(output, synchronous)

This signal indicates to an external device that it has

been granted an access to the processor’s ROM or

DRAM, and that the device should provide an address.

The processor can be placed into a slave configuration

that allows tracing of a master processor. In this configu-

ration, GACK is used to indicate that the processor pipe-

line was held during the previous processor cycle.

GREQ

External Memory Grant Request

(input, synchronous, pull-up resistor)

This signal is used by an external device to request an

access to the processor ’s ROM or DRAM. To perform

this access, the external device supplies an address to

the ROM controller or DRAM controller.

To support a hardware-development system, GREQ

should be either tied High or held at a high-impedance

state during a processor reset.

ID31–ID0

Instruction/Data Bus (bidirectional, synchronous)

The Instruction/Data Bus (ID Bus) transfers instructions

to, and data to and from the processor.

IDP3–IDP0

Instruction/Data Parity

(bidirectional, synchronous)

If parity checking is enabled by the PCE bit of the

DRAM Control Register, IDP3–IDP0 are parity bits for

the ID Bus during DRAM accesses. IDP3 is the parity

bit for ID31–ID24, IDP2 is the parity bit for ID23–ID16,

and so on. If parity is enabled, the processor drives

IDP3–IDP0 with valid parity during DRAM writes, and

expects IDP3–IDP0 to be driven with valid parity during

DRAM reads. These signals are supported on the

Am29243 microcontroller only.

INCLK

Input Clock (input)

This is an oscillator input at twice the system operating

frequency . The processor operates either at the system

operating frequency or at the INCLK frequency , as con-

trolled by the TBO bit in the Configuration Register . The

processor can operate at the INCLK frequency only if

MEMCLK is an output.

INTR3–INTR0

Interrupt Requests 3–0

(input, asynchronous, internal pull-up resistors)

These inputs generate prioritized interrupt requests.

The interrupt caused by INTR0 has the highest priority,

AMDA D V A N C E I N F O R M A T I O N

13

Am29240 Microcontroller Series

and the interrupt caused by INTR3 has the lowest prior-

ity. The interrupt requests are masked in prioritized or-

der by the Interrupt Mask field in the Current Processor

Status Register and are disabled by the DA and DI bits of

the Current Processor Status Register. These signals

have special hardening against metastable states, al-

lowing them to be driven with slow-transition-time

signals.

LSYNC

Line Synchronization (input, asynchronous)

This signal indicates the start of a raster line. This signal

is supported on the Am29240 and Am29245 microcon-

trollers only.

MEMCLK

Memory Clock (input/output)

This is either a clock output or an input from an external

clock generator, as determined by the MEMDRV input. It

operates at the system operating frequency, which is

half of the INCLK frequency . Most processor inputs and

outputs are synchronous to MEMCLK. MEMCLK must

be driven with CMOS levels. MEMCLK must be an out-

put if the processor operates at the INCLK frequency.

MEMDRV

MEMCLK Drive Enable

(input, internal pull-up resistor)

This input determines whether MEMCLK is an output or

an input. If this pin is High, the processor generates a

clock on the MEMCLK output. If this pin is Low , the pro-

cessor accepts a clock generated by the system on the

MEMCLK input. This signal is tied High through an inter-

nal pull-up resistor so the signal can be left unconnected

to configure MEMCLK as an output.

PACK

Parallel Port Acknowledge (output, synchronous)

This signal is used by the processor to acknowledge a

transfer from the host or to indicate to the host that data

has been placed on the port.

PAUTOFD

Parallel Port Autofeed (input, asynchronous)

This signal is used by the host to indicate how line feeds

should be performed or is used to indicate that the host

is busy and cannot accept a data transfer.

PBUSY

Parallel Port Busy (output, synchronous)

This indicates to the host that the Parallel Port is busy

and cannot accept a data transfer.

PIACS5–PIACS0

Peripheral Chip Selects, Regions 5–0

(output, synchronous)

These signals are used to select individual peripheral

devices. DMA channels may be programmed to use

dedicated chip selects during an external peripheral

access.

PIAOE

Peripheral Output Enable (output, synchronous)

This signal enables the selected peripheral device to

drive the ID bus.

PIAWE

Peripheral Write Enable (output, synchronous)

This signal causes data on the ID bus to be written into

the selected peripheral.

PIO15–PIO0

Programmable Input/Output

(input/output, asynchronous)

These signals are available for direct software control

and inspection. PIO15–PIO8 may be individually pro-

grammed to cause processor interrupts. These signals

have special hardening against metastable states, al-

lowing them to be driven with slow-transition-time

signals.

The PIO signals are sampled during a processor reset.

After reset, the sampled value is held in the PIO Input

Register. This sampled value is supplied the first time

this register is read, unless the read is preceded by write

to the PIO Input Register or by a read or write of any oth-

er PIO register. This may be used to indicate system

configuration information to the processor during a

reset.

POE

Parallel Port Output Enable (output, synchronous)

This signal enables an external data buffer containing

data from the host to drive the ID Bus.

PSTROBE

Parallel Port Strobe (input, asynchronous)

This signal is used by the host to indicate that data is on

the Parallel Port or to acknowledge a transfer from the

processor.

PSYNC

Page Synchronization

(input/output, asynchronous)

This signal indicates the beginning of a raster page. This

signal is supported on the Am29240 and Am29245 mi-

crocontrollers only.

AMD A D V A N C E I N F O R M A T I O N

14 Am29240 Microcontroller Series

PWE

Parallel Port Write Enable (output, synchronous)

This signal writes a buffer with data on the ID Bus. Then,

the buffer drives data to the host.

R/W

Read/Write (output, synchronous)

During an external ROM, DRAM, DMA, or PIA access,

this signal indicates the direction of transfer: High for a

read and Low for a write.

RAS3–RAS0

Row Address Strobe, Banks 3–0

(output, synchronous)

A High-to-Low transition on one of these signals causes

a DRAM in the corresponding bank to latch the row ad-

dress and begin an access. RAS3 starts an access in

DRAM Bank 3, and so on. These signals also are used in

other special DRAM cycles.

RESET

Reset (input, asynchronous)

This input places the processor in the Reset mode. This

signal has special hardening against metastable states,

allowing it to be driven with a slow-rise-time signal.

ROMCS3–ROMCS0

ROM Chip Selects, Banks 3–0

(output, synchronous)

A Low level on one of these signals selects the memory

devices in the corresponding ROM bank. ROMCS3 se-

lects devices in ROM Bank 3, and so on. The timing and

access parameters of each bank are individually pro-

grammable.

ROMOE

ROM Output Enable (output, synchronous)

This signal enables the selected ROM Bank to drive the

ID bus. It is used to prevent bus contention when switch-

ing between different ROM banks or switching between

a ROM bank and another device or DRAM bank.

RSWE

ROM Space Write Enable (output, synchronous)

This signal is used to write an alterable memory in a

ROM bank (such as an SRAM or Flash EPROM).

RXDA

Receive Data, Port A (input, asynchronous)

This input is used to receive serial data to Serial Port A.

RXDB

Receive Data, Port B (input, asynchronous)

This input is used to receive data to Serial Port B. This

signal is supported on the Am29240 and Am29243 mi-

crocontrollers only.

STAT2–STAT0

CPU Status (output, synchronous)

These outputs indicate information about the processor

or the current access for the purposes of hardware

debug.

TCK

Test Clock Input

(input, asynchronous, pull-up resistor)

This input is used to operate the Test Access Port. The

state of the Test Access Port must be held if this clock is

held either High or Low . This clock is internally synchro-

nized to MEMCLK for certain operations of the Test Ac-

cess Port controller, so signals internally driven and

sampled by the Test Access Port are synchronous to

processor internal clocks.

TDI

Test Data Input

(input, synchronous to TCK, pull-up resistor)

This input supplies data to the test logic from an external

source. It is sampled on the rising edge of TCK. If it is not

driven, it appears High internally.

TDMA

Terminate DMA (input/output, synchronous)

This signal is either an input or an output as controlled by

the corresponding DMA Control Register. As an input,

this signal can be asserted during an external DMA

transfer (non-fly-by) to terminate the transfer after the

current access. The TDMA input is ignored during fly-by

transfers. As an output, this signal is asserted to indicate

the final transfer of a sequence.

TDO

Test Data Output

(three-state output, synchronous to TCK)

This output supplies data from the test logic to an exter-

nal destination. It changes on the falling edge of TCK. It

is in the high-impedance state except when scanning is

in progress.

TMS

Test Mode Select

(input, synchronous to TCK, pull-up resistor)

This input is used to control the Test Access Port. If it is

not driven, it appears High internally.

AMDA D V A N C E I N F O R M A T I O N

15

Am29240 Microcontroller Series

TR/OE

Video DRAM Transfer/Output Enable

(output, synchronous)

This signal is used with video DRAMs to transfer data to

the video shift register. It is also used as an output en-

able in normal video DRAM read cycles. This signal is

supported on the Am29240 and Am29245 microcontrol-

lers only.

TRAP1–TRAP0

Trap Requests 1–0

(input, asynchronous, internal pull-ups)

These inputs generate prioritized trap requests. The

trap caused by TRAP0 has the highest priority. These

trap requests are disabled by the DA bit of the Current

Processor Status Register. These signals have special

hardening against metastable states, allowing them to

be driven with slow-transition-time signals.

TRIST

Three-State Control

(input, asynchronous, pull-up resistor)

This input is asserted to force all processor outputs into

the high-impedance state. This signal is tied High

through an internal pull-up resistor.

Note:

TRIST

does not control the

MEMCLK

pin. To

three-state

MEMCLK

, the user must drive

MEMDRV

Low.

TRST

Test Reset Input

(input, asynchronous, pull-up resistor)

This input asynchronously resets the Test Access Port.

If TRST is not driven, it appears High internally. TRST

must be tied to RESET, even if the Test Access Port is

not being used.

TXDA

Transmit Data, Port A (output, asynchronous)

This output is used to transmit serial data from Serial

Port A.

TXDB

Transmit Data, Port B (output, asynchronous)

This output is used to transmit data from Serial Port B.

This signal is supported on the Am29240 and Am29243

microcontrollers only.

UCLK

UART Clock (input)

This is an oscillator input for generating the UART (Seri-

al Port) clock. T o generate the UART clock, the oscillator

frequency may be divided by any amount up to 65,536.

The UART clock operates at 16 times the Serial Port’s

baud rate. As an option, UCLK may be driven with

MEMCLK or INCLK. It can be driven with TTL levels.

VCLK

Video Clock (input, asynchronous)

This clock is used to synchronize the transfer of video

data. As an option, VCLK may be driven with MEMCLK

or INCLK. It can be driven with TTL levels. This signal is

supported on the Am29240 and Am29245 microcon-

trollers only.

VDAT

Video Data (input/output, synchronous to VCLK)

This is serial data to or from the video device. This signal

is supported on the Am29240 and Am29245 microcon-

trollers only.

WAIT

Add Wait States

(input, synchronous, internal pull-up)

External accesses are normally timed by the processor .

However, the WAIT signal may be asserted during a

PIA, ROM, or DMA access to extend the access

indefinitely.

WARN

Warn (input, asynchronous, edge-sensitive,

internal pull-up)

A High-to-Low transition on this input causes a non-

maskable WARN trap to occur. This trap bypasses the

normal trap vector fetch sequence, and is useful in situa-

tions where the vector fetch may not work (e.g., when

data memory is faulty). This signal has special harden-

ing against metastable states, allowing it to be driven

with a slow-transition-time signal.

WE

Write Enable (output, synchronous)

This signal is used to write the selected DRAM bank.

“Early write” cycles are used so the DRAM data inputs

and outputs can be tied to the common ID Bus.

AMD A D V A N C E I N F O R M A T I O N

16 Am29240 Microcontroller Series

CONNECTION DIAGRAM

196-Pin PQFP

Top Side View

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

Am29240 Microcontroller Series

Note:

Pin 1 marked for orientation.

AMDA D V A N C E I N F O R M A T I O N

17

Am29240 Microcontroller Series

PQFP PIN DESIGNATIONS (Pin Number)

ÁÁÁÁ

Pin No.

ÁÁÁÁÁÁ

Pin Name

ÁÁÁÁÁ

Pin No.

ÁÁÁÁÁÁ

Pin Name

ÁÁÁÁ

Pin No.

ÁÁÁÁÁÁ

Pin Name

ÁÁÁÁ

Pin No.

ÁÁÁÁÁÁ

Pin Name

ÁÁÁÁ

1

ÁÁÁÁÁÁ

VCC

ÁÁÁÁÁ

50

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

99

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

148

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

2

ÁÁÁÁÁÁ

MEMCLK

ÁÁÁÁÁ

51

ÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

100

ÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

149

ÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

3

ÁÁÁÁÁÁ

MEMDRV

ÁÁÁÁÁ

52

ÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

101

ÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

150

ÁÁÁÁÁÁ

PIO12

ÁÁÁÁ

4

ÁÁÁÁÁÁ

INCLK

ÁÁÁÁÁ

53

ÁÁÁÁÁÁ

TXDB 3

ÁÁÁÁ

102

ÁÁÁÁÁÁ

A23

ÁÁÁÁ

151

ÁÁÁÁÁÁ

PIO11

ÁÁÁÁ

5

ÁÁÁÁÁÁ

ID31

ÁÁÁÁÁ

54

ÁÁÁÁÁÁ

RXDB 3

ÁÁÁÁ

103

ÁÁÁÁÁÁ

A22

ÁÁÁÁ

152

ÁÁÁÁÁÁ

PIO10

ÁÁÁÁ

6

ÁÁÁÁÁÁ

ID30

ÁÁÁÁÁ

55

ÁÁÁÁÁÁ

DTRA

ÁÁÁÁ

104

ÁÁÁÁÁÁ

A21

ÁÁÁÁ

153

ÁÁÁÁÁÁ

PIO9

ÁÁÁÁ

7

ÁÁÁÁÁÁ

ID29

ÁÁÁÁÁ

56

ÁÁÁÁÁÁ

RXDA

ÁÁÁÁ

105

ÁÁÁÁÁÁ

A20

ÁÁÁÁ

154

ÁÁÁÁÁÁ

PIO8

ÁÁÁÁ

8

ÁÁÁÁÁÁ

ID28

ÁÁÁÁÁ

57

ÁÁÁÁÁÁ

UCLK

ÁÁÁÁ

106

ÁÁÁÁÁÁ

A19

ÁÁÁÁ

155

ÁÁÁÁÁÁ

PIO7

ÁÁÁÁ

9

ÁÁÁÁÁÁ

ID27

ÁÁÁÁÁ

58

ÁÁÁÁÁÁ

DSRA

ÁÁÁÁ

107

ÁÁÁÁÁÁ

A18

ÁÁÁÁ

156

ÁÁÁÁÁÁ

PIO6

ÁÁÁÁ

10

ÁÁÁÁÁÁ

ID26

ÁÁÁÁÁ

59

ÁÁÁÁÁÁ

TXDA

ÁÁÁÁ

108

ÁÁÁÁÁÁ

A17

ÁÁÁÁ

157

ÁÁÁÁÁÁ

PIO5

ÁÁÁÁ

11

ÁÁÁÁÁÁ

ID25

ÁÁÁÁÁ

60

ÁÁÁÁÁÁ

ROMCS3

ÁÁÁÁ

109

ÁÁÁÁÁÁ

A16

ÁÁÁÁ

158

ÁÁÁÁÁÁ

PIO4

ÁÁÁÁ

12

ÁÁÁÁÁÁ

ID24

ÁÁÁÁÁ

61

ÁÁÁÁÁÁ

ROMCS2

ÁÁÁÁ

110

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

159

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

13

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

62

ÁÁÁÁÁÁ

ROMCS1

ÁÁÁÁ

111

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

160

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

14

ÁÁÁÁÁÁ

VCC

ÁÁÁÁÁ

63

ÁÁÁÁÁÁ

ROMCS0

ÁÁÁÁ

112

ÁÁÁÁÁÁ

A15

ÁÁÁÁ

161

ÁÁÁÁÁÁ

PIO3

ÁÁÁÁ

15

ÁÁÁÁÁÁ

ID23

ÁÁÁÁÁ

64

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

113

ÁÁÁÁÁÁ

A14

ÁÁÁÁ

162

ÁÁÁÁÁÁ

PIO2

ÁÁÁÁ

16

ÁÁÁÁÁÁ

ID22

ÁÁÁÁÁ

65

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

114

ÁÁÁÁÁÁ

A13

ÁÁÁÁ

163

ÁÁÁÁÁÁ

PIO1

ÁÁÁÁ

17

ÁÁÁÁÁÁ

ID21

ÁÁÁÁÁ

66

ÁÁÁÁÁÁ

BURST

ÁÁÁÁ

115

ÁÁÁÁÁÁ

A12

ÁÁÁÁ

164

ÁÁÁÁÁÁ

PIO0

ÁÁÁÁ

18

ÁÁÁÁÁÁ

ID20

ÁÁÁÁÁ

67

ÁÁÁÁÁÁ

RSWE

ÁÁÁÁ

116

ÁÁÁÁÁÁ

A11

ÁÁÁÁ

165

ÁÁÁÁÁÁ

TDO

ÁÁÁÁ

19

ÁÁÁÁÁÁ

ID19

ÁÁÁÁÁ

68

ÁÁÁÁÁÁ

ROMOE

ÁÁÁÁ

117

ÁÁÁÁÁÁ

A10

ÁÁÁÁ

166

ÁÁÁÁÁÁ

STAT2

ÁÁÁÁ

20

ÁÁÁÁÁÁ

ID18

ÁÁÁÁÁ

69

ÁÁÁÁÁÁ

RAS3

ÁÁÁÁ

118

ÁÁÁÁÁÁ

A9

ÁÁÁÁ

167

ÁÁÁÁÁÁ

STAT1

ÁÁÁÁ

21

ÁÁÁÁÁÁ

ID17

ÁÁÁÁÁ

70

ÁÁÁÁÁÁ

RAS2

ÁÁÁÁ

119

ÁÁÁÁÁÁ

A8

ÁÁÁÁ

168

ÁÁÁÁÁÁ

STAT0

ÁÁÁÁ

22

ÁÁÁÁÁÁ

ID16

ÁÁÁÁÁ

71

ÁÁÁÁÁÁ

RAS1

ÁÁÁÁ

120

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

169

ÁÁÁÁÁÁ

VDAT 2

ÁÁÁÁ

23

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

72

ÁÁÁÁÁÁ

RAS0

ÁÁÁÁ

121

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

170

ÁÁÁÁÁÁ

PSYNC 2

ÁÁÁÁ

24

ÁÁÁÁÁÁ

VCC

ÁÁÁÁÁ

73

ÁÁÁÁÁÁ

CAS3

ÁÁÁÁ

122

ÁÁÁÁÁÁ

A7

ÁÁÁÁ

171

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

25

ÁÁÁÁÁÁ

ID15

ÁÁÁÁÁ

74

ÁÁÁÁÁÁ

CAS2

ÁÁÁÁ

123

ÁÁÁÁÁÁ

A6

ÁÁÁÁ

172

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

26

ÁÁÁÁÁÁ

ID14

ÁÁÁÁÁ

75

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

124

ÁÁÁÁÁÁ

A5

ÁÁÁÁ

173

ÁÁÁÁÁÁ

GREQ

ÁÁÁÁ

27

ÁÁÁÁÁÁ

ID13

ÁÁÁÁÁ

76

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

125

ÁÁÁÁÁÁ

A4

ÁÁÁÁ

174

ÁÁÁÁÁÁ

DREQB

ÁÁÁÁ

28

ÁÁÁÁÁÁ

ID12

ÁÁÁÁÁ

77

ÁÁÁÁÁÁ

CAS1

ÁÁÁÁ

126

ÁÁÁÁÁÁ

A3

ÁÁÁÁ

175

ÁÁÁÁÁÁ

DREQA

ÁÁÁÁ

29

ÁÁÁÁÁÁ

ID11

ÁÁÁÁÁ

78

ÁÁÁÁÁÁ

CAS0

ÁÁÁÁ

127

ÁÁÁÁÁÁ

A2

ÁÁÁÁ

176

ÁÁÁÁÁÁ

TDMA

ÁÁÁÁ

30

ÁÁÁÁÁÁ

ID10

ÁÁÁÁÁ

79

ÁÁÁÁÁÁ

TR/OE

ÁÁÁÁ

128

ÁÁÁÁÁÁ

A1

ÁÁÁÁ

177

ÁÁÁÁÁÁ

TRAP0

ÁÁÁÁ

31

ÁÁÁÁÁÁ

ID9

ÁÁÁÁÁ

80

ÁÁÁÁÁÁ

WE

ÁÁÁÁ

129

ÁÁÁÁÁÁ

A0

ÁÁÁÁ

178

ÁÁÁÁÁÁ

TRAP1

ÁÁÁÁ

32

ÁÁÁÁÁÁ

ID8

ÁÁÁÁÁ

81

ÁÁÁÁÁÁ

GACK

ÁÁÁÁ

130

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

179

ÁÁÁÁÁÁ

INTR0

ÁÁÁÁ

33

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

82

ÁÁÁÁÁÁ

PIACS5

ÁÁÁÁ

131

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

180

ÁÁÁÁÁÁ

INTR1

ÁÁÁÁ

34

ÁÁÁÁÁÁ

VCC

ÁÁÁÁÁ

83

ÁÁÁÁÁÁ

PIACS4

ÁÁÁÁ

132

ÁÁÁÁÁÁ

BOOTW

ÁÁÁÁ

181

ÁÁÁÁÁÁ

INTR2

ÁÁÁÁ

35

ÁÁÁÁÁÁ

ID7

ÁÁÁÁÁ

84

ÁÁÁÁÁÁ

PIACS3

ÁÁÁÁ

133

ÁÁÁÁÁÁ

WAIT

ÁÁÁÁ

182

ÁÁÁÁÁÁ

INTR3

ÁÁÁÁ

36

ÁÁÁÁÁÁ

ID6

ÁÁÁÁÁ

85

ÁÁÁÁÁÁ

PIACS2

ÁÁÁÁ

134

ÁÁÁÁÁÁ

PAUTOFD

ÁÁÁÁ

183

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

37

ÁÁÁÁÁÁ

ID5

ÁÁÁÁÁ

86

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

135

ÁÁÁÁÁÁ

PSTROBE

ÁÁÁÁ

184

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

38

ÁÁÁÁÁÁ

ID4

ÁÁÁÁÁ

87

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

136

ÁÁÁÁÁÁ

PWE

ÁÁÁÁ

185

ÁÁÁÁÁÁ

WARN

ÁÁÁÁ

39

ÁÁÁÁÁÁ

ID3

ÁÁÁÁÁ

88

ÁÁÁÁÁÁ

PIACS1

ÁÁÁÁ

137

ÁÁÁÁÁÁ

POE

ÁÁÁÁ

186

ÁÁÁÁÁÁ

VCLK 2

ÁÁÁÁ

40

ÁÁÁÁÁÁ

ID2

ÁÁÁÁÁ

89

ÁÁÁÁÁÁ

PIACS0

ÁÁÁÁ

138

ÁÁÁÁÁÁ

PACK

ÁÁÁÁ

187

ÁÁÁÁÁÁ

LSYNC 2

ÁÁÁÁ

41

ÁÁÁÁÁÁ

ID1

ÁÁÁÁÁ

90

ÁÁÁÁÁÁ

PIAWE

ÁÁÁÁ

139

ÁÁÁÁÁÁ

PBUSY

ÁÁÁÁ

188

ÁÁÁÁÁÁ

TMS

ÁÁÁÁ

42

ÁÁÁÁÁÁ

ID0

ÁÁÁÁÁ

91

ÁÁÁÁÁÁ

PIAOE

ÁÁÁÁ

140

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

189

ÁÁÁÁÁÁ

TRST

ÁÁÁÁ

43

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

92

ÁÁÁÁÁÁ

R/W

ÁÁÁÁ

141

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

190

ÁÁÁÁÁÁ

TCK

ÁÁÁÁ

44

ÁÁÁÁÁÁ

VCC

ÁÁÁÁÁ

93

ÁÁÁÁÁÁ

DACKB

ÁÁÁÁ

142

ÁÁÁÁÁÁ

PIO15

ÁÁÁÁ

191

ÁÁÁÁÁÁ

TDI

ÁÁÁÁ

45

ÁÁÁÁÁÁ

IDP3 1, 3

ÁÁÁÁÁ

94

ÁÁÁÁÁÁ

DACKA

ÁÁÁÁ

143

ÁÁÁÁÁÁ

PIO14

ÁÁÁÁ

192

ÁÁÁÁÁÁ

RESET

ÁÁÁÁ

46

ÁÁÁÁÁÁ

IDP2 1, 3

ÁÁÁÁÁ

95

ÁÁÁÁÁÁ

DACKD 3

ÁÁÁÁ

144

ÁÁÁÁÁÁ

PIO13

ÁÁÁÁ

193

ÁÁÁÁÁÁ

CNTL1

ÁÁÁÁ

47

ÁÁÁÁÁÁ

IDP1 1, 3

ÁÁÁÁÁ

96

ÁÁÁÁÁÁ

DACKC 3

ÁÁÁÁ

145

ÁÁÁÁÁÁ

DREQD 3

ÁÁÁÁ

194

ÁÁÁÁÁÁ

CNTL0

ÁÁÁÁ

48

ÁÁÁÁÁÁ

IDP0 1, 3

ÁÁÁÁÁ

97

ÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

146

ÁÁÁÁÁÁ

DREQC 3

ÁÁÁÁ

195

ÁÁÁÁÁÁ

TRIST

ÁÁÁÁ

Á

ÁÁ

Á

49

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

GND

ÁÁÁÁÁ

Á

ÁÁÁ

Á

98

ÁÁÁÁÁÁ

ÁÁÁÁÁ

Á

GND

ÁÁÁÁ

ÁÁÁ

Á

147

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

GND

ÁÁÁÁ

Á

ÁÁ

Á

196

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

GND

Notes: All values are typical and preliminary.

1. Defined as a no-connect on the Am29240 microcontroller . 2. Defined as a no-connect on the Am29243 microcontroller .

3. Defined as a no-connect on the Am29245 microcontroller .

AMD A D V A N C E I N F O R M A T I O N

18 Am29240 Microcontroller Series

PQFP PIN DESIGNATIONS (Pin Name)

ÁÁÁÁÁÁ

Pin Name

ÁÁÁÁ

Pin No.

ÁÁÁÁÁÁ

Pin Name

ÁÁÁÁÁ

Pin No.

ÁÁÁÁÁ

Pin Name

ÁÁÁÁÁ

Pin No.

ÁÁÁÁÁÁ

Pin Name

ÁÁÁÁ

Pin No.

ÁÁÁÁÁÁ

A0

ÁÁÁÁ

129

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

76

ÁÁÁÁÁ

INCLK

ÁÁÁÁÁ

4

ÁÁÁÁÁÁ

Reserved

ÁÁÁÁ

149

ÁÁÁÁÁÁ

A1

ÁÁÁÁ

128

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

87

ÁÁÁÁÁ

INTR0

ÁÁÁÁÁ

179

ÁÁÁÁÁÁ

RESET

ÁÁÁÁ

192

ÁÁÁÁÁÁ

A2

ÁÁÁÁ

127

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

98

ÁÁÁÁÁ

INTR1

ÁÁÁÁÁ

180

ÁÁÁÁÁÁ

ROMCS0

ÁÁÁÁ

63

ÁÁÁÁÁÁ

A3

ÁÁÁÁ

126

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

110

ÁÁÁÁÁ

INTR2

ÁÁÁÁÁ

181

ÁÁÁÁÁÁ

ROMCS1

ÁÁÁÁ

62

ÁÁÁÁÁÁ

A4

ÁÁÁÁ

125

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

120

ÁÁÁÁÁ

INTR3

ÁÁÁÁÁ

182

ÁÁÁÁÁÁ

ROMCS2

ÁÁÁÁ

61

ÁÁÁÁÁÁ

A5

ÁÁÁÁ

124

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

130

ÁÁÁÁÁ

LSYNC 2

ÁÁÁÁÁ

187

ÁÁÁÁÁÁ

ROMCS3

ÁÁÁÁ

60

ÁÁÁÁÁÁ

A6

ÁÁÁÁ

123

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

140

ÁÁÁÁÁ

MEMCLK

ÁÁÁÁÁ

2

ÁÁÁÁÁÁ

ROMOE

ÁÁÁÁ

68

ÁÁÁÁÁÁ

A7

ÁÁÁÁ

122

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

147

ÁÁÁÁÁ

MEMDRV

ÁÁÁÁÁ

3

ÁÁÁÁÁÁ

RSWE

ÁÁÁÁ

67

ÁÁÁÁÁÁ

A8

ÁÁÁÁ

119

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

159

ÁÁÁÁÁ

PACK

ÁÁÁÁÁ

138

ÁÁÁÁÁÁ

RXDA

ÁÁÁÁ

56

ÁÁÁÁÁÁ

A9

ÁÁÁÁ

118

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

171

ÁÁÁÁÁ

PAUTOFD

ÁÁÁÁÁ

134

ÁÁÁÁÁÁ

RXDB 3

ÁÁÁÁ

54

ÁÁÁÁÁÁ

A10

ÁÁÁÁ

117

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

183

ÁÁÁÁÁ

PBUSY

ÁÁÁÁÁ

139

ÁÁÁÁÁÁ

STAT0

ÁÁÁÁ

168

ÁÁÁÁÁÁ

A11

ÁÁÁÁ

116

ÁÁÁÁÁÁ

GND

ÁÁÁÁÁ

196

ÁÁÁÁÁ

PIACS0

ÁÁÁÁÁ

89

ÁÁÁÁÁÁ

STAT1

ÁÁÁÁ

167

ÁÁÁÁÁÁ

A12

ÁÁÁÁ

115

ÁÁÁÁÁÁ

GREQ

ÁÁÁÁÁ

173

ÁÁÁÁÁ

PIACS1

ÁÁÁÁÁ

88

ÁÁÁÁÁÁ

STAT2

ÁÁÁÁ

166

ÁÁÁÁÁÁ

A13

ÁÁÁÁ

114

ÁÁÁÁÁÁ

ID0

ÁÁÁÁÁ

42

ÁÁÁÁÁ

PIACS2

ÁÁÁÁÁ

85

ÁÁÁÁÁÁ

TCK

ÁÁÁÁ

190

ÁÁÁÁÁÁ

A14

ÁÁÁÁ

113

ÁÁÁÁÁÁ

ID1

ÁÁÁÁÁ

41

ÁÁÁÁÁ

PIACS3

ÁÁÁÁÁ

84

ÁÁÁÁÁÁ

TDI

ÁÁÁÁ

191

ÁÁÁÁÁÁ

A15

ÁÁÁÁ

112

ÁÁÁÁÁÁ

ID2

ÁÁÁÁÁ

40

ÁÁÁÁÁ

PIACS4

ÁÁÁÁÁ

83

ÁÁÁÁÁÁ

TDMA

ÁÁÁÁ

176

ÁÁÁÁÁÁ

A16

ÁÁÁÁ

109

ÁÁÁÁÁÁ

ID3

ÁÁÁÁÁ

39

ÁÁÁÁÁ

PIACS5

ÁÁÁÁÁ

82

ÁÁÁÁÁÁ

TDO

ÁÁÁÁ

165

ÁÁÁÁÁÁ

A17

ÁÁÁÁ

108

ÁÁÁÁÁÁ

ID4

ÁÁÁÁÁ

38

ÁÁÁÁÁ

PIAOE

ÁÁÁÁÁ

91

ÁÁÁÁÁÁ

TMS

ÁÁÁÁ

188

ÁÁÁÁÁÁ

A18

ÁÁÁÁ

107

ÁÁÁÁÁÁ

ID5

ÁÁÁÁÁ

37

ÁÁÁÁÁ

PIAWE

ÁÁÁÁÁ

90

ÁÁÁÁÁÁ

TR/OE

ÁÁÁÁ

79

ÁÁÁÁÁÁ

A19

ÁÁÁÁ

106

ÁÁÁÁÁÁ

ID6

ÁÁÁÁÁ

36

ÁÁÁÁÁ

PIO0

ÁÁÁÁÁ

164

ÁÁÁÁÁÁ

TRAP0

ÁÁÁÁ

177

ÁÁÁÁÁÁ

A20

ÁÁÁÁ

105

ÁÁÁÁÁÁ

ID7

ÁÁÁÁÁ

35

ÁÁÁÁÁ

PIO1

ÁÁÁÁÁ

163

ÁÁÁÁÁÁ

TRAP1

ÁÁÁÁ

178

ÁÁÁÁÁÁ

A21

ÁÁÁÁ

104

ÁÁÁÁÁÁ

ID8

ÁÁÁÁÁ

32

ÁÁÁÁÁ

PIO2

ÁÁÁÁÁ

162

ÁÁÁÁÁÁ

TRIST

ÁÁÁÁ

195

ÁÁÁÁÁÁ

A22

ÁÁÁÁ

103

ÁÁÁÁÁÁ

ID9

ÁÁÁÁÁ

31

ÁÁÁÁÁ

PIO3

ÁÁÁÁÁ

161

ÁÁÁÁÁÁ

TRST

ÁÁÁÁ

189

ÁÁÁÁÁÁ

A23

ÁÁÁÁ

102

ÁÁÁÁÁÁ

ID10

ÁÁÁÁÁ

30

ÁÁÁÁÁ

PIO4

ÁÁÁÁÁ

158

ÁÁÁÁÁÁ

TXDA

ÁÁÁÁ

59

ÁÁÁÁÁÁ

BOOTW

ÁÁÁÁ

132

ÁÁÁÁÁÁ

ID11

ÁÁÁÁÁ

29

ÁÁÁÁÁ

PIO5

ÁÁÁÁÁ

157

ÁÁÁÁÁÁ

TXDB 3

ÁÁÁÁ

53

ÁÁÁÁÁÁ

BURST

ÁÁÁÁ

66

ÁÁÁÁÁÁ

ID12

ÁÁÁÁÁ

28

ÁÁÁÁÁ

PIO6

ÁÁÁÁÁ

156

ÁÁÁÁÁÁ

UCLK

ÁÁÁÁ

57

ÁÁÁÁÁÁ

CAS0

ÁÁÁÁ

78

ÁÁÁÁÁÁ

ID13

ÁÁÁÁÁ

27

ÁÁÁÁÁ

PIO7

ÁÁÁÁÁ

155

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

1

ÁÁÁÁÁÁ

CAS1

ÁÁÁÁ

77

ÁÁÁÁÁÁ

ID14

ÁÁÁÁÁ

26

ÁÁÁÁÁ

PIO8

ÁÁÁÁÁ

154

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

14

ÁÁÁÁÁÁ

CAS2

ÁÁÁÁ

74

ÁÁÁÁÁÁ

ID15

ÁÁÁÁÁ

25

ÁÁÁÁÁ

PIO9

ÁÁÁÁÁ

153

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

24

ÁÁÁÁÁÁ

CAS3

ÁÁÁÁ

73

ÁÁÁÁÁÁ

ID16

ÁÁÁÁÁ

22

ÁÁÁÁÁ

PIO10

ÁÁÁÁÁ

152

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

34

ÁÁÁÁÁÁ

CNTL0

ÁÁÁÁ

194

ÁÁÁÁÁÁ

ID17

ÁÁÁÁÁ

21

ÁÁÁÁÁ

PIO11

ÁÁÁÁÁ

151

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

44

ÁÁÁÁÁÁ

CNTL1

ÁÁÁÁ

193

ÁÁÁÁÁÁ

ID18

ÁÁÁÁÁ

20

ÁÁÁÁÁ

PIO12

ÁÁÁÁÁ

150

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

50

ÁÁÁÁÁÁ

DACKA

ÁÁÁÁ

94

ÁÁÁÁÁÁ

ID19

ÁÁÁÁÁ

19

ÁÁÁÁÁ

PIO13

ÁÁÁÁÁ

144

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

64

ÁÁÁÁÁÁ

DACKB

ÁÁÁÁ

93

ÁÁÁÁÁÁ

ID20

ÁÁÁÁÁ

18

ÁÁÁÁÁ

PIO14

ÁÁÁÁÁ

143

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

75

ÁÁÁÁÁÁ

DACKC 3

ÁÁÁÁ

96

ÁÁÁÁÁÁ

ID21

ÁÁÁÁÁ

17

ÁÁÁÁÁ

PIO15

ÁÁÁÁÁ

142

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

86

ÁÁÁÁÁÁ

DACKD 3

ÁÁÁÁ

95

ÁÁÁÁÁÁ

ID22

ÁÁÁÁÁ

16

ÁÁÁÁÁ

POE

ÁÁÁÁÁ

137

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

99

ÁÁÁÁÁÁ

DREQA

ÁÁÁÁ

175

ÁÁÁÁÁÁ

ID23

ÁÁÁÁÁ

15

ÁÁÁÁÁ

PSTROBE

ÁÁÁÁÁ

135

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

111

ÁÁÁÁÁÁ

DREQB

ÁÁÁÁ

174

ÁÁÁÁÁÁ

ID24

ÁÁÁÁÁ

12

ÁÁÁÁÁ

PSYNC 2

ÁÁÁÁÁ

170

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

121

ÁÁÁÁÁÁ

DREQC 3

ÁÁÁÁ

146

ÁÁÁÁÁÁ

ID25

ÁÁÁÁÁ

11

ÁÁÁÁÁ

PWE

ÁÁÁÁÁ

136

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

131

ÁÁÁÁÁÁ

DREQD 3

ÁÁÁÁ

145

ÁÁÁÁÁÁ

ID26

ÁÁÁÁÁ

10

ÁÁÁÁÁ

R/W

ÁÁÁÁÁ

92

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

141

ÁÁÁÁÁÁ

DSRA

ÁÁÁÁ

58

ÁÁÁÁÁÁ

ID27

ÁÁÁÁÁ

9

ÁÁÁÁÁ

RAS0

ÁÁÁÁÁ

72

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

148

ÁÁÁÁÁÁ

DTRA

ÁÁÁÁ

55

ÁÁÁÁÁÁ

ID28

ÁÁÁÁÁ

8

ÁÁÁÁÁ

RAS1

ÁÁÁÁÁ

71

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

160

ÁÁÁÁÁÁ

GACK

ÁÁÁÁ

81

ÁÁÁÁÁÁ

ID29

ÁÁÁÁÁ

7

ÁÁÁÁÁ

RAS2

ÁÁÁÁÁ

70

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

172

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

13

ÁÁÁÁÁÁ

ID30

ÁÁÁÁÁ

6

ÁÁÁÁÁ

RAS3

ÁÁÁÁÁ

69

ÁÁÁÁÁÁ

VCC

ÁÁÁÁ

184

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

23

ÁÁÁÁÁÁ

ID31

ÁÁÁÁÁ

5

ÁÁÁÁÁ

Reserved

ÁÁÁÁÁ

51

ÁÁÁÁÁÁ

VCLK 2

ÁÁÁÁ

186

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

33

ÁÁÁÁÁÁ

IDP0 1, 3

ÁÁÁÁÁ

48

ÁÁÁÁÁ

Reserved

ÁÁÁÁÁ

52

ÁÁÁÁÁÁ

VDAT 2

ÁÁÁÁ

169

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

43

ÁÁÁÁÁÁ

IDP1 1, 3

ÁÁÁÁÁ

47

ÁÁÁÁÁ

Reserved

ÁÁÁÁÁ

97

ÁÁÁÁÁÁ

WAIT

ÁÁÁÁ

133

ÁÁÁÁÁÁ

GND

ÁÁÁÁ

49

ÁÁÁÁÁÁ

IDP2 1, 3

ÁÁÁÁÁ

46

ÁÁÁÁÁ

Reserved

ÁÁÁÁÁ

100

ÁÁÁÁÁÁ

WARN

ÁÁÁÁ

185

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

GND

ÁÁÁÁ

Á

ÁÁ

Á

65

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

IDP3 1, 3

ÁÁÁÁÁ

Á

ÁÁÁ

Á

45

ÁÁÁÁÁ

Reserved

ÁÁÁÁÁ

Á

ÁÁÁ

Á

101

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

WE

ÁÁÁÁ

Á

ÁÁ

Á

80

Notes: All values are typical and preliminary.

1. Defined as a no-connect on the Am29240 microcontroller . 2. Defined as a no-connect on the Am29243 microcontroller .

3. Defined as a no-connect on the Am29245 microcontroller .

AMDA D V A N C E I N F O R M A T I O N

19

Am29240 Microcontroller Series

Am29240 MICROCONTROLLER LOGIC SYMBOL

4

2ROMCS3–ROMCS0

STAT2–STAT0

A23–A0

ID31–ID0PSYNC

INTR3–INTR0

RESET

INCLK

TRAP1–TRAP0

3

24

TDO

R/W

32

4

ROMOE

BURST

RSWE

RAS3–RAS0 4

CAS3–CAS0 4

WE

TR/OE

PIACS5–PIACS0 6

PIAOE

PIAWE

TRST

TDI

TCK

TMS

WAIT

WARN

BOOTW

DREQD–DREQA DACKD–DACKA

GACK

GREQ

PIO15–PIO0

PSTROBE

PAUTOFD PBUSY

PACK

POE

PWE

UCLK

RXDB–RXDA TXDB–TXDA

DSRA

DTRA

VCLK

LSYNC

VDAT

16

MEMCLK

2

MEMDRV

TRIST

CNTL1–CNTL0

2

TDMA

4

Am29240 Microcontroller

AMD A D V A N C E I N F O R M A T I O N

20 Am29240 Microcontroller Series

Am29245 MICROCONTROLLER LOGIC SYMBOL

4

2ROMCS3–ROMCS0

STAT2–STAT0

A23–A0

ID31–ID0PSYNC

INTR3–INTR0

RESET

INCLK

TRAP1–TRAP0

3

24

TDO

R/W

32

4

ROMOE

BURST

RSWE

RAS3–RAS0 4

CAS3–CAS0 4

WE

TR/OE

PIACS5–PIACS0 6

PIAOE

PIAWE

TRST

TDI

TCK

TMS

WAIT

WARN

BOOTW

DREQB–DREQA DACKB–DACKA

GACK

GREQ

PIO15–PIO0

PSTROBE

PAUTOFD PBUSY

PACK

POE

PWE

UCLK

RXDA TXDA

DSRA

DTRA

VCLK

LSYNC

VDAT

16

MEMCLK

MEMDRV

TRIST

CNTL1–CNTL0

2

TDMA

2

Am29245 Microcontroller

AMDA D V A N C E I N F O R M A T I O N

21

Am29240 Microcontroller Series

Am29243 MICROCONTROLLER LOGIC SYMBOL

4

2ROMCS3–ROMCS0

STAT2–STAT0

A23–A0

ID31–ID0

INTR3–INTR0

RESET

INCLK

TRAP1–TRAP0

3

24

TDO

R/W

32

4

ROMOE

BURST

RSWE

RAS3–RAS0 4

CAS3–CAS0 4

WE

TR/OE

PIACS5–PIACS0 6

PIAOE

PIAWE

TRST

TDI

TCK

TMS

WAIT

WARN

BOOTW

DREQD–DREQA DACKD–DACKA

GACK

GREQ

PIO15–PIO0

PSTROBE

PAUTOFD PBUSY

PACK

POE

PWE

UCLK

RXDB–RXDA TXDB–TXDA

DSRA

DTRA

16

MEMCLK

2

MEMDRV

TRIST

CNTL1–CNTL0

2

TDMA IDP3–IDP0

4

Am29243 Microcontroller

AMD A D V A N C E I N F O R M A T I O N

22 Am29240 Microcontroller Series

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +125°C. . . . . . . . . . . .

Voltage on any Pin

with Respect to GND –0.5 V to VCC +0.5 V. . . . . . .

Stresses above those listed under Absolute Maximum Ratings

may cause permanent device failure. Functionality at or above

these limits is not implied. Exposure to absolute maximum rat-

ings for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Case Temperature (TC)0°C to +85°C. . . . . . . . . . . . . .

Supply Voltage (VCC) +4.75 V to +5.25 V. . . . . . . . . . .

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

DC CHARACTERISTICS over COMMERCIAL Operating Ranges

Advance Information

Symbol Parameter Description Test Conditions Min Max Unit

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2.0 VCC +0.5 V

VILINCLK INCLK Input Low Voltage Note 1 –0.5 0.8 V

VIHINCLK INCLK Input High Voltage Note 1 VCC –0.8 VCC +0.5 V

VOL Output Low Voltage for

All Outputs except MEMCLK IOL = 3.2 mA 0.45 V

VOH Output High Voltage for

All Outputs except MEMCLK IOH = –400 µA 2.4 V

ILI Input Leakage Current 0.45 V ≤VIN ≤ VCC –0.45 V

Note 2 ±10 or

+10/–200 µA

ILO Output Leakage Current 0.45 V ≤VOUT ≤ VCC –0.45 V ±10 µA

ICCOP Operating Power-Supply Current with

respect to MEMCLK VCC = 5.25 V, Outputs Floating;

Holding RESET active at 25 MHz 14 mA/MHz

VOLC MEMCLK Output Low Voltage IOLC = 20 mA 0.6 V

VOHC MEMCLK Output High Voltage IOHC = –20 mA VCC –0.6 V

IOSGND MEMCLK GND Short Circuit Current VCC = 5.0 V 100 mA

IOSVCC MEMCLK VCC Short Circuit Current VCC = 5.0 V 100 mA

Notes:

1. INCLK is driven with CMOS input levels.

2. The Low input leakage current for the inputs

CNTL1–CNTL0, INTR3–INTR0

,

TRAP1–TRAP0, DREQD–DREQA, TCK, TDI,

TRST, TMS, GREQ, WARN, MEMDRV, WAIT,

and

TRIST

is –200

µ

A. These pins have internal pull-up resistors.

CAPACITANCE

Advance Information

Symbol Parameter Description Test Conditions Min Max Unit

CIN Input Capacitance 15 pF

CINCLK INCLK Input Capacitance 15 pF

CMEMCLK MEMCLK Capacitance fC = 10 MHz 20 pF

COUT Output Capacitance 20 pF

CI/O I/O Pin Capacitance 20 pF

Note: Limits guaranteed by characterization.

AMDA D V A N C E I N F O R M A T I O N

23

Am29240 Microcontroller Series

SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges

Advance Information

16 MHz 20 MHz 25 MHz

No. Parameter Description Test Conditions 1, 8Min Max Min Max Min Max Unit

1INCLK Period (=0.5T) Notes 9, 10, 11 30 25 20 ns

2INCLK High Time Note 9 12 10 8ns

3INCLK Low Time Note 9 12 10 8ns

4INCLK Rise Time Note 9 1 7 1 7 1 7 ns

5INCLK Fall Time Note 9 1 7 1 7 1 7 ns

6MEMCLK Delay from INCLK MEMCLK Output

Notes 3, 8 1 7 1 7 1 7 ns

8 MEMCLK High Time MEMCLK Output

Notes 3, 8 0.5T–3 0.5T–3 0.5T–3 ns

9 MEMCLK Low Time MEMCLK Output

Notes 3, 8 0.5T–3 0.5T–3 0.5T–3 ns

10 MEMCLK Rise Time Notes 3, 8 1 4 1 4 1 4 ns

11 MEMCLK Fall Time Notes 3, 8 1 4 1 4 1 4 ns

12a Synchronous Output Valid Delay from MEMCLK Rising Edge

PIO15–PIO0, STAT2–STAT0,

and PIACS5–PIACS0 MEMCLK Output

Note 1A 1 13 1 12 1 11 ns

CAS3–CAS0 Rising Edge/

CAS3–CAS0 Falling Edge MEMCLK Output

Notes 1B, 4B 1 17/11 1 15/9 1 13/7 ns

All others MEMCLK Output

Note 1B 1 12 1 11 1 10 ns

12b Synchronous Output Valid from MEMCLK Falling Edge

PIO15–PIO0, STAT2–STAT0,

and PIACS5–PIACS0 MEMCLK Output

Note 1A 1 12 1 11 1 10 ns

CAS3–CAS0 Falling Edge MEMCLK Output

Notes 1B, 4B 111 1 9 1 7 ns

All others MEMCLK Output

Note 1B 111 1 10 1 9 ns

13 Synchronous Output Disable

Delay from MEMCLK Rising

Edge

MEMCLK Output 1 12 1 11 1 10 ns

14 Synchronous Input Setup Time to MEMCLK Rising Edge

ID31–ID0 and IDP3–IDP0 for

DRAM access Parity Enabled

Note 4A 18 16 15 ns

ID31–ID0 for DRAM access Parity Disabled

Note 4A 10 8 7 ns

All others 10 8 7 ns

15 Available CAS Access Time

(TCAS–TSetup)Notes 4A, 4B 24 23 18 ns

16a Synchronous Input Hold Time to

MEMCLK Rising Edge Note 4A 0 0 0 ns

16b Synchronous Input Hold Time to

CAS Rising Edge Note 4B 3 3 3 ns

AMD A D V A N C E I N F O R M A T I O N

24 Am29240 Microcontroller Series

SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges (continued)

Advance Information

25 MHz20 MHz16 MHz

No. UnitMaxMinMaxMinMaxMinTest Conditions 1, 8

Parameter Description

17 Asynchronous Input Pulse Width

LSYNC and PSYNC Note 5 Note 5 Note 5

All others 4T 4T 4T ns

18 UCLK Period Note 2 30 25 20 ns

VCLK Period Note 2 25 20 15 ns

19 UCLK High Time Note 2 10 8 6 ns

VCLK High Time Note 2 8 6 4 ns

20 UCLK Low Time Note 2 10 8 6 ns

VCLK Low Time Note 2 8 6 4 ns

21 UCLK Rise time Note 2 0 3 0 3 0 3 ns

VCLK Rise time Note 2 0 3 0 3 0 3 ns

22 UCLK Fall Time Note 2 0 3 0 3 0 3 ns

VCLK Fall Time Note 2 0 3 0 3 0 3 ns

23 Synchronous Output Valid Delay

from VCLK Rise and Fall Note 6 1 16 1 14 1 14 ns

24 Input Setup Time to VCLK Rise

and Fall Notes 6, 7 10 9 9 ns

25 Input Hold Time to VCLK Rise

and Fall Notes 6, 7 0 0 0 ns

Notes:

1. All outputs driving 80 pF, measured at V

OL

= 1.5 V and V

OH

= 1.5 V. For higher capacitance:

A. Add 1-ns output delay per 15 pF loading up to 150-pF total. The minimum delay from

PIAOE

to

PIACS

x is 0 ns if the

capacitance loading on

PIACS

x is equal to or higher than the capacitance loading on

PIAOE

.

B. Add 1-ns output delay per 25 pF loading up to 300-pF total.

2. VCLK and UCLK can be driven with TTL inputs. UCLK must be tied High if it is unused.

3. MEMCLK can drive an external load of 100 pF.

4. ID31–ID0 and IDP3–IDP0 are sampled on the rising edge of MEMCLK for all non-DRAM accesses, simple DRAM accesses,

and the first access of a DRAM page-mode access. ID31–ID0 and IDP3–IDP0 are sampled on the rising edge of

CAS

x for all

DRAM page-mode accesses, except the first access of a DRAM page-mode access. (See Figures 1–4 on pages 26–27.)

A. Applies to ID31–ID0 and IDP3–IDP0 for simple DRAM accesses and the first access of a DRAM page-mode access.

B. Applies to ID31–ID0 and IDP3–IDP0 for DRAM page-mode accesses, except the first access of a DRAM page-mode access.

When ID31–ID0 and IDP3–IDP0 are sampled on

CAS

x, there is no additional setup time required for ID31–ID0 and

IDP3–IDP0 when the parity is enabled.

5. LSYNC and PSYNC minimum width is two bit-times. A bit-time is one period of the internal video clock, which is determined by

the CLKDIV field in the Video Control Register and VCLK.

6. Active VCLK edge depends on the CLKI bit in the Video Control Register.

7. LSYNC and PSYNC can be treated as synchronous signals by meeting the setup and hold times, though the synchronization

delay still applies.

8. The MEMCLK as an input option (i.e., MEMDRV pin is connected to GND) is not supported.

9. INCLK is driven with CMOS input levels.

10.When the user sets the TBO bit, the INCLK period must not be greater than the operating frequency of the part.

1 1. For the 25 MHz part, INCLK = 20 ns minimum (50 MHz maximum) when turbo mode is disabled. When turbo mode is enabled,

INCLK = 30 ns minimum (33 MHz maximum).

AMDA D V A N C E I N F O R M A T I O N

25

Am29240 Microcontroller Series

SWITCHING WAVEFORMS

16a

14

53

21

25

INCLK

MEMCLK

4

0.5 V

2.5 V

VCC – 0.5 V

10 98

0.8 V

1.5 V

VCC –1.0 V 11

6

SYNCHRONOUS

OUTPUTS

SYNCHRONOUS

INPUTS

ASYNCHRONOUS

INPUTS

UCLK, VCLK

18

21 2019

0.8 V

1.5 V

2.0 V 22

VCLK-RELATIVE

OUTPUTS

VCLK-RELATIVE

INPUTS 1.5 V

Note: Video Timing may be

relative to VCLK falling edge

if CLK = 1.

13

17

23

1.5 V

1.5 V 1.5 V

Note:

During AC testing, all inputs are driven at V

IL

= 0.4 V, V

IH

= 2.4 V.

24

CASx

Note: Applies to ID31–ID0 and

IDP3–IDP0 for DRAM page-mode

accesses, except the first access

of a DRAM page-mode access.

See Note 4 on page 24.

12a

16b

1.5 V

12b

15

AMD A D V A N C E I N F O R M A T I O N

26 Am29240 Microcontroller Series

SWITCHING WAVEFORMS (continued)

Column Address

16a

14

1.5 V 1.5 V

1.5 V

ID31–ID0

IDP3–IDP0

A14–A1

R/W

MEMCLK

WE

TR/OE

RAS3–RAS0

CAS3–CAS0

Note:

The RAS3–RAS0

signals are asserted and deasserted on the falling edge of

MEMCLK

.

Row Address

Figure 1. Simple 3/1 DRAM Read Cycle, Am29240 Microcontroller Series

ID31–ID0

IDP3–IDP0

MEMCLK

R/W

WE

TR/OE

RAS3–RAS0

CAS3–CAS0

Row Address

A14–A1 Column Address

Data

Figure 2. Simple 3/1 DRAM Write Cycle, Am29240 Microcontroller Series

AMDA D V A N C E I N F O R M A T I O N

27

Am29240 Microcontroller Series

SWITCHING WAVEFORMS (continued)

1.5 V

Column Address +2/4 +4/8 +6/12

MEMCLK

A14–A1

R/W

WE

TR/OE

RAS3–RAS0

CAS3–CAS0

Note:

The RAS3–RAS0 signals are

asserted and deasserted on the falling edge of

MEMCLK

.

Row Address

ID31–ID0

IDP3–IDP0

1.5 V

1.5 V 1.5 V

14 16a

1.5 V 1.5 V

15

1.5 V 1.5 V 1.5 V

16b 15 16b 15 16b

Figure 3. 3/1 DRAM Page-Mode Read, Am29240 Microcontroller Series

Data

ID31–ID0

IDP3–IDP0

MEMCLK

WE

TR/OE

R/W

RAS3–RAS0

CAS3–CAS0

Row Address Column Address +2/4 +4/8 +6/12

A14–A1

Data Data Data

Figure 4. 3/1 DRAM Page-Mode Write, Am29240 Microcontroller Series

AMD A D V A N C E I N F O R M A T I O N

28 Am29240 Microcontroller Series

SWITCHING TEST CIRCUIT

V

Am29240 Microcontroller

VL

IOL = 3.2 mA

VREF = 1.5 V

IOH = 400 µA

CL

VH

Pin Under Test

THERMAL CHARACTERISTICS

The Am29240 microcontroller series is specified for op-

eration with case temperature ranges for a commercial

temperature device. Case temperature is measured at

the top center of the PQFP package as shown in Figure 5.

ÉÉÉÉ

θJA θCA

θJC

TC

θJA =θJC +θCA

Figure 5. Thermal Resistance — °C/Watt

The various temperatures and thermal resistances can

be determined using the equations shown in Figure 6

along with information given in Table 2. (The variable

P

is power in watts.)

θJA = θJC + θCA

P=I

CCOP ⋅ freq ⋅ VCC

TJ=T

C+P⋅θ

JC

TJ=T

A+P⋅θ

JA

TC=T

J–P⋅θ

JC

TC=T

A+P⋅θ

CA

TA=T

J–P⋅θ

JA

TA=T

C–P⋅θ

CA

Figure 6. Thermal Characteristics Equations

Table 2. Thermal Characteristics (°C/Watt) Surface Mounted

Parameter °C/Watt

θJA Junction-to-Ambient 38

θJC Junction-to-Case 8

θCA Case-to-Ambient 30

AMDA D V A N C E I N F O R M A T I O N

29

Am29240 Microcontroller Series

PHYSICAL DIMENSIONS

PQB 196, Trimmed and Formed

Plastic Quad Flat Pack (measured in inches)

0.020

0.040

S

1.345

1.355

1.475

1.485

1.495

1.505

0.008

0.012

Pin 1 ID

Pin 1

Pin 49

Pin 98

147

Pin 196

–A–

–D–

–B–

See Detail

X

Seating

Plane

–C–

0.025 Basic

Top View

Side View

1.20 Ref.

0.160

0.180

0.130

0.150

S

1.495

1.505

1.475

1.485

1.345

1.355

Note:

Not to scale. For reference only.

AMD A D V A N C E I N F O R M A T I O N

30 Am29240 Microcontroller Series

PHYSICAL DIMENSIONS (continued)

PQB 196, Trimmed and Formed

Plastic Quad Flat Pack (measured in inches)

0.010

0.008

0.012

7° Typ.

0.010 Min

Flat Shoulder

0.045 x 45° Chamfer

0° Min

0.015

0.008 Pin 147

Gage Plane

0°≤0≤8°

Section S–S

Detail X

7° Typ.

0.065 Ref.

0.006

0.008

0.036

0.046

Note:

Not to scale. For reference only.

AMDA D V A N C E I N F O R M A T I O N

31

Am29240 Microcontroller Series

PHYSICAL DIMENSIONS (continued)

Solder Land Recommendations—196-Lead PQFP

0.075 0.012 0.025

1.500

Note:

Not to scale. For reference only.

Trademarks

AMD, the AMD logo, Am29000, MiniMON29K, and Fusion29K are registered trademarks; 29K, AMD Facts-On-Demand, Am29005, Am29030,

Am29035, Am29040, Am29050, Am29200, Am29202, Am29205, Am29240, Am29243, Am29245, Traceable Cache, Scalable Clocking, and

XRAY29K are trademarks of Advanced Micro Devices, Inc.

High C is a registered trademark of MetaW are, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.