4,194,304 WORD x DESCRIPTION 1 BIT DYNAMIC RAM PRELIMINARY The TCS14100AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 4,194,304 words by 1 bit. The TCS14100AP/AJ/ASJ/AZ utilizes TOSHIBAs CMOS Silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and to the system user. Multiplexed address inputs permit the TC514100AP/AJ/ASJ/AZ to be packaged in a standard 18 pin plastic DIP, 26/20 pin plastic SOJ (300/350mil) and 20 pin plastic ZIP, The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment, System oriented features include single power supply of 5V10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. FEATURES 4,194,304 word by 1bit organization Fast access time and cycle time TCSIA1QN0AP/AMASIIAZ 70/80/10 trac RAS Access Time 70ns 80ns 100ns taa Column Address Access Time 35ns 4Gns Sons tcac CAS Access Time 20ns 20n5 25ns tre Cycle Time 136ns 150ns 180ns tec Fast Page Made Cycle Time 45ns 50ns 60ns Single power supply of 5V110% with a built-in Vpy generator PIN NAMES AO~A10) Address Inputs WRITE | Read/Write Input RAS | Row Address Strobe Veco | Power (+ 5V) Dw Data In Vss_-| Ground Dour | Data Out N.C. [No Connection TAS | Column Address Strobe PIN CONNECTION (TOP VIEW) Plastic DIP Plastic $0) Din Ras A.C. al agli Dour AOL a2tt Vecb ASL Plastic ZIP uy TAS ss | WRITE Ald NLC. * Low Power 550mW MAX. Operating (TC514100AP/Ad/ASJ/AZ 70) 468mW MAX. Operating (TC514100AP/AJ/ASJ/AZ 80) 413mW MAX. Operating (TC514100AP/AJ/ASJ/AZ 10) 5.5mW MAX, Standby Outputs unlatched at cycle end allows two- dimensional! chip selection @ Common V/O capability using EARLY WRITE operation Read-Modify-Write, CAS before RAS refresh, RAS-only refresh, Hidden refresh, Fast Page Mode and Test Mode capability e All inputs and outputs TTL compatible 1024 refresh cycles/16ms @ Package TC514100AP : DIP18-P-300E TC514100AJ : SOQUJ26-P-350 TC514100ASJ : SOJ26-P-300A TC514100AZ _: ZIP20-P-400A BLOCK DIAGRAM TAS O- DATA IN ao Ow BUFFER NO.2 CLOCK GENERATOR DATA OUT Dour BUFFER COLUMN AD Om ADORESS 19 coun Al OF BUFFERS (11) J 4 Al Om SENSE AMP. Al O-| ney VO GATING Ad Ow] + -=-4096 --4 AS Om AG OF] x noe z al MEMORY Ao On O| 1024 ARRAY Ag Om ROW =U) iy ADDRESS Sy BLL Ald Om BUFFERS {11} 4 IE v 6 NO.1 CLOCK SUBSTRATE BIAS [-O Vcc Ras GENERATOR GENERATOR OD V55 A-93TC514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 ABSOLUTE MAXIMUM RATINGS ITEM SYMBOL RATING UNITS NOTES input Voltage Vin -1~7 Vv 1 Output Voltage Vout -1~7 Vv 1 Power Supply Voltage Vec ~1~7 Vv 1 Operating Temperature Fopr 0~70 1 Storage Temperature Ts1 -55~150 "Cc 1 Soldering Temperature - Time Tsovoer 260-10 "C+ sec 4 Power Dissipation Po 700 mw 1 Short Circuit Output Current lout 50 mA 1 RECOMMENDED DC OPERATING CONDITIONS (Ta =0~70C) SYMBOL PARAMETER MIN. TYP. MAX, UNIT NOTES Vec Supply Voltage 4.5 5.0 5.5 2 Vie Input High Voltage 2.4 - 6.5 2 Vat input Low Voltage - 1.0 - 0.8 2 A-94TC514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 DC ELECTRICAL CHARACTERISTICS (Vcc =5V 410%, Ta =0~70c) SYMBOL PARAMETER MIN. MAX. | UNITS | NOTES OPERATING CURRENT TCS14100AP/AMASAZ-70 - 100 3.4 leer Average Power Supply Operating Current TCS 14 1OOAP/AIAS HAZ-B0 - 85 mA (RAS, CAS, Address Cycling: tac=tre MIN. ) TCSTA1ODAP/AMASIAZ-10 - 75 5 STANDBY CURRENT lec2 Power Supply Standby Current - 2 mA (RAS = CAS = Vin) RAS ONLY REFRESH CURRENT TCS 14 ODA PAIASAZ-70 - 100 leea Average Power Supply Current, RAS Only Mode TC514 100 APIAJ/AS/AZ-80 - 85 mA 3.5 (RAS Cycling, CAS = Vin: tac = tre MIN. ) TCS 14 1OOAP/AIASI/AZ-10 - 75 FAST PAGE MODE CURRENT TCS 1Q100AP/AVASHAZ-70 - 60 3,4 icca Average Power Supply Current, Fast Page Mode =| 1518100AP/As/ASI/AZ-80 - 50 mA (RAS = Vp, CAS, Address Cycling: tpc=tpc MIN.) | testa1ogaPvasasiaz-10] 9 4s 5 STANDBY CURRENT lees Power Supply Standby Current - 1 mA (RAS = CAS = Vcc = 0.2V) TAS BEFORE RAS REFRESH CURRENT TCS14100APIAMASWAZ-70 = 100 leee Average Power Supply Current, CAS Before RAS | TcS14100AP/A/ASI/AZ-80. - 85 mA 3,5 Mode (RAS, TAS Cycling: tac= tac MIN. ) TCSI4100AP/AVASHAZ-10 | = 75 INPUT LEAKAGE CURRENT lho Input Leakage Current, any input - 10 10 pA (OVS VinS6.5V, All Other Pins Not Under Test = OV} OUTPUT LEAKAGE CURRENT lo ty oa: - 10 10 BA (Doyt is disabled, OVS Voy7S 5.5V) OUTPUT LEVEL Vou use 2.4 - Vv Output H* Level Voltage (loyr = - 5mA) OUTPUT LEVEL Vor a - 0.4 v Output L" Level Voltage (lout = 4.2mA) A-95TC514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Vcc =5V + 10%, Ta=0~70c}(Notes 6, 7, 8) TCS14100AP/ TCS14100AP/ TC514100AP/ SYMBOL PARAMETER AMVASHAZ-70 AJIASUAZ-80 AUASHAZ-10 UNIT | NOTES MIN. MAX. MIN, MAX. MIN. MAX. tre Random Read or Write Cycle Time 130 - 150 ~ 180 - ns tamw Read-Modify-Write Cycle Time 155 - 175 - 210 - ns tec Fast Page Mode Cycie Time 4s - 50 - 60 - ns term Care age Mode Read-Modify-Write 0 _ 5 . 90 _ ns trac Access Time from RAS ~ 70} - so, - 1001 ns . teac Access Time from CAS - 20} - 20] - 25| ms | 9, 14 taa Access Time from Column Address - 35 - 40 - 50] ns 9, 15 tepa Access Time from CAS Precharge - 40 - 4s - 55] ns 9 terz CAS to Output in Low-z 0 - 0 - Q - ns 9 torr Output Buffer Turn-off Delay 0 20 0 20 0 20] ns 10 tr Transition Time (Rise and Fall) 3 50 3 50 3 50} ns 8 tre RAS Precharge Time 50 - 60 - 70 ~ ans tras RAS Pulse Width 70 10,006 80 40,000 100 10,000 | ns trasp RAS Pulse Width (Fast Page Mode) 70] 200,000 80] 200,000 100} 200,000] ns tes RAS Hold Time 20 - 20 - 25 - ns tence ras Mee Me CAS Precharge 40 . 45 . 65 _ ns tes TAS Hold Time 70 - 80 - 100 - ns teas TAS Pulse Width 20 10,600 20 10,000 25 10,000] ns taco RAS to TAS Delay Time 20 50 20 60 25 75| ns 14 trao RAS to Column Address Delay Time 15 35 15 40 20 50} ns 15 terp TAS to RAS Precharge Time 5 - 5 - 10 ~ ns tep CAS Precharge Time 10 - 10 - 10 - ns tase Row Address Set-Up Time 0 - 0 - 0 ns tray Row Address Hold Time 10 - 19 - 15 - ns tase Column Address Set-Up Time 0 - 0 - 0 - ns toan Column Address Hold Time 15 - 15 - 20 - ns tra Column Address to RAS Lead Time 35 - 40 - 50 - ns tacs Read Command Set-Up Time 0 - 0 - 0 - ns tracy Read Command Hold Time 0 - 0 - 0 - ns YW tenn reeeeommend Hold Time referenced 6 . Q _ 0 . ns Nl twen Write Command Hold Time 15 - 15 - 20 - ns A-96TC514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 ELECTRICAL CHARACTGERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) TCS141G0AP/ TCS14100AP/ | TC514100AP/ SYMBOL PARAMETER AMASVAZ-70 AJIASIAZ-B0 AMASJIAZ-10 UNITS] NOTES MIN. MAX. MIN, MAX. MIN. MAX. twe Write Command Pulse Width 15 - 15 - 20 - ns tRWL Write Command to RAS Lead Time 20 - 20 - 25 - ns tewL Write Command to CAS Lead Time 20 - 20 - 25 - ns tos Data Set-Up Time 0 - 0 - 0 - ns i2 tou Data Hold Time 15 - 15 - 20 - ns 12 tree Refresh Period - 16 - 16 - 16] ms twes Write Command Set-UP Time 0 - 0 - 0 - ns 13 tewo CAS to WRITE Delay Time 20 - 20 - . 25 - ns 13 tawo RAS to WRITE Delay Time 70 - 80 - 100 ~ ns 13 tawob Column Address to WRITE Delay Time 35 - 40 - 50 - ns 13 tepwo CAS Precharge to WRITE Delay Time 40 - 45 - 55 - ns 13 tesa CAS Set-Up Time 5 . 5 . 5 _ ns (CAS before RAS Cycle) tour CBS Hold Time 15 . 1s . 7 _ ns (CAS before RAS Cycle) trec RAS to CAS Precharge Time 0 - 0 - 0 - ns Precharge Time err os before RES Counter Test Cycle) 40 ~ 40 ~ 58 ns twrs Write Command Set-Up Time 10 _ 10 . 10 . ns (Test Mode In) twrn Write Command Hold Time 10. _ 10 _ 10 . ns (Test Mode in) twrp WRITE to RAS Precharge Time 10 . 10 _ 10 . ns (CAS before RAS Cycle) twan WRITE to RAS Hold Time 10 . 10 _ 10 . ns (CAS before RAS Cycle} A-97TC514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 ELECTRICAL CHARACTGERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN THE TEST MODE (Vcc =5V + 10%, Ta = 0~70C) (Notes 6, 7, 8) TCS14100AP/ TCSI4100AP/ TCS14100AP/ SYMBOL PARAMETER AVASI/AZ-70 AJ/ASI/AZ-80 AASI/AZ-10 UNIT] NOTES MIN, MAX, MIN. MAX. MIN. MAX. tre Random Read Write Cycle Time 135 - 155 - 185 - ns tamw Read-Modify-Write Cycle Time 160 ~ 480 - 215 - tec Fast Page Mode Cycle Time 50 - 55 - 65 - ns teauw Fast Page Mode Read-Modify-Write 35 . 80 _ 95 _- ng 13 Cycle Time trac Access Time from RAS - 75) = 85) - 105] ns me teac Access Time from TAS - 25}; = 25] = 30] ns | 9, 14 tea Access Time from Column Address - 40 - 45 - 55 | ns 9, 15 lepa, Access Time from CAS Precharge - 4a5{ = sof - 60] ns 9 tras RAS Pulse Width 75 10,000 85 10,000 105 10,000] ns trasp RAS Pulse Width {Fast Page Mode) 75] 200,000 85| 200,000; 105] 200,000T ns tasy RAS Hold Time 25 - 25 - 30 ~ ns tes TAS Hold Time 75 - 85 - 105 - ns truce CAS Prechrge to RAS Hold Time 45 - 50 - 60 - ns teas CAS Pulse Width 25 10,000 25 10,000 30 10,000 | ns tra Column Address to RAS Lead Time 40 ~ 45 - 55 - ns tewo CAS to WRITE Delay Time 25 - 25 - 30 - ns 13 trRwo RAS to WRITE Delay Time 7S > 85 - 105 - ns 13 tawp Column Address to WRITE Delay Time 40 - 45 - 55 - ns 3 tcpwo CAS Precharge to WRITE Delay Time 45 - 50 - 60 - fons 13 CAPACITANCE (Vcc = 5V + 10%, f = IMHz, Ta = 0~70C) SYMBOL PARAMETER MIN. MAX. UNIT Cn Input Capacitance (AQ0~A10, Oyn) - 5 C2 Input Capacitance (RAS, CAS, WRITE) - 7 pF Co Output Capacitance (Dour) - ? A-98TC514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 NOTES: 1, Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. All voltages are referenced to Vss. Tec1, Icc3. Icca, Icce depend on cycle rate. Icc1, Icc4 depend on output loading. Specified values are obtained with the output open. Column address can be changed once or less While RAS=Vj, and CAS=Vin- aon Ff PN An initial pause of 200ps is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved, In case of using internal refresh counter, a minimum of 8 GAS before RAS refresh cycles instead of 8 RAS only refresh cycles are required. 7. AC measurements assume ty=5ns. 8. Vitt (min.) and Vi, (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between Vip and VIL. 9, Measured with a load equivalent to 2 TTL loads and 100pF. 10. torr (max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 11. Either troy or trp must be satisfied for a read cycle. 12. These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in Read-Modify-Write cycles. 13. twes, trwp, tcwp, tawp and topwp are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twcs=twos(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) throughout the entire cycle; If trwp= trwp (min.), tewp=tcwop (min.), tawp= tawp (min.) and tcpwp= tcpwp (min.) (Fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell: If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 14, Operation within the trcp (max.) limit insures that trac (max.) can be met. trcp (max.) is specified as a reference point only: If trcp is greater than the specified trcp (max.) limit, then access time is controlled by tcac. 15. Operation within the trap (max.) limit insures that trac (max.) can be met. trap (max.) is specified as a reference point only: If trap is greater than the specified trap (max.) limit, then access time is controlled by tna. A-991C514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 TIMING WAVEFORMS READ CYCLE COLUMN DATA - OUT FA: H or L A-100TC514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 WRITE CYCLE (EARLY WRITE) Vi TAS Vi Ving AO~AI0 COLUMN Vu Vid WAI Vin Vin Din DATA -IN Vin Vor Dour OPEN Vor AA: "H or L A-1011C514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 READ-MODIFY-WRITE CYCLE AQ~A10 COLUMN Vi Din DATA- IN Dour DATA - OUT Voi YA: H" of L" A-102TC514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 FAST PAGE MODE READ CYCLE trase Vin RAS Vi tere Viq CAS Vit Dour Vo. FA: "H" or L A-1031C514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 FAST PAGE MODE WRITE CYCLE (EARLY WRITE) tre trasp Vin RAS Vu Vu CAS Vil . Vin A0~A10 Vi Vou Dour OPEN Vo. ZA: H or L" A-104TC514100AP/AJ/ASJ/AZ70, TC5141 00AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 FAST PAGE MODE READ-MODIFY-WRITE CYCLE trp tRASP Vin vi A0~A10 Vv VoH= Dour Voi FA: KH or L* A-105TC514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 RAS ONLY REFRESH CYCLE tac ~ t > Vm RAS + , wy N f \ | ha , tere tree Vino $F Vi tasa tRAY nvas . LO \YI MMIII: BZ: H" or L" A-106TC514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ--80 TC514100AP/AJ/ASJ/AZ10 CAS BEFORE RAS REFRESH CYCLE - a . t , <_< Va A RAS RAS \ \ Vi +, je tRPC top | tes tour CAS WRITE iy : AH or L* A-107TC514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 HIDDEN REFRESH CYCLE (READ) COLUMN DATA - OUT KAA: H" or L" A-108TC514100AP/AJd/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 HIDDEN REFRESH CYCLE (WRITE) Vq Vi Vin mer CAS Vin AD~AI0 COLUMN Vip Din 4 DATA- IN Dour OPEN ZB: H" or L* A-109105141 00AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 CAS BEFORE RAS REFRESH COUNTER TEST CYCLE Vin A0~A10 COLUMN Vit READ CYCLE Vou Dout DATA.- OUT WRITE CYCLE Yr Vou Pout vo, Vin WRITE Vir Vin Din DATA -IN Viv READ-MODIFY-WRITE CYCLE Vou Dour DATA- OUT Voi 7 WRITE t Din ; DATA - IN FA: H" or L A-110TC514100AP/AJd/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 WRITE, CAS BEFORE RAS REFRESH CYCLE 6 tap t . <____ Vi RAS _ A RAS \ Vi. * tape tes os = PA WTI twrs a Gy > H" or L" A-114TC514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 TEST MODE The TC514100AP/AJ/ASJ/AZ is the RAM organized 4,194,304 words by 1 bits, it is internally organized 524,288 words by 8 bits. In Test Mode, data are written into 8 sectors in parallel and retrieved the same way. Aion, A1oc and Aoc are not used. If, upon reading, all bits equal (all1"s or O"s), the data output pin indicates a1". If any of the bits differed, the data output pin would indicate a0", Fig.l shows the block diagram of TC514100AP/Ad/ASJ/AZ. In Test Mode, the 4M DRAM can be tested as if it were a512K DRAM. WRITE, CAS Before RAS Refresh Cycle puts the device into Test Mode. And CAS Before RAS Refresh Cycle or RAS Only Refresh Cycle puts it back into Normal Mode, In the Test Mode, WRITE, TAS Before RAS Refresh Cycle performs the refresh operation with the internal refresh address counter. The Test Mode function reduces test times (1/8 in case of N test pattern). A-112TC514100AP/AJ/ASJ/AZ70, TC514100AP/AJ/ASJ/AZ80 TC514100AP/AJ/ASJ/AZ10 BLOCK DIAGRAM IN THE TEST MODE Vv S Aor: Aroc, Aoc Normai Aion: Arne: Age 512K block Ajo Arges Ae ron 73% | 619% block Bion Pines A eo OE _! 512K block Aion Aree Ane Test 512K block Cin Normal Aron Aioc: Moe 512K block Aion Mtoe Age sons Aioc: Age 512K block Test so Aton. Asoc: Age 512K block Aron Argo Age 512K block Aron, Atoce Aoc Fig. 1 A-113