Document # SRAM128 REV B Revised March 2009
P4C1049/P4C1049L
HIGH SPEED 512K x 8
STATIC CMOS RAM
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS
High Speed (Equal Access and Cycle Times)
— 15/20/25 ns (Commercial)
— 20/25/35 ns (Industrial)
— 20/25/35/45/55/70 ns (Military)
Low Power
Single 5V±10% Power Supply
Easy Memory Expansion Using CE and OE Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin Ceramic DIP (600 mil)
—36-Pin SOJ (400 mil)
—36-Pin FLATPACK
—36-Pin LCC (452 mil x 920 mil)
FEATURES
The P4C1049 is a 4 Megabit high-speed CMOS static RAM
organized as 512Kx8. The CMOS memory requires no
clocks or refreshing, and has equal access and cycle times.
Inputs are fully TTL-compatible. The RAM operates from
a single 5V±10% tolerance power supply.
Access times as fast as 15 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The P4C1049
is a member of a family of PACE RAM™ products offering
fast access times.
The P4C1049 device provides asynchronous operation
with matching access and cycle times. Memory locations
are specied on address pins A0 to A18. Reading is accom-
plished by device selection (CE) and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE or OE is HIGH or WE is LOW.
DESCRIPTION
SOLDER-SEAL FLAT-
PACK (FS-4),
SOJ (J9, CJ2)
LCC (L11)
DIP PIN-OUT INSIDE DATASHEET
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
Page 2Document # SRAM128 REV B
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
Sym Parameter Value Unit
VCC
Power Supply Pin with
Respect to GND -0.5 to +7 V
VTERM
Terminal Voltage with
Respect to GND (up to
7.0V)
-0.5 to VCC + 0.5 V
TAOperating Temperature -55 to +125 °C
TBIAS Temperature Under Bias -55 to +125 °C
TSTG Storage Temperature -65 to +150 °C
PTPower Dissipation 1.0 W
IOUT DC Output Current 50 mA
MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDITIONS
Grade(2) Ambient Temp GND VCC
Commercial 0°C to 70°C 0V 5.0V ± 10%
Industrial -40°C to +85°C 0V 5.0V ± 10%
Military -55°C to +125°C 0V 5.0V ± 10%
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Sym Parameter Conditions Typ Unit
CIN Input Capacitance VIN=0V 8 pF
COUT Output Capacitance VOUT=0V 8 pF
Sym Parameter Test Conditions
P4C1049 P4C1049L
Unit
Min Max Min Max
VIH Input High Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V
VIL Input Low Voltage -0.3(3) 0.8 -0.3(3) 0.8 V
VHC CMOS Input High Voltage VCC - 0.2 VCC + 0.3 VCC - 0.2 VCC + 0.3 V
VLC CMOS Input Low Voltage -0.3(3) 0.2 -0.3(3) 0.2 V
VOL
Output Low Voltage (TTL
Load) IOL = +8 mA, VCC = Min 0.4 0.4 V
VOH
Output High Voltage (TTL
Load) IOH = -4 mA, VCC = Min 2.4 2.4 V
ILI Input Leakage Current VCC = Max,
VIN = GND to VCC
MIL -10 +10 -5 +5
µA
IND/COM -5 +5 N/A N/A
ILO Output Leakage Current VCC = Max, CE = VIH,
VOUT = GND to VCC
MIL -10 +10 -5 +5
µA
IND/COM -5 +5 N/A N/A
ISB
Standby Power Supply
Current (TTL Input Levels)
CE ≥ VIH, VCC = Max, f = Max,
Outputs Open
MIL — 45 — 40
mA
IND/COM — 40 — N/A
ISB1
Standby Power Supply
Current (CMOS Input
Levels)
CE ≥ VHC, VCC = Max, f = 0,
Outputs Open
VIN ≤ VLC or VIN ≥ VHC
MIL — 15 — 10
mA
IND/COM — 10 — N/A
N/A = Not applicable
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
Page 3Document # SRAM128 REV B
DATA RETENTION CHARACTERISTICS (P4C1049L Military Temperature Only)
DATA RETENTION WAVEFORM
Sym Parameter Test Conditions Min
Typ* VCC= Max VCC=
Unit
2.0V 2.0V
VDR VCC for Data Retention 3.0 V
ICCDR Data Retention Current CE ≥ VCC -0.2V,
VIN ≥ VCC -0.2V
or VIN ≤ 0.2V
2 3 mA
tCDR Chip Deselect to Data Retention Time 0 ns
tR
†Operation Recovery Time tRC
§ns
* TA = +25°C
§ tRC = Read Cycle Time
† This Parameter is guaranteed but not tested
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Sym Parameter Temperature Range -15 -20 -25 -35 -45 -55 -70 Unit
ICC Dynamic Operating Current*
Commercial 220 185 180 N/A N/A N/A N/A mA
Industrial N/A 190 185 175 N/A N/A N/A mA
Military N/A 200 195 185 175 170 165 mA
* VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
Page 4Document # SRAM128 REV B
Sym Parameter
-15 -20 -25 -35 -45 -55 -70
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tRC Read Cycle Time 15 20 25 35 45 55 70 ns
tAA Address Access Time 15 20 25 35 45 55 70 ns
tAC
Chip Enable Access
Time 15 20 25 35 45 55 70 ns
tOH
Output Hold from Ad-
dress Change 3 3 3 3 3 3 3 ns
tLZ
Chip Enable to Output in
Low Z 3 3 3 3 3 3 3 ns
tHZ
Chip Disable to Output in
High Z 8 9 11 15 20 25 30 ns
tOE
Output Enable Low to
Data Valid 7 9 10 15 20 25 30 ns
tOLZ
Output Enable Low to
Low Z 0 0 0 0 0 0 0 ns
tOHZ
Output Enable High to
High Z 7 9 10 15 20 25 30 ns
tPU
Chip Enable to Power Up
Time 0 0 0 0 0 0 0 ns
tPD
Chip Disable to Power
Down Time 15 20 25 35 45 55 70 ns
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
Page 5Document # SRAM128 REV B
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED) (5, 7)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specication
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air ow.
3. Transient inputs with VIL and IIL not more negative than –2.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE
transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specied in Figure 1. This parameter is sampled
and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the rst
transitioning address.
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym Parameter
-15 -20 -25 -35 -45 -55 -70
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tWC Write Cycle Time 15 20 25 35 45 55 70 ns
tCW
Chip Enable Time to End of
Write 12 14 18 22 30 35 40 ns
tAW Address Valid to End of Write 12 14 16 20 25 35 40 ns
tAS Address Setup Time 0 0 0 0 0 0 0 ns
tWP Write Pulse Width 12 14 16 22 25 30 35 ns
tAH Address Hold Time 0 0 0 0 0 0 0 ns
tDW Data Valid to End of Write 9 11 13 15 20 25 30 ns
tDH Data Hold Time 0 0 0 0 0 0 0 ns
tWZ
Write Enable to Output in
High Z 8 10 11 15 18 25 30 ns
tOW
Output Active from End of
Write 3 3 3 5 5 5 5 ns
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
Page 6Document # SRAM128 REV B
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11)
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
13. Write Cycle Time is measured from the last valid address to the rst
transitioning address.
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10)
AC TEST CONDITIONS TRUTH TABLE
Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 3ns
Input Timing Reference Level 1.5V
Output Timing Reference Level 1.5V
Output Load See Figures 1 and 2
Mode CE OE WE I/O Power
Standby H X X High Z Standby
DOUT Disabled L H H High Z Active
Read L L H DOUT Active
Write L X L High Z Active
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
Page 7Document # SRAM128 REV B
Figure 1. Output Load Figure 2. Thevenin Equivalent
* including scope and test xture.
Note:
Because of the ultra-high speed of the P4C1049/L, care must be taken
when testing this device; an inadequate setup can cause a normal function-
ing part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor ngers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
DOUT to match 166Ω (Thevenin Resistance).
ORDERING INFORMATION
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
Page 8Document # SRAM128 REV B
32-Pin DIP (C10)
32-PIN CERAMIC DIP PIN CONFIGURATION
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
Page 9Document # SRAM128 REV B
SOLDER SEAL FLATPACK
SIDEBRAZED DUAL IN-LINE PACKAGE
Pkg # C10
# Pins 32 (600 mil)
Symbol Min Max
A - 0.225
b 0.014 0.026
b2 0.045 0.065
C 0.008 0.018
D - 1.680
E 0.510 0.620
eA 0.600 BSC
e 0.100 BSC
L 0.125 0.200
Q 0.015 0.070
S1 0.005 -
S2 0.005 -
Pkg # FS-4
# Pins 36
Symbol Min Max
A 0.089 0.125
b 0.015 0.019
c 0.003 0.007
D 0.910 0.930
E 0.505 0.515
E1 - 0.530
E2 0.385 0.395
E3 0.055 0.065
e 0.050 BSC
L 0.300 0.350
Q 0.015 0.038
S - 0.045
M - 0.002
N 36
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
Page 10Document # SRAM128 REV B
SOJ SMALL OUTLINE IC PACKAGE
CERAMIC SOJ SMALL OUTLINE IC PACKAGE
Pkg # J9
# Pins 36
Symbol Min Max
A 0.130 0.145
A1 0.082 -
b 0.015 0.020
C 0.007 0.013
D 0.920 0.930
e 0.050 BSC
E 0.435 0.445
E1 0.395 0.405
E2 0.370 BSC
Q 0.045 0.055
Pkg # CJ2
# Pins 36
Symbol Min Max
A 0.120 0.165
B1 0.030R TYP
B2 0.020 REF
B3 0.025 0.045
D 0.816 0.838
E 0.419 0.431
E2 0.360 0.380
e 0.050 BSC
E1 0.430 0.454
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
Page 11Document # SRAM128 REV B
RECTANGULAR LEADLESS CHIP CARRIER
Pkg # L11
# Pins 36
Symbol Min Max
A 0.080 0.100
A1 0.054 0.066
B 0.022 0.028
D 0.910 0.930
D1 0.840 0.860
E 0.445 0.460
e .050 BSC
L .100 TYP
L2 0.115 0.135
P - 0.006
R .009 TYP
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
Page 12Document # SRAM128 REV B
REVISIONS
DOCUMENT NUMBER SRAM 128
DOCUMENT TITLE P4C1049/P4C1049L - HIGH SPEED 512K X 8 STATIC CMOS RAM
REV ISSUE DATE ORIGINATOR DESCRIPTION OF CHANGE
OR Oct-2005 JDB New Data Sheet
A Jan-2008 JDB Added CJ2 Ceramic SOJ Package
B Mar-2009 JDB Added C10 Ceramic DIP Package