August 1999 1/70
Rev. 2.8
ST62T00C/T01C
ST62T03C/E01C
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
OSCILLATOR SAFEGUARD, SAFE RESET AND 16 PINS
■3.0 to 6.0V Supply Operating Range
■8 MHz Maximum Clock Frequency
■-40 to +125°C Operating Temperature Range
■Run, Wait and Stop Modes
■5 Interrupt Vectors
■Look-up Table capability in Program Memory
■Data Storage in Program Memory:
User selectable size
■Data RAM: 64bytes
■User Programmable Options
■9 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input (except ST62T03C)
■3I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
■8-bit Timer/Counter with 7-bit programmable
prescaler
■Digital Watchdog
■Oscillator Safe Guard
■Low Voltage Detector for Safe Reset
■8-bit A/D Converter with up to 4 analog inputs
■On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
■Power-on Reset
■One external Non-Maskable Interrupt
■ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
DEVICE OTP
(Bytes) EPROM
(Bytes) I/O Pins Analog
inputs
ST62T00C 1036 - 9 4
ST62T01C 1836 - 9 4
ST62T03C 1036 - 9 None
ST62E01C - 1836 9 4
(See end of Datasheet for Ordering Information)
PDIP16
PSO16
CDIP16W
SSOP16
1
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Table of Contents
70
Document
Page
2
ST62T00C/T01C/ST62T03C/E01C . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4.3 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 14
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.3 Oscillator Safe Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.4 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.5 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.6 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.4 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.3 I/O Port Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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4.1.4 I/O Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.5 I/O Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2.1 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.3 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ST62P00C/P01C/P03C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.2.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ST6200C/01C/03C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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ST62T00C/T01C ST62T03C/E01C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T00C,T01C,T03C and ST62E01C de-
vices are low cost members of the ST62xx 8-bit
HCMOS family of microcontrollers, which is target-
ed at low to medium complexity applications. All
ST62xx devices are based on a building block ap-
proach: a common core is surrounded by a
number of on-chip peripherals.
The ST62E01C is the erasable EPROM version of
the ST62T00C,T01C,T03C and device, which
may be used to emulate the ST62T00C,T01C and
T03C device, as well as the respective
ST6200C,01C and 03C ROM devices.
OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
tionality s elec tin g as RO M op tion s the o pti ons d e-
fined in the programmable option bytes of the
OTP/EPROM versions.
OTP devices off er all th e advantag es of user p ro-
grammability at low cost, which make them the
ideal c hoi ce in a wide r ang e of ap pli c ations wher e
frequen t code change s, multiple code version s or
last minute programmability are required.
These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit program-
mable p rescal er,an 8- bit A/ D Conve rter wit h up to
4 analog inputs and a Digital Watchdog timer,
making them well suited for a wid e range of auto-
motive , appli anc e and ind us trial appli cati ons .
Figure 1. Block Diagram
TEST
NMI INTERRUPT
PROGRAM
1836 Bytes
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
POWER
SUPPLY OSCILLATOR RESET
DATA ROM
USER
SELECTABLE
DATA RAM
64 Bytes
PORT A
PORT B
TIMER
DIGITAL
8 BIT CORE
TEST/VPP
(ST62T01C, E01C)
8-BIT
A/D CONVERTER PA1..PA3 (20mA Sink)
VDDVSS OSCin OSCout RESET
WATCHDOG
:
MEMORY
PB0..PB1
1036 Bytes
(ST62T00C,T03C)
(*) Analog input availability depend on versions
PB3,PB5..PB7 / Ain (*)
4
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ST62T00C/T01C ST62T0 3C/E 01C
1.2 PIN DESCRIPTIONS
VDD and VSS. Power is supplied to the MCU via
these two pins. VDD is the power connection and
VSS is the ground connection.
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be c onnected between t hese two pins.
The OSCin pin is the inp ut pin, the O SCout pi n is
the output pin.
RESET. The active-low RESET pin is used to re-
start the mi crocon troller . Internal pull-up i s provi d-
ed at this pin.
TEST/VPP. The TEST mu st be held at VSS for nor-
mal operation. If TEST pin is connected to a
+12.5V le vel during the reset phase, the EPROM
programming Mode is entered.
NMI. The NMI pin provides the capability for asyn-
chronous interruption, by applying an external non
maskable interrupt to the MCU. The NMI input is
falling ed ge sensitive. The user can select as op-
tion the availability of an on-chip pull-up at this pin.
PA1-PA3. These 3 lines are organized as one I/O
port (A). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or push-pull outputs. PA1-
PA3 can also sink 20mA for direct LED driving.
PB0..PB1,PB3,PB5-PB7. These 6 lines are or-
ganized as one I/O port (B). Each line may be con-
figured under software control as inputs with or
without internal pull-up resistors, interrupt generat-
ing inputs with pull-up resistors, open-drain or
push-pull outputs. PB3,PB5..-PB7 can be used as
analog inputs for the A/D converter on the
ST62T00C, T01C and E01C.
Figure 2. ST62T03C,T00C, T01C, and E01C Pin
Configuration
1
2
3
4
5
6
7
8
11
12
13
14
15
16
VDD
OSCin
OSCout
NMI
VPP/TEST
RESET
Ain*/PB7
Ain*/PB6
VSS
PA1/20 mA Sink
PA2/20 mA Sink
PA3/20 mA Sink
PB0
PB1
PB3/Ain*
PB5/Ain*
*Analog input availability depend on device
10
9
5
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ST62T00C/T01C ST62T03C/E01C
1.3 MEMORY MAP
1.3.1 Introduction
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.
Briefly, Program space contains user program
code in OTP and user vectors; Data space con-
tains user data in RAM and in OTP, and Stack
space accommodates six levels of stack for sub-
routine and interrupt service routine nesting.
Figure 3. Memory Addressing Diagram
PROGRAM SPACE
PROGRAM
INTERRUPT &
RESET VECTORS ACCUMULATOR
DATA RAM
BANK SELECT
WINDOW SELECT
RAM
X REGIST ER
Y REGIST ER
V REGIST ER
W REGIST ER
DATA RE AD -O NL Y
WINDOW
RAM / EEPRO M
BANKING AREA
000h
03Fh
040h
07Fh
080h
081h
082h
083h
084h
0C0h
0FFh
0-63
DATA SPACE
0000h
0FF0h
0FFFh
MEMORY MEMORY
DATA READ-ONLY
MEMORY
6
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ST62T00C/T01C ST62T0 3C/E 01C
MEMORY MAP (Cont’d)
1.3.2 Program Space
Program Space comprises the instructions to be
executed, the data required for immediate ad-
dressing mode instructions, the reserved factory
test area and t he user vectors . Program Spac e is
addressed via the 12-bit Program Counter register
(PC register)Program Memory Protection.
The Progr am Me mory in OTP o r EPRO M dev ices
can be protected against external readout of mem-
ory by sel ecting t he READOUT PROT ECTION op-
tion in the option byte.
In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.
Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the OTP contents. Returned
parts with a protection set can therefore not be ac-
cepted.
Figure 4. Program Memory Map
(*) Reserved areas should be filled with 0FFh
0000h
0AFFh
0B00h
0B9Fh
NOT IMPLEMENTED
RESERVED*
USER
PROGRAM MEMORY
(OTP)
1024 BYTES
0BA0h
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED*
RESERVED
INTERRUPT VECTORS
NMI VECT OR
USER RE SE T VE CT OR
0000h
07FFh
0800h
087Fh
NOT IMPLEMENTED
RESERVED*
USER
PROGRAM MEMORY
(OTP/EPROM)
1824 BYTES
0880h
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED*
RESERVED
INTERR UP T VE CT O RS
NMI VECTOR
USER RESET VECTOR
ST62T03C,T00C ST62T01C, E01C
7
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ST62T00C/T01C ST62T03C/E01C
MEMORY MAP (Cont’d)
1.3.3 Data Space
Data Space accommodates all the data necessary
for processing the user program. This space com-
prises th e RAM r esource, the proces sor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in OTP/
EPROM.
1.3.3.1 Data ROM
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently con-
tains the pr ogram code to be exec ute d, as well as
the constants and look-up tables required by the
application.
The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window throu gh which it is possibl e to access the
read-only data stored in OTP/EPROM.
1.3.3.2 Data RAM
In ST6200C/01C/03C devices, the data space in-
cludes 6 0 bytes of RAM, the acc umulator (A), the
indirect reg isters (X), (Y), the short direct registers
(V), (W), the I/O port registers, the peripheral data
and control registers, the interrupt option register
and the Data ROM Window register (DRW regis-
ter).
1.3.4 Stack Space
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
Tab le 1. ST6 200C /01C/ 03C Dat a Memo ry Sp ace
RESERVED 000h
03Fh
DATA ROM WINDOW AREA
64 BYTES
040h
07Fh
X REGISTER 080h
Y REGISTER 081h
V REGISTER 082h
W REGISTER 083h
DATA RAM 60 BYTES 084h
0BFh
PORT A DATA REGISTE R 0C0h
PORT B DATA REGISTE R 0C1h
RESERVED 0C2h
RESERVED 0C3h
PORT A DIRECTION REGISTER 0C4h
PORT B DIRECTION REGISTER 0C5h
RESERVED 0C6h
RESERVED 0C7h
INTER R UPT OPT I ON REGISTE R 0C8 h*
DATA ROM WINDOW REGISTER 0C9h*
RESERVED 0CAh
0CBh
PORT A OPTION REGISTER 0CCh
PORT B OPTION REGISTER 0CDh
RESERVED 0CEh
RESERVED 0CFh
A/D DATA REGISTER (except ST62T03C) 0D0h
A/D CONTROL REGISTER (except ST62T03C) 0D1h
TIMER PRESCALER REGISTER 0D2h
TIMER COUNTER REGISTER 0D3h
TIMER STATUS CONTROL REGISTER 0D4h
RESERVED 0D5h
0D6h
0D7h
WATCHDOG REGISTER 0D8h
RESERVED 0D9h
0FEh
ACCUMULATOR 0FFh
* WRITE ONLY REGISTER
8
9/70
ST62T00C/T01C ST62T0 3C/E 01C
MEMORY MAP (Cont’d)
1.3.5 Data Window Register (DWR)
The Data read-only memory window is located from
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes locat-
ed anywhere in program memory, between ad-
dress 0000h and 0FFFh (top memory address de-
pends on the specific device). All the program
memory can therefore be used to store either in-
structions or read-only data. Indeed, the window
can be m oved in steps of 64 bytes alon g the pro-
gram memory by writing the appropriate code in the
Data Window Register (DWR).
The DWR can be addressed like any RAM location
in the Data Space, it is however a write-only regis-
ter and therefore cannot be accessed using single-
bit operati ons. Thi s r eg ister is use d to po si tio n the
64-byte rea d- onl y d ata wind ow ( fr om a ddres s 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte to b e read as data in progr am mem ory is
obtained by concatenating the 6 least significant
bits of the re gis te r ad dres s gi v en in the i ns tru ct ion
(as least significant bits) and the content of the
DWR register (as most significant bits), as illustrat-
ed in Figure 5 below. For instance, when address-
ing location 0040h of the Data Space, with 0 load-
ed in the DWR register, the physical location ad-
dressed in program memory is 00h. The DWR reg-
ister is not cleared on reset, therefore it must be
written to prior to the first access to the Data read-
only memory window area.
Data Window Register (DWR)
Address: 0C9h — Write Only
Bits 6, 7 = Not used.
Bit 5-0 = DWR5-DWR0:
Data read-only memory
Window Register Bits.
These are the Data read-
only memory Window bits that correspond to the
upper bits of the data read-only memory space.
Caution:
This regist er is undefined on res et. Nei-
ther read nor single bit instructions may be used to
address this register.
Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR co ntents should not be changed while exe-
cuting an interrupt service routine, as the service
routine cannot save and then restore the register’s
previous contents. If it is impossi ble to avoid wr it-
ing to the DWR during the interrupt service routine,
an image of the re gister must be save d in a RAM
location, and each time the program writes to the
DWR, it must also write to the image register. The
image register must be written first so that, if an in-
terrupt occurs between the two instructions, the
DWR is not affected.
Figure 5. Data read-only memory Window Memory Addressing
70
- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
DATA ROM
WINDOW REGIS T ER
CONTENTS DATA SPACE ADDR ESS
40h-7Fh
IN INSTRUCTIO N
PROGR AM SPACE ADDRESS
765432 0
543210
543210
READ
1
67891011
01
VR01573C
12
1
0DATA SPACE ADDRESS
:
:
59h
000
01001
11
Example:
(DWR)
DWR=28h
1100000001
ROM
ADDRESS:A19h 11
13
01
9
10/70
ST62T00C/T01C ST62T03C/E01C
1.4 PROGRAMMING MODES
1.4.1 Option Bytes
The two Option Bytes allow configuration capabili-
ty to the MCUs. Option byte’s content is automati-
cally read, and the selected options enabled, when
the chip reset is activated.
It can only be accessed during the programming
mode. This access is made either automatically
(copy from a master device) or by selecting the
OPTION BYTE PROGRAMMING mode of the pro-
grammer.
The option bytes are located in a non-user map.
No address has to be specified.
EPROM Code Option Byte (LSB)
EPROM Code Option Byte (MSB)
D15-D11. Reserved. Must be cleared
D10. Reserved. Must be set to 1.
EXTCNTL.
Externa l STOP MODE control.
. When
EXTCNTL is high, STOP mode is available with
watchdog a cti ve b y set tin g NMI pin to one.. W hen
EXTCNTL is low, STOP mode is not available with
the watchdog active.
LVD.
LVD RESET enable.
When this bit is set, safe
RESET is performed by MCU when the supply
voltage is too low. When this bit is cleared, only
power-on reset or external RESET are active.
PROTECT.
Readout Protection.
This bit allows the
protec tio n of t he s oftwa re co nte nts aga ins t pi rac y.
When the bit PROTECT is set high, readout of the
OTP contents is prevented by hardware.. When
this bit is low, the user program can be read.
OSCIL.
Oscillator selection
. When this bit is low,
the osci llator must be con trolled by a qua rtz crys-
tal, a ce ra mic resonato r or an external freque ncy.
When it is high, the oscillator must be controlled by
an RC network, with only the resistor having to be
externally provided.
D5. Reserved. Must be cleared to zero.
D4. Reserved. Must be set to one.
NMI PULL.
NMI Pull-Up
. This bit must be set high
to configure the NMI pin with a pull-up resistor.
When it is low, no pull-up is provided.
D2. Reserved. Must be set to 1.
WDACT. This bit controls the watchdog activation.
When it is high, hardware activation is selected.
The softwar e activation is se lected w hen WDACT
is low.
OSGEN.
Oscillator Safe Guard
. This bit must be
set high to enable the Oscillator Safe Guard.
When this bit is low, the OSG is disabled.
The Opt ion b yte i s written duri ng pr ogramming ei -
ther by using the PC menu (PC driven Mode) or
automatically (stand-alone mode)
70
PRO-
TECT OSCIL - - NMI
PULL - WDACT OS-
GEN
15 8
------
EXTC-
NTL LVD
10
11/70
ST62T00C/T01C ST62T0 3C/E 01C
PROGRAMMING MODES (Cont’d)
1.4.2 Program Memory
EPROM/OTP programming mode is set by a
+12.5V v oltage appli ed to the TES T/VPP pin. The
programming flow of the ST62T00C,T01C,T03C
and E01C is described in the User Man ual of the
EPROM Programming Board.
Table 2. ST62T00C, T03C Program Memory Map
Table 3. ST62T01C,E01C Program Memory Map
Note: OTP/EPROM devices can be programmed
with the development tools available from STMi-
croelectronics (ST62E2X-EPB or ST622X-KIT).
1.4.3 EPROM Erasing
The EPROM of the windowed package of the
MCUs may be erased by exposure to Ultra Violet
light. The erasure characteristic of the MCUs is
such that erasure begin s when the memory is ex-
posed to light with a wave lengths shorter than ap-
proximately 4000Å. It should be noted that sun-
lights and some types of fluorescent lamps have
wavelengths in the range 3000-4000Å.
It is thus recommended that the window of the
MCUs packages be covered by an opaque label to
prev ent un inte ntion al er asure p robl ems wh en tes t-
ing the application in such an environment.
The recommended erasure procedure of the
MCUs EPROM is the exposure to short wave ul-
traviolet light which have a wave-length 2537A.
The integrated dose (i.e. U.V. intensity x exposure
time) for erasure should be a minimum of 30W-
sec/cm2. The erasure time wi th this dos age is ap-
proximately 30 to 40 minutes using an ultraviolet
lamp with 12000µW/cm2 power rating. The
ST62E01C should be plac ed withi n 2.5cm (1In ch)
of the lamp tubes during erasure.
Device Address Description
0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Device Address Description
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
11
12/70
ST62T00C/T01C ST62T03C/E01C
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communic ating with on-chi p I/O , Memo ry and Pe-
ripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 6; the controller being externally
linked to both the Reset and Oscillator circuits,
while the core is linked to the dedicated on-chip pe-
riphera ls via the serial dat a bus and indire ctly, for
interrupt purposes, through the control registers.
2.2 CPU REGISTERS
The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumu lator can be addr essed in Data
space as a RAM location at address FFh. Thus the
ST6 can man ipulate the accu mulator just lik e a ny
other register in Data space.
Indirect Registers (X, Y). These two indirect reg-
ister s are us ed as p ointers to mem or y l oc ati ons in
Data spa ce. They are us ed in the re gister- indire ct
addressing mode. These registers can be ad-
dressed in the data space as RAM locations at ad-
dresses 80h (X) and 81h (Y). They can also be ac-
cessed with the direct, short direct, or bit direct ad-
dressing modes. Accordingly, the ST6 instruction
set can use the indirect registers as any other reg-
ister of the data space.
Short Direct Registers (V, W). These two regis-
ters are used to save a byte in short direct ad-
dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W ). They c an al so be access ed us ing the di -
rect and bit direct addressing modes. Thus, the
ST6 instr uction set can us e the short direct regi s-
ter s as any other register of the data space.
Program Counter (PC). The program co unter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper-
and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
Figure 6. ST6 Core Block Diagram
PROGRAM
RESET
OPCODE FLAG
VALUES 2
CONTROLLER
FLAGS ALU
A-DATA B-DATA
ADDRESS/READ LINE
DATA SPACE
INTERRUPTS
DATA
RAM/EEPROM
DATA
ROM/EPROM
RESULT S TO DATA SPACE (WRITE LINE)
ROM/EPROM
DEDICATIONS
ACCUMULATOR
CONTROL
SIGNALS
OSCin OSCout
ADDRESS
DECODER 256
12 Program Counter
and
6 LAYER ST AC K
0,01 TO 8MHz
VR01811
12
13/70
ST62T00C/T01C ST62T0 3C/E 01C
CPU REGISTERS (Cont’d)
However, if the program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
Bank Switch register.
The PC value is incremented after reading the ad-
dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU , where they are adde d; the resul t is then
shifted back into the PC. The program counter can
be changed in the following ways:
- JP (Jump) instructionPC=Jump address
- CALL instructionPC= Call address
- Relative Branch Instruction.PC= PC +/- offset
- Interrupt PC=Interrupt vector
- Reset PC= Reset vector
- RET & RETI instructionsPC= Pop (stack)
- Normal instructionPC= PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation, another pair is used dur-
ing Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt mode (CNMI, ZN-
MI).
The ST6 CPU uses the pair of flags associated
with the c urrent m ode: as soon as an i nterrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Inte rrupt flags (resp. the N MI flags)
instead of the Normal flags. When the RETI in-
struction is executed, the previously used set of
flags is restor ed. It s hould be not ed that each f lag
set can only be addressed in its own context (Non
Maskable Inte rru pt, Normal Interrupt or Main rou-
tine). The flags are not cleared during context
switching and thus retain their status.
The Carry flag is set wh en a ca rry or a b orro w oc -
curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the va lue of
the bit tested in a bit test instruction; it also partici-
pates in the rotate left instruction.
The Zero flag is set if the result of the last arithme-
tic or logical operation was equal to zero; other-
wise it is cleared.
Switching between the three sets of flags is per-
formed automatically when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is
automati cally selec ted after the reset of the MCU,
the ST6 core uses at first the NMI flags.
Stack. The ST6 CPU includes a true LIFO hard-
ware stack which eliminates the need for a stack
pointer. The stack consists of six separate 12-bit
RAM locations that do not belong to the data
space RAM area. When a subroutine call (or inter-
rupt request) occurs, the contents of each level are
shifted into the next higher level, while the content
of th e PC is shifted into the first lev el (the or iginal
contents of the sixth stack level are lost). When a
subr outi ne or in terr upt retu rn oc cu rs (RE T or RETI
inst ructions), the first leve l register is sh ifted back
into the P C and the val ue of each lev el is popped
back into the previous level. Since the accumula-
tor, in common with all other data space registers,
is not stored in this stack, management of these
registers should be performed within the subrou-
tine. The stack will remain in its “deepest” position
if more than 6 nested calls or interrupts are execut-
ed, and consequently the last return address will
be lost. It will also remain in its highest position if
the stack is empty and a RET or RETI is executed.
In this case the next instruction will be executed.
Figure 7. ST6 CPU Programming Mode
l
SHORT
DIRECT
ADDRESSING
MODE
V REGISTER
WREGISTER
PROGRAM COUNTER
SIX LEVELS
STACK REGISTER
CZNORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
INDEX
REGISTER
VA000423
b7
b7
b7
b7
b7
b0
b0
b0
b0
b0
b0b11
ACCUMULATOR
YREG.POINTER
XREG.POINTER
CZ
CZ
13
14/70
ST62T00C/T01C ST62T03C/E01C
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTE M
The MCU featu res a Ma in Osci ll ato r wh ich c an be
driven by an external clock, or used in conjunction
with an AT- cut par al le l res on ant crys tal or a s uit a-
ble ce ramic reso nator, or with a n exte rnal resist or
(RNET). In addition, a Low Frequency Auxiliary Os-
cillator (LFAO) can be switched in for security rea-
sons, to reduce power consumption, or to offer the
benefits of a back-up clock system.
The Oscillator Safeguard (OSG) option filters
spikes from the oscillator lines, provides access to
the LFAO to provide a backup oscillator in the
event o f main osci llator failur e and also a utomati-
cally lim its the internal clock freq uency (fINT) as a
function of VDD, in order to guarantee correct oper-
ation. These functions are illustrated in Figure 9,
Figure 10, Figure 11 and Figure 12.
Figure 8 illustrates various possible oscillator con-
figurations using an external crystal or ceramic res-
onator, an external clock input, an external resistor
(RNET), or the lowest cost solution using only the
LFAO. CL1 an CL2 should have a capacitance in the
range 12 to 22 pF for an oscillator frequency in the
4-8 MHz range.
The internal MCU c lo ck fr eque nc y (fINT) is di vi ded
by 12 to drive the Timer, the A/D converter and the
Watchdog timer, and by 13 to drive the CPU core,
as may be seen in Figure 11.
With an 8MHz oscillator frequency, the fastest ma-
chine cycle is therefore 1.625µs.
A machine cycle is the smallest unit of time needed
to execute any operation (for instance, to increment
the Prog ram Counte r). An in structi on may req uire
two, four, or five machine cycles for execution.
3.1.1 Main Oscillator
The oscillator configuration may be specified by se-
lecting the appropriate option. When the CRYSTAL/
RESONATOR option is selected, it must be used with
a quartz crystal, a ceramic resonator or an external
signal provided on the OSCin pin. When the RC NET-
WORK option is selected, the system clock is gen-
erated by an external resistor.
The main oscillator can be turned off (when the
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register. The
Low Frequency Auxiliary Oscillator is automatical-
ly started.
Figure 8. Oscillator Configurations
INTEGRATED C LO C K
CRYSTAL/RESONATOR option
OSG ENABLED opt ion
OSCin OSCout
CL1n CL2
ST6xxx
CRYSTAL/RESONATOR CLOCK
CRYSTAL/RESONATOR option
OSCin OSCout
ST6xxx
EXTERNAL CLOCK
CRYSTAL/RESONATOR option
NC
OSCin OSCout
ST6xxx
NC
OSCin OSCout
RNET
ST6xxx
RC NETWORK
RC NETWORK option
NC
14
15/70
ST62T00C/T01C ST62T0 3C/E 01C
CLOCK SYSTEM (Cont’d)
Turning on the main oscillator is achieved by re-
setting the OSCOFF bit of the A/D Converter Con-
trol Register or by resetting the MCU. Restarting
the main os cillator impl ies a delay c omprising the
oscillator start up delay period plus the duration of
the software instruction at fLFAO clock frequency.
3.1.2 Low Frequency Auxiliary Oscillator
(LFAO)
The Low Fr equency Auxi liary Osci llator has thr ee
main purposes. Firstly, it can be used to reduce
power co nsumptio n in non t iming c ritical r outines.
Secondly , it offers a fully integr ated syste m clock,
without any external components. Lastly, it acts as
a safety oscillator in case of main oscillator failure.
This oscillator is available when the OSG ENA-
BLED option is selected. In this case, it automati-
cally starts one of its periods after the first missing
edge from the main oscillator, whatever the reason
(main oscillator defective, no clock circuitry provid-
ed, main oscillator switched off...).
User code, normal interrupts, WAIT and STOP in-
structions, are processed as normal, at the re-
duced fLFAO frequency. The A/D converter accura-
cy is decreased, since the internal frequency is be-
low 1MHz.
At power on, the Low Frequency Auxiliary Oscilla-
tor starts faster than the Main Oscillator. It there-
fore feeds the on-chip counter generating the POR
delay until the Main Oscillator runs.
The Low Frequency Auxiliary Oscillator is auto-
matically switched off as soon as the main oscilla-
tor starts.
ADCR
Address: 0D1h — Read/Write
Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0:
ADC Control Register
. These bits are not used.
Bit 2 = OSCOFF. Wh en lo w, t his bit enables m a in
oscillator to run. The main oscillator is switched off
when OSCOFF is high.
3.1.3 Oscillator Safe Guard
The Oscillator Safe Guard (OSG) affords drastical-
ly increas ed operatio nal integrity i n S T 62x x dev ic -
es. The OSG circuit provides three basic func-
tions: it filters spikes from the oscillator lines which
would result in over frequency to the ST62 CPU; it
gives access to the Low Frequency Auxiliary Os-
cillator (LFAO), used to ensure minimum process-
ing in case of main oscillator failure, to offer re-
duced power consumption or to provide a fixed fre-
quency low cost oscillator; finally, it automatically
limits the internal clock frequ ency as a fu nction of
supply voltage, in order to ensure correct opera-
tion even if the power supply should drop.
The OSG is enabled or disabled by choosing the
relevant OSG option. It may be vi ewed as a fi lter
whose cross-over frequency is device dependent.
Spikes on the oscillator lines result in an effectively
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over fre-
quency for a given power supply voltage. The
OSG filters out such spikes (as illustrated in Figure
9). In all cases, when the OSG is active, the maxi-
mum internal clock frequency, fINT, is limited to
fOSG, whic h is supp ly volt age depe ndent. This re-
lationship is illustrated in Figure 12.
When the OSG is enabled, the Low Frequency
Auxili ar y Osci l la tor m ay be acce ss ed. Thi s os ci ll a-
tor starts operating after the first missing edge of
the main oscillator (see Figure 10).
Over-frequency, at a given power supply level, is
seen by the OSG as spik es; it therefor e filters out
some cycles in order that the internal clock fre-
quency of the device is kept within the range the
particular device can stand (depending on VDD),
and below fOSG: the maximum authorised frequen-
cy with OSG enabled.
Note. The OSG should be used wherever possible
as it provide s maximum safety. Care mus t be tak-
en, however, as it can increase power consump-
tion and reduce the maximum operating frequency
to fOSG.
Warning: Care has to be taken when using the
OSG, as the internal frequency is defined between
a minimum and a maximum value and is not accu-
rate.
For precis e timin g measurem ents, it is not recom -
mended to use the OSG and it should not be ena-
bled in applications that use the SPI or the UART.
It should also be noted that power consumption in
Stop mode is higher when the OSG is enabled
(around 50µA at nominal conditions and room
temperature).
70
ADCR
7ADCR
6ADCR
5ADCR
4ADCR
3OSC
OFF ADCR
1ADCR
0
15
16/70
ST62T00C/T01C ST62T03C/E01C
CLOCK SYSTEM (Cont’d)
Figure 9. OSG Filtering Principle
Figure 10. OSG Emergency Oscillator Principle
(1)
VR001932
(3)
(2)
(4)
(1)
(2)
(3)
(4)
Maximum Frequency for the device to work correctly
Actual Quartz Crystal Frequency at OSCin pin
Noise from OSCin
Resulting Internal Frequency
Main
VR001933
Internal
Emergency
Oscillator
Frequency
Oscillator
16
17/70
ST62T00C/T01C ST62T0 3C/E 01C
CLOCK SYSTEM (Cont’d)
Figure 11. Clock Circuit Block Diagram
Figure 12. Maximum Operating Frequency (fMAX) versus Supply Voltage (VDD)
Notes:
1. In this area, operation is guaranteed at the
quartz crystal frequency.
2. When the OSG is disabled, operation in this
area is guaranteed at the crystal frequency. When
the OSG is enabled, operation in this area is guar-
anteed at a frequency of at least fOSG Min.
3. When the OSG is disabled, operation in this
area is guaranteed at the quartz crystal frequency.
When th e OSG is enabled, access to th is area is
prevented. The internal frequency is kept a fOSG.
4. When the OSG is disabled, operation in this
area is not guaranteed
When th e OSG is enabled, access to th is area is
prevented. The internal frequency is kept at fOSG.
MAIN
OSCILLATOR
OSG
LFAO
M
U
X
Core
: 13
: 12
: 1
TIMER 1
Watchdog
POR
fINT
Main Oscillator off
12.5 3.644.555.56
8
7
6
5
4
3
2
Maximum FREQUENCY (MHz)
SUPPLY VOLTAGE (VDD)
FUNCTIONALITY IS NOT
3
43
2
1
fOSG
fOSG Min
GUARANTEED
IN THIS AREA
VR01807
17
18/70
ST62T00C/T01C ST62T03C/E01C
3.2 RESETS
The MCU can be reset in four ways:
– by the external Reset input being pulled low;
– by Power-on Reset;
– by the digital Watchdog peripheral timing out.
– by Low Voltage Detection (LVD)
3.2.1 RESET Input
The RESET pin may be connected to a devic e of
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the MCU internal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on
the RESET pi n are accep table, provi ded VDD has
completed its rising phase and that the oscillator is
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset sta te as long as the
RESET pin is held low.
If RESET activation occurs in the RUN or WAIT
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are con-
figured as inputs with pull-up resistors and the
main Oscillator is restarted. When the level on the
RESET pin then goes high, the initialization se-
quence is executed following expiry of the internal
delay period.
If RESET pin activation occurs in the STOP mode,
the osci llator starts u p and all Inpu ts and Outputs
are configured as inputs with pull-up resistors.
When the l evel of the RESET pin then g oes high,
the initialization sequence is executed following
expiry of the internal delay period.
3.2.2 Power-on Reset
The func tio n o f th e P OR c irc ui t c onsis ts i n w ak ing
up the MCU by detecting around 2V a dynamic
(rising edge) variation of the VDD Supply. At the
beginning of this sequence, the MCU is configured
in the Reset state: all I/O ports are configured as
inputs with pull-up resistors and no instruction is
executed. When the power supply voltage rises to
a sufficient level, the oscillator starts to operate,
whereupon an internal delay is initiated, in order to
allow the o sci llator to fully stab iliz e before exe cut-
ing the first instruction. The initialization sequence
is execu ted immediate ly following the internal de -
lay.
To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a suffi-
cient level for the chosen frequency (see recom-
mended operation) before the reset signal is re-
leased. In addition, supply rising must start from
0V.
As a consequence, the POR does not allow to su-
pervise static, slowly rising, or falling, or noisy
(prese n tin g oscil lat ion ) VDD su ppl ies.
An externa l RC network co nnected to th e RESET
pin, or the LVD reset can be used instead to get
the best performances.
Figure 13. Reset and Interrupt Processing
INT LATCH CLEARED
NMI MASK SET
RESET
( IF PRESEN T )
SELECT
NMI MODE FLAGS
IS RESET STILL
PRESENT?
YES
PUT FFEH
ON ADDRESS BUS
FROM RESET LOCATIONS
FFE/FFF
NO
FETCH INSTRUCTION
LOAD PC
VA000427
18
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ST62T00C/T01C ST62T0 3C/E 01C
RESETS (Cont’d)
3.2.3 Watchdog Reset
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal res et wil l be acti va ted. This, am ong st oth-
er things, resets the watchdog counter.
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.
3.2.4 LVD Reset
The on-chip Low Voltage Detector, selectable as
user option, features static Reset when supply
voltage is below a referen ce value . Thanks to this
feature, external reset circuit can be removed
while keeping the application safety. This SAFE
RESET is effective as well in Power-on ph ase as
in power supply drop with different reference val-
ues, allowing hysteresis effect. Reference value in
case of vol tage drop has been set lower than the
ref er en ce v al u e fo r p ow e r- on i n or de r to avoid any
parasitic Reset when MCU start's running and
sinking current on the supply.
As long as the supply voltage is below the refer-
ence value, there is a internal and static RESET
command. The MCU can start only when the sup-
ply voltage rises over the reference value. There-
fore, only two operating mode exist for the MCU:
RESET active below the voltage reference, and
running mode over the voltage reference as
shown on the Figure 14, that represen ts a power -
up, power-down sequence.
Note: When the RE SE T sta te is c ontr ol led by one
of the internal RESET sources (Low Voltage De-
tector, Watchdog, Power on Reset), the RESET
pin is tied to low logic level.
Figure 14. LVD Reset on Power-on and Power-down (Brown-out)
3.2.5 Application Notes
No external resistor is requi red between VDD and
the Reset pin, thanks to the built-in pull-up device. Direct external connection of the pin RESET to
VDD must be avoided in order to ensure safe be-
haviour of the internal reset sources (AND.Wired
structure).
RESET
RESET
VR02106A
time
VUp
Vdn
VDD
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ST62T00C/T01C ST62T03C/E01C
RESETS (Cont’d)
3.2.6 MCU Initialization Sequence
When a res et occurs th e stack is re set, the PC is
load ed wit h the addr ess of t he Reset Vector (l ocat-
ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the In-
terrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. The in-
itialisation routine should therefore be terminated
by a R ETI instruction, i n order to r evert to normal
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. If, how-
ever, a pending interrupt is present, it will be serv-
iced.
Figure 15. Reset and Interrupt Processing
Figure 16. Reset Block Diagram
RESET
RESET
VECTOR
JP JP:2 BYTES/4 CYC LES
RETI RETI: 1 BYTE/2 CYCLES
INITIALIZATION
ROUTINE
VA00181
VDD
RESET
RPU
RESD1)
POWER
WATCHDOG RESET
CK
COUNTER
RESET
ST6
INTERNAL
RESET
fOSC
RESET
ON RES E T
LVD RESET
VR02107A
AND. Wired
1) Res i stive ESD protection. Value not guar anteed.
20
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ST62T00C/T01C ST62T0 3C/E 01C
RESETS (Cont’d)
Table 4. Register Reset Status
Register Address(es) Status Comment
Oscillator Control Register
Port Data Registers
Port Direction Register
Port Option Register
Interrupt Option Register
TIMER Status/Control
0DCh
0C0h to 0C1h
0C4h to 0C5h
0CCh to 0CDh
0C8h
0D4h
00h
fINT = fOSC; OSG disabled
I/O are Input with pull-up
I/O are Input with pull-up
I/O are Input with pull-up
Interrupt disabled
TIMER dis ab led
X, Y, V, W, Register
Accumulator
Data RAM
Data ROM Win do w Re gis te r
A/D Result Register
080H TO 083H
0FFh
084h to 0BFh
0C9h
0D0h
Undefined As written if programmed
TIMER Counter Register
TIMER Prescaler Register
Watchdo g Co un ter Re gis te r
A/D Control Register
0D3h
0D2h
0D8h
0D1h
FFh
7Fh
FEh
40h
Max count loaded
A/D in Standby (When available)
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ST62T00C/T01C ST62T03C/E01C
3.3 DIGITAL WATCHDO G
The digital Watchdog consists of a reloadable
downcounter timer which can be used to provide
controlled recovery from software upsets.
The Watchdog circuit generates a Reset when the
downcounter reaches zero. User software can
prevent this reset by reloading the counter, and
should therefore be written so that the counter is
regularly reloaded while the user program runs
correctly. In the event of a software mishap (usual-
ly caused by externally generated interference),
the user program will no longer behave in its usual
fashion and the timer register will thus not be re-
loaded periodically. Consequently the timer will
decrement down to 00h and r eset the M CU. In or-
der to maximise the effectiveness of the Watchdog
function, user software must be written with this
co ncept in mind.
Watchdog behaviour is governed by two options,
known as “WATCHDOG ACTIVATION” (i.e.
HARDWARE or SOFTWARE) and “EXTERNAL
STOP MODE CONTROL” (see Table 5).
In the SOFTWARE option, the Watchdog is disa-
bled until bit C of the DWDR register has been set.
When the Watchdog is disabled, low power Stop
mode is available. Once activated, the Watchdog
cannot be disabled, except by resetting the MCU.
In the HARDWARE option, the Watchdog is per-
manently enabled. Since the oscillator will run con-
tinuously, low power mode is not available. The
STOP instruction is interpreted as a WAIT instruc-
tion, and the Watchdog continues to countdown.
However, when the EXTERNAL STOP MODE
CONTROL option has been selected low power
consumption may be achieved in Stop Mode.
Execution of the STOP instruction is then gov-
erned by a secondary function associated with the
NMI pin. If a STOP instruction is encountered
when the NMI pin is low, it is interpreted as WAIT,
as described above. If, however, the STOP in-
struction is encountered when the NMI pin is high,
the Wat chdog counter is frozen and the CPU en -
ters STOP mode.
When the MCU exits STOP mode (i.e. when an in-
terrupt is generated), the Watchdog resumes its
activity.
Table 5. Recommended Option Choices
Functions Required Recommended Options
Stop Mode & Watchdog “EXTE RNAL STO P MODE” & “ HARDWARE WATCHDOG ”
Stop Mode “SOFTWARE WATCHDOG”
Watchdog “HARDWARE WATCHDOG”
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ST62T00C/T01C ST62T0 3C/E 01C
DIGITAL WATCHDOG (Cont’d)
The Watchdog is associated with a Data space
register (Digital WatchDog Register, DWDR, loca-
tion 0D8h) which is described in greater detail in
Section 3 .3.1 Di git al Wat ch dog Regi s ter ( DWDR).
This register is set to 0FEh on Reset: bit C is
cleared to “0”, which disables the Watchdog; the
timer downcounter bits, T0 to T5, and the SR bit
are all set to “1”, thus selecting the longest Watch-
dog timer period. This time period can be set to the
user’s requirements by setting the appropriate val-
ue for bits T0 to T5 in the DWDR register. The SR
bit must be set to “1”, since it is this bit which gen-
erates the Reset signal when it changes to “0”;
clearing thi s bit would gene rate an im mediat e Re-
set.
It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as-
sociated bits in the down counter: bit 7 of the
DWDR regi ster c orres ponds, i n fac t, to T0 and bit
2 to T5. The user should bear in mind the fact that
these bi ts are i nverted an d shifte d with r espect to
the physical counter bits when writing to this regis-
ter. The relationship between the DWDR register
bits and the physical implementation of the Watch-
dog timer downcounter is illustrated in Figure 17.
Onl y the 6 m ost si gnif icant bits ma y be us ed to de -
fine th e tim e per iod, since i t is bit 6 whic h tr iggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator
frequency of 8MHz, this is equivalent to timer peri-
ods ranging from 384µs to 24.576ms).
Figure 17. Watchdog Counter Control
WATCHDOG CONTROL REGISTER
D0
D1
D3
D4
D5
D6
D7
WATCHDOG COUNTER
C
SR
T5
T4
T3
T2
T1
D2
T0
OSC ÷12
RESET
VR02068A
÷28
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ST62T00C/T01C ST62T03C/E01C
DIGITAL WATCHDOG (Cont’d)
3.3.1 Digital Watchdog Register (DWDR)
Address: 0D8h — Read/Write
Reset status: 1111 1110b
Bit 0 = C:
Watchdog Control bit
If the hardware option is selected, this bit is forced
high and the user cannot change it (the Watchdog
is always acti ve). W hen th e software option is se-
lected, th e Watchdog fu nction is acti vated by se t-
ting bit C to 1, and cannot th en be disa bled (save
by resetting the MCU).
When C is kep t low the counte r can be used as a
7-bit timer.
This bit is cleared to “0” on Reset.
Bit 1 = SR:
Software Reset bit
This bit triggers a Reset when cleared.
When C = “0” (Watchdog disabled) it is the MSB of
the 7-bit timer.
This bit is set to “1” on Reset.
Bits 2-7 = T5-T0:
Downcounter bits
It should be noted that the register bits are re-
versed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog
downcounte r and bit -2 (T5) is the MSB.
These bits are set to “1” on Reset.
3.3.2 Application Notes
The Watc hdog plays an impor tant suppor ting role
in the high noise immunity of ST62xx devices, and
should be used wherever possible. Watchdog re-
lated opti ons sh ould be sel ected on the basis of a
trade-off between application security and STOP
mode availability.
When S TOP mo de is not requi red, hardwar e acti-
vation without EXTERNAL STOP MODE CON-
TROL should be preferred, as it provides maxi-
mum security, especially during power-on.
When STOP mode is required, hardware activa-
tion and EXTERNAL STOP MODE CONTROL
should be chosen . NMI shou ld be hi gh by de fault,
to allow STOP mode to be entered when the MCU
is idle.
The NMI p in c an be conne cted to an I/O l ine (s ee
Figure 18) to allow its state to be controlled by soft-
ware. The I/O line can then be used to keep NMI
low while Watchdog protection is required, or to
avoid noise or key bounce. When no more
proc essi ng is r equi re d, the I/O line i s rel eas ed an d
the device placed in STOP mode for lowest power
consumption.
When software activation is selected and the
Watchdog is not activated, the downcounter may
be used as a simple 7-bit timer (remember that the
bits are in reverse order).
The software activation option should be chosen
only wh en the Watch dog co unter is to be us ed as
a timer. To ensure the Watchdog has not been un-
expectedly activated, the following instructions
should be executed within the first 27 instructions:
jrr 0, WD, #+3
ldi WD, 0FDH
70
T0 T1 T2 T3 T4 T5 SR C
24
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ST62T00C/T01C ST62T0 3C/E 01C
DIGITAL WATCHDOG (Cont’d)
These instructions test the C bit and Reset the
MCU (i.e. disable the Watchdog) if the bit is set
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
In all modes, a minimum of 28 instructions are ex-
ecuted after activation, before the Watchdog can
generate a Reset. Consequently, user software
should load the watchdog counter within the first
27 instructions following Watchdog activation
(software mode), o r within the firs t 27 ins tructions
executed following a Reset (hardware activation).
It should be noted that when the GEN bit is low (in-
terrupts disabled), the NMI interrupt is active but
cannot cause a wake up from STOP/WAIT modes.
Figure 18. A typical circuit making use of the
EXERNAL STOP MODE CONTROL feature
Figure 19. Digital Watchdog Block Diagram
NMI
SWITCH
I/O
VR02002
RSFF
8
DAT A BUS VA00010
-2 -12
OSCILLATOR
RESET
WRITE
RESET
DB0
R
S
Q
DB1.7 SETLOAD
78
-2
SET
CLOCK
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ST62T00C/T01C ST62T03C/E01C
3.4 INTERRU PTS
The CPU can manage four Maskable Interrupt
sources, in addition to a Non Maskable Interrupt
sourc e (to p prio rity i nterrup t). Each so urce i s asso-
ciated with a specific Interrupt Vector which con-
tains a Jump instruction to the associated interrupt
service routine. These v ectors ar e loca ted in P ro-
gram space (see Table 6).
When an interrupt source generates an interrupt
request, and interrupt processing is enabled, the
PC register is loaded with the address of the inter-
rupt vector (i.e. of the Jump instruction), which
then causes a Jump to the relevant interrupt serv-
ice routine, thus servicing the interrupt.
Interrupt sources are linked to events either on ex-
ternal p ins, or o n c hip per i phe rals . S ev eral e ve nts
can be ORed on the same interrupt source, and
relevant flags are available to determine which
event triggered the interrupt.
The Non Maskable Interrupt request has the high-
est priority and can interrupt any interrupt routine
at any time; the othe r four inte rr upts canno t inter-
rupt each other. If more than one interrupt request
is pend ing, these are proc essed by t he pr ocess or
cor e accor ding to t heir pr iority level: source #1 has
the higher priority while source #4 the lower. The
priority of each interrupt source is fixed.
Table 6. Interrupt Vector Map
3.4.1 Interrupt request
All interrupt sources but the Non Maskable Inter-
rupt source can be disabled by setting accordingly
the GEN bit of the Interrupt Option Register (IOR).
This GEN bit also defines if an interrupt source, in-
cluding the Non Maskable Interrupt source, can re-
start the MCU from STOP/WAIT modes.
Interrupt reques t from th e Non M as kable I nterrupt
source #0 is latched by a flip flop which is automat-
ically reset by the core at the beginning of the non-
maskable interrupt service routine.
Interrupt request from source #1 can be config-
ured either as edge or level sensitive by setting ac-
cordingly the LES bit of the Interrupt Option Regis-
ter (I O R ) .
Interrupt r equest from s ource #2 ar e always edge
sensit ive. The edge polarity can be c onfigured b y
setti ng acco rdin gly t he ESB b it o f th e In te rrupt Op-
tion Register (IOR).
Interrupt request from sources #3 & #4 are level
sensitive.
In edge sensitive mode, a latch is set when a edge
occurs on the interrupt source line and is cleared
when the associated interrupt routine is started.
So, the occurrence of an interrupt can be stored,
until completion of the running interrupt routine be-
fore being processed. If several interrupt requests
occurs before completion of the running interrupt
routine, only the first request is stored.
Storage of interrupt requests is not available in lev-
el sensitive mode. To be taken into account, the
low level must be present on the interrupt pin when
the MCU samples the line after instruction execu-
tion.
At the end of ev ery instruc tion, the MCU tes ts the
interrupt lines: if there is an interrupt request the
next instruction is not execute d and the appropri-
ate interrupt service routine is executed instead.
Table 7. Interrupt Option Register Description
Interru pt So urc e Priority Vect or Ad dr es s
Interrupt source #0 1 (FFCh-FFDh)
Interrupt source #1 2 (FF6h-FF7h)
Interrupt source #2 3 (FF4h-FF5h)
Interrupt source #3 4 (FF2h-FF3h)
Interrupt source #4 5 (FF0h-FF1h) GEN SET Enable all interrupts
CLEARED Disable all interrupts
ESB SET Rising edge mode on inter-
rupt source #2
CLEARED Falling edge mode on inter-
rupt source #2
LES SET Level-sensitive mode on in-
terrupt source #1
CLEARED Falling edge mode on inter-
rupt source #1
OTHERS NOT USED
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ST62T00C/T01C ST62T0 3C/E 01C
INTERRUPTS (Cont’d)
3.4.2 Interrupt Procedure
The interrupt procedure is very similar to a call pro-
cedure, indeed the user can consider the interrupt
as an asynchronous call procedure. As this is an
asynchronous event, the user cannot know the
context an d th e ti me at wh ic h i t oc cu rre d. A s a r e-
sult, the user should save all Data space registers
which may be used within the interrupt routines.
There are separate sets of processor flags for nor-
mal, inter rupt and non-mask able interrupt modes,
which are automatically switched and so do not
need to be saved.
The foll owing list summar izes the inter rupt proce-
dure:
MCU
– The interrupt is detected.
– The C and Z flags are replaced by the interrupt
flags (or by the NMI flag s).
– The PC contents are stored in the first level of
the stack.
– The normal interrupt lines are inhibited (NMI still
active).
– The first internal latch is cleared.
– The associated interrupt vector is loaded in the PC.
WARNING: In some circumstances, when a
maskable interrupt occurs while the ST6 core is in
NORMAL m ode and espe cially during the execu-
tion of an "ldi IOR, 00h" instruction (disabling all
maskable interrupts): if the interrupt arrives during
the first 3 cyc les of the "ldi" instruction (which is a
4-cycle instruction) the core will switch to interrupt
mode BUT the flags CN and ZN will NOT switch to
the interrupt pair CI and ZI.
User
– User selected registers are saved within the in-
ter rupt service routine (normally on a software
stack).
– The source of the interrupt is found by polling the
interrupt flags (if more than one source is associ-
ated with the same vector).
– The interru pt is servic ed .
– Return from interrupt (RETI)
MCU
– Automatically the MCU switches back to the nor-
mal flag set (or the interrupt flag set) and pops
the previous PC value from the stack.
The interrupt routine usually begins by the identify-
ing the device which generated the interrupt re-
quest (by polling). The user should save the regis-
ter s whic h ar e use d wi th in th e in ter rupt ro uti ne i n a
software stack. After the RETI instruction is exe-
cuted, the MCU returns to the main routine.
Figure 20. Interrupt Processing Flow Chart
INSTRUCTION
FETCH
INSTRUCTION
EXECUTE
INSTRUCTION
WAS
THE INSTRUCTION
A RETI ?
?
CLEAR
INTERRUPT MASK
SELECT
PROGRAM FLAGS
"POP"
THE STACKED PC
?CHECK IF THERE IS
AN INTERRUPT REQUEST
AND INTERRUPT MASK
SELECT
INTERNAL MODE FLAG
PUSH THE
PC INTO THE STACK
LOAD PC FROM
INTERRUPT VECTOR
(FFC/FFD)
SET
INTERRUPT MASK
NO
NO
YES IS THE CORE
ALREADY IN
NORMAL MODE?
VA000014
YES
NO
YES
27
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ST62T00C/T01C ST62T03C/E01C
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interr upt O pti on Regis ter (IO R) i s used to e n-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
Bit 7, Bits 3-0 =
Unused
.
Bit 6 = LES:
Level/Edge Selection bit
.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 = ESB:
Edge Selection bit
.
The bit ESB selects the polarity of the interrupt
sour ce #2.
Bit 4 = GEN:
Global Enable Interrupt
. When this bit
is se t to one , al l i nte rrup ts ar e e nab led . W hen thi s
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Interrupt sources available on the ST62E01C/
T01C are su mmarized in the Table 8 with associ-
ated mask bit to enable/disable the interrupt re-
quest.
Table 8. Interrupt Requests and Mask Bits
*Except ST62T03C
70
- LES ESB GEN - - - -
Peripheral Register Address
Register Mask bit Masked Interrupt Source Interrupt
vector
GENERAL IOR C8h GEN All Interrupts, excluding
NMI
TIMER TSCR D4h ETI TMZ: TIMER Overflow Vector 3
A/D CONVERTER(*) ADCR D1h EAI EOC: End of Conversion Vector 4
Port PAn ORPA-DRPA C4h-CCh ORPAn-DRPAn PAn pin Vector 1
Port PBn ORPB-DRPB C5h-CDh ORPBn-DRPBn PBn pin Vector 2
28
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ST62T00C/T01C ST62T0 3C/E 01C
INTERRUPTS (Cont’d)
Figure 21. Interrupt Block Diagram
NMI
VDD
FF
CLK Q
CLR
INT #0 - NMI (FFC,D)
I0 Start
RESTART FROM
STOP/WAIT
INT #1 (FF6,7)
FF
CLK Q
CLR
PBE 0
MUX
1
PORT A
PORT B
Bits
INT #2 (FF4,5)
INT #3 (FF2,3)
TMZ
ETI
TIMER
FF
CLK Q
CLR
IOR REG. C8H, bit 5
I1 Start
I2 Start
IOR REG. C8H, bit 6
PBE
PBE
VDD
FROM REGISTER
SINGL E BIT ENABLE
PORT A, B
PBE
INT #4 (FF0,1)
EAI
EOC
ADC(*)
GEN VA0426T
(*)Except on ST62T03C
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ST62T00C/T01C ST62T03C/E01C
3.5 POWER SAVING MODES
The WAIT and STOP modes have been imple-
mented in the ST62xx family of MCUs in order to
reduce the product’s electrical consumption during
idle periods. These two power saving modes are
described in the following paragraphs.
In addition, the Low Frequency Auxiliary Oscillator
(LFAO) c an be u se d i nstead of th e m ain os cil lat or
to reduce power consumption in RUN and WAIT
modes.
3.5.1 WAIT Mode
The MCU goes into WAIT mode as soon as the
WAIT instruction is executed. The microcontroller
can be con sidered as bei ng in a “so ftware fro zen”
state where the core stops processing the pro-
gram instructions, the RAM contents and peripher-
al registers are preserved as long as the power
supply voltage is higher than the RAM retention
voltage. In this mode the peripherals are still ac-
tive.
WAIT mode ca n be used when the user wan ts to
reduce the MCU power consumption during idle
periods, while not losing track of time or the capa-
bility of mon itoring ex ternal ev ents. The activ e os-
cillator (main osci llator or LFAO) is not s topped in
order to provide a clock signal to the peripherals.
Timer counting may be enabled as well as the
Timer interrupt, before entering the WAIT mode:
this allows the WAIT mode to be exited when a
Timer interr upt occurs . The same app lies to other
peripherals which use the clock signal.
If the power consumption has to be further re-
duced, the Low Frequency Auxiliary Oscillator
(LFAO) can be used in place of the main oscillator,
if its operating frequency is lower. If required, the
LFAO must be switched on before entering the
WAIT mode.
If the WAIT m ode is exited due to a Res et (either
by activa ting the external pin or generated by the
Watch do g ), t h e MC U en te r s a no r ma l re se t proce-
dure. If an interrupt is generated during WAIT
mode, the MCU’s behaviour depends on the state
of the p rocesso r core prio r to the WA IT instru ction,
but also on the kind of interrupt request which is
generated. This is described in the following para-
graphs. The processor core does not generate a
delay following the occurrence of the interrupt, be-
cause the oscillator clock is still available and no
stabilisation period is necessary.
3.5.2 STOP Mode
If the Watchdog is disabled, STOP mode is availa-
ble. When in STOP mode, the MCU is placed in
the lowest power consumption mode. In this oper-
ating mode, the microcontroller can be considered
as being “frozen”, no instruction is executed, the
oscillator is stopped, the RAM contents and pe-
ripheral registers are preserved as long as the
power supply voltage is higher than the RAM re-
tention vo ltage, and the S T62x x co re wai ts fo r the
occurrence of an external interrupt request or a
Reset to exit the STOP state.
If the STOP state is exited due to a Reset (by acti-
vating the external pin) the MCU will enter a nor-
mal reset pr oced ure. Beha viou r in r espo nse to in-
terrupts depends on the state of the processor
core prior to issuing the STOP instruction, and
also on th e kind of interrup t request th at is gener-
ated.
This case will be described in the following para-
graphs . The proc esso r core generate s a de lay af -
ter occ urrence of th e interrupt request, in order to
wait for complete stabilisation of the oscillator, be-
fore executing the first instruction.
30
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ST62T00C/T01C ST62T0 3C/E 01C
POWER SAVING MODE (Cont’d)
3.5.3 Exit from WAIT and STOP Modes
The following paragraphs describe how the MCU
exits from WAIT and STOP modes, when an inter-
rupt occurs (not a Reset). It should be noted that
the restart sequence depends on the original state
of the MCU (normal, interrupt or non-maskable in-
terrupt mode) prior to entering WAIT or STOP
mode, as well as on the interrupt type.
Interrupts do not affect the oscillator selection,
consequently, when the LFAO is used, the user
program must manage oscillator selection as soon
as normal RUN mode is resumed.
3.5.3.1 Normal Mode
If the MCU was in the main routine when the WAIT
or STOP instruction was executed, exit from Stop
or Wait mode will occur as soon as an interrupt oc-
curs; the relate d in ter rupt r ou tin e is ex ecuted and,
on completion, the instruction which follows the
STOP or WAIT instruction is then executed, pro-
viding no other interrupts are pending.
3.5.3.2 Non Maskable Interrupt Mode
If the ST OP o r WA IT ins tr uc tio n h as be en exe cu t-
ed during exe cut io n of t he no n-mas k abl e i nterr upt
routine, the MCU exits from the Stop or Wait mode
as soon as an interrupt occurs: the instruction
which foll ows the ST OP or WA IT ins tr ucti on i s ex-
ecuted, and the MCU remains in non-maskable in-
terrupt mode, even if another interrupt has been
generated.
3.5.3.3 Normal Interrupt Mode
If the MCU was in interrupt mode before the STOP
or WAIT instruction was executed, it exits from
STOP or WAIT mode as soon as an interrupt oc-
curs. Nevertheless, two cases must be consid-
ered:
– If the interrupt is a normal one, the interrupt rou-
tine in which the WAIT or STOP mode was en-
tered will be completed, starting with the
execution of the instruction which follows the
STOP or the WAIT instruction, and the MCU is
still in the interrupt mode. At the end of this rou-
tine pending interrupts will be serviced in accord-
ance with their priority.
– In the event of a non-maskable interrupt, the
non-maskable interrupt service routine is proc-
essed first, then the routine in which the WAIT or
STOP mode was entered will be completed by
executing the instruction following the STOP or
WAIT instruction. The MCU remains in normal in-
terrupt mode.
Notes:
To achieve the lowest power consumption during
RUN or WAIT modes, the user program must take
care of:
– configuring unused I/Os as inputs without pull-up
(these should be externally tied to well defined
logic l evels);
– placing all peripherals in their power down
modes before entering STOP mode;
– selecting the Low Frequency Auxiliary Oscillator
(provided this runs at a lower frequency than the
main oscillator).
When the har dwa re ac tiv ate d W atc hdo g is s el ect -
ed, or when the software Watchdog is enabled, the
STOP instruction is disabled and a WAIT instruc-
tion will be executed in its place.
If all interrupt sources are disabled (GEN low), the
MCU can only be restarted by a Reset. Although
setting GEN l ow does not mask the NMI as an in -
terrupt, it will stop it generating a wake-up signal.
The WAIT a nd STOP instr uctions are n ot execut-
ed if an enabled interrupt request is pending.
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ST62T00C/T01C ST62T03C/E01C
4 ON-CHIP PERIPH ERALS
4.1 I/O PORTS
The MCU features Input/Output lines which may
be individually programmed as any of the following
input or output configurati ons:
– Input without pull-up or interrupt
– Input with pull-up and interrupt
– Input with pull-up, but without interrupt
– Analog input
– Push-pull output
– Open drain output
The lines are organised as bytewise Ports.
Each port is associated with 3 registers in Data
space. Each bit of these registers is associated
with a parti cular line ( for insta nce, bits 0 of P ort A
Data, Direction and Option registers are associat-
ed with the PA0 line of Port A).
The DATA registers (DRx), are used to read the
voltage le vel values of the lines which have been
configur ed as inputs, or to wr ite the logic value of
the signa l to be output on the lines con figured as
outputs. The port data registers can be read to get
the effective logic levels of the pins, but they can
be also written by user software, in conjunction
with the related option registers, to select the dif-
ferent input mode options.
Single -bit oper ations o n I /O regi sters are possib le
but care is necessary because reading in input
mode is done from I/O pins while writing will direct-
ly affect the Port data register causing an unde-
sired change of the input configuration.
The Data Direction registers (DDRx) allow the
data direction (input or output) of each pin to be
set.
The Option registers (ORx) are used to select the
different port options available both in input and in
output mode.
All I/O registers can be read or written to just as
any ot her RAM l ocat ion in D ata sp ace , so no ex tra
RAM cells are needed for port data storage and
manipulation. During MCU initialization, all I/O reg-
isters are cleared and the input mode with pull-ups
and no interrupt generation is selected for all the
pins, thus avoiding pin conflicts.
Figure 22. I/O Port Block Diagram
VDD
RESET
SIN CONTROL S
SOUT
SHIFT
REGISTER
DATA
DATA
DIRECTION
REGISTER
REGISTER
OPTION
REGISTER
INPUT/OUTPUT
TO INTERRUPT
VDD
TO ADC VA00413
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ST62T00C/T01C ST62T0 3C/E 01C
I/O PORTS (Cont’d)
4.1.1 Operating Modes
Each pin may be individually programmed as input
or output with various configurations.
This is achieved by writing the relevant bit in the
Data (DR), Data Direction (DDR) and Option reg-
isters (OR). Table 9 illustrates the various port
configurations which can be selected by user soft-
ware.
4.1.1.1 Input Options
Pull-up, High Impedance Option. All input lines
can be individually programmed with or without an
internal pull-up by programming the OR and DR
registers accordingly. If the pull-up option is not
selected, the input pin will be in the high-imped-
ance state.
4.1.1.2 Interrupt Options
All input lines can be individually connected by
software to the interrupt system by programming
the OR and DR registers accordingly. The inter-
rupt trigger modes (falling edge, rising edge and
low level) can be configured by software as de-
scribed in the Interrupt Chapter for each port.
4.1.1.3 Analog Input Options
Some p ins can b e con fig ured as anal og in puts b y
programming the OR and DR registers according-
ly. These analog inputs are connected to the on-
chip 8-bi t An alog to Digital Conv erter .
ONLY ONE
pin should be programmed as an analog input at
any time, since by selecting more than one input
simultaneously their pins will be effectively short-
ed.
Table 9. I/O Port Option Selection
Note: X = Don’t care
DDR OR DR Mode Option
0 0 0 Input With pull-up, no interrupt
0 0 1 Input No pull-up, no interrupt
0 1 0 Input With pull-up and with interrupt
0 1 1 Input Analog input (when available)
1 0 X Output Open-drain output (20mA sink when available)
1 1 X Output Push-pull output (20mA sink when available)
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ST62T00C/T01C ST62T03C/E01C
I/O PORTS (Cont’d)
4.1.2 Safe I/O State Switching Sequence
Switching the I/O ports from one state to another
should be done in a s eq uen ce whi ch en su re s that
no unwanted side effects can occur. The recom-
mended safe transitions are illustrated in Figure
23. All other transitions are potentially risky and
should be av oided when changing the I/O operat-
ing mode, as it is most likely that undesirable side-
effects will be experienced, such as spurious inter-
rupt generation or two pins shorted together by the
analog multiplexer.
Single bit instructions (SET, RES, INC and DEC)
should be used with great caution on Ports Data
registers, since these instructions make an implicit
read and write back of the entire register. In port
input mode, however, the data register reads from
the input pins directly, and not from the data regis-
ter latches. Since data register information in input
mode is used to set the characteristics of the input
pin (interrupt, pull-up, analog input), these may be
unintentionally reprogrammed depending on the
state of the input pins. As a general rule, it is better
to limit the use of single bit instructions on data
registers to when the whole (8-bit) port is in output
mode. In the case of inputs or of mixed inputs and
outpu ts, it is advi sable to keep a copy of the data
register in RAM. Single bit instructions may then
be used on the RAM copy, after which the whole
copy register can be written to the port data regis-
ter:
SET bit, datacopy
LD a, datacopy
LD DRA, a
Warning: Care must also be taken to not use in-
structions that act on a whole port register (INC,
DEC, or read operations) when all 8 bits are not
available on the device. Unavailable bits must be
masked by software (AND instruction).
The WAIT and STOP instructions allow the
ST62xx to be used in sit uations where low power
consumption is needed. The lowest power con-
sumption is achieved by configuring I/Os in input
mode with well-defined logic levels.
The user must take care not to switch outputs with
heavy loads during the conversion of one of the
analog in puts in order to avoid any distur bance to
the conversion.
Figure 23. Diagram showing Safe I/O State Transitions
Note *. xxx = DDR, OR, DR Bits respectively
Interrupt
pull-up
Output
Open Drain
Output
Push-pull
Input
pull-up (Reset
state)
Input
Analog
Output
Open Drain
Output
Push-pull
Input
010*
000
100
110
011
001
101
111
34
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ST62T00C/T01C ST62T0 3C/E 01C
I/O PORTS (Cont’d)
4.1.3 I/O Port Option Registers
ORA/B (CCh PA, CDh PB) Read/Write
Bit 7-0 = Px7 - Px0:
Port A an d B Opti on Regi st er
bits.
4.1.4 I/O Port Data Direction Registers
DDRA/B (C4h PA, C5h PB) Read/Write
Bit 7-0 = Px7 - Px0:
Port A and B Data Direction
Registers bits.
4.1.5 I/O Port Data Registers
DRA/B (C0h PA, C1h PB) Read/Write
Bit 7-0 = Px7 - Px0 :
Port A an d B Data Registers
bits.
Note: X = Don’t care
70
Px7Px6Px5Px4Px3Px2Px1Px0
70
Px7Px6Px5Px4Px3Px2Px1Px0
70
Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0
35
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ST62T00C/T01C ST62T03C/E01C
I/O PORTS (Cont’d)
Table 10. I/O Port Option Selections
Note 1. Provided the correct configuration has been selected.
MODE AVAILABLE ON(1) SCHEMATIC
Input PA1-PA3
PB0,PB1,PB3,PB5-PB7
Input
with pull up
PA1-PA3
PB0,PB1,PB3,PB5-PB7
Input
with pull up
with interrupt
PA1-PA3
PB0,PB1,PB3,PB5-PB7
Analog Input PB3,PB5-PB7
(Except ST62T03C)
Open drain output
5mA
Open drain output
20mA
PB0,PB1,PB3,PB5-PB7
PA1-PA3
Push-pu ll out pu t
5mA
Push-pu ll out pu t
20mA
PB0,PB1,PB3,PB5-PB7
PA1-PA3
Data in
Interrupt
Data in
Interrupt
Data in
Interrupt
Data out
ADC
Data out
36
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ST62T00C/T01C ST62T0 3C/E 01C
4.2 TIMER
The MCU features an on-chip Timer peripheral,
co nsist ing of an 8-bi t c oun ter w ith a 7-bi t pr og ram-
mable prescaler, giving a maximum count of 215.
Figure 24 shows the Timer Block Diagram. The
content of t he 8-bit counter can be r ead/written in
the Timer/Counter register, TCR, which can be ad-
dressed in Data space as a RAM location at ad-
dress 0D3h. The state of the 7-bit prescaler can be
read in the PSC register at address 0D2h. The
control logic device i s mana ged in the TSCR reg-
ister as described in the following paragraphs.
The 8-bit counter is decrement by the output (ris-
ing edge) coming from the 7-bit prescaler and can
be loaded a nd re ad unde r program contr ol. W hen
it decrements to zero then the TMZ (Timer Zero)bit
in the TSCR is s et. If the ETI (Enable Ti mer Inter-
rupt) bit in the TSCR is also set, an interrupt re-
quest is generated. The Timer interrupt can be
used to exit the MCU from WAIT mode.
The pre scal er input is the in ter nal fre quen cy ( f INT)
divided by 12. The prescaler decrements on the
rising edge. Depe nding on the divis ion fact or pro-
gramme d by PS 2, PS1 and P S0 bi ts in the TSCR
(see Figure 1 1), the cloc k input o f the timer/c oun-
ter regi st er i s multiplexe d to different s our ces . Fo r
division factor 1, the clock input of the prescaler is
also th at of timer/co unter; for f actor 2, bit 0 of the
prescaler register is connected to the clock input of
TCR. This bit changes its state at half the frequen-
cy of the prescaler input clock. For factor 4, bit 1 of
the PSC is connected to the clock input of TCR,
and so forth. The prescaler initialize bit, PSI, in the
TSCR register must be set to allow the prescaler
(and he nc e the counter) to s tart. If it i s cl eare d, al l
the pres cale r bits are set and the counter is inhib -
ited from counting. The prescaler can be loaded
with any value between 0 and 7Fh, if bit PSI is set.
The prescaler tap is selected by means of the
PS2/PS1/PS0 bits in the control register.
Figure 25 illustrates the Timer’s working principle.
Figure 24. Timer Block Diagram
DATA BUS
8-BIT
COUNTER STATUS/CONTROL
REGISTER
INTERRUPT
LINE
VR02070A
3
888
6
5
4
3
2
1
0
SELECT
1 OF 7
12
b7 b6 b5 b4 b3 b2 b1 b0
TMZ ETI D5 D4 PSI PS2 PS1 PS0
fINT
PSC
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ST62T00C/T01C ST62T03C/E01C
TIMER (Cont’d)
4.2.1 Timer Operation
The Timer prescaler is clocked by the prescaler
clock input (fINT ÷ 12).
The user can s elect the desir ed presc aler divi sion
ratio through the PS2, PS1, PS0 bits. When the
TCR count reaches 0, it sets the TMZ bit in the
TSCR. The TMZ bit c an be tested u nder program
control to perform a timer function whenever it
goes high.
4.2.2 Timer Interrupt
When the counter register decrements to zero with
the ETI (Enab le Timer Interrupt) bit set to one, an
interrupt request associated with Interrupt Vector
#3 is g ene ra ted. W hen the counter dec rements to
zero, the TMZ bit in the TSCR register is set to
one.
4.2.3 Application Notes
TMZ is set when the counter reaches zero; howev-
er, it may also be set by writing 00h in the TCR
register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts wh en leaving th e interrupt se rvice
routine. After reset, the 8-bit counter register is
loaded with 0FFh, while the 7-bit prescaler is load-
ed with 07Fh, and the TSCR register is cleared.
This means that the Timer is stopped (PSI=“0”)
and the timer interrupt is disabled.
Figure 25. Timer Working Principle
BIT0 BIT1 BIT2 BIT3 BIT6BIT5BIT4
CLOCK
7-BIT PRESCALER
8-1 MULTIPLEXER
8-BIT COUNTER
BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7
102
34567PS0
PS1
PS2
VA00186
38
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ST62T00C/T01C ST62T0 3C/E 01C
TIMER (Cont’d)
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence,
and the TMZ bit is not set until the 8-bit counter
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time.
4.2.4 Timer Registers
Timer Status Control Register (TSCR)
Address: 0D4h — Read/Write
Bit 7 = TMZ:
Timer Zero bit
A low-to-high transition indicates that the timer
count register has decrement to zero. This bit
must be cleared by user software before starting a
new count.
Bit 6 = ETI:
Enable Timer Interrup
When set, enables the timer interrupt request
(vector #3). If ETI=0 the timer interrupt is disabled.
If ETI=1 and TMZ=1 an interrupt request is gener-
ated.
Bit 5 = D5:
Reserved
Must be set to “1”.
Bit 4 = D4
Do not care.
Bit 3 = PSI:
Presc ale r Ini t ia li ze Bi t
Used to initialize the prescaler and inhibit its count-
ing. When P SI=“0” the presca ler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as
PSI=“0” both counter and prescaler are not run-
ning.
Bit 2, 1, 0 = PS2, PS1, PS0:
Prescaler Mux. Se-
lect.
These bits select the division ratio of the pres-
caler register.
Table 11. Prescaler Division Factors
Timer Counter Register TCR
Address: 0D3h — Read/Write
Bit 7-0 = D7-D0:
Counter Bits.
Prescaler Register PSC
Address: 0D2h — Read/Write
Bit 7 = D7: Always read as "0".
Bit 6-0 = D6-D0: Prescaler Bits.
70
TMZ ETI D5 D4 PSI PS2 PS1 PS0
PS2 PS1 PS0 Divided by
0 0 0 1
0 0 1 2
0 1 0 4
0118
10016
10132
11064
111128
70
D7 D6 D5 D4 D3 D2 D1 D0
70
D7 D6 D5 D4 D3 D2 D1 D0
39
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ST62T00C/T01C ST62T03C/E01C
4.3 A/D CONVERTER (ADC)
The A/D conver ter per ipheral is an 8-bi t ana log to
digital converter with analog inputs as alternate I/O
functions ( the number o f which is devi ce depend-
ent), offering 8-bit resolution with a typical conver-
sion time of 70u s (at an osci llator cloc k frequency
of 8MHz).
The ADC conver ts the input voltage b y a process
of successive approximations, using a clock fre-
quency derived from the oscillator with a division
factor of twelve. With an oscillator clock frequency
less than 1.2MHz, conversion accuracy is de-
creased.
Selection of the input pin is done by configuring
the related I/O lin e as an analog inp ut via the Op-
tion an d Data regist ers (refe r to I/O p orts des crip-
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
than one I/O pin is selec ted as an analog inp ut si -
multaneously, to avoid device malfunction.
The ADC uses two registers in the data space: the
ADC data c onversion register, A DR, which stores
the conversion result, and the ADC control regis-
ter, ADCR, used to program the ADC functions.
A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto-
maticall y cle ars (r es ets to “ 0” ) the En d Of C onver -
sion Bit (EOC). When a conversion is complete,
the EOC bit is autom atically se t to “1”, in ord er to
flag tha t conversi on is co mplete and that the data
in the ADC data con versi on register is valid. Ea ch
conversion has to be separately initiated by writing
to the STA bit.
The STA bit is continuously scanned so that, if the
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before com-
pleting the previous one. The start bit (STA) is a
write only bit, any attempt to read it will show a log-
ical “0”.
The A/D converter features a maskable interrupt
associated with the end of conversion. This inter-
rupt is ass ociated with interrupt v ector #4 an d oc-
curs when the EOC bi t is set (i .e. when a conver-
sion is completed) . The interrupt i s masked us ing
the EAI (interrupt mask) bit in the control register.
The power consumption of the device can be re-
duced by turning off the ADC peripheral. This is
done by setting the PDS bit in the ADC control reg-
ister to “0”. If PDS=“1”, the A/D is powered and en-
abled for convers ion. This bit must be set at least
one instruction before the beginning of the conver-
sion to allow stabilisation of the A/D converter.
This action is also needed before entering WAIT
mode, since the A/D comparator is not automati-
cally disabled in WAIT mode.
During Reset, any conversion in progress is
stopped, the control register is reset to 40h and the
ADC interrupt is masked (EAI=0).
Figure 26. ADC Block Diagram
4.3.1 Application Notes
The A/D convert er does no t featur e a sample and
hold circuit. The analog voltage to be measured
should therefore be stable during the entire con-
versio n cycle . Volt age vari atio n shoul d not exc eed
±1/2 LSB for the optimum conversion accuracy. A
low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
version.
When selected as an analog channel, the input pin
is internally connected to a capacitor Cad of typi-
cally 12pF. For m aximu m accu racy, th is cap acito r
must be fully charged at the beginning of co nver-
sion. In the worst case, conversion starts one in-
struction (6.5 µs) after the channel has been se-
lected. In worst case conditions, the impedance,
ASI, of the analog voltage source is calculated us-
ing the following formula:
6.5µs = 9 x Cad x ASI
(capacitor charged to over 99.9%), i.e. 30 kΩ in-
cluding a 50% guardband. ASI can be higher if Cad
has been charged for a longer period by adding in-
structions before the start of conversion (adding
more than 26 CPU cycles is pointless).
CONTROL REGISTER
CONVERTER
VA00418
RESULT REGISTER
RESET
INTERRUPT
CLOCK
AV
AVDD
Ain
8
CORE
CONTROL SIGNAL S
SS
8
CORE
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ST62T00C/T01C ST62T0 3C/E 01C
A/D CONVERTER (Cont’d)
Since the ADC is on the same chip as the micro-
processor, the user should not switch heavily load-
ed output s ignals durin g conversion, i f high preci-
sion is required. Such switching will affect the sup-
ply voltages used as analog references.
The accuracy of the conversion depends on the
quality of the power supplies (VDD and VSS). The
user must take special care to ensure a well regu-
lated refe rence v oltage is pres ent on th e VDD and
VSS pins (power supply voltage variations must be
less than 5V/ms). This implies, in particular, that a
suitable decoupling capacitor is used at the VDD
pin.
The converter resolution is given by::
The Input voltage (Ain) which is to be converted
must be constant for 1µs before conversion and
remain constant during conversion.
Conversion resolution can be improved if the pow-
er supply voltage (VDD) to the microcontroller is
lowered.
In order to optimise conversion resolution, the user
can configure the microcontroller in WAIT mode,
because this mode minimises noise disturbances
and power suppl y vari ations du e to output switc h-
ing. Ne vert heless, the W AI T inst ructi on s hould be
executed as soon as poss ible after the begi nning
of the conversion, because execution of the WAIT
instruction may cause a small variation of the VDD
voltage. The negative effect of this variation is min-
imized at the beginning of the conversion when the
converter is less sensitive, rather than at the end
of conversion, when the less significant bits are
determined.
The best configuration, from an accuracy stand-
point, is WAIT mode with the Timer stopped. In-
deed, only the ADC peripheral and the oscillator
are then still working. The MCU must be woken up
from WAIT mo de by the AD C interrupt at the end
of the conversion. It should be noted that waking
up the microcontroller could also be done using
the Timer interrupt, but in this case the Timer will
be working and the resulting noise could affect
conversion accuracy.
A/D Converter Control Register (ADCR)
Address: 0D1h — Read/Write
Bit 7 = EAI:
Enable A/D Interrupt.
If this bit is set to
“1” the A/D interrupt is enabled, when EAI=0 the
interrupt is disabled.
Bit 6 = EOC:
End of conversion.
Read Only
. This
read only bit indicates when a conversion has
been completed. This bit is automatically reset to
“0” when the STA bit is written. If the user is using
the interrupt option then this bit can be used as an
interrupt pending bit. Data in the data conversion
register are valid only when this bit is set to “1”.
Bit 5 = STA
: Start of Conversion. Write Only
. Writ-
ing a “1” to this bit will start a conversion on the se-
lected channel and automatically reset to “0” the
EOC bit. If the bit is set again when a conversion is
in progress, the present conversion is stopped and
a new one will take place. This bit is write only, any
attempt to read it will show a logical zero.
Bit 4 = PDS
: Power Dow n Selection.
This bit acti -
vates the A/D converter if set to “1”. Writing a “0” to
this bi t wi ll put the ADC in p owe r d own mod e (id le
mode).
Bit 3-0 = D3-D0. Not used
A/D Converter Data Register (ADR)
Address: 0D0h — Read only
Bit 7-0 = D7-D0
: 8 Bit A/D Conversion Result.
V
DD
V
SS
–
256
----------------------------
70
EAI EOC STA PDS D3 D2 D1 D0
70
D7 D6 D5 D4 D3 D2 D1 D0
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ST62T00C/T01C ST62T03C/E01C
5 SO FTWARE
5.1 ST6 ARCHITECTURE
The ST6 s oftware has been design ed to full y use
the hardware in the most efficient way possible
while keeping byte usage to a minimum; in short,
to provide byte efficient programming capability.
The ST6 core has the ability to set or clear any
register or RAM location bit of the Data space with
a single instruction. Furthermore, the program
may branch to a selected address depending on
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET
or RES instruction is processed.
5.2 ADDRESSING MODES
The ST6 core offers nine addressing modes,
which are described in the following paragraphs.
Three different address spaces are available: Pro-
gram space, Data space, and Stack space. Pro-
gram spa ce conta ins th e instr uction s whi ch are to
be executed, plus the data for immediate mode in-
structions. Data space contains the Accumulator,
the X,Y,V and W registers, peripheral and Input/
Output registers, the RAM locations and Data
ROM locations (for storage of tables and con-
stants). Stack space contains six 12-bit RAM cells
used to stack the return addresses for subroutines
and interrupts .
Immediate. In the immediate addressing mode,
the operand of the instruction follows the opcode
location. As the operand is a ROM byte, the imme-
diate addressing mode is used to access con-
stants which do not change during program execu-
tion (e.g., a constant used to initialize a loop coun-
ter).
Direct. In the direct addressing mode, the address
of t h e by te w hi ch i s processe d by t h e in str u ction is
stored in the location which follows the opcode. Di-
rect addressing allows the user to directly address
the 256 bytes in Data Space memory with a single
two-byte instruction.
Short Direct. The core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in
the short-direct addressing mode. In this case, the
instruction is only one byte and the selection of the
location to be processed is contained in the op-
code. Short direct addressing is a subset of the di-
rect addressing mode. (Note that 80h and 81h are
also indirect registers).
Extended. In the extended addr essing mode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) which use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.
An extended addressing mode instruction is two-
byte long.
Program Counter Relative. The relative address-
ing mode is only used in conditional branch in-
structions. The instruction is used to perform a test
and, if the condition is true, a branch with a span of
-15 to +16 locations around the address of the rel-
ative instruction. If the condition is not true, the in-
struction which follows the relative instruction is
executed. The relative addressing mode instruc-
tion is one-byte long. The opcode is obtained in
adding the three most significant bits which char-
acterize the kind of the test, one bit which deter-
mines whether th e branch i s a forwar d (when it i s
0) or backward (when it is 1) branch and the four
less significant bits which give the span of the
branch (0h to Fh) which must be added or sub-
tracte d to the add ress of t he relati ve ins tructio n to
obtain the address of the branch.
Bit Direct. In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the ad-
dress of the byte in which the specified bit must be
set or cleared. Thus, any bit in the 256 locations of
Data space memory can be set or cleared.
Bit Test & Branch. The bit test and branch ad-
dressing mode is a combination of direct address-
ing and relative addressing. The bit test and
branc h ins tr uct io n is th re e-by te lon g. The bi t i den -
tification and the tested condition are included in
the opcode byte. The address of the byte to be
test ed follows immed iately the opcod e in the Pro-
gram space. The third byte is the jump displace-
ment, which is in the range of -127 to +128. This
displacement can be determined using a label,
which is conv er ted by the assem bl er .
Indirect. In the indirect addressing mode, the byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the in-
direct registers, X or Y (80h,81h). The indirect reg-
ister is selected by the bit 4 of the opcode. A regis-
ter indirect instruction is one byte long.
Inherent. In the inherent addressing mode, all the
information necessary to execute the instruction is
contained in the opcode. These instructions are
one byte long.
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ST62T00C/T01C ST62T0 3C/E 01C
5.3 INSTRUCTION SET
The ST6 c ore offers a set of 40 basic i nstructio ns
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be di-
vided into six different types: load/store, arithme-
tic/logic, conditional branch, control instructions,
jump/cal l, and bi t manipulati on. Th e follow ing par-
agraphs describe the different types.
All the instructions belonging to a given type are
presented in individual tables.
Load & Store. These inst ru ction s us e on e, two or
three bytes in relation with the addressing mode.
One operand is the Accumulator for LOAD and the
other operand is obtained from data memory using
one of the addressing modes.
For Load Immediate one operand can be any of
the 256 data space bytes while the other is always
immedi ate data .
Table 12. Load & Store Instructions
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Regi sters
# . Immediate data (stored in ROM memory)
rr. Data space regist er
∆. Affected
* . Not Affected
Instruction Addressing Mode Bytes Cycles Flags
ZC
LD A, X Short Direct 1 4 ∆ *
LD A, Y Short Direct 1 4 ∆ *
LD A, V Short Direct 1 4 ∆ *
LD A, W Short Direct 1 4 ∆ *
LD X, A Short Direct 1 4 ∆ *
LD Y, A Short Direct 1 4 ∆ *
LD V, A Short Direct 1 4 ∆ *
LD W, A Short Direct 1 4 ∆ *
LD A, rr Direct 2 4 ∆ *
LD rr, A Direct 2 4 ∆ *
LD A, (X) Indirect 1 4 ∆ *
LD A, (Y) Indirect 1 4 ∆ *
LD (X), A Indirect 1 4 ∆ *
LD (Y), A Indirect 1 4 ∆ *
LDI A, #N Immediate 2 4 ∆ *
LDI rr, #N Immediate 3 4 * *
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ST62T00C/T01C ST62T03C/E01C
INSTRUCTION SET (Cont’d)
Arithmetic and Logic. These instructions are
used to perform the arithmetic calculations and
logic operations. In AND, ADD, CP, SUB instruc-
tions one operand is always the accumulator while
the other can be either a data space memory con-
tent or an imm ediate valu e in rel ation with the ad-
dressing mode. In CLR, DEC, INC instructions the
operand can be any of the 256 data space ad-
dresses. In COM, RLC, SLA the operand is always
the accumulator.
Table 13. Arithmetic & Logic Instructions
Notes:
X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected
# . Immediate data (stored in ROM memory)* . Not Affec ted
rr. Data s pace register
Instruction Addressing Mode Bytes Cycles Flags
ZC
ADD A, (X) Indirect 1 4 ∆∆
ADD A, (Y) Indirect 1 4 ∆∆
ADD A, rr Direct 2 4 ∆∆
ADDI A, #N Im me dia te 2 4 ∆∆
AND A, (X) Indirect 1 4 ∆∆
AND A, (Y) Indirect 1 4 ∆∆
AND A, rr Direct 2 4 ∆∆
ANDI A, #N Im me dia te 2 4 ∆∆
CLR A Short Direct 2 4 ∆∆
CLR r Direct 3 4 * *
COM A In he ren t 1 4 ∆∆
CP A, (X) Indirect 1 4 ∆∆
CP A, (Y) Indirect 1 4 ∆∆
CP A, rr Direct 2 4 ∆∆
CPI A, #N Immediate 2 4 ∆∆
DEC X Short Direct 1 4 ∆*
DEC Y Short Direct 1 4 ∆*
DEC V Short Direct 1 4 ∆*
DEC W Short Direct 1 4 ∆*
DEC A Direct 2 4 ∆*
DEC rr Direct 2 4 ∆*
DEC (X) Indirect 1 4 ∆*
DEC (Y) Indirect 1 4 ∆*
INC X Short Direct 1 4 ∆*
INC Y Short Direct 1 4 ∆*
INC V Short Direct 1 4 ∆*
INC W Short Direct 1 4 ∆*
INC A Direct 2 4 ∆*
INC rr Direct 2 4 ∆*
INC (X) Indirect 1 4 ∆*
INC (Y) Indirect 1 4 ∆*
RLC A Inherent 1 4 ∆∆
SLA A Inherent 2 4 ∆∆
SUB A, (X) Indirect 1 4 ∆∆
SUB A, (Y) Indirect 1 4 ∆∆
SUB A, rr Direct 2 4 ∆∆
SUBI A, #N Im me diate 2 4 ∆∆
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ST62T00C/T01C ST62T0 3C/E 01C
INSTRUCTION SET (Cont’d)
Conditional Branch. The branch instructions
achieve a branch i n the progr am when the selec t-
ed condition is met.
Bit Manipulation Instructions. These instruc-
tions can handle any bit in data space memory.
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
branch operations.
Control Instructions. The control instructions
control the MCU operations during program exe-
cution.
Jump and Call. These two instructions are used
to perform long (12-bit) jumps or subroutines call
inside the whole program space.
Table 14. Conditional Branch Instructions
Notes:
b. 3-bit address rr. Data space register
e. 5 bit signed dis placement in the r ange -15 to +16<F128M> ∆ . Affected. The tested bit is shifted into carry.
ee. 8 bit signed dis placement in the r ange -126 to +129 * . Not Affected
Table 15. Bit Manipulation Instructions
Notes:
b. 3-bi t address; * . Not< M > Affected
rr. D ata space register;
Table 16. Control Instructions
Notes:
1. This instruction is deactivated<N>and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.
∆ . Affected
*. Not Af fe cte d
Table 17. Jump & Call Instructions
Notes:
abc. 12-bit address;
* . Not Affected
Instru ctio n Branch If Bytes Cycles Flags
ZC
JRC e C = 1 1 2 * *
JRNC e C = 0 1 2 * *
JRZ e Z = 1 1 2 * *
JRNZ e Z = 0 1 2 * *
JRR b, rr, ee Bit = 0 3 5 * ∆
JRS b, rr, ee Bit = 1 3 5 * ∆
Instruction Addressing Mode Bytes Cycles Flags
ZC
SET b,rr Bit Direct 2 4 * *
RES b,rr Bit Direct 2 4 * *
Instruction Addressing Mode Bytes Cycles Flags
ZC
NOP Inherent 1 2 * *
RET Inherent 1 2 * *
RETI Inherent 1 2 ∆∆
STOP (1) Inherent 1 2 * *
WAIT Inherent 1 2 * *
Instruction Addressing Mode Bytes Cycles Flags
ZC
CALL abc Extended 2 4 * *
JP abc Extend ed 2 4 * *
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ST62T00C/T01C ST62T03C/E01C
Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW 0
0000 1
0001 2
0010 3
0011 4
0100 5
0101 6
0110 7
0111
LOW
HI HI
0
0000
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD 0
0000
e abc e b0,rr,ee e # e a,(x)
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
1
0001
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 LDI 1
0001
e abc e b0,rr,ee e x e a,nn
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
2
0010
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 CP 2
0010
e abc e b4,rr,ee e # e a,(x)
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
3
0011
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 CPI 3
0011
e abc e b4,rr,ee e a,x e a,nn
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
4
0100
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 ADD 4
0100
e abc e b2,rr,ee e # e a,(x)
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
5
0101
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 ADDI 5
0101
e abc e b2,rr,ee e y e a,nn
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
6
0110
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 INC 6
0110
e abc e b6,rr,ee e # e (x)
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
7
0111
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 7
0111
e abc e b6,rr,ee e a,y e #
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc
8
1000
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD 8
1000
e abc e b1,rr,ee e # e (x),a
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
9
1001
2 RNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 9
1001
e abc e b1,rr,ee e v e #
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc
A
1010
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 AND A
1010
e abc e b5,rr,ee e # e a,(x)
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
B
1011
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 ANDI B
1011
e abc e b5,rr,ee e a,v e a,nn
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
C
1100
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 SUB C
1100
e abc e b3,rr,ee e # e a,(x)
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
D
1101
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 SUBI D
1101
e abc e b3,rr,ee e w e a,nn
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
E
1110
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 DEC E
1110
e abc e b7,rr,ee e # e (x)
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
F
1111
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC F
1111
e abc e b7,rr,ee e a,w e #
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc
Abbreviations for Addressing Modes: Legend:
dir Direct # Indicates Illegal Instructions
sd Short Direct e 5 Bit Displacement
imm Immediate b 3 Bit Addre ss
inh Inherent rr 1byte dataspace address
ext Ex tended nn 1 byte immediat e data
b.d Bit Direct abc 12 bit address
bt Bit Test ee 8 bit Displacement
pcr Program Counter Relative
ind Indirect
2JRC
e
1prc
Mnemonic
Address i ng Mode
Bytes
Cycle
Operand
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Opcode Map Summary (Continued)
LOW 8
1000 9
1001 A
1010 B
1011 C
1100 D
1101 E
1110 F
1111
LOW
HI HI
0
0000
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 LDI 2 JRC 4 LD 0
0000
e abc e b0,rr e rr,nn e a,(y)
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind
1
0001
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD 1
0001
e abc e b0,rr e x e a,rr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2
0010
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 COM 2 JRC 4 CP 2
0010
e abc e b4,rr e a e a,(y)
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind
3
0011
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 CP 3
0011
e abc e b4,rr e x,a e a,rr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
4
0100
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RETI 2 JRC 4 ADD 4
0100
e abc e b2,rr e e a,(y)
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
5
0101
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 ADD 5
0101
e abc e b2,rr e y e a,rr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
6
0110
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 STOP 2 JRC 4 INC 6
0110
e abc e b6,rr e e (y)
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
7
0111
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 INC 7
0111
e abc e b6,rr e y,a e rr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
8
1000
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 JRC 4 LD 8
1000
e abc e b1,rr e # e (y),a
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind
9
1001
2 RNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD 9
1001
e abc e b1,rr e v e rr,a
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
A
1010
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 RCL 2 JRC 4 AND A
1010
e abc e b5,rr e a e a,(y)
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
B
1011
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 AND B
1011
e abc e b5,rr e v,a e a,rr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
C
1100
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RET 2 JRC 4 SUB C
1100
e abc e b3,rr e e a,(y)
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
D
1101
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 SUB D
1101
e abc e b3,rr e w e a,rr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
E
1110
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 WAIT 2 JRC 4 DEC E
1110
e abc e b7,rr e e (y)
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
F
1111
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 DEC F
1111
e abc e b7,rr e w,a e rr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
Abbreviations for Addressing Modes: Legend:
dir Direct # Indicates Illegal Instructions
sd Short Direct e 5 Bit Displacement
imm Immediate b 3 Bit Addre ss
inh Inherent rr 1byte dataspace address
ext Ex tended nn 1 byte immediat e data
b.d Bit Direct abc 12 bit address
bt Bit Test ee 8 bit Displacement
pcr Program Counter Relative
ind Indirect
2JRC
e
1prc
Mnemonic
Address i ng Mode
Bytes
Cycle
Operand
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ST62T00C/T01C ST62T03C/E01C
6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static volt ages, how-
ever it is advisable to take normal precaution to
avoid application of any voltage higher than the
specified maximum rated voltages.
For proper operation it is recommended that VI
and VO be higher than VSS and lower than VDD.
Reliability is enhanced if unused inputs are con-
nected to an appropriate logic voltage level (V DD
or VSS).
Power Considerations.The average chip-junc-
tion temperature, Tj, in Celsius can be obtained
from:Tj=TA + PD x RthJA
Where:TA = Ambient Temperature.
RthJA =Package thermal resistance (junc-
tion-to ambient).
PD = Pint + Pport.
Pint =IDD x VDD (chip internal power).
Pport =Port power dissipation (determined
by the user).
Notes:
- Stresses above those listed as “absolute maximum rat ings” may c ause permanent damage to the device. This is a stress rating only and
functi onal operation of the dev ice at these conditions is not implied. Exposure to maximum rating cond itions for extend ed periods may
affect dev ice reliability .
- (1) Within these limits, clamping diodes are guarantee to be not condu ctive. Voltag es outside these limit s are authoris ed as lo ng as injection
current is kept within the specification.
Symbol Parameter Value Unit
VDD Supply Voltage -0.3 to 7.0 V
VIInput Voltage VSS - 0.3 to VDD + 0.3(1) V
VOOutput Volta ge VSS - 0.3 to VDD + 0.3(1) V
IVDD Total Current into VDD (source) 80 m A
IVSS Total Current out of VSS (sink) 100 mA
Tj Junction Temperature 150 °C
TSTG S torag e Temp eratu re -60 to 150 °C
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ST62T00C/T01C ST62T0 3C/E 01C
6.2 RECOMMENDED OPERATING CONDITIONS
Notes:
1. Care mus t be taken i n case of negat ive curre nt injection, where adapt ed impeda nce must be res pected on analog sourc es to not affect the
A/D conversion. For a -1mA injection, a maxi mum 10 KΩ is recomme nded.
2.An oscillator frequency above 1MHz is recommended for reliable A/D res ults
Figure 27. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (VDD)
The sh aded area is outside the rec ommended operating range; device func tionality is not gua ranteed under these c onditions.
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
TAOperatin g Te mp erat ure 6 Suffix Vers ion
1 Suffix Version
3 Suffix Version
-40
0
-40
85
70
125 °C
VDD Operatin g Su pp ly Vo ltag e fOSC = 4MHz, 1 & 6 Suffix
fOSC = 4MHz, 3 Suffix
fosc= 8MHz , 1 & 6 Suffix
fosc= 8MHz , 3 Suffix
3.0
3.0
3.6
4.5
6.0
6.0
6.0
6.0 V
fOSC Oscillator Frequency2) VDD = 3.0V, 1 & 6 Suffix
VDD = 3.0V , 3 Suffix
VDD = 3.6V , 1 & 6 Suffix
VDD = 3.6V , 3 Suffix
0
0
0
0
4.0
4.0
8.0
4.0 MHz
IINJ+ Pin Injection Current (positive) VDD = 4.5 to 5.5V +5 mA
IINJ- Pin Injection Current (negative) VDD = 4.5 to 5.5V -5 mA
8
7
6
5
4
3
2
1
2.5 3 44.5 55.5 6
SUPPLY VOLTAGE (VDD)
Maximum FREQUENCY (MHz)
FUNCTIONALITY IS NOT
GUARANTEED IN
THIS AR EA
3 Suffix version
1 & 6 Suffix version
3.6
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ST62T00C/T01C ST62T03C/E01C
6.3 DC ELECTRICAL CHARACTERIS TICS
(TA = -40 to +125°C unless otherwise specified)
Notes:
(1) Hysteresis v oltage between switching levels
(2) All peripherals running
(3) All peripherals in stand-by + option byte programmed (except LVD)
(4) Chara cterized but not tested; option byte programmed except LVD
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
VIL Input Low Level Vo lta ge
All Input pins VDD x 0.3 V
VIH Input High Level Voltage
All Input pins VDD x 0.7 V
VHys Hysteres is Voltage (1)
All Input pins VDD= 5V
VDD= 3V 0.2
0.2 V
Vup LVD Threshold in power-on 4.1 4.3
Vdn L VD threshold in powerdown 3.5 3.8
VOL
Low Level Output Voltage
All Output pin s VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = + 3mA 0.1
0.8 V
Low Level Output Voltage
20 mA Sink I/O pins VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = +7mA
VDD= 5.0V; IOL = +15mA
0.1
0.8
1.3
VOH High Level Output Voltage
All Output pin s VDD= 5.0V; IOH = -10µA
VDD= 5.0V; IOH = -3. 0m A 4.9
3.5 V
RPU Pull-up Resistance All Input pins 40 100 350 ΚΩ
RESET pin 150 350 900
IIL
IIH
Input Leakage Current
All Input pins but RESE T VIN = VSS (No Pull-Up configured)
VIN = VDD 0.1 1.0 µA
Input Leakage Current
RESET pin VIN = VSS
VIN = VDD -8 -16 -30
10
IDD
Supply Current in RESET
Mode VRESET=VSS
fOSC=8MHz 3.5 mA
Supply Current in
RUN Mo de (2) VDD=5.0V fINT=8MHz 3.5 mA
Supply Current in WAIT
Mode (3) VDD=5.0V fINT=8MHz 500 µA
Supply Current in WAIT
Mode (4) VDD=3V fINT=32K 30 µA
Supply Current in STOP
Mode, with LV D dis abled(3) ILOAD=0mA
VDD=5.0V 20 µA
Supply Current in STOP
Mode, with LV D ena bled(3) ILOAD=0mA
VDD=5.0V 500
Retention EPROM Data Retention TA = 55°C 10 years
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ST62T00C/T01C ST62T0 3C/E 01C
DC ELECTRICAL CHARACTERISTICS (Cont’d)
(TA = -40 to +85°C unless otherwise specified))
Note:
(*) All Peripherals in stand-by.
6.4 AC ELECTRICAL CHARACTERIS TICS
(TA = -40 to +125°C unless otherwise specified)
Notes:
1. Period f or whic h VDD has to be connected at 0V to allow internal Reset function at next power-up.
2 An oscillator frequency above 1MHz is recommended for reliable A/D result s.
3. Measu r e performed with OSCin pin soldered on PCB, with an around 2p F equivalent capacitance.
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
Vup LVD Threshold in power-on Vdn +50 mV 4.1 4.3 V
Vdn L VD threshold in powerdown 3.6 3.8 V up -50 mV V
VOL
Low Level Output Voltage
All Output pin s VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = + 5mA
VDD= 5.0V; IOL = + 10mAv
0.1
0.8
1.2 V
Low Level Output Voltage
20 mA Sink I/O pins
VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = +10mA
VDD= 5.0V; IOL = +20mA
VDD= 5.0V; IOL = +30mA
0.1
0.8
1.3
2.0
VOH High Level Output Voltage
All Output pin s VDD= 5.0V; IOH = -10µA
VDD= 5.0V; IOH = -5. 0m A 4.9
3.5 V
IDD Supply Current in STOP
Mode, with LV D dis abled(*) ILOAD=0mA
VDD=5.0V 10 µA
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
tREC Supply Recovery Time (1) 100 ms
fLFAO Internal frequency with LFAO active 200 400 800 kHz
fOSG Internal Frequency with OSG
enabled2) VDD = 3V
VDD = 3.6V
VDD = 4.5V
2
2
4fOSC MHz
fRC Internal frequency with RC oscillator
and OSG disabled2) 3)
VDD=5.0V
R=47kΩ
R=100kΩ
R=470kΩ
4
2.7
800
5
3.2
850
5.8
3.5
900
MHz
MHz
kHz
CIN Input Capacitance All Inputs Pins 10 pF
COUT Output Capacitance All Outputs Pins 10 pF
51
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ST62T00C/T01C ST62T03C/E01C
6.5 A/D CONVERTER CHARACTERISTICS
(TA = -40 to +125°C unless otherwise specified)
Notes:
1. Noise at VDD, VSS <10mV
2. With oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased.
6.6 TIMER CHARACTERIS TICS
(TA = -40 to +125°C unless otherwise specified)
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
Res Resolution 8 Bit
ATOT Total Accuracy (1) (2) fOSC > 1.2MHz
fOSC > 32kHz ±2
±4LSB
tCConve rsio n Tim e fOSC = 8MHz (TA < 85°C)
fOSC = 4 MHz 70
140 µs
ZIR Zero Input Reading Conversion result when
VIN = VSS 00 Hex
FSR Full Scale Reading Conversion result when
VIN = VDD FF Hex
ADIAnalog Input Current During
Conversion VDD= 4.5V 1.0 µA
ACIN Analog Input Capacitance 2 5 pF
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
fIN Input Frequency on TIMER Pin MHz
tWPulse Width at TIMER Pin VDD = 3.0V
VDD >4.5V 1
125 µs
ns
IINT
4
----------
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ST62T00C/T01C ST62T0 3C/E 01C
Figure 28.. RC frequency versus Vcc
Figure 29. LVD thresholds versus temperature
33.544.555.56
0.1
1
10
0+]
VDD (volts)
Frequency
R=47K
R=100K
R=470K
This curves represents typical variations and is given for guidance only
3.6
3.7
3.8
3.9
4
4.1
4.2
Temp
Vthresh.
-40°C 25°C 95°C 125°C
Vup
Vdn
This curves represents typical variations and is given for guidance only
53
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ST62T00C/T01C ST62T03C/E01C
Figure 30. Idd WAIT versus Vcc at 8 M hz for OTP devices
Figure 31. Idd STOP versus Vcc for OTP devices
Figure 32. Idd STOP versus Vcc for ROM devices
0
0.2
0.4
0.6
0.8
1
1.2
Vdd
Idd WAIT (mA)
3V 4V 5V 6V
T = -40°C
T = 25°C
T = 95°C
T = 125°C
This curves represents typical variations and is given for guidance only
-2
0
2
4
6
8
Vdd
Idd WAIT (µA)
3V 4V 5V 6V
T = -40°C
T = 25°C
T = 95°C
T = 125°C
This curves represents typical variations and is given for guidance only
-0.5
0
0.5
1
1.5
2
Vdd
Idd STOP (µA)
3V 4V 5V 6V
T = -40°C
T = 25°C
T = 95°C
T = 125°C
This curves represents typical variations and is given for guidance only
54
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ST62T00C/T01C ST62T0 3C/E 01C
Figure 33. Idd WAIT versus Vcc at 8Mhz for ROM devices
Figure 34. Idd WAIT (µA) Fosc=32KHz (option byte programmed to 00h)
Figure 35. Idd RUN versus Vcc at 8 Mhz for ROM and OTP devices
0
0.2
0.4
0.6
0.8
Vdd
Idd WAIT (mA)
3V 4V 5V 6V
T = -40°C
T = 25°C
T = 95°C
T = 125°C
This curves represents typical variations and is given for guidance only
This curves represents typical variations and is given for guidance only
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
Vdd (volts)
Idd Wait (µA)
2.5 3 3.5 4 4.5 5 5.5 6
T = -40C
T = 25C
T = 95C
T = 125C
1
2
3
4
5
Vdd
Idd RU N (mA)
3V 4V 5V 6V
T = -40°C
T = 25°C
T = 95°C
T = 125°C
This curves represents typical variations and is given for guidance only
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ST62T00C/T01C ST62T03C/E01C
Figure 36. Vol versus Iol on all I/O port at Vdd=5V
Figure 37. Vol versus Iol on all I/O port at T=25°C
Figure 38. Vol versus Iol for High sink (20mA) I/Oports at T=25°C
010203040
0
2
4
6
8
Iol (mA)
Vol (V)
T = -40°C
T = 25°C
T = 95°C
T = 125°C
This curves represents typical variations and is given for guidance only
0 10203040
0
2
4
6
8
I ol (mA)
Vol (V)
Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V
This curves represents typical variations and is given for guidance only
0 10203040
0
1
2
3
4
5
Iol (mA)
Vo l (V)
Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V
This curves represents typical variations and is given for guidance only
56
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ST62T00C/T01C ST62T0 3C/E 01C
Figure 39. Vol versus Iol for High sink (20mA) I/O ports at Vdd=5V
Figure 40. Voh versus Ioh on all I/O port at 25°C
Figure 41. Voh versus Ioh on all I/O port at Vdd=5V
0 10203040
0
1
2
3
4
5
Iol (mA)
Vol (V)
T = -40°C
T = 25°C
T = 95°C
T = 125°C
This curves represents typical variations and is given for guidance only
0 10203040
-2
0
2
4
6
Ioh (mA)
Voh (V)
Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V
This curves represents typical variations and is given for guidance only
0 10203040
-2
0
2
4
6
Ioh (mA)
Voh (V)
T = -40°C
T = 25°C
T = 95°C
T = 125°C
This curves represents typical variations and is given for guidance only
57
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ST62T00C/T01C ST62T03C/E01C
7 GENERAL INFORMATION
7.1 PACKAGE MECHANICAL DATA
Figure 42. 16-Pin Plastic Dual In Line Package (B), 300-mil Width
Figure 43. 16-Pin Ceramic Side-Brazed Dual In-Line Package
Dim. mm inches
Min Typ Max Min Typ Max
A5.33 0.210
A1 0.38 0.015
A2 2.92 3.30 4.95 0.115 0.130 0.195
b0.36 0.56 0.014 0.022
b2 1.52 1.78 0.060 0.070
c0.20 0.25 0.36 0.008 0.010 0.014
D18.67 19.18 19.69 0.735 0.755 0.775
e2.54 0.100
E1 6.10 6.35 7.11 0.240 0.250 0.280
L2.92 3.30 3.81 0.115 0.130 0.150
Number of Pins
N16
PDIP16
Dim. mm inches
Min Typ Max Min Typ Max
A3.78 0.149
A1 0.38 0.015
B0.36 0.46 0.56 0.014 0.018 0.022
B1 1.14 1.37 1.78 0.045 0.054 0.070
C0.20 0.25 0.36 0.008 0.010 0.014
D19.86 20.32 20.78 0.782 0.800 0.818
D1 17.78 0.700
E1 7.04 7.49 7.95 0.277 0.295 0.313
e2.54 0.100
G6.35 6.60 6.86 0.250 0.260 0.270
G1 9.47 9.73 9.98 0.373 0.383 0.393
G2 1.02 0.040
L2.92 3.30 3.81 0.115 0.130 0.150
S1.27 0.050
Ø4.22 0.166
Number of Pins
N16
CDIP16W
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ST62T00C/T01C ST62T0 3C/E 01C
PACKAGE MECHANICAL DATA (Cont ’ d )
Figure 44. 16-Pin Plastic Small Outline Package (M), 300-mil Width
Figure 1. 16-Pin Plastic Shrink Small Outline Package, 0.209” Width
Dim. mm inches
Min Typ Max Min Typ Max
A2.35 2.65 0.0926 0.1043
A1 0.10 0.0040
B0.33 0.51 0.013 0.020
C0.32 0.0125
D10.10 10.50 0.3977 0.4133
E7.40 7.60 0.2914 0.2992
e1.27 0.050
H10.01 10.64 0.394 0.419
h0.25 0.74 0.010 0.029
K0° 8° 0° 8°
L0.41 1.27 0.016 0.050
G0.10 0.004
Number of Pins
N16
SO16
Dim. mm inches
Min Typ Max Min Typ Max
A1.73 1.86 1.99 0.068 0.073 0.078
A1 0.05 0.13 0.21 0.002 0.005 0.008
B0.25 0.38 0.010 0.015
C0.09 0.20 0.004 0.008
D6.07 6.20 6.33 0.239 0.244 0.249
E7.65 7.80 7.90 0.301 0.307 0.311
E1 5.20 5.30 5.38 0.205 0.209 0.212
e0.65 0.026
G0.076 0.003
K0° 4° 8° 0° 4° 8°
L0.63 0.75 0.95 0.025 0.030 0.037
Number of Pins
N16
SSOP16
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ST62T00C/T01C ST62T03C/E01C
7.2 ORDERING INFORMATION
Table 18. OTP/EPROM VERSION ORDERING INFORMATION
Sales Type I/O Program
Memory (Bytes) Analog
input Temperature Range Package
ST62T00CB6
9
1036 (OTP )
4-40 to + 85°C
PDIP16
ST62T00CM6 PSO16
ST62T01CB6 1836 (O TP ) PDIP16
ST62T01CM6 PSO16
ST62T01CN6 SSOP16
ST62T03CB6 1036 (O TP ) None PDIP16
ST62T03CM6 PSO16
ST62T01CB3 1836 (OTP) -40 to +125°C PDIP16
ST62T01CM3 PSO16
ST62T01CN3 SSOP16
ST62E01CF1 1836(EPROM) 4 0 to +70°C CDIP16W
60
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Rev. 2.8
ST62P00C/P01C/P03C
8-BIT FASTROM MCUs WITH A/D CONVERTER,
OSCILLATOR SAFEGUA RD , SAFE RESET AND 16 PINS
■3.0 to 6.0V Supply Operating Range
■8 MHz Maximum Clock Frequency
■-40 to +125°C Operating Temperature Range
■Run, Wait and Stop Modes
■5 Interrupt Vectors
■Look-up Table capability in Program Memory
■Data Storage in Program Memory:
User selectable size
■Data RAM: 64bytes
■9 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input (except ST62P03C)
■3 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
■8-bit Timer/Counter with 7-bit programmable
prescaler
■Digital Watchdog
■Oscillator Safe Guard
■Low Voltage Detector for Safe Reset
■8-bit A/D Converter with up to 4 analog inputs
■On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
■Power-on Reset
■One external Non-Maskable Interrupt
■ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
(See end of Datasheet for Ordering Information)
PDIP16
PSO16
SSOP16
DEVICE ROM
(Bytes) I/O Pins Analog
inputs
ST62P00C 1036 9 4
ST62P01C 1836 9 4
ST62P03C 1036 9 None
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ST62P00C/P01C/P03C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62P00C/P01C & P03C are the Factory Ad-
vanced Service Technique ROM (FASTROM) ver-
sions of ST62T00C,T01C and T03C OTP devices.
They offer the same functionality as OTP devices,
selecting as FASTROM options the options de-
fined in the p rogramm ab le optio n byte of the O TP
version.
1.2 ORDERING INFORMATI ON
The fol lowing s ec tio n d eal s wi th the pr oc ed ure for
transfer of customer codes to STMicroelectronics.
1.2.1 Transfer of Customer Code
Customer code is made up of the ROM contents
and the list of the selected FASTROM options.
The ROM contents are to be sent on diskette, or
by electronic means, with the hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.
The selec ted options are c ommunicated to STMi-
croelectronics using the correctly filled OPTION
LIST appende d.
1.2.2 Listing Generation and Verification
When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
from it. This listing refe rs exac tly to the ROM co n-
tents and options which will be used to produce
the specified MCU. The listing is then returned to
the customer who must thoroughly check, com-
plete, sign and return it to STMicroelectronics. The
signed listing forms a part of the contractual agree-
ment for the production of the specific customer
MCU.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractu al points .
Table 1. ROM Memory Map for ST62P00C,P03C
Table 2. ROM Memory Map for ST62P01C
Table 3. FASTROM version Ordering Information
(*) Advanced information
Device Address Description
0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Device Address Description
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Sales Type ROM Analog inputs Temperature Range Package
ST62P00CB1/XXX
ST62P00CB6/XXX
ST62P00CB3/XXX (*) 1036 Bytes
4
0 to +70°C
-40 to + 85°C
-40 to + 125°C PDIP16
ST62P00CM1/XXX
ST62P00CM6/XXX
ST62P00CM3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°C PSO16
ST62P01CB1/XXX
ST62P01CB6/XXX
ST62P01CB3/XXX (*)
1836 Bytes
0 to +70°C
-40 to + 85°C
-40 to + 125°C PDIP16
ST62P01CM1/XXX
ST62P01CM6/XXX
ST62P01CM3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°C PSO16
ST62P01CN1/XXX
ST62P01CN6/XXX
ST62P01CN3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°C SSOP16
ST62P03CB1/XXX
ST62P03CB6/XXX
ST62P03CB3/XXX (*) 1036 Bytes None
0 to +70°C
-40 to + 85°C
-40 to + 125°C PDIP16
ST62P03CM1/XXX
ST62P03CM6/XXX
ST62P03CM3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°C PSO16
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ST62P00C/P01C/P03C
ST62P00C/P01C/P03C FASTROM MICROCONTROLLER OPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device: [ ] ST62P00C [ ] ST62P01C [ ] ST62P03C
Package: [ ] Dual in Line Plastic
[ ] Small Outline Plastic with conditionning:
[ ] Standard (Stick)
[ ] Tape & Reel
[ ] Shrink Small Outline Plastic
Temperature Range: [ ] 0°C to + 70°C [ ] - 40°C to + 85°C [ ] - 40°C to + 125°C
Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator
[ ] RC Network
Watchdog Selection: [ ] Software Activation
[ ] Hardware Activation
Readout Protection: [ ] Disabled
[ ] Enabled
External STOP Mode Control[ ] Enabled [ ] Disabled
LVD Reset [ ] Enabled [ ] Disabled
NMI pin pull-up [ ] Enabled [ ] Disabled
OSG [ ] Enabled [ ] Disabled
Comments :
Supply Operating Range in the application:
Oscillator Fequency in the application:
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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ST62P00C/P01C/P03C
Notes:
64
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Rev. 2.8
ST6200C/01C/03C
8-BIT ROM MCUs WITH A/D CONVERTER,
OSCILLATOR SAFEGUA RD , SAFE RESET AND 16 PINS
■3.0 to 6.0V Supply Operating Range
■8 MHz Maximum Clock Frequency
■-40 to +125°C Operating Temperature Range
■Run, Wait and Stop Modes
■5 Interrupt Vectors
■Look-up Table capability in Program Memory
■Data Storage in Program Memory:
User selectable size
■Data RAM: 64bytes
■9 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input (except ST6203C)
■3 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
■8-bit Timer/Counter with 7-bit programmable
prescaler
■Digital Watchdog
■Oscillator Safe Guard
■Low Voltage Detector for Safe Reset
■8-bit A/D Converter with up to 4 analog inputs
■On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
■Power-on Reset
■One external Non-Maskable Interrupt
■ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
(See end of Datasheet for Ordering Information)
PDIP16
PSO16
SSOP16
DEVICE ROM
(Bytes) I/O Pins Analog
inputs
ST6200C 1036 9 4
ST6201C 1836 9 4
ST6203C 1036 9 None
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ST6200C/01C/03C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST6200C/01C and 03C are mask pro-
grammed ROM version of ST62T00C,T01C and
T03C OTP devices.
They offer the same functionality as OTP devices,
selecting as ROM options the options defined in
the programmable option byte of the OTP version.
Figure 1. Programming wave form
1.2 ROM READOUT PROTECTION
If the ROM READOUT PROTECTION option is
selected, a protection fuse can be blown to pre-
vent any access to the program memory content.
In case the user wants to blow this fuse, high volt-
age must be applied on the TEST pin.
Figure 2. Programming Ci rcuit
Note: ZPD15 is used for overvoltage protection
0.5s min
TEST
15
14V typ
10
5
TEST
100mA
4mA typ
VR02001
max
150 µs typ
t
VR02003
TEST
5V
100nF
47mF
PROTECT
100nF
VDD
VSS
ZPD15
15V
14V
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ST6200C/01C/03C
ST6200C/01C/03C MICROCONTROLLER OPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device: [ ] ST6200C [ ] ST6201C [ ] ST6203C
Package: [ ] Dual in Line Plastic
[ ] Small Outline Plastic with conditionning:
[ ] Standard (Stick)
[ ] Tape & Reel
[ ] Shrink Small Outline Plastic
Temperature Range: [ ] 0°C to + 70°C [ ] - 40°C to + 85°C [ ] - 40°C to + 125°C
Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ _ "
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Maximum character count: DIP16: 9
SO16: 6
Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator
[ ] RC Network
Watchdog Selection: [ ] Software Activation
[ ] Hardware Activation
ROM Readout Protection: [ ] Disabled (Fuse cannot be blown)
[ ] Enabled (Fuse can be blown by the customer)
Note: No part is delivered with protected ROM.
The fuse must be blown for protection to be effective.
External STOP Mode Control[ ] Enabled [ ] Disabled
LVD Reset [ ] Enabled [ ] Disabled
NMI pin pull-up [ ] Enabled [ ] Disabled
OSG [ ] Enabled [ ] Disabled
Comments :
Supply Operating Range in the application:
Oscillator Fequency in the application:
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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ST6200C/01C/03C
1.3 ORDERING INFORMATI ON
The fol lowing s ec tio n d eal s wi th the pr oc ed ure for
transfer of customer codes to STMicroelectronics.
1.3.1 Transfer of Customer Code
Customer code is made up of the ROM contents
and the list of the selected mask options. The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file gener-
ated by the development tool. All unused bytes
must be set to FFh.
The selected mask options are communicated to
STMicroelectronics using the correctly filled OP-
TION LIST appended.
1.3.2 Listing Generation and Verification
When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
from it. This listing refers exactly to the mask which
will be used to produce the specified MCU. The
listing is then returned to the customer who must
thoroughly check, complete, sign and return it to
STMicroelectronics. The signed listing forms a
part of the contractual agreement for the creation
of the specific customer mask.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractu al points .
Table 4. ROM Memory Map for ST6200C,03C
Table 5. ROM Memory Map for ST6201C
Device Address Description
0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Device Address Description
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
68
69/70
ST6200C/01C/03C
ORDERING INFORMATION (Cont’d)
Table 6. ROM version Ordering Information
Sales Type ROM Analog inputs Temperature Range Package
ST6200CB1/XXX
ST6200CB6/XXX
ST6200CB3/XXX 1036 Bytes
4
0 to +70°C
-40 to + 85°C
-40 to + 125°C PDIP16
ST6200CM1/XXX
ST6200CM6/XXX
ST6200CM3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C PSO16
ST6201CB1/XXX
ST6201CB6/XXX
ST6201CB3/XXX
1836 Bytes
0 to +70°C
-40 to + 85°C
-40 to + 125°C PDIP16
ST6201CM1/XXX
ST6201CM6/XXX
ST6201CM3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C PSO16
ST6201CN1/XXX
ST6201CN6/XXX
ST6201CN3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C SSOP16
ST6203CB1/XXX
ST6203CB6/XXX
ST6203CB3/XXX 1036 Bytes None
0 to +70°C
-40 to + 85°C
-40 to + 125°C PDIP16
ST6203CM1/XXX
ST6203CM6/XXX
ST6203CM3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C PSO16
69
70/70
ST6200C/01C/03C
Notes:
Information f urnished is believed to be accurat e and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such inf ormation nor for any infri ngement of patents or other rights of third parties whic h may result f rom its use. No license is grant ed
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to ch ange without notice. This publicat ion supersedes and replaces all information previously supplied. STMicroelectr onics products are not
authorized for use as criti cal components in life su pport devices or systems witho ut the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics - All Rights Reserved.
Purchas e of I2C Components by STMicroelectronics conveys a lic ense under the Philips I2C Patent. Rights to use t hese components in an
I2C system is granted provided that the system c onforms to the I2C Standard Specification as defined by Philips.
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