- 1 -
K4B1G1646I
Rev. 1.1, Mar. 2016
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1Gb I-die DDR3L SDRAM x16 only
96FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
1.35V
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K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
Revision History
Revision No. History Draft Date Remark Editor
1.0 - First Spec. Release 16th Feb. 2016 - J.Y. Lee
1.1 - Change of IDD5B on page 41 29th Mar. 2016 - J.Y. Lee
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K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
Table Of Contents
1Gb I-die DDR3L SDRAM x16 only
1. Ordering Information ..................................................................................................................................................... 5
2. Key Features................................................................................................................................................................. 5
3. Package pinout/Mechanical Dimension & Addressing.................................................................................................. 6
3.1 x16 Package Pinout (Top view) : 96ball FBGA Package ........................................................................................ 6
3.2 FBGA Package Dimension (x16)............................................................................................................................. 7
4. Input/Output Functional Description.............................................................................................................................. 8
5. DDR3 SDRAM Addressing ........................................................................................................................................... 9
6. Absolute Maximum Ratings .......................................................................................................................................... 10
6.1 Absolute Maximum DC Ratings............................................................................................................................... 10
6.2 DRAM Component Operating Temperature Range ................................................................................................ 10
7. AC & DC Operating Conditions..................................................................................................................................... 10
7.1 Recommended DC operating Conditions ................................................................................................................ 10
8. AC & DC Input Measurement Levels ............................................................................................................................ 11
8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 11
8.2 VREF Tolerances .................................................................................................................................................... 13
8.3 AC & DC Logic Input Levels for Differential Signals................................................................................................ 14
8.3.1. Differential signals definition ............................................................................................................................ 14
8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .................................................. 14
8.3.3. Single-ended requirements for differential signals ........................................................................................... 15
8.4 Differential Input Cross Point Voltage...................................................................................................................... 17
8.5 Slew rate definition for Differential Input Signals ..................................................................................................... 17
8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 18
9. AC & DC Output Measurement Levels ......................................................................................................................... 18
9.1 Single-ended AC & DC Output Levels..................................................................................................................... 18
9.2 Differential AC & DC Output Levels......................................................................................................................... 18
9.3 Single-ended Output Slew Rate .............................................................................................................................. 19
9.4 Differential Output Slew Rate .................................................................................................................................. 20
9.5 Reference Load for AC Timing and Output Slew Rate ............................................................................................ 20
9.6 Overshoot/Undershoot Specification ....................................................................................................................... 21
9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 21
9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 22
9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 23
9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 25
9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 25
9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 26
9.8.2. ODT Temperature and Voltage sensitivity ....................................................................................................... 28
9.9 ODT Timing Definitions ........................................................................................................................................... 29
9.9.1. Test Load for ODT Timings.............................................................................................................................. 29
9.9.2. ODT Timing Definitions .................................................................................................................................... 29
10. IDD Current Measure Method..................................................................................................................................... 32
10.1 IDD Measurement Conditions ............................................................................................................................... 32
11. 1Gb DDR3 SDRAM I-die IDD Specification Table ...................................................................................................... 41
12. Input/Output Capacitance ........................................................................................................................................... 42
13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1866 ...................................................................... 43
13.1 Clock Specification ................................................................................................................................................ 43
13.1.1. Definition for tCK(avg).................................................................................................................................... 43
13.1.2. Definition for tCK(abs).................................................................................................................................... 43
13.1.3. Definition for tCH(avg) and tCL(avg).............................................................................................................. 43
13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 43
13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 43
13.1.6. Definition for tERR(nper)................................................................................................................................ 43
13.2 Refresh Parameters by Device Density................................................................................................................. 44
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 44
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K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
13.3.1. Speed Bin Table Notes .................................................................................................................................. 48
14. Timing Parameters by Speed Grade .......................................................................................................................... 49
14.1 Jitter Notes ............................................................................................................................................................ 53
14.2 Timing Parameter Notes........................................................................................................................................ 54
14.3 Address/Command Setup, Hold and Derating : .................................................................................................... 55
14.4 Data Setup, Hold and Slew Rate Derating : .......................................................................................................... 64
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K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
1. Ordering Information
[ Table 1 ] Samsung 1Gb DDR3L I-die ordering information table
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. 13th digit stands for below.
"Y" : Commercial temp
"M" : Industrial temp
3. Backward compatible to DDR3L-1600(11-11-11), DDR3L-1333(9-9-9)
2. Key Features
[ Table 2 ] 1Gb DDR3 I-die Speed bins
Organization DDR3L-1600 (11-11-11) DDR3L-1866 (14-14-14)3Package
64Mx16 K4B1G1646I-BYK0 K4B1G1646I-BYMA 96FBGA
64Mx16 K4B1G1646I-BMK0 K4B1G1646I-BMMA 96FBGA
Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Unit
6-6-6 7-7-7 9-9-9 11-11-11 13-13-13
tCK(min) 2.5 1.875 1.5 1.25 1.071 ns
CAS Latency 6 7 9 11 13 nCK
tRCD(min) 15 13.125 13.5 13.75 13.91 ns
tRP(min) 15 13.125 13.5 13.75 13.91 ns
tRAS(min) 37.5 37.5 36 35 34 ns
tRC(min) 52.5 50.625 49.5 48.75 47.91 ns
• JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
•V
DDQ = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin,
667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin,
• 933MHz fCK for 1866Mb/sec/pin
• 8 Banks
• Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,12,13
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9(DDR3-1866)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at
85C < TCASE < 95 C
• Asynchronous Reset
• Support Industrial Temp ( -40~95C)
- tREFI 7.8us at -40C < TCASE < 85C
- tREFI 3.9us at 85C < TCASE < 95C
• Package : 96 balls FBGA - x16
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
The 1Gb DDR3 SDRAM I-die is organized as a 8Mbit x 16 I/Os x 8banks
device. This synchronous device achieves high speed double-data-rate
transfer rates of up to 1866Mb/sec/pin(DDR3-1866)for general applications.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V) power supply
and 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V) VDDQ.
The 1Gb DDR3 I-die device is available in 96ball FBGA(x16).
NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing
Diagram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
3. Package pinout/Mechanical Dimension & Addressing
3.1 x16 Package Pinout (Top view) : 96ball FBGA Package
1 2 3 4 5 6 7 8 9
AVDDQ DQU5 DQU7 DQU4 VDDQ VSS A
BVSSQ VDD VSS DQSU DQU6 VSSQ B
CVDDQ DQU3 DQU1 DQSU DQU2 VDDQ C
DVSSQ VDDQ DMU DQU0 VSSQ VDD D
EVSS VSSQ DQL0 DML VSSQ VDDQ E
FVDDQ DQL2 DQSL DQL1 DQL3 VSSQ F
GVSSQ DQL6 DQSL VDD VSS VSSQ G
HVREFDQ VDDQ DQL4 DQL7 DQL5 VDDQ H
JNC VSS RAS CK VSS NC J
KODT VDD CAS CK VDD CKE K
LNC CS WE A10/AP ZQ NC L
MVSS BA0 BA2 NC VREFCA VSS M
NVDD A3 A0 A12/BC BA1 VDD N
PVSS A5 A2 A1 A4 VSS P
RVDD A7 A9 A11 A6 VDD R
TVSS RESET NC NC A8 VSS T
Populated ball
Ball not populated
Ball Locations (x16)
Top view
(See the balls through the package)
1234 89567
A
B
C
D
E
F
G
H
J
K
L
N
M
P
R
T
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K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
3.2 FBGA Package Dimension (x16)
A
B
C
D
E
F
G
H
J
L
M
N
P
R
T
7.50 ± 0.10
3.20
0.80
6.00
(Datum B)
(Datum A)
0.10MAX
0.9 0.1
#A1
87654329
1.60
7.50 ± 0.10
13.30 ± 0.10
0.37 0.05
#A1 INDEX MARK
TOP VIEW
13.30 ± 0.10
K
0.80 x15 = 12.00
B
A
0.80 0.40
96 - 0.48 Solder ball
0.2 ABM
MOLDING AREA
(Post Reflow 0.50 0.05) (0.30)
(0.60)
BOTTOM VIEW
Units : Millimeters
1
0.80 x 8 6.40
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K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
4. Input/Output Functional Description
[ Table 3 ] Input/Output function description
Symbol Type Function
CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of
the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
CKE Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and
output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or
Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become
stable during the power on and initialization sequence, it must be maintained during all operations (including Self-
Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT
and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh.
CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on
systems with multiple Ranks. CS is considered part of the command code.
ODT Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When
enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode
Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is pro-
grammed to disable ODT.
RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM
(DMU), (DML) Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-
dent with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of
DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1.
BA0 - BA2 Input
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being
applied. Bank address also determines if the mode register or extended mode register is to be accessed during a
MRS cycle.
A0 - A12 Input
Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands
to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions,
see below)
The address inputs also provide the op-code during Mode Register Set commands.
A10 / AP Input
Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be per-
formed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge)
A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or
all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses.
A12 / BC Input Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be per-
formed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details
RESET Input
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH.
RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and
20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low.
DQ Input/Output Data Input/ Output: Bi-directional data bus.
DQS, (DQS) Input/Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the
x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data
strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide dif-
ferential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and
does not support single-ended.
TDQS, (TDQS)Output
Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When
disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/
x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1.
NC No Connect: No internal electrical connection is present.
VDDQ Supply DQ Power Supply: 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V)
VSSQ Supply DQ Ground
VDD Supply Power Supply: 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V)
VSS Supply Ground
VREFDQ Supply Reference voltage for DQ
VREFCA Supply Reference voltage for CA
ZQ Supply Reference Pin for ZQ calibration
NOTE : Input only pins (BA0-BA2, A0-A12, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination.
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K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
5. DDR3 SDRAM Addressing
1Gb
2Gb
4Gb
8Gb
NOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered.
Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG8
where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
Configuration 256Mb x 4 128Mb x 8 64Mb x 16
# of Bank 8 8 8
Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2
Auto precharge A10/AP A10/AP A10/AP
Row Address A0 - A13 A0 - A13 A0 - A12
Column Address A0 - A9,A11 A0 - A9 A0 - A9
BC switch on the fly A12/BC A12/BC A12/BC
Page size *1 1 KB 1 KB 2 KB
Configuration 512Mb x 4 256Mb x 8 128Mb x 16
# of Bank 8 8 8
Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2
Auto precharge A10/AP A10/AP A10/AP
Row Address A0 - A14 A0 - A14 A0 - A13
Column Address A0 - A9,A11 A0 - A9 A0 - A9
BC switch on the fly A12/BC A12/BC A12/BC
Page size *1 1 KB 1 KB 2 KB
Configuration 1Gb x 4 512Mb x 8 256Mb x 16
# of Bank 8 8 8
Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2
Auto precharge A10/AP A10/AP A10/AP
Row Address A0 - A15 A0 - A15 A0 - A14
Column Address A0 - A9,A11 A0 - A9 A0 - A9
BC switch on the fly A12/BC A12/BC A12/BC
Page size *1 1 KB 1 KB 2 KB
Configuration 2Gb x 4 1Gb x 8 512Mb x 16
# of Bank 8 8 8
Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2
Auto precharge A10/AP A10/AP A10/AP
Row Address A0 - A15 A0 - A15 A0 - A15
Column Address A0 - A9,A11,A13 A0 - A9,A11 A0 - A9
BC switch on the fly A12/BC A12/BC A12/BC
Page size *1 2 KB 2 KB 2 KB
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K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
6. Absolute Maximum Ratings
6.1 Absolute Maximum DC Ratings
[ Table 4 ] Absolute Maximum DC Ratings
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be
equal to or less than 300mV.
6.2 DRAM Component Operating Temperature Range
[ Table 5 ] Temperature Range
NOTE :
1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document
JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-
tained between 0-85C under all operating conditions
3. The Industrial Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-
tained between -40-85C under all operating conditions
4. Some applications require operation of the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the Manual Self-Refresh mode with Extended Temperature Range
capability (MR2 A6 = 0b and MR2 A7 = 1b).
7. AC & DC Operating Conditions
7.1 Recommended DC operating Conditions
[ Table 6 ] Recommended DC Operating Conditions
NOTE :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. VDD & VDDQ rating are determined by operation voltage.
Symbol Parameter Rating Units NOTE
VDD Voltage on VDD pin relative to Vss -0.4 V ~ 1.80 V V 1,3
VDDQ Voltage on VDDQ pin relative to Vss -0.4 V ~ 1.80 V V 1,3
VIN, VOUT Voltage on any pin relative to Vss -0.4 V ~ 1.80 V V 1
TSTG Storage Temperature -55 to +100 C 1, 2
Symbol Parameter rating Unit NOTE
TOPER Operating Temperature Range Normal 0 to 95 C 1, 2, 4
Industrial -40 to 95 C 1, 3, 4
Symbol Parameter Operation Voltage Rating Units NOTE
Min. Typ. Max.
VDD Supply Voltage 1.35V 1.283 1.35 1.45 V 1, 2, 3
1.5V 1.425 1.5 1.575 V 1, 2, 3
VDDQ Supply Voltage for Output 1.35V 1.283 1.35 1.45 V 1, 2, 3
1.5V 1.425 1.5 1.575 V 1, 2, 3
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K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
8. AC & DC Input Measurement Levels
8.1 AC & DC Logic input levels for single-ended signals
[ Table 7 ] Single-ended AC & DC input levels for Command and Address (1.35V)
NOTE : 1. For input only pins except RESET, VREF = VREFCA(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V , the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIHL.CA(AC150),
VIH/L.CA(AC135), VIH/L.CA(AC125)etc.) apply. The 1.5 V levels (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIHL.CA(AC125)etc.) do not
apply when the device is operated in the 1.35 voltage range.
[ Table 8 ] Single-ended AC & DC input levels for Command and Address(1.5V)
NOTE : 1. For input only pins except RESET, VREF = VREFCA(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125); VIH.CA(AC175) value is used when Vref + 0.175V is
referenced, VIH.CA(AC150) value is used when Vref + 0.150V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is referenced, and VIH.CA(AC125) value is
used when Vref + 0.125V is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175) value is used when Vref - 0.175V is
referenced, VIL.CA(AC150) value is used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced, and VIL.CA(AC125) value is
used when Vref - 0.125V is referenced.
9. VREFCA(DC) is measured relative to VDD at the same point in time on the same device
Symbol Parameter DDR3L-800/1066/1333/1600 DDR3L-1866 Unit NOTE
Min. Max. Min. Max.
1.35V
VIH.CA(DC90) DC input logic high VREF + 90 VDD VREF + 90 VDD mV 1
VIL.CA(DC90) DC input logic low VSS VREF - 90 VSS VREF - 90 mV 1
VIH.CA(AC160) AC input logic high VREF + 160 Note 2 - - mV 1,2,5
VIL.CA(AC160) AC input logic low Note 2 VREF - 160 --mV1,2,5
VIH.CA(AC135) AC input logic high VREF+135 Note 2 VREF+135 Note 2 mV 1,2,5
VIL.CA(AC135) AC input logic lowM Note 2 VREF-135 Note 2 VREF-135 mV 1,2,5
VIH.CA(AC125) AC input logic high - - VREF + 125 Note 2 mV 1,2,5
VIL.CA(AC125) AC input logic low - - Note 2 VREF + 125 mV 1,2,5
VREFCA(DC) Reference Voltage for ADD,
CMD inputs 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V3,4
Symbol Parameter DDR3-800/1066/1333/1600 DDR3-1866 Unit NOTE
Min. Max. Min. Max.
1.5V
VIH.CA(DC100) DC input logic high VREF + 100 VDD VREF + 100 VDD mV 1,5
VIL.CA(DC100) DC input logic low VSS VREF - 100 VSS VREF - 100 mV 1,6
VIH.CA(AC175) AC input logic high VREF + 175 Note 2 - - mV 1,2,7
VIL.CA(AC175) AC input logic low Note 2 VREF - 175 --mV1,2,8
VIH.CA(AC150) AC input logic high VREF+150 Note 2 - - mV 1,2,7
VIL.CA(AC150) AC input logic low Note 2 VREF-150 --mV1,2,8
VIH.CA(AC135) AC input logic high - - VREF + 135 Note 2 mV 1,2,7
VIL.CA(AC135) AC input logic low - - Note 2 VREF - 135 mV 1,2,8
VIH.CA(AC125) AC input logic high - - VREF+125 Note 2 mV 1,2,7
VIL.CA(AC125) AC input logic low - - Note 2 VREF-125 mV 1,2,8
VREFCA(DC) Reference Voltage for ADD,
CMD inputs 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V 3,4,9
- 12 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 9 ] Single-ended AC & DC input levels for DQ and DM (1.35V)
NOTE :
1. For input only pins except RESET, VREF = VREFDQ(DC)
2.See "Overshoot and Undershoot specifications" section.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV.
5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V, the respective levels in JESD79-3 ( VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/
L.DQ(AC150), VIH/L.DQ(AC135), etc. ) apply. The 1.5 V levels (VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135), etc. ) do not apply when the
device is operated in the 1.35 voltage range.
[ Table 10 ] Single-ended AC & DC input levels for DQ and DM (1.5V)
NOTE :
1. For input only pins except RESET, VREF = VREFDQ(DC)
2.See "Overshoot and Undershoot specifications" section.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135); VIH.DQ(AC175) value is used when Vref + 0.175V is referenced,
VIH.DQ(AC150) value is used when Vref + 0.150V is referenced, and VIH.DQ(AC135) value is used when Vref + 0.135V is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135); VIL.DQ(AC175) value is used when Vref - 0.175V is referenced,
VIL.DQ(AC150) value is used when Vref - 0.150V is referenced, and VIL.DQ(AC135) value is used when Vref - 0.135V is referenced.
9. VREFDQ(DC) is measured relative to VDD at the same point in time on the same device
10. Optional in DDR3 SDRAM for DDR3-800/1066/1333/1600: Users should refer to the DRAM supplier data sheetand/or the DIMM SPD to determine if DDR3 SDRAM devices
support this option.
Symbol Parameter DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866 Unit NOTE
Min. Max. Min. Max. Min. Max.
1.35V
VIH.DQ(DC90) DC input logic high VREF + 90 VDD VREF + 90 VDD VREF + 90 VDD mV 1
VIL.DQ(DC90) DC input logic low VSS VREF - 90 VSS VREF - 90 VSS VREF - 90 mV 1
VIH.DQ(AC160) AC input logic high VREF + 160 Note 2----mV1,2,5
VIL.DQ(AC160) AC input logic low Note 2 VREF - 160 ----mV1,2,5
VIH.DQ(AC135) AC input logic high VREF + 135 Note 2 VREF + 135 Note 2 - - mV 1,2,5
VIL.DQ(AC135) AC input logic low Note 2 VREF - 135 Note 2 VREF - 135 - - mV 1,2,5
VIH.DQ(AC130) AC input logic high ----
VREF + 130 Note 2 mV 1,2,5
VIL.DQ(AC130) AC input logic low ----Note 2
VREF - 130 mV 1,2,5
VREFDQ(DC) Reference Voltage for DQ,
DM inputs 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V3,4
Symbol Parameter DDR3-800/1066 DDR3-1333/1600 DDR3-1866 Unit NOTE
Min. Max. Min. Max. Min. Max.
1.5V
VIH.DQ(DC100) DC input logic high VREF + 100 VDD VREF + 100 VDD VREF + 100 VDD mV 1,5
VIL.DQ(DC100) DC input logic low VSS VREF - 100 VSS VREF - 100 VSS VREF - 100 mV 1,6
VIH.DQ(AC175) AC input logic high VREF + 175 NOTE 2 - - - - mV 1,2,7
VIL.DQ(AC175) AC input logic low NOTE 2 VREF - 175 ----mV1,2,8
VIH.DQ(AC150) AC input logic high VREF + 150 NOTE 2 VREF + 150 NOTE 2 - - mV 1,2,7
VIL.DQ(AC150) AC input logic low NOTE 2 VREF - 150 NOTE 2 VREF - 150 - - mV 1,2,8
VIH.DQ(AC135) AC input logic high VREF + 135 NOTE 2 VREF + 135 NOTE 2 VREF + 135 NOTE 2 mV 1,2,7,10
VIL.DQ(AC135) AC input logic low NOTE 2 VREF - 135 NOTE 2 VREF - 135 NOTE 2 VREF - 135 mV 1,2,8,10
VREFDQ(DC) Reference Voltage for DQ,
DM inputs 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V3,4,9
- 13 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
8.2 VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage
VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7 on
page 11. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF
.
"VREF" shall be understood as VREF(DC), as defined in Figure 1 .
This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing
and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
voltage
VDD
VSS
time
- 14 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
8.3 AC & DC Logic Input Levels for Differential Signals
8.3.1 Differential signals definition
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
[ Table 11 ] Differential AC & DC Input Levels
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group,
then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig-
nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"
Symbol Parameter
DDR3-800/1066/1333/1600/1866
unit NOTE1.35V 1.5V
min max min max
VIHdiff differential input high +0.18 NOTE 3 +0.20 NOTE 3 V 1
VILdiff differential input low NOTE 3 -0.18 NOTE 3 -0.20 V 1
VIHdiff(AC) differential input high ac 2 x (VIH(AC) - VREF)NOTE 3 2 x (VIH(AC) - VREF)NOTE 3 V 2
VILdiff(AC) differential input low ac NOTE 3 2 x (VIL(AC) - VREF)NOTE 3 2 x (VIL(AC) - VREF)V2
0.0
tDVAC
VIH.DIFF.MIN
half cycle
Differential Input Voltage (i.e. DQS-DQS, CK-CK)
time
tDVAC
VIH.DIFF.AC.MIN
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
- 15 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 12 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.35V)
NOTE: Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
[ Table 13 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.5V)
NOTE : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VILdiff(ac)
level.
8.3.3 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for
single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax [approximately equal to the ac-levels { VIH(AC) / VIL(AC)} for ADD/CMD signals] in every
half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax [approximately the ac-levels { VIH(AC) / VIL(AC)} for DQ signals] in every half-cycle
proceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD sig-
nals, then these ac-levels apply also for the single-ended signals CK and CK .
Slew Rate [V/ns]
DDR3L-800/1066/1333/1600 DDR3L-1866
tDVAC [ps] @ |VIH/
Ldiff(AC)| = 320mV
tDVAC [ps] @ |VIH/
Ldiff(AC)| = 270mV
tDVAC [ps]
@ |VIH/Ldiff(ac)|
=270mV
tDVAC [ps]
@ |VIH/Ldiff(ac)|
=250mV
tDVAC [ps]
@ |VIH/Ldiff(ac)|
=260mV
min max min max min max min max min max
> 4.0 189 - 201 - 163 - 168 - 176 -
4.0 189 - 201 - 163 - 168 - 176 -
3.0 162 - 179 - 140 - 147 - 154 -
2.0 109 - 134 - 95 - 105 - 111 -
1.8 91 - 119 - 80 - 91 - 97 -
1.6 69 - 100 - 62 - 74 - 78 -
1.4 40 - 76 - 37 - 52 - 56 -
1.2 note - 44 - 5 - 22 - 24 -
1.0 note - note - note - note - note -
< 1.0 note - note - note - note - note -
Slew Rate [V/ns]
DDR3-800/1066/1333/1600 DDR3-1866
tDVAC [ps]
@ VIH/Ldiff(AC)= 350mV
tDVAC [ps]
@ VIH/Ldiff(AC)= 300mV
tDVAC [ ps ]
@ VIH/L diff(ac)
=270mv
(DQS - DQS#) only
(Optional)
tDVAC [ps]
@ VIH/Ldiff(AC)
= 270mV
tDVAC [ps]
@ VIH/Ldiff(AC)
=250mV(CK - CK#) only
min max min max min max min max min max
> 4.0 75 - 175 - 214 - 134 - 139 -
4.0 57 - 170 - 214 - 134 - 139 -
3.0 50 - 167 - 191 - 112 - 118 -
2.0 38 - 119 - 146 - 67 - 77 -
1.8 34 - 102 - 131 - 52 - 63 -
1.6 29 - 81 - 113 - 33 - 45 -
1.4 22-54-88- 9 -23-
1.2 note - 19 - 56 - note - note -
1.0 note - note - 11 - note - note -
< 1.0 note - note - note - note - note -
- 16 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
Figure 3. Single-ended requirement for differential signals
Note that while ADD/CMD and DQ signal requirements are with respect to VREF
, the single-ended components of differential signals have a requirement
with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common
mode characteristics of these signals.
[ Table 14 ] Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU
NOTE :
1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs.
2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the
reduced level applies also here
3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max,
VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"
Symbol Parameter DDR3-800/1066/1333/1600/1866 Unit NOTE
Min Max
VSEH
Single-ended high-level for strobes (VDD/2)+0.175 NOTE3 V 1, 2
Single-ended high-level for CK, CK (VDD/2)+0.175 NOTE3 V 1, 2
VSEL
Single-ended low-level for strobes NOTE3 (VDD/2)-0.175 V1, 2
Single-ended low-level for CK, CK NOTE3 (VDD/2)-0.175 V1, 2
VDD or VDDQ
VSEH min
VDD/2 or VDDQ/2
VSEL max
VSEH
VSS or VSSQ
VSEL
CK or DQS
time
- 17 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
8.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signal to the mid level between of VDD and VSS.
Figure 4. VIX Definition
[ Table 15 ] Cross point voltage for differential input signals (CK, DQS) : 1.35V
NOTE :
1. The relationbetween Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix(Min) - VSEL 25mV
VSEH - ((VDD/2) + Vix(Max)) 25mV
[ Table 16 ] Cross point voltage for differential input signals (CK, DQS) : 1.5V
NOTE :
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing VSEL / VSEH of at least VDD/2
±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.
8.5 Slew rate definition for Differential Input Signals
See 14.3 “Address/Command Setup, Hold and Derating :” on page 50 for single-ended slew rate definitions for address and command signals.
See 14.4 “Data Setup, Hold and Slew Rate Derating :” on page 56 for single-ended slew rate definitions for data signals.
Symbol Parameter DDR3L-800/1066/1333/1600/1866 Unit NOTE
Min Max
VIX Differential Input Cross Point Voltage relative to VDD/2 for CK,CK -150 150 mV 1
VIX Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS -150 150 mV
Symbol Parameter DDR3-800/1066/1333/1600/1866 Unit NOTE
Min Max
VIX Differential Input Cross Point Voltage relative to VDD/2 for CK,CK -150 150 mV
-175 175 mV 1
VIX Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS -150 150 mV
VDD
CK, DQS
VDD/2
CK, DQS
VSS
VIX
VIX
VIX
- 18 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
8.6 Slew rate definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table 17 and Figure 5.
[ Table 17 ] Differential input slew rate definition
NOTE :
The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds.
Figure 5. Differential Input Slew Rate definition for DQS, DQS, and CK, CK
9. AC & DC Output Measurement Levels
9.1 Single-ended AC & DC Output Levels
[ Table 18 ] Single-ended AC & DC output levels
NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test
load of 25 to VTT=VDDQ/2.
9.2 Differential AC & DC Output Levels
[ Table 19 ] Differential AC & DC output levels
NOTE : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test
load of 25 to VTT=VDDQ/2 at each of the differential outputs.
Description Measured Defined by
From To
Differential input slew rate for rising edge (CK-CK and DQS-DQS)VILdiffmax VIHdiffmin [VIHdiffmin - VILdiffmax] / Delta TRdiff
Differential input slew rate for falling edge (CK-CK and DQS-DQS)VIHdiffmin VILdiffmax [VIHdiffmin - VILdiffmax] / Delta TFdiff
Symbol Parameter DDR3-800/1066/1333/1600/1866 Units NOTE
VOH(DC) DC output high measurement level (for IV curve linearity) 0.8 x VDDQ V
VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5 x VDDQ V
VOL(DC) DC output low measurement level (for IV curve linearity) 0.2 x VDDQ V
VOH(AC) AC output high measurement level (for output SR) VTT + 0.1 x VDDQ V1
VOL(AC) AC output low measurement level (for output SR) VTT - 0.1 x VDDQ V1
Symbol Parameter DDR3-800/1066/1333/1600/1866 Units NOTE
VOHdiff(AC) AC differential output high measurement level (for output SR) +0.2 x VDDQ V1
VOLdiff(AC) AC differential output low measurement level (for output SR) -0.2 x VDDQ V1
VIHdiffmin
0
VILdiffmax
delta TRdiff
delta TFdiff
- 19 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
9.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in Table 20 and Figure 6.
[ Table 20 ] Single-ended output slew rate definition
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 21 ] Single-ended output slew rate
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ signals in
the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining
DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
Figure 6. Single-ended Output Slew Rate Definition
Description Measured Defined by
From To
Single ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / Delta TRse
Single ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / Delta TFse
Parameter Symbol Operation
Voltage
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Units
Min Max Min Max Min Max Min Max Min Max
Single ended output slew rate SRQse 1.35V 1.75 51) 1.75 51) 1.75 51) 1.75 51) 1.75 51) V/ns
1.5V 2.552.552.552.552.55V/ns
VOH(AC)
VOL(AC)
delta TRsedelta TFse
VTT
- 20 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
9.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and
VOHdiff(AC) for differential signals as shown in Table 22 and Figure 7.
[ Table 22 ] Differential output slew rate definition
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 23 ] Differential output slew rate
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
diff : Differential Signals
For Ron = RZQ/7 setting
Figure 7. Differential Output Slew Rate Definition
9.5 Reference Load for AC Timing and Output Slew Rate
Figure 8 represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate
measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. Sys-
tem designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their
production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
Figure 8. Reference Load for AC Timing and Output Slew Rate
Description Measured Defined by
From To
Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / Delta TRdiff
Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / Delta TFdiff
Parameter Symbol Operation
Voltage
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Units
Min Max Min Max Min Max Min Max Min Max
Differential output slew rate SRQdiff 1.35V 3.5 12 3.5 12 3.5 12 3.5 12 3.5 12 V/ns
1.5V 510510510510512V/ns
VOHdiff(AC)
VOLdiff(AC)
delta TRdiffdelta TFdiff
VTT
VDDQ
DUT
DQ
DQS
DQS
VTT = VDDQ/2
25
CK/CK
Reference
Point
- 21 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
9.6 Overshoot/Undershoot Specification
9.6.1 Address and Control Overshoot and Undershoot specifications
[ Table 24 ] AC overshoot/undershoot specification for Address and Control pins (A0-A12, BA0-BA2. CS. RAS. CAS. WE. CKE, ODT)
Figure 9. Address and Control Overshoot and Undershoot Definition
Parameter Specification Unit
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866
1.35V
Maximum peak amplitude allowed for overshoot area (See Figure 9) 0.4 0.4 0.4 0.4 0.4 V
Maximum peak amplitude allowed for undershoot area (See Figure 9) 0.4 0.4 0.4 0.4 0.4 V
Maximum overshoot area above VDD (See Figure 9) 0.67 0.5 0.4 0.33 0.28 V-ns
Maximum undershoot area below VSS (See Figure 9) 0.67 0.5 0.4 0.33 0.28 V-ns
1.5V
Maximum peak amplitude allowed for overshoot area (See Figure 9) 0.4 0.4 0.4 0.4 0.4 V
Maximum peak amplitude allowed for undershoot area (See Figure 9) 0.4 0.4 0.4 0.4 0.4 V
Maximum overshoot area above VDD (See Figure 9) 0.67 0.5 0.4 0.33 0.28 V-ns
Maximum undershoot area below VSS (See Figure 9) 0.67 0.5 0.4 0.33 0.28 V-ns
(A0-A15, BA0-BA3, CS#, RAS#, CAS#, WE#, CKE, ODT)
NOTE:
1. The sum of the applied voltage (VDD) and peak amplitude overshoot voltage is not to exceed absolute maximum DC ratings
2. The sum of applied voltage (VDD) and the peak amplitude undershoot voltage is not to exceed absolute maximum DC ratings
Overshoot Area
Maximum Amplitude
VDD
Undershoot Area
Maximum Amplitude
VSS
Volts
(V)
Time (ns)
- 22 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
[ Table 25 ] AC overshoot/undershoot specification for Clock, Data, Strobe and Mask (DQ, DQS, DQS, DM, CK, CK)
Figure 10. Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
Parameter Specification Unit
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866
1.35V
Maximum peak amplitude allowed for overshoot area (See Figure 10) 0.4 0.4 0.4 0.4 0.4 V
Maximum peak amplitude allowed for undershoot area (See Figure 10) 0.4 0.4 0.4 0.4 0.4 V
Maximum overshoot area above VDDQ (See Figure 10) 0.25 0.19 0.15 0.13 0.10 V-ns
Maximum undershoot area below VSSQ (See Figure 10) 0.25 0.19 0.15 0.13 0.10 V-ns
1.5V
Maximum peak amplitude allowed for overshoot area (See Figure 10) 0.4 0.4 0.4 0.4 0.4 V
Maximum peak amplitude allowed for undershoot area (See Figure 10) 0.4 0.4 0.4 0.4 0.4 V
Maximum overshoot area above VDDQ (See Figure 10) 0.25 0.19 0.15 0.13 0.10 V-ns
Maximum undershoot area below VSSQ (See Figure 10) 0.25 0.19 0.15 0.13 0.10 V-ns
(CK, CK#, DQ, DQS, DQS#, DM)
NOTE:
1. The sum of the applied voltage (VDD) and peak amplitude overshoot voltage is not to exceed absolute maximum DC ratings
2. The sum of applied voltage (VDD) and the peak amplitude undershoot voltage is not to exceed absolute maximum DC ratings
Overshoot Area
Maximum Amplitude
VDDQ
Undershoot Area
Maximum Amplitude
VSSQ
Volts
(V)
Time (ns)
- 23 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
9.7 34ohm Output Driver DC Electrical Characteristics
A functional representation of the output buffer is shown below. Output driver impedance RON is defined by the value of external reference resistor RZQ
as follows:
RON34 = RZQ/7 (Nominal 34.3ohms +/- 10% with nominal RZQ=240ohm)
The individual Pull-up and Pull-down resistors (RONpu and RONpd) are defined as follows
Figure 11. Output Driver : Definition of Voltages and Currents
RONpu =
VDDQ-VOUT
l Iout l
under the condition that RONpd is turned off
RONpd =
VOUT
l Iout l
under the condition that RONpu is turned off
VDDQ
DQ
VSSQ
RON
Pu
Ipd
RON
Pd
To
other
circuity
Output Driver
Ipu
Iout
Vout
- 24 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 26 ] Output Driver DC Electrical Characteristics, assuming RZQ=240ohms ;
entire operating temperature range ; after proper ZQ calibration
NOTE :
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibra-
tion, see following section on voltage and temperature sensitivity
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS
3. Pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 X VDDQ. Other calibration schemes may be used to achieve the linearity spec shown
above, e.g. calibration at 0.2 X VDDQ and 0.8 X VDDQ
4. Measurement definition for mismatch between pull-up and pull-down, MMpupd: Measure RONpu and RONpd. both at 0.5 X VDDQ:
RONnom Resistor Vout Min Nom Max Units Notes
1.35V
34Ohms
RON34pd
VOLdc = 0.2 x VDDQ 0.6 1.0 1.15
RZQ/7
1,2,3
VOMdc = 0.5 x VDDQ 0.9 1.0 1.15 1,2,3
VOHdc = 0.8 x VDDQ 0.9 1.0 1.45 1,2,3
RON34pu
VOLdc = 0.2 x VDDQ 0.9 1.0 1.45 1,2,3
VOMdc = 0.5 x VDDQ 0.9 1.0 1.15 1,2,3
VOHdc = 0.8 x VDDQ 0.6 1.0 1.15 1,2,3
40Ohms
RON40pd
VOLdc = 0.2 x VDDQ 0.6 1.0 1.15
RZQ/6
1,2,3
VOMdc = 0.5 x VDDQ 0.9 1.0 1.15 1,2,3
VOHdc = 0.8 x VDDQ 0.9 1.0 1.45 1,2,3
RON40pu
VOLdc = 0.2 x VDDQ 0.9 1.0 1.45 1,2,3
VOMdc = 0.5 x VDDQ 0.9 1.0 1.15 1,2,3
VOHdc = 0.8 x VDDQ 0.6 1.0 1.15 1,2,3
Mismatch between Pull-up and Pull-down,
MMpupd VOMdc = 0.5 x VDDQ -10 10 % 1,2,4
1.5V
34Ohms
RON34pd
VOLdc = 0.2 x VDDQ 0.6 1.0 1.1
RZQ/7
1,2,3
VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 1,2,3
VOHdc = 0.8 x VDDQ 0.9 1.0 1.4 1,2,3
RON34pu
VOLdc = 0.2 x VDDQ 0.9 1.0 1.4 1,2,3
VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 1,2,3
VOHdc = 0.8 x VDDQ 0.6 1.0 1.1 1,2,3
40Ohms
RON40pd
VOLdc = 0.2 x VDDQ 0.6 1.0 1.1
RZQ/6
1,2,3
VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 1,2,3
VOHdc = 0.8 x VDDQ 0.9 1.0 1.4 1,2,3
RON40pu
VOLdc = 0.2 x VDDQ 0.9 1.0 1.4 1,2,3
VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 1,2,3
VOHdc = 0.8 x VDDQ 0.6 1.0 1.1 1,2,3
Mismatch between Pull-up and Pull-down,
MMpupd VOMdc = 0.5 x VDDQ -10 10 % 1,2,4
MMpupd = RONpu - RONpd x 100
RONnom
- 25 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
9.7.1 Output Drive Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to Table 27 and Table 28.
T = T - T(@calibration); V = VDDQ - VDDQ (@calibration); VDD = VDDQ
*dRONdT and dRONdV are not subject to production test but are verified by design and characterization
[ Table 27 ] Output Driver Sensitivity Definition
[ Table 28 ] Output Driver Voltage and Temperature Sensitivity
9.8 On-Die Termination (ODT) Levels and I-V Characteristics
On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of MR1 register.
ODT is applied to the DQ,DM, DQS/DQS and TDQS,TDQS (x8 devices only) pins.
A functional representation of the on-die termination is shown below. The individual pull-up and pull-down resistors (RTTpu and RTTpd) are defined as
follows :
Chip in Termination Mode
Figure 12. On-Die Termination : Definition of Voltages and Currents
Min Max Units
RONPU@VOHDC 0.6 - dRONdTH * |T| - dRONdVH * |V| 1.1 + dRONdTH * |T| + dRONdVH * |V| RZQ/7
RON@VOMDC 0.9 - dRONdTM * |T| - dRONdVM * |V| 1.1 + dRONdTM * |T| + dRONdVM * |V| RZQ/7
RONPD@VOLDC 0.6 - dRONdTL * |T| - dRONdVL * |V| 1.1 + dRONdTL * |T| + dRONdVL * |V| RZQ/7
Speed Bin 800/1066/1333 1600/1866 Units
Min Max Min Max
dRONdTM 01.501.5
%/C
dRONdVM 0 0.15 0 0.13 %/mV
dRONdTL 01.501.5
%/C
dRONdVL 0 0.15 0 0.13 %/mV
dRONdTH 01.501.5
%/C
dRONdVH 0 0.15 0 0.13 %/mV
RTTpu =
VDDQ-VOUT
l Iout l
under the condition that RTTpd is turned off
RTTpd =
VOUT
l Iout l
under the condition that RTTpu is turned off
VDDQ
DQ
VSSQ
RTTPu
Ipd
RTTPd
To
other
circuitry
like
RCV,
...
ODT
Ipu
Iout
VOUT
Iout=Ipd-Ipu
- 26 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
9.8.1 ODT DC Electrical Characteristics
Table 29 provides and overview of the ODT DC electrical characteristics. They values for RTT60pd120, RTT60pu120, RTT120pd240, RTT120pu240, RTT40pd80,
RTT40pu80, RTT30pd60, RTT30pu60, RTT20pd40, RTT20pu40 are not specification requirements, but can be used as design guide lines:
[ Table 29 ] ODT DC Electrical Characteristics, assuming RZQ=240ohm +/- 1% entire operating temperature range; after proper ZQ calibration
1.35V
MR1 (A9,A6,A2) RTT RESISTOR Vout Min Nom Max Unit Notes
(0,1,0) 120 ohm
RTT120pd240
VOL(DC) 0.2XVDDQ 0.6 1.0 1.15 RZQ 1,2,3,4
0.5XVDDQ 0.9 1.0 1.15 RZQ 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.45 RZQ 1,2,3,4
RTT120pu240
VOL(DC) 0.2XVDDQ 0.9 1.0 1.45 RZQ 1,2,3,4
0.5XVDDQ 0.9 1.0 1.15 RZQ 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.15 RZQ 1,2,3,4
RTT120 VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/2 1,2,5
(0,0,1) 60 ohm
RTT60pd120
VOL(DC) 0.2XVDDQ 0.6 1.0 1.15 RZQ/2 1,2,3,4
0.5XVDDQ 0.9 1.0 1.15 RZQ/2 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.45 RZQ/2 1,2,3,4
RTT60pu120
VOL(DC) 0.2XVDDQ 0.9 1.0 1.45 RZQ/2 1,2,3,4
0.5XVDDQ 0.9 1.0 1.15 RZQ/2 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.15 RZQ/2 1,2,3,4
RTT60 VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/4 1,2,5
(0,1,1) 40 ohm
RTT40pd80
VOL(DC) 0.2XVDDQ 0.6 1.0 1.15 RZQ/3 1,2,3,4
0.5XVDDQ 0.9 1.0 1.15 RZQ/3 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.45 RZQ/3 1,2,3,4
RTT40pu80
VOL(DC) 0.2XVDDQ 0.9 1.0 1.45 RZQ/3 1,2,3,4
0.5XVDDQ 0.9 1.0 1.15 RZQ/3 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.15 RZQ/3 1,2,3,4
RTT40 VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/6 1,2,5
(1,0,1) 30 ohm
RTT30pd60
VOL(DC) 0.2XVDDQ 0.6 1.0 1.15 RZQ/4 1,2,3,4
0.5XVDDQ 0.9 1.0 1.15 RZQ/4 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.45 RZQ/4 1,2,3,4
RTT30pu60
VOL(DC) 0.2XVDDQ 0.9 1.0 1.45 RZQ/4 1,2,3,4
0.5XVDDQ 0.9 1.0 1.15 RZQ/4 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.15 RZQ/4 1,2,3,4
RTT30 VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/8 1,2,5
(1,0,0) 20 ohm
RTT20pd40
VOL(DC) 0.2XVDDQ 0.6 1.0 1.15 RZQ/6 1,2,3,4
0.5XVDDQ 0.9 1.0 1.15 RZQ/6 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.45 RZQ/6 1,2,3,4
RTT20pu40
VOL(DC) 0.2XVDDQ 0.9 1.0 1.45 RZQ/6 1,2,3,4
0.5XVDDQ 0.9 1.0 1.15 RZQ/6 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.15 RZQ/6 1,2,3,4
RTT20 VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/12 1,2,5
Deviation of VM w.r.t VDDQ/2, VM -5 5 % 1,2,5,6
- 27 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
1.5V
MR1 (A9,A6,A2) RTT RESISTOR Vout Min Nom Max Unit Notes
(0,1,0) 120 ohm
RTT120pd240
VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ 1,2,3,4
0.5XVDDQ 0.9 1.0 1.1 RZQ 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ 1,2,3,4
RTT120pu240
VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ 1,2,3,4
0.5XVDDQ 0.9 1.0 1.1 RZQ 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ 1,2,3,4
RTT120 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/2 1,2,5
(0,0,1) 60 ohm
RTT60pd240
VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ/2 1,2,3,4
0.5XVDDQ 0.9 1.0 1.1 RZQ/2 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/2 1,2,3,4
RTT60pu240
VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ/2 1,2,3,4
0.5XVDDQ 0.9 1.0 1.1 RZQ/2 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/2 1,2,3,4
RTT60 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/4 1,2,5
(0,1,1) 40 ohm
RTT40pd240
VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ/3 1,2,3,4
0.5XVDDQ 0.9 1.0 1.1 RZQ/3 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/3 1,2,3,4
RTT40pu240
VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ/3 1,2,3,4
0.5XVDDQ 0.9 1.0 1.1 RZQ/3 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/3 1,2,3,4
RTT40 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/6 1,2,5
(1,0,1) 30 ohm
RTT60pd240
VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ/4 1,2,3,4
0.5XVDDQ 0.9 1.0 1.1 RZQ/4 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/4 1,2,3,4
RTT60pu240
VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ/4 1,2,3,4
0.5XVDDQ 0.9 1.0 1.1 RZQ/4 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/4 1,2,3,4
RTT60 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/8 1,2,5
(1,0,0) 20 ohm
RTT60pd240
VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ/6 1,2,3,4
0.5XVDDQ 0.9 1.0 1.1 RZQ/6 1,2,3,4
VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/6 1,2,3,4
RTT60pu240
VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ/6 1,2,3,4
0.5XVDDQ 0.9 1.0 1.1 RZQ/6 1,2,3,4
VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/6 1,2,3,4
RTT60 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/12 1,2,5
Deviation of VM w.r.t VDDQ/2, VM -5 5 % 1,2,5,6
- 28 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
NOTE :
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibra-
tion, see following section on voltage and temperature sensitivity
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS
3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XVDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g.
calibration at 0.2XVDDQ and 0.8XVDDQ.
4. Not a specification requirement, but a design guide line
5. Measurement definition for RTT:
Apply VIH(AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test and measure current I(VIL(AC)) respectively
6. Measurement definition for VM and VM : Measure voltage (VM) at test pin (midpoint) with no load
9.8.2 ODT Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to table below
T = T - T(@calibration); V = VDDQ - VDDQ (@calibration); VDD = VDDQ
[ Table 30 ] ODT Sensitivity Definition
[ Table 31 ] ODT Voltage and Temperature Sensitivity
NOTE : These parameters may not be subject to production test. They are verified by design and characterization.
Min Max Units
RTT 0.9 - dRTTdT * |T| - dRTTdV * |V| 1.6 + dRTTdT * |T| + dRTTdV * |V| RZQ/2,4,6,8,12
Min Max Units
dRTTdT 01.5
%/C
dRTTdV 00.15%/mV
RTT =
VIH(AC) - VIL(AC)
I(VIH(AC)) - I(VIL(AC))
VM =
2 x VM
VDDQ
x 100
- 1
- 29 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
9.9 ODT Timing Definitions
9.9.1 Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in Figure 13.
Figure 13. ODT Timing Reference Load
9.9.2 ODT Timing Definitions
Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table 32 and subsequent figures. Measurement reference settings are provided
in Table 33 .
[ Table 32 ] ODT Timing Definitions
[ Table 33 ] Reference Settings for ODT Timing Measurements
Symbol Begin Point Definition End Point Definition Figure
tAON Rising edge of CK - CK defined by the end point of ODTLon Extrapolated point at VSSQ Figure 14
tAONPD Rising edge of CK - CK with ODT being first registered high Extrapolated point at VSSQ Figure 15
tAOF Rising edge of CK - CK defined by the end point of ODTLoff End point: Extrapolated point at VRTT_Nom Figure 16
tAOFPD Rising edge of CK - CK with ODT being first registered low End point: Extrapolated point at VRTT_Nom Figure 17
tADC Rising edge of CK - CK defined by the end point of ODTLcnw, ODTL-
cwn4 of ODTLcwn8
End point: Extrapolated point at VRTT_Wr and VRTT_Nom
respectively Figure 18
Measured
Parameter RTT_Nom Setting RTT_Wr Setting VSW1[V] VSW2[V] NOTE
tAON RZQ/4 NA 0.05 0.10
RZQ/12 NA 0.10 0.20
tAONPD RZQ/4 NA 0.05 0.10
RZQ/12 NA 0.10 0.20
tAOF RZQ/4 NA 0.05 0.10
RZQ/12 NA 0.10 0.20
tAOFPD RZQ/4 NA 0.05 0.10
RZQ/12 NA 0.10 0.20
tADC RZQ/12 RZQ/2 0.20 0.25
VDDQ
CK,CK
DUT DQ, DM
DQS , DQS
TDQS , TDQS RTT
=25 ohm
VTT=
VSSQ
Timing Reference Points
VSSQ
- 30 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
Figure 14. Definition of tAON
Figure 15. Definition of tAONPD
CK
CK
Begin point : Rising edge of CK - CK
defined by the end point of ODTLon
t
AON
V
TT
DQ, DM
DQS , DQS
TDQS , TDQS V
SSQ
T
SW1
T
SW2
V
SW1
V
SW2
End point Extrapolated point at V
SSQ
V
SSQ
CK
CK
Begin point : Rising edge of CK - CK
with ODT being first registered high
t
AONPD
V
TT
DQ, DM
DQS , DQS
TDQS , TDQS V
SSQ
T
SW1
T
SW2
V
SW1
V
SW2
End point Extrapolated point at V
SSQ
V
SSQ
- 31 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
Figure 16. Definition of tAOF
Figure 17. Definition of tAOFPD
Figure 18. Definition of tADC
CK
CK
Begin point : Rising edge of CK - CK
defined by the end point of ODTLoff
t
AOF
V
TT
DQ, DM
DQS , DQS
TDQS , TDQS
V
RTT_Nom
T
SW1
T
SW2
V
SW1
V
SW2
End point Extrapolated point at V
RTT_Nom
V
SSQ
TD_TAON_DEF
CK
CK
Begin point : Rising edge of CK - CK
with ODT being first registered low
t
AOFPD
V
TT
DQ, DM
DQS , DQS
TDQS , TDQS
V
RTT_Nom
T
SW1
T
SW2
V
SW1
V
SW2
End point Extrapolated point at V
RTT_Nom
V
SSQ
CK
CK
Begin point : Rising edge of CK - CK
defined by the end point of ODTLcnw
t
ADC
V
TT
DQ, DM
DQS , DQS
TDQS , TDQS
V
RTT_Nom
T
SW11
T
SW21
V
SW1
End point Extrapolated point at V
RTT_Nom
V
RTT_Wr
End point Extrapolated point at V
RTT_Wr
t
ADC
V
SW2
Begin point : Rising edge of CK - CK defined by
the end point of ODTLcwn4 or ODTLcwn8
End point
Extrapolated point
at V
RTT_Nom
T
SW12
T
SW22
V
RTT_Nom
V
SSQ
- 32 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
10. IDD Current Measure Method
10.1 IDD Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and
IDDQ measurements.
- IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and
IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in
IDD currents.
- IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied
together. Any IDD current is not included in IDDQ currents.
Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO
power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ
are using one merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply :
- "0" and "LOW" is defined as VIN <= VILAC(max).
- "1" and "HIGH" is defined as VIN >= VIHAC(min).
- "FLOATING" is defined as inputs are VREF = VDD / 2.
- "Timing used for IDD and IDDQ Measured - Loop Patterns" are provided in Table 34
- "Basic IDD and IDDQ Measurement Conditions" are described in Table 35
- Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 32 on page 31 through Table 39.
- IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
- Attention : The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.
- Define D = {CS, RAS, CAS, WE} := {HIGH, LOW, LOW, LOW}
- Define D = {CS, RAS, CAS, WE} := {HIGH, HIGH, HIGH, HIGH}
- RESET Stable time is : During a Cold Bood RESET (Initialization), current reading is valid once power is stable and RESET has been LOW for 1ms;
During Warm Boot RESET(while operating), current reading is valid after RESET has been LOW for 200ns + tRFC
[ Table 34 ] Timing used for IDD and IDDQ Measured - Loop Patterns
Parameter Bin DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Unit
6-6-6 7-7-7 9-9-9 11-11-11 13-13-13
tCKmin(IDD) 2.5 1.875 1.5 1.25 1.071 ns
CL(IDD) 6 7 9 11 13 nCK
tRCDmin(IDD) 6 7 9 11 13 nCK
tRCmin(IDD) 21 27 33 39 45 nCK
tRASmin(IDD) 15 20 24 28 32 nCK
tRPmin(IDD) 6 7 9 11 13 nCK
tFAW(IDD) x4/x81620202426nCK
x162027303233nCK
tRRD(IDD) x4/x844455nCK
x1646566nCK
tRFC(IDD) - 512Mb 36 48 60 72 85 nCK
tRFC(IDD) - 1Gb 44 59 74 88 103 nCK
tRFC(IDD) - 2Gb 64 86 107 128 150 nCK
tRFC(IDD) - 4Gb 104 139 174 208 243 nCK
tRFC(IDD) - 8Gb 140 187 234 280 328 nCK
- 33 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
Figure 19. Measurement Setup and Test Load for IDD and IDDQ Measurements
Figure 20. Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement.
I
DDQ
I
DD
V
DD
V
DDQ
RESET
CK/CK
CKE
CS
RAS, CAS, WE
A, BA
ODT
ZQ
V
SS
V
SSQ
DQS, DQS
DQ, DM,
TDQS, TDQS
V
DDQ
/2
R
TT
= 25 Ohm
[
NOTE
: DIMM level Output test load condition may be different from above]
Application specific
memory channel
environment
Channel
IO Power
Simulation
IDDQ
Measurement
Correlation
Correction
Channel IO Power
Number
IDDQ
Test Load
IDDQ
Simulation
- 34 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 35 ] Basic IDD and IDDQ Measurement Conditions
Symbol Description
IDD0
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: High between ACT and PRE; Command, Address,
Bank Address Inputs: partially toggling according to Table 32 on page 31 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active
at a time: 0,0,1,1,2,2,... (see Table 32); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 32
IDD1
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: High between ACT, RD and PRE; Command,
Address, Bank Address Inputs, Data IO: partially toggling according to Table 33 on page 32 ; DM:stable at 0; Bank Activity: Cycling with one bank active at
a time: 0,0,1,1,2,2,... (see Table 33); Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 33
IDD2N
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-
gling according to Table 34 on page 32 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Reg-
isters2); ODT Signal: stable at 0; Pattern Details: see Table 34
IDD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-
gling according to Table 35 on page 33 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Reg-
isters2); ODT Signal: toggling according to Table 35 ; Pattern Details: see Table 35
IDDQ2NT Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
IDD2P0
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;
Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pre-
charge Power Down Mode: Slow Exi3)
IDD2P1
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 34 on page 32; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;
Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pre-
charge Power Down Mode: Fast Exit3)
IDD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;
Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0
IDD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-
gling according to Table 34 on page 32 ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Regis-
ters2); ODT Signal: stable at 0; Pattern Details: see Table 34
IDD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0;
Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0
IDD4R
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: par-
tially toggling according to Table 36 on page 33 ; Data IO: seamless read data burst with different data between one burst and the next one according to
Table 36 ; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7 on page 11); Output Buffer and
RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 36
IDDQ4R Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
IDD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: par-
tially toggling according to Table 37 on page 34 ; Data IO: seamless write data burst with different data between one burst and the next one according to
Table 37; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 37); Output Buffer and RTT:
Enabled in Mode Registers2); ODT Signal: stable at HIGH; Pattern Details: see Table 37
IDD5B
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 34 on page 32 ; BL: 81); AL: 0; CS: High between REF; Command, Address, Bank Address
Inputs: partially toggling according to Table 38 on page 34 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38);
Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 38
IDD6
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Normal5); CKE: Low; External clock: Off; CK and CK:
LOW; CL: see Table 34 on page 32 ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self-
Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING
IDD6ET
Self Refresh Current: Extended Temperature Range
TCASE: 0°C - 95°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Extended5); CKE: Low; External clock: Off; CK and
CK#: LOW; CL: see Table 34 on page 32; BL: 81); AL: 0; CS#, Command, Address, Bank Address, Data IO: MID-LEVEL;DM:stable at 0; Bank Activity:
Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: MID-LEVEL
- 35 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 35 ] Basic IDD and IDDQ Measurement Conditions
NOTE :
1. Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
2. Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
3. Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
4. Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
5. Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
6. Read Burst type : Nibble Sequential, set MR0 A[3]=0B
Symbol Description
IDD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 34 on page 32 ; BL: 81); AL: CL-1; CS: High between ACT and RDA;
Command, Address, Bank Address Inputs: partially toggling according to Table 39 on page 35 ; Data IO: read data bursts with different data between one
burst and the next one according to Table 39 ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing,
see Table 39 ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: see Table 39
IDD8
RESET Low Current
RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :
FLOATING
- 36 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 36 ] IDD0 Measurement - Loop Pattern1)
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
CK/CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2)
toggling
Static High
0 0 ACT001100000000 -
1,2 D, D100000000000 -
3,4 D, D 111100000000 -
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE001000000000 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC + 0 ACT00110000 0 0 F0-
1*nRC + 1, 2 D, D10000000 0 0 F0-
1*nRC + 3, 4 D, D 11110000 0 0 F0-
... repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
1*nRC + nRASPRE00100000 0 0 F0
... repeat 1...4 until 2*nRC - 1, truncate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead
- 37 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 37 ] IDD1 Measurement - Loop Pattern1)
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
[ Table 38 ] IDD2 and IDD3N Measurement - Loop Pattern1)
NOTE :
1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
CK/CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2)
toggling
Static High
0 0 ACT 001100000000 -
1,2 D, D 100000000000 -
3,4 D, D 111100000000 -
... repeat pattern 1...4 until nRCD- 1, truncate if necessary
nRCD RD 010100000000 00000000
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 001000000000 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 00110000 0 0 F0-
1*nRC + 1, 2 D, D 10000000 0 0 F0-
1*nRC + 3, 4 D, D 11110000 0 0 F0-
... repeat pattern nRC + 1,..., 4 until nRC + nRCD - 1, truncate if necessary
1*nRC + nRCD RD 01010000 0 0 F0 00110011
... repeat pattern nRC + 1,..., 4 until nRC +nRAS - 1, truncate if necessary
1*nRC + nRAS PRE 00100000 0 0 F0-
... repeat pattern nRC + 1,..., 4 until 2 * nRC - 1, truncate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead
CK/CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2)
toggling
Static High
0 0 D 100000000000 -
1 D 100000000000 -
2D
11110000 0 0 F0-
3D
11110000 0 0 F0-
1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 12-15 repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 16-19 repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 20-23 repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 24-27 repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 28-31 repeat Sub-Loop 0, use BA[2:0] = 7 instead
- 38 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 39 ] IDD2NT and IDDQ2NT Measurement - Loop Pattern1)
NOTE :
1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
[ Table 40 ] IDD4R and IDDQ4R Measurement - Loop Pattern1)
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
CK/CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2)
toggling
Static High
0 0 D 100000000000 -
1 D 100000000000
2D
11110000 0 0 F0
3D
11110000 0 0 F0
1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2 8-11 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3 12-15 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6 24-27 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7 28-31 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
CK/CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2)
toggling
Static High
0 0 RD 010100000000 00000000
1 D 100000000000 -
2,3 D,D 111100000000 -
4 RD 01010000 0 0 F0 00110011
5 D 10000000 0 0 F0-
6,7 D,D 11110000 0 0 F0-
1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1
2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7
- 39 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 41 ] IDD4W Measurement - Loop Pattern1)
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
[ Table 42 ] IDD5B Measurement - Loop Pattern1)
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
CK/CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2)
toggling
Static High
0 0 WR 010010000000 00000000
1 D 100010000000 -
2,3 D,D 111110000000 -
4 WR 01001000 0 0 F0 00110011
5 D 10001000 0 0 F0-
6,7 D,D 11111000 0 0 F0-
1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1
2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7
CK/CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2)
toggling
Static High
0 0 REF 000100000000 -
1 1,2 D 100000000000 -
3,4 D,D 11110000 0 0 F 0 -
5...8 repeat cycles 1...4, but BA[2:0] = 1
9...12 repeat cycles 1...4, but BA[2:0] = 2
13...16 repeat cycles 1...4, but BA[2:0] = 3
17...20 repeat cycles 1...4, but BA[2:0] = 4
21...24 repeat cycles 1...4, but BA[2:0] = 5
25...28 repeat cycles 1...4, but BA[2:0] = 6
29...32 repeat cycles 1...4, but BA[2:0] = 7
2 33...nRFC - 1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
- 40 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 43 ] IDD7 Measurement - Loop Pattern1)
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation. DQ signals are MID-LEVEL.
CK/CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2)
toggling
Static High
0
0 ACT 00110000 0 0 00-
1 RDA 01010000 1 0 00 00000000
2 D 10000000 0 0 00-
... repeat above D Command until nRRD - 1
1
nRRD ACT 00110100 0 0 F0-
nRRD + 1 RDA 01010100 1 0 F0 00110011
nRRD + 2 D 10000100 0 0 F0-
... repeat above D Command until 2*nRRD-1
2 2 * nRRD repeat Sub-Loop 0, but BA[2:0] = 2
3 3 * nRRD repeat Sub-Loop 1, but BA[2:0] = 3
44 * nRRD D 10000300 0 0 F0-
Assert and repeat above D Command until nFAW - 1, if necessary
5 nFAW repeat Sub-Loop 0, but BA[2:0] = 4
6 nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5
7 nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6
8 nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7
9 nFAW+4*nRRD D 10000700 0 0 F0-
Assert and repeat above D Command until 2*nFAW - 1, if necessary
10
2*nFAW+0 ACT 00110000 0 0 F0-
2*nFAW+1 RDA 01010000 1 0 F0 00110011
2*nFAW+2 D 10000000 0 0 F0-
Repeat above D Command until 2*nFAW + nRRD - 1
11
2*nFAW+nRRD ACT 00110100 0 0 00-
2*nFAW+nRRD+1 RDA 01010100 1 0 00 00000000
2*nFAW+nRRD+2 D 10000100 0 0 00-
Repeat above D Command until 2*nFAW + 2*nRRD - 1
12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2
13 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3
14 2*nFAW+4*nRRD D 10000300 0 0 00-
Assert and repeat above D Command until 3*nFAW - 1, if necessary
15 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4
16 3*nFAW+nRRD repeat Sub-Loop 11, but BA[2:0] = 5
17 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6
18 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7
19 3*nFAW+4*nRRD D 10000700 0 0 00-
Assert and repeat above D Command until 4*nFAW - 1, if necessary
- 41 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
11. 1Gb DDR3 SDRAM I-die IDD Specification Table
[ Table 44 ] IDD Specification for 1Gb DDR3 I-die
NOTE :
1. VDD condition : 1.45V for 1.35V operation
2. Applicable for MR2 setting A6=0 and A7=0. Temperature range for IDD6 is 0 - 85°C at commercial temperature, -40 - 85°C at industrial temperature.
-. Commercial temperature : K4B2G1646Q-BYxx
-. Industrial temperature : K4B2G1646Q-BMxx.
3. Applicable for MR2 setting A6=0 and A7=1. Temperature range for IDD6ET is 0 - 95°C at commercial temperature & industrial temperature.
Symbol
64Mx16 (K4B1G1646I)
Unit NOTEDDR3-1600 DDR3-1866
11-11-11 13-13-13
1.35V 1.5V 1.35V 1.5V
IDD0 38 41 39 41 mA
IDD1 58 60 59 60 mA
IDD2P0(slow exit)10111011mA
IDD2P1(fast exit)10111011mA
IDD2N13141315mA
IDD2NT 15 17 16 18 mA
IDDQ2NT 126 132 126 132 mA
IDD2Q13141314mA
IDD3P15151515mA
IDD3N25293030mA
IDD4R 110 118 124 134 mA
IDDQ4R 96 100 96 100 mA
IDD4W 95 105 110 120 mA
IDD5B 162 164 166 168 mA
IDD6 10 11 10 11 mA 2
IDD6ET 14 16 14 16 mA 3
IDD7 180 187 190 195 mA
IDD8 10 11 10 11 mA
- 42 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
12. Input/Output Capacitance
[ Table 45 ] Input/Output Capacitance
NOTE :
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization.
The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with
VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.5V or 1.35V, VBIAS=VDD/2 and on-
die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Units NOTE
Min Max Min Max Min Max Min Max Min Max
1.35V
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)CIO 1.4 2.5 1.4 2.5 1.4 2.3 1.4 2.2 1.4 2.0 pF 1,2,3
Input capacitance
(CK and CK) CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.4 pF 2,3
Input capacitance delta
(CK and CK) CDCK 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4
Input capacitance
(All other input-only pins) CI 0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pF 2,3,6
Input/Output capacitance delta
(DQS and DQS) CDDQS 0 0.2 0 0.2 0 0.15 0 0.15 0 0.15 pF 2,3,5
Input capacitance delta
(All control input-only pins) CDI_CTRL -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF 2,3,7,8
Input capacitance delta
(all ADD and CMD input-only pins) CDI_ADD_CMD -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF 2,3,9,10
Input/output capacitance delta
(DQ, DM, DQS, DQS, TDQS, TDQS)CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11
Input/output capacitance of ZQ pin CZQ - 3 - 3 - 3 - 3 - 3 pF 2, 3, 12
1.5V
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)CIO 1.4 3.0 1.4 2.7 1.4 2.5 1.4 2.3 1.4 2.2 pF 1,2,3
Input capacitance
(CK and CK) CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 pF 2,3
Input capacitance delta
(CK and CK) CDCK 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4
Input capacitance
(All other input-only pins) CI 0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 pF 2,3,6
Input capacitance delta
(DQS and DQS) CDDQS 0 0.2 0 0.2 0 0.15 0 0.15 0 0.15 pF 2,3,5
Input capacitance delta
(All control input-only pins) CDI_CTRL -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF 2,3,7,8
Input capacitance delta
(all ADD and CMD input-only pins) CDI_ADD_CMD -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF 2,3,9,10
Input/output capacitance delta
(DQ, DM, DQS, DQS, TDQS, TDQS)CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11
Input/output capacitance of ZQ pin CZQ - 3 - 3 - 3 - 3 - 3 pF 2, 3, 12
- 43 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
13. Electrical Characteristics and AC timing for DDR3-800 to
DDR3-1866
13.1 Clock Specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3
SDRAM device.
13.1.1 Definition for tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to
rising edge.
13.1.2 Definition for tCK(abs)
tCK(abs) is defind as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to produc-
tion test.
13.1.3 Definition for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses:
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses:
13.1.4 Definition for note for tJIT(per), tJIT(per, Ick)
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200}
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not subject to production test.
13.1.5 Definition for tJIT(cc), tJIT(cc, Ick)
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of {tCKi+1-tCKi}
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not subject to production test.
13.1.6 Definition for tERR(nper)
tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to production test.
N
j=1
tCKj NN=200
N
j=1
tCHj N x tCK(avg) N=200
N
j=1
tCLj N x tCK(avg) N=200
- 44 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
13.2 Refresh Parameters by Device Density
[ Table 46 ] Refresh parameters by device density
NOTE :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in
this material.
2. Supported only for Industrial Temperature.
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
[ Table 47 ] DDR3-800 Speed Bins
[ Table 48 ] DR3-1066 Speed Bins
Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units NOTE
All Bank Refresh to active/refresh cmd time tRFC 110 160 260 350 ns
Average periodic refresh interval tREFI
0CTCASE 85C7.8 7.8 7.8 7.8 s
-40CTCASE 85C7.8 7.8 7.8 7.8 s 2
85CTCASE 95C3.9 3.9 3.9 3.9 s 1
Speed DDR3-800
Units NOTECL-nRCD-nRP 6 - 6 - 6
Parameter Symbol min max
Internal read command to first data tAA 15 20 ns
ACT to internal read or write delay time tRCD 15 -ns
PRE command period tRP 15 -ns
ACT to ACT or REF command period tRC 52.5 -ns
ACT to PRE command period tRAS 37.5 9*tREFI ns
CL = 5 CWL = 5 tCK(AVG) 3.0 3.3 ns 1,2,3,4,10,11
CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3
Supported CL Settings 5,6 nCK
Supported CWL Settings 5nCK
Speed DDR3-1066
Units NOTECL-nRCD-nRP 7 - 7 - 7
Parameter Symbol min max
Internal read command to first data tAA 13.125 20 ns
ACT to internal read or write delay time tRCD 13.125 -ns
PRE command period tRP 13.125 -ns
ACT to ACT or REF command period tRC 50.625 -ns
ACT to PRE command period tRAS 37.5 9*tREFI ns
CL = 5 CWL = 5 tCK(AVG) 3.0 3.3 ns 1,2,3,4,5,10,
11
CWL = 6 tCK(AVG) Reserved ns 4
CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,5
CWL = 6 tCK(AVG) Reserved ns 1,2,3,4
CL = 7 CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,9
CL = 8 CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3
Supported CL Settings 5,6,7,8 nCK
Supported CWL Settings 5,6 nCK
- 45 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 49 ] DDR3-1333 Speed Bins
Speed DDR3-1333
Units NOTECL-nRCD-nRP 9 -9 - 9
Parameter Symbol min max
Internal read command to first data tAA 13.5
(13.125)920 ns
ACT to internal read or write delay time tRCD 13.5
(13.125)9-ns
PRE command period tRP 13.5
(13.125)9-ns
ACT to ACT or REF command period tRC 49.5
(49.125)9-ns
ACT to PRE command period tRAS 36 9*tREFI ns
CL = 5 CWL = 5 tCK(AVG) 3.0 3.3 ns 1,2,3,4,6,10,
11
CWL = 6,7 tCK(AVG) Reserved ns 4
CL = 6
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,6
CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,6
CWL = 7 tCK(AVG) Reserved ns 4
CL = 7
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,6
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4
CL = 8
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,6
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4
CL = 9 CWL = 5,6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,9
CL = 10 CWL = 5,6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3
Supported CL Settings 5,6,7,8,9,10 nCK
Supported CWL Settings 5,6,7 nCK
- 46 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 50 ] DDR3-1600 Speed Bins
Speed DDR3-1600
Units NOTECL-nRCD-nRP 11-11-11
Parameter Symbol min max
Internal read command to first data tAA 13.75
(13.125)920 ns
ACT to internal read or write delay time tRCD 13.75
(13.125)9-ns
PRE command period tRP 13.75
(13.125)9-ns
ACT to ACT or REF command period tRC 48.75
(48.125)9-ns
ACT to PRE command period tRAS 35 9*tREFI ns
CL = 5 CWL = 5 tCK(AVG) 3.0 3.3 ns 1,2,3,4,7,10,
11
CWL = 6,7,8 tCK(AVG) Reserved ns 4
CL = 6
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,7
CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,7
CWL = 7, 8 tCK(AVG) Reserved ns 4
CL = 7
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,7
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,7
CWL = 8 tCK(AVG) Reserved ns 4
CL = 8
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,7
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,7
CWL = 8 tCK(AVG) Reserved ns 1,2,3,4
CL = 9
CWL = 5,6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,7
CWL = 8 tCK(AVG) Reserved ns 1,2,3,4
CL = 10
CWL = 5,6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,7
CWL = 8 tCK(AVG) Reserved ns 1,2,3,4
CL = 11 CWL = 5,6,7 tCK(AVG) Reserved ns 4
CWL = 8 tCK(AVG) 1.25 <1.5 ns 1,2,3,9
Supported CL Settings 5,6,7,8,9,10,11 nCK
Supported CWL Settings 5,6,7,8 nCK
- 47 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 51 ] DDR3-1866 Speed Bins
Speed DDR3-1866
Units NOTECL-nRCD-nRP 13-13-13
Parameter Symbol min max
Internal read command to first data tAA 13.91
(13.125)12 20 ns
ACT to internal read or write delay time tRCD 13.91
(13.125)12 -ns
PRE command period tRP 13.91
(13.125)12 -ns
ACT to ACT or REF command period tRC 47.91
(47.125)12 -ns
ACT to PRE command period tRAS 34 9*tREFI ns
CL = 5 CWL = 5 tCK(AVG) 3.0 3.3 ns 1,2,3,4,8,10,
11
CWL = 6,7,8,9 tCK(AVG) Reserved ns 4
CL = 6
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,8
CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,8
CWL = 7,8,9 tCK(AVG) Reserved ns 4
CL = 7
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 2.5 ns 1,2,3,4,8
CWL = 7,8,9 tCK(AVG) Reserved ns 4
CL = 8
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,8
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,8
CWL = 8,9 tCK(AVG) Reserved ns 4
CL = 9
CWL = 5,6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 1.875 ns 1,2,3,4,8
CWL = 8 tCK(AVG) Reserved ns 4
CWL = 9 tCK(AVG) Reserved ns 4
CL = 10
CWL = 5,6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,8
CWL = 8 tCK(AVG) Reserved ns 1,2,3,4,8
CL = 11
CWL = 5,6,7 tCK(AVG) Reserved ns 4
CWL = 8 tCK(AVG) 1.25 1.5 ns 1,2,3,4,8
CWL = 9 tCK(AVG) Reserved ns 1,2,3,4
CL = 12 CWL = 5,6,7,8 tCK(AVG) Reserved ns 4
CWL = 9 tCK(AVG) Reserved ns 1,2,3,4
CL = 13 CWL = 5,6,7,8 tCK(AVG) Reserved ns 4
CWL = 9 tCK(AVG) 1.071 <1.25 ns 1,2,3,9
Supported CL Settings 5,6,7,8,9,10,11,13 nCK
Supported CWL Settings 5,6,7,8,9 nCK
- 48 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
13.3.1 Speed Bin Table Notes
Absolute Specification {TOPER; VDDQ = VDD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)};
NOTE :
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements
from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-
anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],
rounding up to the next "Supported CL".
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or
1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. "Reserved" settings are not allowed. User must program a different value.
5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
8. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
9. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,
DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte
20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte
18), and tRPmin (Byte 20). DDR3-1866(CL13) devices supporting downshift to DDR3-1600(CL11) or DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in
SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600 devices supporting down binning to DDR3-1333 or DDR3-1066 should program
13.125ns in SPD byte for tAAmin (Byte 16), tRCDmin (Byte 18) and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be
programmed accodingly. For example, 49.125ns, (tRASmin + tRPmin = 36ns + 13.125ns) for DDR3-1333 and 48.125ns (tRASmin + tRPmin = 35ns + 13.125ns) for DDR3-
1600.
10. DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.
11. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not mandatory in SPD coding.
12. For devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin must be 13.125ns. SPD setting must be programed to match. For example,
DDR3-1866 devices supporting down binning to DDR3-1600 or DDR3-1333 or 1066 should program 13.125ns in SPD bytes for tAAmin(byte16), tRCDmin(Byte18) and tRP-
min (byte20). Once tRP (Byte20) is programmed to 13.125ns, tRCmin (Byte21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRPmin =
34ns + 13.125ns)
- 49 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
14. Timing Parameters by Speed Grade
[ Table 52 ] Timing Parameters by Speed Bin(Cont.)
Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866
Units NOTE
Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Clock Timing
Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OF
F) 8 - 8 - 8 - 8 - 8 - ns 6
Average Clock Period tCK(avg) See Speed Bins Table ps
Clock Period tCK(abs)
tCK(avg)mi
n +
tJIT(per)min
tCK(avg)ma
x +
tJIT(per)ma
x
tCK(avg)mi
n +
tJIT(per)min
tCK(avg)ma
x +
tJIT(per)ma
x
tCK(avg)mi
n +
tJIT(per)min
tCK(avg)ma
x +
tJIT(per)ma
x
tCK(avg)mi
n +
tJIT(per)min
tCK(avg)ma
x +
tJIT(per)ma
x
tCK(avg)mi
n +
tJIT(per)min
tCK(avg)ma
x +
tJIT(per)ma
x
ps
Average high pulse width tCH(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)
Average low pulse width tCL(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)
Clock Period Jitter tJIT(per) -100 100 -90 90 -80 80 -70 70 -60 60 ps
Clock Period Jitter during DLL locking period tJIT(per, lck) -90 90 -80 80 -70 70 -60 60 -50 50 ps
Cycle to Cycle Period Jitter tJIT(cc) 200 180 160 140 120 ps
Cycle to Cycle Period Jitter during DLL locking period tJIT(cc, lck) 180 160 140 120 100 ps
Cumulative error across 2 cycles tERR(2per) - 147 147 - 132 132 - 118 118 -103 103 -88 88 ps
Cumulative error across 3 cycles tERR(3per) - 175 175 - 157 157 - 140 140 -122 122 -105 105 ps
Cumulative error across 4 cycles tERR(4per) - 194 194 - 175 175 - 155 155 -136 136 -117 117 ps
Cumulative error across 5 cycles tERR(5per) - 209 209 - 188 188 - 168 168 -147 147 -126 126 ps
Cumulative error across 6 cycles tERR(6per) - 222 222 - 200 200 - 177 177 -155 155 -133 133 ps
Cumulative error across 7 cycles tERR(7per) - 232 232 - 209 209 - 186 186 -163 163 -139 139 ps
Cumulative error across 8 cycles tERR(8per) - 241 241 - 217 217 - 193 193 -169 169 -145 145 ps
Cumulative error across 9 cycles tERR(9per) - 249 249 - 224 224 - 200 200 -175 175 -150 150 ps
Cumulative error across 10 cycles tERR(10per) - 257 257 - 231 231 - 205 205 -180 180 -154 154 ps
Cumulative error across 11 cycles tERR(11per) - 263 263 - 237 237 - 210 210 -184 184 -158 158 ps
Cumulative error across 12 cycles tERR(12per) - 269 269 - 242 242 - 215 215 -188 188 -161 161 ps
Cumulative error across n = 13, 14 ... 49, 50 cycles tERR(nper) tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 + 0.68ln(n))*tJIT(per)max ps 24
Absolute clock HIGH pulse width tCH(abs) 0.43 -0.43 -0.43 -0.43 -0.43 -tCK(avg) 25
Absolute clock Low pulse width tCL(abs) 0.43 -0.43 -0.43 -0.43 -0.43 -tCK(avg) 26
Data Timing
DQS,DQS to DQ skew, per group, per access tDQSQ -200 -150 -125 -100 -85 ps 13
DQ output hold time from DQS, DQS tQH 0.38 -0.38 -0.38 -0.38 -0.38 -tCK(avg) 13, g
DQ low-impedance time from CK, CK tLZ(DQ) -800 400 -600 300 -500 250 -450 225 -390 195 ps 13,14, f
DQ high-impedance time from CK, CK tHZ(DQ) -400 -300 -250 -225 -195 ps 13,14, f
Data setup time to DQS, DQS referenced to
VIH(AC)VIL(AC) levels
1.35V
tDS(base)
AC160 90 -40 -------psd, 17
tDS(base)
AC135 140 -90 -45 -25 - - - ps d, 17
tDS(base)
AC125 --------10 -ps d, 17
1.5V
tDS(base)
AC175 75 -25 -------ps d, 17
tDS(base)
AC150 125 -75 -30 -10 - - - ps d, 17
tDS(base)
AC135 --------68 -ps d, 17
Data hold time from DQS, DQS referenced to
VIH(DC)VIL(DC) levels
1.35V
tDH(base)
DC90 160 -110 -75 -55 -30 -ps d, 17
1.5V
tDH(base)
DC100 150 -100 -65 -45 -20 -ps d, 17
DQ and DM Input pulse width for each input tDIPW 600 -490 -400 -360 -320 -ps 28
- 50 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 52 ] Timing Parameters by Speed Bin (Cont.)
Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866
Units NOTE
Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Data Strobe Timing
DQS, DQS differential READ Preamble tRPRE 0.9 Note 19 0.9 Note 19 0.9 Note 19 0.9 Note 19 0.9 NOTE 19 tCK(avg) 13, 19, g
DQS, DQS differential READ Postamble tRPST 0.3 Note 11 0.3 Note 11 0.3 Note 11 0.3 Note 11 0.3 NOTE 11 tCK(avg) 11, 13, b
DQS, DQS differential output high time tQSH 0.38 -0.38 -0.4 -0.4 -0.4 -tCK(avg) 13, g
DQS, DQS differential output low time tQSL 0.38 -0.38 -0.4 -0.4 -0.4 -tCK(avg) 13, g
DQS, DQS differential WRITE Preamble tWPRE 0.9 -0.9 -0.9 -0.9 -0.9 -tCK(avg)
DQS, DQS differential WRITE Postamble tWPST 0.3 -0.3 -0.3 -0.3 -0.3 -tCK(avg)
DQS, DQS rising edge output access time from rising
CK, CK tDQSCK -400 400 -300 300 -255 255 -225 225 -195 195 ps 13,f
DQS, DQS low-impedance time (Referenced from RL-
1) tLZ(DQS) -800 400 -600 300 -500 250 -450 225 -390 195 ps 13,14,f
DQS, DQS high-impedance time (Referenced from
RL+BL/2) tHZ(DQS) -400 -300 -250 -225 -195 ps 12,13,14
DQS, DQS differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg) 29, 31
DQS, DQS differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg) 30, 31
DQS, DQS rising edge to CK, CK rising edge tDQSS -0.25 0.25 -0.25 0.25 -0.25 0.25 -0.27 0.27 -0.27 0.27 tCK(avg) c
DQS,DQS falling edge setup time to CK, CK rising edge tDSS 0.2 -0.2 -0.2 -0.18 -0.18 -tCK(avg) c, 32
DQS,DQS falling edge hold time to CK, CK rising edge tDSH 0.2 -0.2 -0.2 -0.18 -0.18 -tCK(avg) c, 32
Command and Address Timing
DLL locking time tDLLK 512 -512 -512 -512 -512 -nCK
internal READ Command to PRECHARGE Command
delay tRTP
max
(4nCK,7.5
ns)
-
max
(4nCK,7.5
ns)
-
max
(4nCK,7.5n
s)
-
max
(4nCK,7.5
ns)
-
max
(4nCK,7.5
ns)
- e
Delay from start of internal write transaction to internal
read command tWTR
max
(4nCK,7.5
ns)
-
max
(4nCK,7.5
ns)
-
max
(4nCK,7.5n
s)
-
max
(4nCK,7.5
ns)
-
max
(4nCK,7.5
ns)
-e,18
WRITE recovery time tWR 15 -15 -15 -15 -15 -ns e
Mode Register Set command cycle time tMRD 4 - 4 - 4 - 4 - 4 - nCK
Mode Register Set command update delay tMOD
max
(12nCK,15
ns)
-
max
(12nCK,15
ns)
-
max
(12nCK,15
ns)
-
max
(12nCK,15
ns)
-
max
(12nCK,15
ns)
-
CAS to CAS command delay tCCD 4 - 4 - 4 - 4 - 4 - nCK
Auto precharge write recovery + precharge time tDAL(min) WR + roundup (tRP / tCK(AVG)) nCK
Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - 1 - 1 - nCK 22
ACTIVE to PRECHARGE command period tRAS See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” ns e
ACTIVE to ACTIVE command period for 1KB page size tRRD
max
(4nCK,10n
s)
-
max
(4nCK,7.5
ns)
-max
(4nCK,6ns) -
max
(4nCK,6ns
)
-
max
(4nCK,
5ns)
- e
ACTIVE to ACTIVE command period for 2KB page size tRRD
max
(4nCK,10n
s)
-
max
(4nCK,10n
s)
-
max
(4nCK,7.5n
s)
-
max
(4nCK,7.5
ns)
-
max
(4nCK,
6ns)
- e
Four activate window for 1KB page size tFAW 40 -37.5 -30 -30 -27 -ns e
Four activate window for 2KB page size tFAW 50 -50 -45 -40 -35 -ns e
Command and Address setup time to CK, CK refer-
enced to VIH(AC) / VIL(AC) levels
1.35V
tIS(base)
AC160 215 -140 -80 -60 - - - ps b,16
tIS(base)
AC135 365 -290 -205 -185 - - - ps b,16,27
tIS(base)
AC125 - - - - - - - - 75 -ps b,16,27
1.5V
tIS(base)
AC175 200 -125 -65 -45 - - - ps b,16
tIS(base)
AC150 350 -275 -190 -170 - - - ps b,16,27
tIS(base)
AC135 ----- - - - 65 -ps b,16
tIS(base)
AC125 ----- - - - 150 -ps b,16,27
- 51 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 52 ] Timing Parameters by Speed Bin (Cont.)
Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866
Units NOTE
Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Command and Address Timing
Command and Address hold time from CK, CK refer-
enced to VIH(DC) / VIL(DC) levels
1.35V
tIH(base)
DC90 285 -210 -150 -130 -110 -ps b,16
1.5V
tIH(base)
DC100 275 200 140 120 -100 -ps b,16
Control & Address Input pulse width for each input tIPW 900 -780 -620 -560 -535 -ps 28
Calibration Timing
Power-up and RESET calibration time tZQinitI 512 -512 -512 -512 -
max(512n
CK,640ns
)
-nCK
Normal operation Full calibration time tZQoper 256 -256 -256 -256 -
max(256n
CK,320ns
)
-nCK
Normal operation short calibration time tZQCS 64 -64 -64 -64 -max(64nC
K,80ns) -nCK 23
Reset Timing
Exit Reset from CKE HIGH to a valid command tXPR
max(5nC
K, tRFC +
10ns)
-
max(5nC
K, tRFC +
10ns)
-
max(5nC
K, tRFC +
10ns)
-
max(5nC
K, tRFC +
10ns)
-
max(5nC
K,
tRFC(min)
+ 10ns)
-
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked
DLL tXS
max(5nC
K,tRFC +
10ns)
-
max(5nC
K,tRFC +
10ns)
-
max(5nC
K,tRFC +
10ns)
-
max(5nC
K,tRFC +
10ns)
-
max(5nC
K,tRFC(m
in) + 10ns)
-
Exit Self Refresh to commands requiring a locked
DLL tXSDLL tDLLK(mi
n) -tDLLK(mi
n) -tDLLK(mi
n) -tDLLK(mi
n) -tDLLK(mi
n) -nCK
Minimum CKE low width for Self refresh entry to exit
timing tCKESR tCKE(min
) + 1tCK -tCKE(min
) + 1tCK -tCKE(min
) + 1tCK -tCKE(min)
+ 1tCK -tCKE(min)
+ 1nCK -
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE) tCKSRE
max(5nC
K,
10ns)
-
max(5nC
K,
10ns)
-
max(5nC
K,
10ns)
-
max(5nC
K,
10ns)
-
max(5nC
K,
10ns)
-
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit tCKSRX
max(5nC
K,
10ns)
-
max(5nC
K,
10ns)
-
max(5nC
K,
10ns)
-
max(5nC
K,
10ns)
-
max(5nC
K,
10ns)
-
Power Down Timing
Exit Power Down with DLL on to any valid com-
mand;Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
tXP
max
(3nCK,
7.5ns)
-
max
(3nCK,
7.5ns)
-
max
(3nCK,6n
s)
-
max
(3nCK,6n
s)
-max(3nC
K,6ns) -
Exit Precharge Power Down with DLL frozen to com-
mands requiring a locked DLL tXPDLL
max
(10nCK,
24ns)
-
max
(10nCK,
24ns)
-
max
(10nCK,
24ns)
-
max
(10nCK,
24ns)
-max(10nC
K,24ns) - 2
CKE minimum pulse width tCKE
max
(3nCK,
7.5ns)
-
max
(3nCK,
5.625ns)
-
max
(3nCK,
5.625ns)
-
max
(3nCK,5n
s)
-max(3nC
K,5ns) -
Command pass disable delay tCPDED 1 - 1 - 1 - 1 - 2 - nCK
Power Down Entry to Exit Timing tPD tCKE(min
)9*tREFI tCKE(min
)9*tREFI tCKE(min
)9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCK(avg) 15
Timing of ACT command to Power Down entry tACTPDEN 1 - 1 - 1 - 1 - 1 - nCK 20
Timing of PRE command to Power Down entry tPRPDEN 1 - 1 - 1 - 1 - 1 - nCK 20
Timing of RD/RDA command to Power Down entry tRDPDEN RL + 4 +1 -RL + 4 +1 -RL + 4 +1 -RL + 4 +1 -RL + 4 +1 -
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF) tWRPDEN
WL + 4
+(tWR/
tCK(avg))
-
WL + 4
+(tWR/
tCK(avg))
-
WL + 4
+(tWR/
tCK(avg))
-
WL + 4
+(tWR/
tCK(avg))
-
WL + 4
+(tWR/
tCK(avg))
-nCK 9
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF) tWRAPDEN WL + 4
+WR +1 -WL + 4
+WR +1 -WL + 4
+WR +1 -WL + 4
+WR +1 -WL + 4
+WR +1 -nCK 10
Timing of WR command to Power Down entry
(BC4MRS) tWRPDEN
WL + 2
+(tWR/
tCK(avg))
-
WL + 2
+(tWR/
tCK(avg))
-
WL + 2
+(tWR/
tCK(avg))
-
WL + 2
+(tWR/
tCK(avg))
-
WL + 2
+(tWR/
tCK(avg))
-nCK 9
Timing of WRA command to Power Down entry
(BC4MRS) tWRAPDEN WL +2
+WR +1 -WL +2
+WR +1 -WL +2
+WR +1 -WL +2
+WR +1 -WL +2
+WR +1 -nCK 10
Timing of REF command to Power Down entry tREFPDEN 1 - 1 - 1 - 1 - 1 - 20,21
Timing of MRS command to Power Down entry tMRSPDEN tMOD(mi
n) -tMOD(mi
n) -tMOD(mi
n) -tMOD(min
)-tMOD(min
)-
ODT Timing
ODT high time without write command or with write
command and BC4 ODTH4 4 - 4 - 4 - 4 - 4 - nCK
ODT high time with Write command and BL8 ODTH8 6 - 6 - 6 - 6 - 6 - nCK
- 52 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 52 ] Timing Parameters by Speed Bin
Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866
Units NOTE
Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
ODT Timing
Asynchronous RTT turn-on delay (Power-Down with
DLL frozen) tAONPD 28.5 28.5 28.5 28.5 28.5 ns
Asynchronous RTT turn-off delay (Power-Down with
DLL frozen) tAOFPD 28.5 28.5 28.5 28.5 28.5 ns
RTT turn-on tAON -400 400 -300 300 -250 250 -225 225 -195 195 ps 7,f
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference tAOF 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) 8,f
RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) f
Write Leveling Timing
First DQS/DQS rising edge after write
leveling mode is programmed tWLMRD 40 -40 -40 -40 -40 -tCK(avg) 3
DQS/DQS delay after write leveling
mode is programmed tWLDQSEN 25 -25 -25 -25 -25 -tCK(avg) 3
Write leveling setup time from rising CK, CK crossing
to rising DQS, DQS crossing tWLS 325 -245 -195 -165 -140 -ps
Write leveling hold time from rising DQS, DQS cross-
ing to rising CK, CK crossing tWLH 325 -245 -195 -165 -140 -ps
Write leveling output delay tWLO 0 9 0 9 0 9 0 7.5 07.5 ns
Write leveling output error tWLOE 0 2 0 2 0 2 0 2 0 2 ns
- 53 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
14.1 Jitter Notes
Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the
input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm,
another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
Specific Note b These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition
edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is,
these parameters should be met whether clock jitter is present or not.
Specific Note c These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK)
crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative
to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
Specific Note d These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data
strobe signal (DQS(L/U), DQS(L/U)) crossing.
Specific Note e For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)},
which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the
device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge com-
mand at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.
Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input
clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = +
193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(der-
ated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to
tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the
min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=
12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input
clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has
tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min +
tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) =
tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/
max usage!)
- 54 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
14.2 Timing Parameter Notes
1. Actual value dependant upon measurement level definitions see "Device Operation & Timing Diagram Datasheet".
2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register
5. Value must be rounded-up to next higher integer value
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"
8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles as programmed in MR0
11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing
Diagram Datasheet.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated
by 14.1-Jitter Notes on page 53
13. Value is only valid for RON34
14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.
15. tREFI depends on TOPER
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,
VREF(DC) = VREFDQ(DC). For input only pins except RESET, VREF(DC)=VREFCA(DC).
See Address/Command Setup, Hold and Derating : on page 55. .
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,
VREF(DC)= VREFDQ(DC). For input only pins except RESET, VREF(DC)=VREFCA(DC).
See Data Setup, Hold and Slew Rate Derating : on page 64.
18. Start of internal write transaction is defined as follows ;
For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL
19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram Data-
sheet"
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down
IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time
such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming
the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-
ject to in the application, is illustrated. The interval could be defined by the following formula:
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% /C, VSens = 0.15% / mV, Tdriftrate = 1C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu-
lated as:
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-
nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
28. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC)
29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.
30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.
31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
0.5
(1.5 x 1) + (0.15 x 15) = 0.133
~
~
128ms
- 55 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
14.3 Address/Command Setup, Hold and Derating :
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see
Table 53) to the tIS and tIH derating value (see Table 55) respectively.
Example: tIS (total setup time) = tIS(base) + tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(DC) to ac
region’, use nominal slew rate for derating value (see 21-Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and
tIS on page 60). If the actual signal is later than the nominal slew rate line anywhere between shaded ’VREF(DC) to ac region’, the slew rate of a tangent
line to the actual signal from the ac level to dc level is used for derating value (see 23-Illustration of tangent line for setup time tDS (for DQ with respect to
strobe) and tIS on page 62).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC).
Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If
the actual signal is always later than the nominal slew rate line between shaded ’dc to VREF(DC) region’, use nominal slew rate for derating value (see 22-
Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH on page 61). If the actual signal is earlier than the nominal slew
rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used
for derating value (see 24-Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH on page 63).
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see Table 51).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in Table 55, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
[ Table 53 ] ADD/CMD Setup and Hold Base-Values for 1V/ns (1.35V)
NOTE :
1. AC/DC referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate
2. The tIS(base) AC135 specifications are adjusted from the tIS(base) AC160 specification by adding an additional 125 ps for DDR3L-800/1066 or 100ps for DDR3L-1333/1600
of derating to accommodate for the lower alternate threshold of 135 mV and another 25 ps to account for the earlier reference point [(160mv - 135 mV) / 1 V/ns].
3. The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75 ps for DDR3L-1866 of derating to accommodate for the
lower alternate threshold of 135 mV and another 10 ps to account for the earlier reference point [(135mv - 125 mV) / 1 V/ns].
[ Table 54 ] ADD/CMD Setup and Hold Base-Values for 1V/ns (1.5V)
NOTE:
1.AC/DC referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate
2.The tIS(base) AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 125 ps for DDR3-800/1066 or 100ps for DDR3-1333/1600 of
derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
3.The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75 ps for DDR3-1866 and 65ps for DDR3-2133 to
accommodate for the lower alternate threshold of 125 mV and another 10 ps to account for the earlier reference point [(135 mv - 125 mV) / 1 V/ns].
[ps] DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 reference Note
DDR3L
tIS(base) AC160 215 140 80 60 -V
IH/L(AC) 1
tIS(base) AC135 365 290 205 185 65 VIH/L(AC) 1,2
tIS(base) AC125 ----150 VIH/L(AC) 1,3
tIH(base)-DC90 285 210 150 130 110 VIH/L(DC) 1
[ps] DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 reference
DDR3
tIS(base) AC175 200 125 65 45 -V
IH/L(AC)
tIS(base) AC150 350 275 190 170 -V
IH/L(AC)
tIS(base) AC135 ----65 VIH/L(AC)
tIS(base) AC125 ----150 VIH/L(AC)
tIS(base) AC100 275 200 140 120 100 VIH/L(DC)
- 56 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 55 ] Derating values DDR3L-800/1066/1333/1600 tIS/tIH-AC/DC based AC160 Threshold (1.35V)
[ Table 56 ] Derating values DDR3L-800/1066/1333/1600 tIS/tIH-AC/DC based - Alternate AC135 Threshold (1.35V)
[ Table 57 ] Derating values DDR3L-1866 tIS/tIH-AC/DC based - Alternate AC125 Threshold (1.35V)
tIS, tIH Derating [ps] AC/DC based
AC160 Threshold -> VIH(AC) = VREF(DC) + 160mV, VIL(AC) = VREF(DC) - 160mV
CLK,CLK Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH
CMD/
ADD
Slew
rate
V/ns
2.080458045804588539661104691127912095
1.553305330533061386946775485649380
1.0000000881616242432344050
0.9-1-3-1-3-1-3 7 51513232131313947
0.8-3-8-3-8-3-8 5 1139211729273743
0.7 -5 -13 -5 -13 -5 -13 3 -5 11 3 19 11 27 21 35 37
0.6 -8 -20 -8 -20 -8 -20 0 -12 8 -4 16 4 24 14 32 30
0.5 -20 -30 -20 -30 -20 -30 -12 -22 -4 -14 4 -6 12 4 20 20
0.4 -40 -45 -40 -45 -40 -45 -32 -37 -24 -29 -16 -21 -8 -11 0 5
tIS, tIH Derating [ps] AC/DC based
Alternate AC135 Threshold -> VIH(AC) = VREF(DC) + 135mV, VIL(AC) = VREF(DC) - 135mV
CLK,CLK Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH
CMD/
ADD
Slew
rate
V/ns
2.06845684568457653846192691007910895
1.545304530453053386146695477648580
1.0000000881616242432344050
0.9 2 -3 2 -3 2 -310 5 1813262134314247
0.8 3 -8 3 -8 3 -8 11 1 19 9 271735274343
0.7 6 -13 6 -13 6 -13 14 -5 22 3 30 11 38 21 46 37
0.69-209-209-2017-1225-433 4 41144930
0.5 5 -30 5 -30 5 -30 13 -22 21 -14 29 -6 37 4 45 20
0.4 -3 -45 -3 -45 -3 -45 6 -37 14 -29 22 -21 30 -11 38 5
tIS, tIH Derating [ps] AC/DC based
Alternate AC135 Threshold -> VIH(AC) = VREF(DC) + 125mV, VIL(AC) = VREF(DC) - 125mV
CLK,CLK Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH
CMD/
ADD
Slew
rate
V/ns
2.0634563456345715379618769957910395
1.542304230423050385846665474648280
1.0000000881616242432344050
0.9 3 -3 3 -3 3 -3 11 5 19 13 27 21 35 31 43 47
0.86-8 6 -86-8141229301738274643
0.7 10 -13 10 -13 10 -13 18 -5 26 3 34 11 42 21 50 37
0.6 16 -20 16 -20 16 -20 24 -12 32 4 40 -4 48 14 56 30
0.5 15 -30 15 -30 15 -30 23 -22 31 -14 39 -6 47 4 55 20
0.4 13 -45 13 -45 13 -45 21 -37 29 -29 37 -21 45 -11 53 5
- 57 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 58 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-AC/DC based AC175 Threshold(1.5V)
[ Table 59 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-AC/DC based AC150 Threshold (1.5V)
[ Table 60 ] Derating values DDR3-1866 tIS/tIH-AC/DC based Alternate AC135 Threshold (1.5V)
tIS, tIH Derating [ps] AC/DC based
Alternate AC175 Threshold -> VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV
CLK,CLK Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH
CMD/
ADD
Slew
rate
V/ns
2.08850885088509658104661127412084128100
1.559345934593467427550835891689984
1.0000000881616242432344050
0.9-2-4-2-4-2-4 6 41412222030303846
0.8-6-10-6-10-6-10 2 -210 6 181426243440
0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34
0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24
0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10
0.4 -62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10
tIS, tIH Derating [ps] AC/DC based
Alternate AC150 Threshold -> VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV
CK,CK Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH
CMD/
ADD
Slew
rate
V/ns
2.075507550755083589166997410784115100
1.550345034503458426650745882689084
1.0000000881616242432344050
0.9 0 -4 0 -4 0 -4 8 4 1612242032304046
0.8 0 -100-10 0-10 8 -2 16 6 241432244040
0.70-160-160-168-816024832184034
0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24
0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10
0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10
tIS, tIH Derating [ps] AC/DC based
Alternate AC125 Threshold -> VIH(AC) = VREF(DC) + 135mV, VIL(AC) = VREF(DC) - 135mV
CLK,CLK Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH
CMD/
ADD
Slew
rate
V/ns
2.068506850685076588466927410084108100
1.545344534453453426150695877688584
1.0000000881616242432344050
0.9 2 -4 2 -4 2 -4 10 4 1812262034304246
0.8 3 -10 3 -10 3 -1011 -2 19 6 271435244340
0.7 6 -16 6 -16 6 -16 14 -8 22 0 30 8 38 18 46 34
0.6 9 -26 9 -26 9 -26 17 -18 25 -10 33 -2 41 8 49 24
0.5 5 -40 5 -40 5 -40 13 -32 21 -24 29 -16 37 -6 45 10
0.4 -3 -60 -3 -60 -3 -60 6 -52 14 -44 22 -36 30 -26 38 -10
- 58 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 61 ] Derating values DDR3-1866 tIS/tIH-AC/DC based - Alternate AC125 Threshold
[ Table 62 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid ADD/CMD transition (1.35V)
NOTE : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
tIS, tIH Derating [ps] AC/DC based
Alternate AC125 Threshold -> VIH(AC) = VREF(DC) + 125mV, VIL(AC) = VREF(DC) - 125mV
CLK,CLK Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH
CMD/
ADD
Slew
rate
V/ns
2.06350635063507158796687749584103100
1.542344234423450425850665874688284
1.0000000881616242432344050
0.9 4 -4 4 -4 4 -4 12 4 2012282036304446
0.8 6 -10 6 -10 6 -10 14 -2 22 6 30 14 38 24 46 40
0.7 11 -16 11 -16 11 -16 19 -8 27 0 35 8 43 18 51 34
0.6 16 -26 16 -26 16 -26 24 -18 32 -10 40 -2 48 8 56 24
0.5 15 -40 15 -40 15 -40 23 -32 31 -24 39 -16 47 -6 55 10
0.4 13 -60 13 -60 13 -60 21 -52 29 -44 37 -36 45 -26 53 -10
Slew Rate[V/ns]
1.35V
DDR3L-800/1066/1333/1600 DDR3L-1866
tVAC @160mV [ps] tVAC @135mV [ps] tVAC @135mV [ps] tVAC @125mV [ps]
min max min max min max min max
>2.0 200 - 213 - 200 - 205 -
2.0 200 - 213 -200 - 205 -
1.5 173 - 190 - 178 - 184 -
1.0 120 - 145 -133 -143 -
0.9 102 - 130 - 118 - 129 -
0.8 80 -111-99 -111 -
0.7 51 - 87 - 75 - 89 -
0.6 13 -55-43 -59 -
0.5 Note - 10 - Note - 18 -
< 0.5 Note -10-Note-18-
- 59 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 63 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid ADD/CMD transition (1.5V)
NOTE : Note: Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
Slew Rate[V/ns]
1.5V
DDR3-800/1066/1333/1600 DDR3-1866
tVAC @175mV [ps] tVAC @150mV [ps] tVAC @135mV [ps] tVAC @125mV [ps]
min max min max min max min max
>2.0 75 - 175 - 168 - 173 -
2.0 57 - 170 - 168 - 173 -
1.5 50 - 167 - 145 - 152 -
1.0 38 - 130 -100 - 110 -
0.9 34 - 113 - 85 - 96 -
0.8 29 -93-66 - 79 -
0.7 22 - 66 - 42 - 56 -
0.6 Note -30-10 - 27 -
0.5 Note - Note - Note - Note -
< 0.5 Note -Note-Note-Note-
- 60 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
Figure 21. Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock).
VSS
CK
CK
tDS tDH
Setup Slew Rate
Setup Slew Rate
Rising Signal
Falling Signal
TF TR
VREF(DC) - VIL(AC)max
TF
=VIH(AC)min - VREF(DC)
TR
=
VDDQ
VIH(AC) min
VIH(DC) min
VREF(DC)
VIL(DC) max
VIL(AC) max
nominal slew
rate
nominal
slew rate
VREF to ac
region
VREF to ac
region
tIS tIH
tDS tDH
tIS tIH
tVAC
tVAC
NOTE :Clock and Strobe are drawn on a different time scale.
DQS
DQS
- 61 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
Figure 22. Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock).
VSS
CK
CK
Hold Slew Rate
Hold Slew Rate
Falling Signal
Rising Signal
TR TF
VREF(DC) - VIL(DC)max
TR
=VIH(DC)min - VREF(DC)
TF
=
VDDQ
VIH(AC) min
VIH(DC) min
VREF(DC)
VIL(DC) max
VIL(AC) max
nominal
slew rate
nominal
slew rate
dc to VREF
region
tIS tIH tIS tIH
dc to VREF
region
NOTE :Clock and Strobe are drawn on a different time scale.
tDS tDH tDS tDH
DQS
DQS
- 62 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
Figure 23. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock)
VSS
Setup Slew Rate
Setup Slew Rate
Rising Signal
Falling Signal
TF
TR
tangent line[VREF(DC) - VIL(AC)max]
TF
=
tangent line[VIH(AC)min - VREF(DC)]
TR
=
VDDQ
VIH(AC) min
VIH(DC) min
VREF(DC)
VIL(DC) max
VIL(AC) max
tangent
tangent
VREF to ac
region
VREF to ac
region
line
line
nominal
line
nominal
line
CK
CK
tIS tIH tIS tIH
tVAC
NOTE :Clock and Strobe are drawn on a different time scale.
tDS tDH tDS tDH
DQS
DQS
tVAC
- 63 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
Figure 24. Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock)
VSS
Hold Slew Rate
TF
TR
tangent line [ VIH(DC)min - VREF(DC) ]
TF
=
VDDQ
VIH(AC) min
VIH(DC) min
VREF(DC)
VIL(DC) max
VIL(AC) max
tangent
tangent
dc to VREF
region
dc to VREF
region
line
line
nominal
line
nominal
line
Falling Signal
Hold Slew Rate tangent line [ VREF(DC) - VIL(DC)max ]
TR
=
Rising Signal
CK
CK
tIS tIH tIS tIH
NOTE :Clock and Strobe are drawn on a different time scale.
tDS tDH tDS tDH
DQS
DQS
- 64 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
14.4 Data Setup, Hold and Slew Rate Derating :
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value (see
Table 64) to the tDS and tDH (see Table 55) derating value respectively. Example: tDS (total setup time) = tDS(base) + tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min.
Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max
(see 25-Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS on page 68). If the actual signal is always ear-
lier than the nominal slew rate line between shaded ’VREF(DC) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the
nominal slew rate line anywhere
between shaded ’VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see 27-
Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS on page 70).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC).
Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC)
(see - on page 69). If the actual signal is always later than the nominal slew rate line between shaded ’dc level to VREF(DC) region’, use nominal slew rate
for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tan-
gent line to the actual signal from the dc level to VREF(DC) level is used for derating value (see 28-Illustration of tangent line for hold time tDH (for DQ with
respect to strobe) and tIH on page 71).
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see Table 56).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
[ Table 64 ] Data Setup and Hold Base-Values
NOTE :
1. AC/DC referenced for 2V/ns DQ-slew rate and 4V/ns DQS slew rate
2. AC/DC referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate
3. Optional in DDR3 SDRAM
[ Table 65 ] Derating values DDR3L-800/1066 tDS/tDH-AC/DC based - AC160(1.35V)
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
[ps] reference DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 NOTE
DDR3
tDS(base) AC175 VIH/L(AC)SR=1V/ns 75 25 - - - 2
tDS(base) AC150 VIH/L(AC)SR=1V/ns 125 75 30 10 - 2
tDS(base) AC135 VIH/L(AC)SR=1V/ns 165 115 60 40 -2,3
tDS(base) AC135 VIH/L(AC)SR=2V/ns ----68 1
tDH(base) DC100 VIH/L(DC)SR=1V/ns 150 100 65 45 - 3
tDH(base) DC100 VIH/L(DC)SR=2V/ns ----70 1
DDR3L
tDS(base) AC160 VIH/L(DC)SR=1V/ns 90 40 - - - 2
tDS(base) AC135 VIH/L(DC)SR=1V/ns 140 90 45 25 - 2
tDS(base) AC135 VIH/L(DC)SR=2V/ns ----70 1
tDH(base) DC90 VIH/L(DC)SR=1V/ns 160 110 75 55 - 2
tDH(base) DC90 VIH/L(DC)SR=2V/ns ----75 1
tDS, tDH Derating in [ps] AC/DC based1
AC160 Threshold -> VIH(ac)=VREF(dc)+160mV, VIL(ac)=VREF(dc)-160mV
DQS,DQS Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ
Slew
rate
V/ns
2.0804580458045 - - - - - - - - - -
1.55330533053306138 - - - - - - - -
1.0000000881616
- - - - - -
0.9 -- -1-3-1-3 7 515132321 - - - -
0.8 ---- -3 -8 5 1 13 9 21 17 29 27 - -
0.7 ------ 3 -5 11 3 191127213537
0.6 -------- 8 -4 16 4 24143230
0.5 ----------4-61242020
0.4 -------------8-1105
- 65 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 66 ] Derating values for DDR3L-800/1066/1333/1600 tDS/tDH - AC135 (1.35V)
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
[ Table 67 ] Derating values for DDR3L-1866 tDS/tDH - AC130 (1.35V)
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
[ Table 68 ] Derating values DDR3-800/1066 tDS/tDH - AC175 (1.5V)
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
tDS, tDH Derating in [ps] AC/DC based1
Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV
DQS,DQS Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ
Slew
rate
V/ns
2.0684568456845 - - - - - - - -
1.54530453045305338 - - - - - - - -
1.0000000881616- - - - - -
0.9 - - 2 -3 2 -3 10 5 18 13 26 21 - - - -
0.8 - - - - 3 -8 11 1 19 9 27 17 35 27 - -
0.7 - - - - - - 14 -5 22 3 30 11 38 21 46 37
0.6 - - - - - - - - 25 -4 33 4 41 14 49 30
0.5----------29-63744520
0.4------------30-11385
tDS, tDH Derating in [ps] AC/DC based1
Alternate AC130 Threshold -> VIH(ac)=VREF(dc)+130mV, VIL(ac)=VREF(dc)-130mV
DQS,DQS Differential Slew Rate
8.0 V/ns 7.0 V/ns 6.0 V/ns 5.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ
Slew
rate
V/ns
4.0332333233323------------------
3.52819281928192819----------------
3.022152215221522152215--------------
2.5--139139139139139------------
2.0----0000000000- - --------
1.5-------22-15-22-15-22-15-22-15-14-7--------
1.0---------65-45-65-45-65-45-57-37-49-29------
0.9-----------62-48-62-48-54-40-46-32-38-24----
0.8-------------61-53-53-45-45-37-37-29-29-19--
0.7---------------49-50-41-42-33-34-25-24-17-8
0.6-----------------37-49-29-41-21-31-13-15
0.5-------------------31-51-23-41-15-25
0.4---------------------28-56-20-40
tDS, tDH Derating in [ps] AC/DC based1
DQS,DQS Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ
Slew
rate
V/ns
2.0885088508850----------
1.55934593459346742 - - - - - - - -
1.0000000881616- - - - - -
0.9- - -2-4-2-4 6 414122220 - - - -
0.8 - - - - -6 -10 2 -2 10 6 18 14 26 24 - -
0.7-------3-85013821182934
0.6---------1-107-21582324
0.5-----------11-16-2-6610
0.4-------------30-26-22-10
- 66 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 69 ] Derating values for DDR3-800/1066/1333/1600 tDS/tDH - AC150 (1.5V)
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
[ Table 70 ] Derating values for DDR3-1866 tDS/tDH - AC135 (1.5V)
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
[ Table 71 ] Derating values for DDR3-800/1066/1333/1600 tDS/tDH - AC135 (1.5V)
NOTE : 1. Cell contents shaded in red are defined as ’not supported’.
tDS, tDH Derating in [ps] AC/DC based1
DQS,DQS Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ
Slew
rate
V/ns
2.0755075507550----------
1.55034503450345842 - - - - - - - -
1.0000000881616- - - - - -
0.9- - 0 -4 0 -4 8 4 16122420 - - - -
0.8 - - - - 0 -10 8 -2 16 6 24 14 32 24 - -
0.7 - - - - - - 8 -8 16 0 24 8 32 18 40 34
0.6--------15-1023-23183924
0.5----------14-1622-63010
0.4------------7-2615-10
tDS, tDH derating in [ps] AC/DC based
Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV
Alternate DC 100 Threshold -> VIH(dc)=VREF(dc)+100mV, VIL(dc)=VREF(dc)-100mV
DQS,DQS Differential Slew Rate
8.0 V/ns 7.0 V/ns 6.0 V/ns 5.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ
Slew
rate
V/ns
4.0342534253425------------------
3.52921292129212921----------------
3.023172317231723172317 - - - - - - - - - - - - - -
2.5--14101410141014101410------------
2.0- - - - 0000000000 - - - - - - - - - -
1.5 - - - - - - -23 -17 -23 -17 -23 -17 -23 -17 -15 -9 - - - - - - - -
1.0 - - - - - - - - -68 -50 -68 -50 -68 -50 -60 -42 -52 -34 - - - - - -
0.9 - - - - - - - - - - -66 -54 -66 -54 -58 -46 -50 -38 -42 -30 - - - -
0.8-------------64-60-56-52-48-44-40-36-32-36--
0.7 - - - - - - - - - - - - - - -53 -59 -45 -51 -37 -43 -29 -33 -21 -17
0.6-----------------43-61-35-53-27-43-19-27
0.5-------------------39-66-31-56-23-40
0.4---------------------38-76-30-60
tDS, tDH derating in [ps] AC/DC based
Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV
Alternate DC 100 Threshold -> VIH(dc)=VREF(dc)+100mV, VIL(dc)=VREF(dc)-100mV
DQS,DQS Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4V/ns 1.2V/ns 1.0V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ
Slew
rate
V/ns
2.0685068506850----------
1.54534453445345342 - - - - - - - -
1.0000000881616- - - - - -
0.9 - - 2 -4 2 -4 10 4 18 12 26 20 - - - -
0.8 - - - - 3 -10 11 -2 19 6 27 14 35 24 - -
0.7------14-822030838184634
0.6--------25-1033-24184924
0.5----------29-1637-64510
0.4------------30-2638-10
- 67 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
[ Table 72 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid DQ transition (1.35V)
NOTE : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
[ Table 73 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid DQ transition (1.5V)
NOTE : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
Slew Rate[V/ns]
1.35V
DDR3L-800/1066 (AC160) DDR3L-800/1066/1333/1600 (AC135) DDR3L-1866 (AC130)
tVAC[ps] tVAC[ps] tVAC[ps]
min max min max min max
>2.0 165 - 113 - 95 -
2.0 165 -113 -95 -
1.5 138 - 90 - 73 -
1.0 85 -45 -30 -
0.9 67 - 30 - 16 -
0.8 45 -11 -Note-
0.7 16 - Note - - -
0.6 Note -Note---
0.5 Note - Note - - -
<0.5 Note -Note---
Slew Rate[V/ns]
tVAC[ps] DDR3-800/1066
(AC175)
tVAC[ps] DDR3-800/1066/
1333/1600 (AC150)
tVAC[ps] DDR3-800/1066/
1333/1600 (AC135)
tVAC[ps] DDR3-1866
(AC135)
min max min max min max min max
>2.0 75 - 105 - 113 - 93 -
2.0 57 -105 -113 - 93 -
1.5 50 - 80 - 90 - 70 -
1.0 38 -30 -45 - 25 -
0.9 34 - 13 - 30 - note -
0.8 29 -note -11 - note -
0.7 note - note - note - - -
0.6 note -note -note - - -
0.5 note - note - note - - -
<0.5 note -note -note - - -
- 68 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
Figure 25. Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock).
VSS
CK
CK
tDS tDH
Setup Slew Rate
Setup Slew Rate
Rising Signal
Falling Signal
TF TR
VREF(DC) - VIL(AC)max
TF
=VIH(AC)min - VREF(DC)
TR
=
VDDQ
VIH(AC) min
VIH(DC) min
VREF(DC)
VIL(DC) max
VIL(AC) max
nominal slew
rate
nominal
slew rate
VREF to ac
region
VREF to ac
region
tIS tIH
tDS tDH
tIS tIH
tVAC
tVAC
NOTE :Clock and Strobe are drawn on a different time scale.
DQS
DQS
- 69 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
Figure 26. Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock).
VSS
CK
CK
Hold Slew Rate
Hold Slew Rate
Falling Signal
Rising Signal
TR TF
VREF(DC) - VIL(DC)max
TR
=VIH(DC)min - VREF(DC)
TF
=
VDDQ
VIH(AC) min
VIH(DC) min
VREF(DC)
VIL(DC) max
VIL(AC) max
nominal
slew rate
nominal
slew rate
dc to VREF
region
tIS tIH tIS tIH
dc to VREF
region
NOTE :Clock and Strobe are drawn on a different time scale.
tDS tDH tDS tDH
DQS
DQS
- 70 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
Figure 27. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock)
VSS
Setup Slew Rate
Setup Slew Rate
Rising Signal
Falling Signal
TF
TR
tangent line[VREF(DC) - VIL(AC)max]
TF
=
tangent line[VIH(AC)min - VREF(DC)]
TR
=
VDDQ
VIH(AC) min
VIH(DC) min
VREF(DC)
VIL(DC) max
VIL(AC) max
tangent
tangent
VREF to ac
region
VREF to ac
region
line
line
nominal
line
nominal
line
CK
CK
tIS tIH tIS tIH
tVAC
NOTE :Clock and Strobe are drawn on a different time scale.
tDS tDH tDS tDH
DQS
DQS
tVAC
- 71 -
K4B1G1646I datasheet DDR3L SDRAM
Rev. 1.1
Figure 28. Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock)
VSS
Hold Slew Rate
TF
TR
tangent line [ VIH(DC)min - VREF(DC) ]
TF
=
VDDQ
VIH(AC) min
VIH(DC) min
VREF(DC)
VIL(DC) max
VIL(AC) max
tangent
tangent
dc to VREF
region
dc to VREF
region
line
line
nominal
line
nominal
line
Falling Signal
Hold Slew Rate tangent line [ VREF(DC) - VIL(DC)max ]
TR
=
Rising Signal
CK
CK
tIS tIH tIS tIH
NOTE :Clock and Strobe are drawn on a different time scale.
tDS tDH tDS tDH
DQS
DQS
