Advanced CUSTOMER ERRATA AND INFORMATION SHEET Page 1 MCU Part: 68336.F Mask Set: 02F60K Division Report Generated: Jul 09, 96 13:03 ========================================= | 68336.F 02F60K Modules | ========================================= | Current Module Revision | ========================================= | CPU32.16.0 | | CTM4.2.0 | | QADC.7.0 | | QSM.12.0A | | SIM.16.0A | | SRAM_4KA.7.0 | | STDPORT.23.0 | | TPU.7.0 | | TPUSRAM_3.5KB.8.0 | | VCO.13.1 | ========================================= MODULAR_AR_26 Customer Information 68336.F DESCRIPTION: After power-up (Vdd greater than Vdd min.) of the MCU, input/output and output-only port pins on the CPU32 module (IFETCH, IPIPE) may be in an indeterminate state for up to 15 ms (depends on supply ramp up conditions). Input/output pins on this module may be in output mode (instead of high impedance) for a short time, which may create a conflict with external drive logic (was item 68336:002). WORKAROUND: If a known state is required on these pins, before the 15 ms port initialization period, external reset control logic must condition these lines. MODULAR_AR_27 Customer Information 68336.F DESCRIPTION: The VSTBY pin is connected to the TPUSRAM to maintain RAM data when VDD is not present (standby operation). On revisions of the 68336 after Revision C, the VSTBY pin will additionally supply standby power to the 4 K SRAM module (was item 68336:003). WORKAROUND: Not applicable Advanced CUSTOMER ERRATA AND INFORMATION SHEET Page 2 MCU Part: 68336.F Mask Set: 02F60K Division Report Generated: Jul 09, 96 13:03 MODULAR_AR_977 Customer Information 68336.F DESCRIPTION: On revisions older than revision D (revision 0-C) pin 1 was a Vss pin and pin 160 was Vdd. These pins have been made "No Connects" on revision D and newer revisions to allow for pin compatibility with other parts in the family (68376...) which use these as functional pins. WORKAROUND: No change to board layouts required unless newer family parts, such as the 68376 are put into older systems where pins 1 and 160 are supply pins. In this case board modifications will be required. MODULAR_AR_975 Customer Information CPU32.16.0 DESCRIPTION: When a spurious interrupt awakens the MCU from LPSTOP, the spurious interrupt handler is not called, and the CPU sits idle until another IRQ is detected. The effect is the same as if the STOP instruction was actually executed, from the point that the spurious interrupt occurs, instead of the LPSTOP instruction. WORKAROUND: If power consumption is important and LPSTOP is used, do not allow any spurious interrupts to occur during the LPSTOP state. MODULAR_AR_823 Customer Information CPU32.16.0 DESCRIPTION: In previous versions of this module, when exiting BDM, FREEZE negated after the DSI/FETCH signal turns around from an input to an output. This meant that an external development system could be driving DSI while the MPU was still driving IFETCH. The timing has been changed to insure that on exit of BDM FREEZE is negated prior to IFETCH changing to an output. Also, on entry to BDM, the DSI/IFETCH pin goes to a high impedance state prior to asserting FREEZE. (Previous related versions of this issue were CPU32:062 and AR_221). WORKAROUND: None required. Advanced CUSTOMER ERRATA AND INFORMATION SHEET Page 3 MCU Part: 68336.F Mask Set: 02F60K Division Report Generated: Jul 09, 96 13:03 MODULAR_AR_1018 Customer Information CPU32.16.0 DESCRIPTION: The stack frame is incorrect when bus error occurs (internal or external BERR asserted) on a write cycle immediately followed by the "TRAP #n" instruction. WORKAROUND: Avoid bus error occurrence when "TRAP #n" is run. If bus error cannot be avoided, insert "NOP" before running "TRAP #n", or modify the return address in the bus error exception frame to direct the CPU back to the correct flow. MODULAR_AR_1020 Customer Information CPU32.16.0 DESCRIPTION: Incorrect operation occurs as a result of the following sequence of conditions: A bus error or address error condition occurs during an operand cycle of a MOVEM instruction. After the exception processing, the CPU re-fetches the MOVEM instruction. If the re-fetch cycle of the MOVEM instruction is terminated by a bus error condition, an error condition occurs. WORKAROUND: Do not allow a bus error condition to occur for a fetch cycle of the MOVEM instruction, if that fetch occurs after exception processing of a bus error or address error on a MOVEM operand cycle. MODULAR_AR_981 Customer Information QADC.7.0 DESCRIPTION: Currently there is a specification for Differential Nonlinearity (DNL) in the QADC reference manual (QADCRM/AD) of +/- 0.5 counts. This specification will no longer be supported. (This was previously AR_941). WORKAROUND: Do not use the documented DNL specification. Advanced CUSTOMER ERRATA AND INFORMATION SHEET Page 4 MCU Part: 68336.F Mask Set: 02F60K Division Report Generated: Jul 09, 96 13:03 MODULAR_AR_956 Customer Erratum SIM.16.0A DESCRIPTION: When operating in PLL mode (MODCK = 1 at RESET negation), if the PIT or software watchdog prescalars are enabled, neither prescalar control bit may be changed again. In PLL mode, the reset state of the PTP (PITR register) and SWP (SYPCR register) bits is "0" (prescalars disabled). If either bit is written to a "1", subsequent writes to either bit will have no effect. WORKAROUND: If a prescalar is to be used, choose either the PIT prescalar or the software watchdog prescalar and set the appropriate prescalar enable bit. Only 1 prescalar may be used, and the control bit, once written, cannot be turned off. If no prescalar is to be used, be careful to ensure that neither prescalar enable bit is inadvertently set - once set, it cannot be cleared. MODULAR_AR_825 Customer Erratum SIM.16.0A DESCRIPTION: Certain conditions will produce Periodic Interrupt Timer (PIT) timeout period errors. The worst case error occurs if LPSTOP mode is entered and exited using the PIT, and the system clock is set to minimum PLL control bits in SYNCR register set to: Y=0, and W =0) prior to entry into LPSTOP and then set to maximum at LPSTOP exit (STSIM=0, VCO off in LPSTOP, therefore the PLL must re-lock). Also, on exiting from LPSTOP, the CPU will be held off of the bus until the PLL is re-locked. PIT period variations may appear as PIT counter missing or gaining clocks (the PIT is clocked by the EXTAL reference clock in LPSTOP, if STSIM = 0). Furthermore, a PIT period error is introduced whenever the PLL frequency is changed (whether LPSTOP is involved or not). (Previously AR_653). WORKAROUND: To increase timeout accuracy for the PIT when switching to a low system frequency before entering LPSTOP, restrict minimum PLL frequency before going into LPSTOP. The minimum PLL frequency must be determined by experimentation. Advanced CUSTOMER ERRATA AND INFORMATION SHEET Page 5 MCU Part: 68336.F Mask Set: 02F60K Division Report Generated: Jul 09, 96 13:03 MODULAR_AR_876 Customer Information SIM.16.0A DESCRIPTION: When the internal PLL clock system is not used (MODCK=0) at RESET negation) then the following behavior may occur. During power down, if the external clock degrades such that it no longer meets the AC Timing Specification for the External Clock Input High/Low Time (tXCHL), then the Input/Output and Output-only pins of the integration module and other modules may become active. Assertion of the external RESET pin under these conditions does not guarantee the level on the RESET pin will be internally recognized and the internal RESET signal may be negated under these anomalous conditions. The internal RESET signal is used to hold the Input/Output and Output-only pins in their respective high impedance mode. If the on-chip PLL is used for the clock source there is no problem as the PLL will meet the specifications to the minimum Vdd. WORKAROUND: If an External Clock is used, then insure that the External Clock signal does not degrade and violate the specifications as power goes down. Alternately, protect external devices that may be damaged (ex: non-volatile memories). MODULAR_AR_908 Customer Information SIM.16.0A DESCRIPTION: The documentation for the state of the RMC/PE3, SIZ[1:0]/PE[7:6] and DS/PE4 pins is inconsistent between the users manuals (MC68...USM) and the SIM/SCIM reference manuals (Module..RM). The users manuals indicate the pins are in a high impedance state while RESET is asserted, which is correct. The SCIM/SIM manuals indicate the pin state is determined by the data bus configuration while RESET is asserted, which is not correct. WORKAROUND: Refer to documentation in the users manuals for the RESET state of these pins. MODULAR_AR_658 Customer Information SIM.16.0A DESCRIPTION: The loss of clock reference feature is not supported and may not function. Disregard bit position 4 in the SYNCR register (previously the SLIMP bit), this bit is now reserved. Insure that the bit position 2 (previously the RSTEN bit) in the SYNCR register is always written to it's RESET state of %0. (This was previously IM:077). WORKAROUND: Do not rely on the loss of clock LIMP mode feature. Advanced CUSTOMER ERRATA AND INFORMATION SHEET Page 6 MCU Part: 68336.F Mask Set: 02F60K Division Report Generated: Jul 09, 96 13:03 MODULAR_AR_987 Customer Erratum VCO.13.1 DESCRIPTION: The "PLL Lock Time" (tlpll) specification is documented as 20 ms. This value applies to the time for the PLL to lock after changing the W or Y bits in the synthesizer control register (SYNCR) while the PLL is running, and to the period required for the PLL to lock after LPSTOP is exited. This specification does not apply at warm start-up (with VDDSYN applied and crystal stable, followed by VDD power application). The range of time required for the warm start-up period is a minimum of 20 ms with a maximum of 75 ms. The range of time is dependent on the charge state of the XFC capacitor at power up. (This was previously IM:098, VCO:059, and AR_806). WORKAROUND: Allow additional lock time (75 ms total lock time) under warm start-up conditions. MODULAR_AR_652 Customer Information VCO.13.1 DESCRIPTION: In some Phase Lock Loop (PLL) documentation a single 0.1 uF capacitor from the XFC pin to the Vddsyn supply pin is shown. An alternate filter may reduce PLL jitter under noisy system conditions. External noise can be filtered by proper supply layout techniques (low pass filtering). Other possible sources of noise are: A) arbitrating the bus away, B) entering and exiting STOP (CPU32) or WAI (CPU16), or LPSTOP if the VCO is active (STSIM=1). Current systems that are operating correctly may not require this filter change. Also, leakage from the XFC pin must not be greater than that of a 15 M Ohm resistor to meet PLL jitter specifications (refer to Electrical Characteristics section of MCU users manual). If the PLL is not enabled (MODCK=0 at RESET) then the new XFC filter is not required. (Previously IM:090). WORKAROUND: The improved filter replaces the single 0.1 uF capacitor between VDDsyn and XFC with a combination of components consisting of an 18 K Ohm resistor in series with a 0.1 uF capacitor. This series combination is then connected in parallel with a 3300 pF capacitor and placed between VDDsyn and XFC. It is recommended that this filter be used in new designs. The use of reference frequencies very different from those stated below and fSYS values other than 16.78 MHz may require different filter values to minimize PLL jitter characteristics. Versions of the integration module that are configured for either a slow option (ex: 32.768 kHz) or a fast option (ex: 4.194 MHz) crystal source use the same filter component values. Revision 0.0, 20 NOV 96 last update: Mar 26 1998