PUSB3F96X - NXP SEMICONDUCTORS

Important notice

Dear Customer,

On 7 February 2017 the former NXP Standard Product business became a new company with the

tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS

semiconductors with its focus on the automotive, industrial, computing, consumer and wearable

application markets

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use

the references to Nexperia, as shown below.

Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,

use http://www.nexperia.com

Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use

salesaddresses@nexperia.com (email)

Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on

the version, as shown below:

reserved

Should be replaced with:

If you have any questions related to the data sheet, please contact our nearest sales office via e-mail

or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and

understanding,

Kind regards,

Team Nexperia

1. Product profile

1.1 General description

The device is designed to protect high-speed interfaces such as SuperSpeed USB,

High-Definition Multimedia Interfac e (HDMI), DisplayPort, extern al Ser ial Ad van ce d

Technology Att achment (eSATA) a nd Low Voltage Dif ferential Signaling (LVDS) interfaces

against ElectroStatic Discharge (ESD).

The device includes four high-level ESD protection diode structures for ultra high-speed

signal lines and is encapsulated in a leadless small DFN2510A-10 (SOT1176- 1) plastic

package.

All signal lines are protected by a special diode configuration offering ultra low line

capacitance of only 0.5 pF. These diodes utilize a unique snap-back structure in order to

provide protection to downstream components fr om ESD voltages up to 10 kV contact

exceeding IEC 61000-4-2, level 4.

1.2 Features and benefits

System ESD protection for USB 2.0 and SuperS peed USB 3.0, HDMI 2.0, DisplayPort,

eSATA and LVDS

All signal lines with integrated rail-to-rail clamping diodes for downstream

ESD protection of 10 kV exceeding IEC 61000-4-2, level 4

Matched 0.5 mm trace spacing

Signal lines with 0.05 pF matching capacitance between signal pairs

Line capacitance of only 0.5 pF for each channel

Design-friendly ‘pass-through’ signal routing

1.3 Applications

The device is designed for high-speed receiver and transmitter port protection:

TVs and monitors

DVD recorders and players

Notebooks, main board graphic cards and ports

Set-top boxes and game consoles

PUSB3F96

ESD protection for ultra high-speed interfaces

Rev. 3 — 29 September 2014 Product data sheet

XSON10

Product data sheet Rev. 3 — 29 September 2014 2 of 15

NXP Semiconductors PUSB3F96

ESD protection for ultra high-speed interfaces

2. Pinning information

3. Ordering information

4. Marking

5. Limiting values

[1] All pins to ground.

Table 1. Pinning

Pin Symbol Description Simplified outline Graphic symbol

1 CH1 channel 1 ESD protection

2 CH2 channel 2 ESD protection

3 GND ground

4 CH3 channel 3 ESD protection

5 CH4 channel 4 ESD protection

6 n.c. not connected

7 n.c. not connected

8 GND ground

9 n.c. not connected

10 n.c. not connected

Transparent top view

109876

12345

3, 8

018aaa001

1 5

Table 2. Orderin g information

Type number Package

Name Description Version

PUSB3F96 DFN2510A-10 plastic extremely thin small outline package;

no leads; 10 terminals; body 1 2.5 0.5 mm SOT1176-1

Table 3. Marking codes

Type number Marking code

PUSB3F96 96

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VIinput voltage 0.5 +5.5 V

VESD electrostatic discharge

voltage IEC 61000-4-2, level 4 [1]

contact discharge 10 +10 kV

air discharge 15 +15 kV

Tamb ambient temperature 40 +85 C

Tstg storage temperature 55 +125 C

Product data sheet Rev. 3 — 29 September 2014 3 of 15

NXP Semiconductors PUSB3F96

ESD protection for ultra high-speed interfaces

6. Characteristics

[1] This parameter is guaranteed by design.

[2] According to IEC 61000-4-5 (8/20 s current waveform).

[3] 100 ns Transmission Line Pulse (TLP); 50 ; pulser at 80 ns.

Table 5. Characteristics

Tamb =25



C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VBR breakdown voltage II=1mA 6--V

ILR reverse leakage current per channel; VI=3V --1A

VFforward voltage II=1mA -0.7-V

Cline line capacitance f = 1 MHz; VI=3.3V [1] -0.50.6pF

Cline line capacitance

difference f=1MHz; V

I=3.3V [1] -0.05-pF

rdyn dynamic resistance surge [2]

positive transient - 0.41 - 

negative transient - 0.26 - 

TLP [3]

positive transient - 0.43 - 

negative transient - 0.28 - 

VCL clamping voltage IPP =5.2A [2]

positive transient - 4.6 - V

IPP =4.4 A [2]

negative transient - 2.2 - V

Product data sheet Rev. 3 — 29 September 2014 4 of 15

NXP Semiconductors PUSB3F96

ESD protection for ultra high-speed interfaces

differential mode

Fig 1. Insertion loss; typical values Fig 2. Relative capacitance as a function of input

voltage; typical values

Sdd21 normalized to 100 ;

differential pairs CH1/CH2 versus CH3/CH4 tr= 200 ps; differential pair CH1 + CH2

(1) PUSB3F96 on reference board

(2) Reference board without device under test (DUT)

Fig 3. Crosstalk; typical values Fig 4. Differential Time Domain Reflectometer (TDR)

plot; typical values

aaa-009367

-6

-10

-2

Sdd21

(dB)

-14

f (MHz)

1061010

109

107108

VI (V)

054231

aaa-009368

0.4

0.8

1.2

aCline

Cline VI0 V=

---------------------------------

aaa-009369

-40

-20

Sdd21

(dB)

-60

f (MHz)

1061010

109

107108

t (ns)

40.0 42.041.540.5 41.0

aaa-009370

100

110

120

Zdif

(Ω)

(1)

(2)

Product data sheet Rev. 3 — 29 September 2014 5 of 15

NXP Semiconductors PUSB3F96

ESD protection for ultra high-speed interfaces

Data rate: 5 Gbit/s

Vertical scale: 166.3 mV/div

Horizontal scale: 20 ps/div

Fig 5. USB 3.0 eye diagram, Printed-Circuit Bo ard (PCB) with PUSB3F96

Data rate: 5 Gbit/s

Vertical scale: 166.3 mV/div

Horizontal scale: 20 ps/div

Fig 6. USB 3.0 eye diagram, PCB without PUSB3F96 (reference)

aaa-014157

aaa-014158

Product data sheet Rev. 3 — 29 September 2014 6 of 15

NXP Semiconductors PUSB3F96

ESD protection for ultra high-speed interfaces

Test frequency: 148.5 MHz

Differential swing voltage: 810 mV

Horizontal scale: 34 ps/div

Fig 7. HDMI 2.0 TP1 eye diagram, PCB with PUSB3F96 (2160p, 60 Hz)

Test frequency: 148.5 MHz

Differential swing voltage: 800 mV

Horizontal scale: 34 ps/div

Fig 8. HDMI 2.0 TP1 eye diagram, PCB without PUSB3F96 (2160p, 60 Hz, reference)

aaa-014159

aaa-014160

Product data sheet Rev. 3 — 29 September 2014 7 of 15

NXP Semiconductors PUSB3F96

ESD protection for ultra high-speed interfaces

Test frequency: 148.5 MHz

Differential swing voltage: 809 mV

Horizontal scale: 34 ps/div

Remark: Measured at Test Point 2 (TP2) worst cable emulator, reference cable equalizer and

worst case positive skew.

Fig 9. HDMI 2.0 TP2 eye diagram, PCB with PUSB3F96 (2160p, 60 Hz)

Test frequency: 148.5 MHz

Differential swing voltage: 820 mV

Horizontal scale: 34 ps/div

Remark: Measured at Test Point 2 (TP2) worst cable emulator, reference cable equalizer and

worst case positive skew.

Fig 10. HDMI 2 .0 TP2 eye diagram, PCB without PUSB3F96 (2160p , 60 Hz, reference)

aaa-014161

aaa-014162

Product data sheet Rev. 3 — 29 September 2014 8 of 15

NXP Semiconductors PUSB3F96

ESD protection for ultra high-speed interfaces

The device uses an advanced clamping stru cture showing a negative dynamic resist ance.

This snap-back behavior strongly reduces the clamping voltage to the system behind the

ESD protection during an ESD event. Do not con nect unlimited DC current sources to the

data lines to avoid keeping the ESD protection device in snap-back state after exceeding

breakdown voltage (due to an ESD pulse for instance).

IEC 61000-4-5; tp=8/20s; positive pulse IEC 61000-4-5; tp=8/20s; negative pulse

Fig 11. Dynamic resistance with positive clamping;

typical valu e s Fig 12. Dynamic resistance with negative clamping;

typical values

tp= 100 ns; Transmission Line Pulse (TLP) tp= 100 ns; Transmission Line Pulse (TLP)

Fig 13. Dynamic resistance with positive clamping;

typical valu e s Fig 14. Dynamic resistance with negative clamping;

typical values

VCL (V)

0642

aaa-009371

IPP

(A)

VCL (V)

-2.5 0-0.5-1.5 -1.0-2.0

aaa-009372

-4

-2

IPP

(A)

-6

VCL (V)

01284

aaa-009373

(A)

VCL (V)

-6 0-2-4

aaa-009374

(A)

-14

-12

-10

-8

-6

-4

-2

Product data sheet Rev. 3 — 29 September 2014 9 of 15

NXP Semiconductors PUSB3F96

ESD protection for ultra high-speed interfaces

7. Application information

The device is designed to provide high-level ESD protection for high-speed serial

data buses such as HDMI, DisplayPort, eSATA and LVDS data lines.

When designing the Printed-Circuit Board (PCB), give careful consideration to impedance

matching and signal cou pling. Do not connect the sig nal lines to unlimited current sources

like, for example, a battery.

A basic application diagram for the ESD protection of an HDMI interface is shown in

Figure 15.

Fig 15. Application diagram of HDMI ESD protection using PUSB3F96

aaa-006751

n.c.

CEC

TMDS_D2+

GND

TMDS_GND

TMDS_D1+

TMDS_GND

TMDS_D0+

TMDS_GND

TMDS_CLK+

TMDS_GND

TMDS_CLK-

DDC_CLK

DDC_DAT

GND

+5 V

PUSB3F96

IP4221CZ6

TMDS_D1–

TMDS_D2–

TMDS_CH2+

TMDS_CH1+

TMDS_CH1–

TMDS_CH2–

TMDS_CH2+

TMDS_CH1+

TMDS_CH1–

TMDS_CH2–

GND

TMDS_D0–

HDMI

CONNECTOR

PUSB3F96

654

100 nF

123

HOT PLUG DETECTION

Product data sheet Rev. 3 — 29 September 2014 10 of 15

NXP Semiconductors PUSB3F96

ESD protection for ultra high-speed interfaces

8. Package outline

Fig 16. Package outline DFN2510A-10 (SOT1176-1)

12-05-23Dimensions in mm

0.4

0.3

0.45

0.35

0.05 max

0.5 max

0.127

0.25

0.15

1.1

0.9

0.2 min

0.5

2.6

2.4

Product data sheet Rev. 3 — 29 September 2014 11 of 15

NXP Semiconductors PUSB3F96

ESD protection for ultra high-speed interfaces

9. Soldering

Fig 17. Reflow so ld ering footprint DFN2510A-10 (SOT1176-1)

SOT1176-1

Remark:

Stencil of 75 μm is recommended.

A stencil of 75 μm gives an aspect ratio of 0.77

With a stencil of 100 μm one will obtain an aspect ratio of 0.58

Footprint information for reflow soldering of DFN2510A-10 package

solder land plus solder paste

occupied area

solder land

solder paste deposit

solder resist

ByHy

0.05

PD 0.05

Dimensions in mm

Ay By C D Hy

1.25 0.3 0.475 0.2

0.5 1.5

2.45

Generic footprint pattern

Refer to the package outline drawing for actual layout

sot1176-1_fr

Product data sheet Rev. 3 — 29 September 2014 12 of 15

NXP Semiconductors PUSB3F96

ESD protection for ultra high-speed interfaces

10. Revision history

Table 6. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PUSB3F96 v.3 20140929 Product data sheet - PUSB3F96 v.2

Modifications: •Section 1 “Product profile”: updated

•Figure 5 to 10: added

PUSB3F96 v.2 20131101 Product data sheet - PUSB3F96 v.2

PUSB3F96 v.1 20130226 Product data sheet - -

Product data sheet Rev. 3 — 29 September 2014 13 of 15

NXP Semiconductors PUSB3F96

ESD protection for ultra high-speed interfaces

11. Legal information

11.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

11.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full informatio n see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agr eed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

11.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect , incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liabil ity towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with t heir

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessa ry

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms an d conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property right s.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminar y specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 3 — 29 September 2014 14 of 15

NXP Semiconductors PUSB3F96

ESD protection for ultra high-speed interfaces

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims result ing from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

11.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

12. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PUSB3F96

ESD protection for ultra high-speed interfaces

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 September 2014

Documen t identifier: PUSB3F9 6

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

13. Contents

1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 General description . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Application information. . . . . . . . . . . . . . . . . . . 9

8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

9 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

10 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13

11.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13

11.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

11.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

11.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

12 Contact information. . . . . . . . . . . . . . . . . . . . . 14

13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15