AD7763BCP - Analog Devices, Inc.

Serial Interface, 625 kSPS, 24-Bit

Σ∆

ADC

Preliminary Technical Data

AD7763

Rev. PrD | Page 1 of 24

FEATURES

High performance 24-bit Sigma-Delta ADC

118dB SNR at 78kHz output data rate

106dB SNR at 625 kHz output data rate

625 kHz maximum fully filtered output word rate

Programmable over-sampling rate (32x to 256x)

Flexible serial interface

Fully differential modulator input

On-chip differential amplifier for signal buffering

Low pass FIR filter with default or user programmable

coefficients

Over-range alert bit

Digital offset and gain correction registers

Low power and power down modes

Synchronization of multiple devices via SYNC pin

APPLICATIONS

Data acquisition systems

Vibration analysis

Instrumentation

FUNCTIONAL BLOCK DIAGRAM

DIFF

Multi-Bit

Sigma-Delta

Modulator

AD7763

Control Logic,

I/O and

Registers

Reconstruction

Programmable

Decimation

FIR Filter

Engine

VIN+VIN-

AVDD1

AGND

VREF+

MCLK

SDEN

DGND

BUF

VDRIVE

AVDD2

AVDD3

AVDD4

DVDD

DECAP1

RBIAS

MCLKGND

ADR2:0

CLKDIV

DECAP2

DECAP3

REFGND

SCP

I2S

SCR

SDL

DRDY

SCO

SDO

SDI

FSI

FSO

RESET

SYNC

SH2:0

Figure 1.

PRODUCT OVERVIEW

The AD7763 high performance, 24-bit, sigma delta analog to

digital converter combines wide input bandwidth and high

speed with the benefits of sigma delta conversion, as well as

performance of 106dB SNR at 625 kSPS making it ideal for high

speed data acquisition. A wide dynamic range combined with

significantly reduced anti-aliasing requirements simplifies the

design process. An integrated buffer to drive the reference, a

differential amplifier for signal buffering and level shifting, an

over-range flag, internal gain & offset registers and a low-pass

digital FIR filter make the AD7763 a compact highly integrated

data acquisition device requiring minimal peripheral

component selection. In addition the device offers

programmable decimation rates and the digital FIR filter can be

adjusted if the default characteristics are not appropriate to the

application. The AD7763 is ideal for applications demanding

high SNR without necessitating design of complex front end

signal processing.

The differential input is sampled at up to 40MS/s by an analog

modulator. The modulator output is processed by a series of

low-pass filters, the final one having default or user

programmable coefficients. The sample rate, filter corner

frequencies and output word rate are set by a combination of

the external clock frequency and the configuration registers of

the AD7763.

The reference voltage supplied to the AD7763 determines the

analog input range. With a 4V reference, the analog input range

is ±3.2V differential biased around a common mode of 2V. This

common mode biasing can be achieved using the on-chip

differential amplifiers, further reducing the external signal

conditioning requirements.

The AD7763 is available in an exposed paddle 64-lead TQFP

and 48-lead CSP packages and is specified over the industrial

temperature range from -40°C to +85°C.

Rev. PrD

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

AD7763 Preliminary Technical Data

Rev. PrD | Page 2 of 24

TABLE OF CONTENTS

TABLE OF CONTENTS.................................................................. 2

AD7763—Specifications.................................................................. 3

Timing Specifications....................................................................... 6

Timing Diagrams.............................................................................. 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Functional Descriptions.......................... 9

Terminology .................................................................................... 11

Typical Performance Characteristics ........................................... 12

Theory of Operation ...................................................................... 13

AD7763 Interface............................................................................ 14

Clocking the AD7763 .................................................................... 16

Driving The AD7763 ..................................................................... 17

Using The AD7763..................................................................... 17

Bias Resistor Selection ............................................................... 18

Programmable FIR Filter............................................................... 19

Downloading a User-Defined Filter ............................................ 20

Example Filter Download ......................................................... 20

AD7763 Registers........................................................................... 22

Non Bit-Mapped Registers........................................................ 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

Rev PrA: Preliminary Datasheet

Rev PrB: Preliminary Datasheet

Rev PrC: Preliminary Datasheet

Preliminary Technical Data AD7763

Rev. PrD | Page 3 of 24

AD7763—SPECIFICATIONS

Table 1. VDD1 = 2.5 V, VDD2 = 5 V, VREF = 4.096 V, TA = +25°C, Full Power Mode using on-chip amplifierwith components as shown in

Table 8 , unless otherwise noted

Parameter Test Conditions/Comments Specifcation Unit

DYNAMIC PERFORMANCE1

Decimate by 256 MCLK = 40MHz, ODR = 78.125kHz, FIN = 1kHz Sine Wave

Dynamic Range 2 Modulator inputs shorted TBD dB min

120.8 dB typ

Signal to Noise Ratio (SNR)2 117 dB typ

Non-harmonic 120 dBFS typ Spurious Free Dynamic Range (SFDR) 2

Input Amplitude = -60dB 129 dBFS typ

Input Amplitude = -0.5dB -100 dB typ

TBD dB max Input Amplitude = -6dB

-103 dB typ

Total Harmonic Distortion (THD) 2

Input Amplitude = -60dB -66 dB typ

Decimate by 64 MCLK = 40MHz, ODR = 312.5kHz, FIN =100kHz Sine Wave

TBD dB min Dynamic Range2 Modulator inputs shorted

114 dB typ

TBD dB max Signal to Noise Ratio (SNR) 2 Modulator inputs shorted

109 dB typ

Spurious Free Dynamic Range (SFDR) 2 Non-harmonic 109 dBFS typ

Input Amplitude = -0.5dB -102 dB typ

TBD dB max

Total Harmonic Distortion (THD) 2

Input Amplitude = -6dB

-110 dB typ

Decimate by 32 MCLK = 40MHz, ODR = 625kHz, FIN = 100kHz Sine Wave

Dynamic Range2 Modulator inputs shorted 110 dB typ

Signal to Noise Ratio (SNR) 2 TBD dB min

104 dB typ

Spurious Free Dynamic Range (SFDR) 2 Non-harmonic 120 dBFS typ

Input Amplitude = -0.5dB -102 dB typ

TBD dB max

Total Harmonic Distortion (THD) 2

Input Amplitude = -6dB

TBD dB typ

DC ACCURACY

Resolution 24 Bits

Differential Nonlinearity2 Guaranteed monotonic to 24 bits 1 LSB typ

Integral Nonlinearity2 At 16 bits 1 LSB typ

Zero Error2 0.03 % typ

Gain Error2 0.01 % typ

Zero Error Drift 0.0006 % /°C typ

Gain Error Drift 1.4 ppm /°C

typ

DIGITAL FILTER RESPONSE

Decimate by 32

Group Delay MCLK = 40MHz TBD µS typ

Decimate by 64

Group Delay MCLK = 40MHz TBD µS typ

Decimate by 128

Group Delay MCLK = 24.576MHz 480 µS typ

ANALOG INPUT

Differential Input Voltage Vin(+) – Vin(-), VREF = 2.5V ±2 V pk-pk

Vin(+) – Vin(-), VREF = 4.096V ±3.25 V pk-pk

DC Leakage Current ±2 µA max

AD7763 Preliminary Technical Data

Rev. PrD | Page 4 of 24

Parameter Test Conditions/Comments Specifcation Unit

Input Capacitance At internal buffer inputs 5 pF typ

At modulator inputs 55 pF typ

REFERENCE INPUT/OUTPUT

VREF Input Voltage VDD3 = 3.3V +2.5 Volts

DD3 = 5V +4.096 Volts

VREF Input DC Leakage Current ±1 µA max

VREF Input Capacitance 5 pF max

POWER REQUIREMENTS

AVDD1 (Modulator Supply) ±5% +2.5 Volts

AVDD2 (General Supply) ±5% +5 Volts

AVDD3 (Diff-Amp Supply) +3.15/+5.25 V min/max

AVDD4 (Ref Buffer Supply) +3.15/+5.25 V min/max

DVDD ±5% +2.5 Volts

VDRIVE +1.65/+2.7 V min/max

Full Power Mode

AIDD1 (Modulator) 50 mA typ

AIDD2 (General) 35 mA typ

AIDD4 (Reference Buffer) AVDD4 = +5V 35 mA typ

Low Power Mode

AVDD1 (Modulator) 26 mA typ

AIDD2 (General) 20 mA typ

AIDD4 (Reference Buffer) AVDD4 = +5V 10 mA typ

AIDD3 (Diff Amp) AVDD3 = +5V, Both Modes 42 mA typ

DIDD Both Modes 45 mA typ

Standby Mode

AVDD1 (Modulator) 210 µA typ

AIDD2 (General) 30 nA typ

AIDD3 (Diff Amp AVDD3 = +5V 30 nA typ

AIDD4 (Reference Buffer) AVDD4 = +5V 30 nA typ

DIDD Clock Stopped 250 µA typ

Clock Running 690 µA typ

POWER DISSIPATION

Full Power Mode

Modulator (P1) 125 mW typ

General (P2) 175 mW typ

Reference Buffer (P4) AVDD4 = +3.3V 101 mW typ

AVDD4 = +5V 175 mW typ

Low Power Mode

Modulator (P1) 65 mW typ

General (P2) 100 mW typ

Reference Buffer (P4) AVDD4 = +3.3V 27 mW typ

AVDD4 = +5V 50 mW typ

Differential Amplifier (P3) AVDD3 = +3.3V 116 mW typ

AVDD3 = +5V 210 mW typ

Preliminary Technical Data AD7763

Rev. PrD | Page 5 of 24

Parameter Test Conditions/Comments Specifcation Unit

Digital Power 112.5 mW typ

Total Power Dissipation Full Power Mode TBD mW max

Low Power Mode TBD mW max

Standby Mode Clock Stopped 1.2 mW typ

Clock Running 2.3 mW typ

DIGITAL I/O

Input Capacitance TBD pF typ

VINH TBD V min

VINL TBD V max

VOH TBD V min

VOL TBD V max

1 All specifications in dB’s are referred to a full-scale input, FS. Tested with an input signal at 0.5dB below full-scale, unless otherwise specified.

2 See Terminology

AD7763 Preliminary Technical Data

Rev. PrD | Page 6 of 24

TIMING SPECIFICATIONS

Table 2. VDD1 = 2.5 V, VDD2 = 5 V, VREF = 4.096 V, VDRIVE = TBD V, TA = +25°C, CLOAD = 25pF, Full Power Mode, unless otherwise noted

Parameter Limit at TMIN, TMAX Unit Description

fMCLK 1 MHz min Applied Master Clock Frequency

40 MHz max

fICLK 500 kHz min Internal Modulator Clock Derived from MCLK.

20 MHz max

t13 1 × tICLK or 0.5 × tICLK4 typ SCO High Period

t2 1 × tICLK or 0.5 × tICLK typ SCO Low Period

t3 TBD typ

DRDY Low Period

t4 32 × tSCO5 typ

FSO Low Period

t5 TBD ns max Initial Data Access Time

t6 TBD6 ns max SCO Rising Edge to SDO Valid

t7 TBD nS min SDO Valid after SCO Falling Edge

t8 8/16 × tSCO typ

FSO Falling Edge to SDL Falling Edge

t9 TBD typ SDL Pulse Width

t10 TBD ns max

FSO Rising Edge to SDO Three-state

t11 TBD min

FSI Low Period

t12 TBD xS min SDI Setup Time

t13 TBD xS min SDI Hold Time

3 tICLK = 1/fICLK

4 SCO frequency selected by SCR pin

5 tSCO = t1+t2

6 All edges mentioned refer to SCP=0. Invert SCO edges for SCP=1

Preliminary Technical Data AD7763

Rev. PrD | Page 7 of 24

TIMING DIAGRAMS

t5t6

t8t9

D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0

t10

SCO(O)

DRDY (O)

FSO (O)

SDO (O)

SDL (O)

Figure 2. Serial Read Timing Diagram

t1t2

32 SCLKs

t11

t12 t13

ALL AD2 AD1 AD0 RA11 RA10 RA1 RA0 D15 D14 D1 D0

SCO (O)

FSI (I)

SDI (I)

Figure 3. AD7763 Register Write

SERIAL DATA FROM ADC0 SERIAL DATA FROM ADC1 SERIAL DATA FROM ADC2 SERIAL DATA FROM ADC3

2CLKs

SCO (O)

DRDY (O)

FSO 0 (O)

FSO 3 (O)

FSO 2 (O)

FSO 1 (O)

SDO (O)

Figure 4. Serial Read Timing Using Multiple AD7763 Devices

AD7763 Preliminary Technical Data

Rev. PrD | Page 8 of 24

ABSOLUTE MAXIMUM RATINGS

Table 3. TA = 25°C, unless otherwise noted.

Parameters Rating

VDD to GND TBD

VIN+ to GND TBD

VIN– to GND TBD

Digital input voltage to GND TBD

Digital output voltage to GND TBD

VREF to GND TBD

Input current to any pin except supplies7 TBD

Operating temperature range

Commercial (A, B version) −40°C to +85°C

Storage temperature range −65°C to +150°C

Junction temperature 150°C

TQFP Exposed Paddle Package

θJA thermal impedance 92.7 °C/W

θJC thermal impedance 5.1 °C/W

CSP Package

θJA thermal impedance 26.7 °C/W

θJC thermal impedance 30 °C/W

Lead temperature, soldering

Vapor phase (60 secs) 215°C

Infrared (15 secs) 220°C

ESD TBD kV

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

7 Transient currents of up to TBD mA do not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Preliminary Technical Data AD7763

Rev. PrD | Page 9 of 24

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

SDI

SDL

SCP

DECAP2

DECAP3

AGND

AVDD2

AGND

ADR0

ADR1

ADR2

SH0

VDRIVE

DGND

DVDD

SH1

SH2

DRDY

RESET

SYNC

DGND

AGND

AVDD1

17 18 19 20 21 22 23 24

RBIAS

AGND

VINA1+

VINA1-

VOUTA1-

VOUTA1+

AGND

AVDD3

VIN+

VIN-

AVDD2

AGND

64 63 62 61 60 59 58

VDRIVE

DGND

I2S

SCR

CDIV

SCO

SDO

DGND

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AD7763

DGND

MCLK

AVDD2

AVDD1

AGND

VREF+

AGND

AVDD4

25 26 27 31302928 32

57 56 55 54 53 52 51 50 49

AGND

DECAP1

REFGND

MCLKGND

FSI

FSO

SDEN

DGND

Figure 4. 64-Lead TQFP Pin Configuration

SH0

PIN 1

IDENTIFIER

AD7763

TOP VIEW

(Not to Scale)

VDRIVE

MCLK

AVDD2

AVDD1

DECAP1

REFGND

VREF+

AVDD4

AVDD2

RBIAS

VINA1+

VINA1-

VOUTA1-

VOUTA1+

AVDD3

VIN+

VIN-

AVDD2

DECAP2

AGND

AVDD1

SYNC

RESET

DRDY

DVDD

VDRIVE

ADR2

ADR1

ADR0

SCP

SDL

FSI

SDI

SDO

SCO

FSO

SDEN

CDIV

SCR

I2S

DECAP3

SH1

SH2

MCLKGND

DGND

Figure 5. 48-PIN LFCSP Pin Configuration

Table 4. Pin Function Descriptions

TQFP Pin

Number

CSP Pin

Number

Pin Mnemonic Description

6, 33 5, 25 AVDD1 +2.5V power supply for modulator. These pins should be decoupled to AGND with 100nF and

10µF capacitors on each pin.

4, 14, 15,

4, 10, 11,

AVDD2 +5V power supply. These pins should be decoupled to AGND with TBD nF and TBD µF

capacitors on each pin.

24 17 AVDD3 +3.3V to +5V power supply for differential amplifier. These pins should be decoupled to AGND

with a 100nF capacitor.

12 9 AVDD4 +3.3V to +5V power supply for reference buffer. This pin should be decoupled to AGND with a

10nF capacitor in series with a 10Ω resistor.

5, 7, 11,

13, 16, 18,

23, 28, 31,

32, 34

23, 24,

Paddle

AGND Power supply ground for analog circuitry. In the Chip Scale package, most of the internal

AGND pads are down-bonded to the exposed paddle. This paddle then become the main

analog ground connection for the AD7763.

9 7 REFGND Reference Ground. Ground connection for the reference voltage.

41 31 DVDD +2.5V power supply for digital circuitry and FIR filter. This pin should be decoupled to DGND

with a 100nF capacitor.

44, 63 1, 32 VDRIVE Logic power supply input, +1.8V to +2.5V. The voltage supplied at these pins will determine

the operating voltage of the logic interface. Both these pins must be connected together and

tied to the same supply. Each pin should also be decoupled to DGND with a 100nF capacitor.

1, 35, 42,

43, 53, 58,

62, 64

45,

Paddle

DGND Ground Reference for digital circuitry. In the Chip Scale package, all the internal DGND pads

are down-bonded to the exposed paddle. This paddle then becomes the single ground

connection for the AD7763.

AD7763 Preliminary Technical Data

Rev. PrD | Page 10 of 24

TQFP Pin

Number

CSP Pin

Number

Pin Mnemonic Description

19 13 VINA1+ Positive Input to Differential Amplifier.

20 14 VINA1- Negative Input to Differential Amplifier.

21 15 VOUTA1- Negative Output from Differential Amplifier.

22 16 VOUTA1+ Positive Output from Differential Amplifier.

25 18 VIN+ Positive Input to the Modulator.

26 19 VIN- Negative Input to the Modulator.

10 8 VREF+ Reference Input. The input range of this pin is determined by the reference buffer supply

voltage (AVDD4). See Reference Section for more details.

8 6 DECAP1 Decoupling Pin. A 100nF capacitor must be inserted between this pin and AGND.

29 21 DECAP2 Decoupling Pin. A TBD µF capacitor must be inserted between this pin and AGND.

30 22 DECAP3 Decoupling Pin. A TBD µF capacitor must be inserted between this pin and AGND.

17 12 RBIAS Bias Current setting pin. A resistor must be inserted between this pin and AGND. For more

details on this, see the Bias Resistor Section.

37 27

RESET A falling edge on this pin resets all internal digital circuitry. Holding this pin low keeps the

AD7763 in a reset state.

3 3 MCLK Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate

will depend on the frequency of this clock. See Clocking Section for more details.

2 2 MCLKGND Master Clock ground sensing pin.

36 26

SYNC Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to

synchronize multiple devices in a system.

38 28

DRDY Data Ready Output. Each time that new conversion data is available, an active low pulse, ½ICLK

period wide, is produced on this pin. See AD7763 Interface Section for further details.

39, 40, 45 29, 30,

SH2:0 Share Pins 2:0. For multiple AD7763 devices sharing a common serial bus, hardwiring these

pins with the number of devices sharing the bus will ensure the correct number of DRDY

pulses are generated. See Sharing the Serial Bus in the AD7763 Interface Section for further

details.

46-48 34-36 ADR2:0 Address 2:0. To allow multiple AD7763 devices share a common serial bus, each device must

be given an individual, hard-wired address. See Sharing the Serial Bus in the AD7763 Interface

Section for further details.

49 37 SCP Serial Clock Polarity. Determines which edge of SCO that the data bits are clocked out and

valid on. All timing diagrams are shown with SCP=0 and all SCO edges shown should be

inverted for SCP=1.

50 38 SDL Serial Data Latch. A pulse is output on this pin after every 16 Data bits. The pulse is one SCO

period wide and could be used in conjunction with FSO as an alternative framing method for

serial transfers requiring a framing signal more frequently than every 32 bits.

51 39

FSI Frame Sync In. The status of this pin is checked on the falling edge of SCO. If this pin is low

then the first data bit will be latched in on the next SCO falling edge.

52 40 SDI Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI

event has been latched. 32 bits are required for each write; the first 16-bit word contains the

device and register address and the second word contains the data.

54 41 SDO Serial Data Out. Address, Status and Data bits are clocked out on this line during each serial

transfer. If SCP=0, each bit is clocked out on an SCO rising edge and valid on the falling edge.

55 42 SCO Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of this

clock is either equal to ICLK or ICLK/2 depending on the state of the SCR pin. See the Clocking

the AD7763 and AD7763 Interface sections for further details.

56 43

FSO Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide.

57 44

SDEN Serial Data Enable. When this pin is logic high, SDO will remain in three-state.

59 46 CLKDIV Clock Divider. This pin is used to select the ratio of MCLK to ICLK. See the Clocking the AD7763

Section for further details.

60 47 SCR Serial Clock Rate. This pin as well as the state of the CLKDIV pin programs the SCO

frequency.See Table 6 for details..

61 48 I2S I2S Select. A logic 1 on this pin changes the serial data out mode from SPI to I2S compatible.

Preliminary Technical Data AD7763

Rev. PrD | Page 11 of 24

TERMINOLOGY

Signal to Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the

rms sum of all other spectral components below the Nyquist

frequency, excluding harmonics and dc.

Total Harmonic Distortion (THD)

The ratio of the rms sum of harmonics to the fundamental. For

the AD7763, it is defined as

()

VVVVV

20dBTHD ++++

=log

where:

V1 is the rms amplitude of the fundamental.

V2, V3, V4, V5, and V6 are the rms amplitudes of the second to

the sixth harmonics.

Dynamic Range

The dynamic range is the ratio of the rms value of the full scale

to the rms noise measured with the inputs shorted together. The

value for dynamic range is expressed in decibels.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the

ADC output spectrum (up to fS/2 and excluding dc) to the rms

value of the fundamental. Normally, the value of this

specification is determined by the largest harmonic in the

spectrum, but, for ADCs where the harmonics are buried in the

noise floor, it is a noise peak.

Non-Harmonic Spurious Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the

peak spurious spectral component excluding harmonics.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities creates distortion

products at sum and difference frequencies of mfa ± nfb, where

m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms

are those for which neither m nor n are equal to zero. For

example, the second-order terms include (fa + fb) and (fa − fb),

while the third-order terms include (2fa + fb), (2fa − fb), (fa +

2fb) and (fa − 2fb).

The AD7763 is tested using the CCIF standard, where two input

frequencies near the top end of the input bandwidth are used.

In this case, the second-order terms are usually distanced in

frequency from the original sine waves, while the third-order

terms are usually at a frequency close to the input frequencies.

As a result, the second- and third-order terms are specified

separately. The calculation of the intermodulation distortion is

as per the THD specification, where it is the ratio of the rms

sum of the individual distortion products to the rms amplitude

of the sum of the fundamentals expressed in dB.

Integral Nonlinearity (INL)

The maximum deviation from a straight line passing through

the endpoints of the ADC transfer function.

Differential Nonlinearity (DNL)

The difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Zero Error

The zero error is the difference between the ideal midscale

input voltage (0V) and the actual voltage producing the

midscale output code,

Gain Error

The first transition (from 100…00 to 100…01) should occur for

an analog voltage ½ LSB above the nominal negative full scale.

The last transition (from 011…10 to 011…11) should occur for

an analog voltage 1 ½ LSB below the nominal full scale. The

gain error is the deviation of the difference between the actual

level of the last transition and the actual level of the first

transition from the difference between the ideal levels.

AD7763 Preliminary Technical Data

Rev. PrD | Page 12 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

Default Conditions: TA = 25°C, TBD, unless otherwise noted.

ALL CAPS ( Init ial cap)

000

000 000 000 000 000 000

ALL CAPS ( Init ial cap)

000

TBD

Figure 6. TBD

ALL CAPS ( Init ial cap)

000

000 000 000 000 000 000

ALL CAPS ( Init ial cap)

000

TBD

Figure 7. TBD

ALL CAPS ( Init ial cap)

000

000 000 000 000 000 000

ALL CAPS ( Init ial cap)

000

TBD

Figure 8. TBD

ALL CAPS ( Init ial cap)

000

000 000 000 000 000 000

ALL CAPS ( Init ial cap)

000

TBD

Figure 9. TBD

ALL CAPS ( Init ial cap)

000

000 000 000 000 000 000

ALL CAPS ( Init ial cap)

000

TBD

Figure 10. TBD

ALL CAPS ( Init ial cap)

000

000 000 000 000 000 000

ALL CAPS ( Init ial cap)

000

TBD

Figure 11. TBD

Preliminary Technical Data AD7763

Rev. PrD | Page 13 of 24

THEORY OF OPERATION

The AD7763 employs a sigma-delta conversion technique to

convert the analog input into an equivalent digital word. The

modulator samples the input waveform and outputs an

equivalent digital word to the digital filter at a rate equal to ICLK.

Due to the high over-sampling rate, which spreads the

quantization noise from 0 to fICLK, the noise energy contained in

the band of interest is reduced (Figure 12a). To further reduce

the quantization noise, a high order modulator is employed to

shape the noise spectrum; so that most of the noise energy is

shifted out of the band of interest (Figure 12b).

The digital filtering which follows the modulator removes the

large out-of-band quantization noise (Figure 12c) while also

reducing the data rate from fICLK at the input of the filter to fICLK/8

or less at the output of the filter, depending on the decimation

rate used.

Digital filtering has certain advantages over analog filtering. It

does not introduce significant noise or distortion and can be

made perfectly linear phase.

The AD7763 employs three Finite Impulse Response (FIR)

filters in series. By using different combinations of decimation

ratios and filter selection and bypassing, data can be obtained

from the AD7763 at a large range of data rates. The first filter

receives data from the modulator at ICLK MHz where it is

decimated by four to output data at (ICLK/4) MHz.

BAND OF INTEREST

fICLK/2

DIGITAL FILTER CUTOFF FREQUENCY

BAND OF INTEREST

QUANTIZATION NOISE

fICLK/2

BAND OF INTEREST

fICLK/2

NOISE SHAPING

Figure 12. Sigma-Delta ADC

The second filter allows the decimation rate to be chosen from

4x to 32x or to be completely bypassed. The third filter has a

fixed decimation rate of 2x and is user programmable as well as

having a default configuration. It is described in detail in the

Programmable FIR Filter Section. This filter can also be

bypassed. Table 5 below shows some characteristics of the

default filter. The group delay of the filter is defined to be the

delay to the centre of the impulse response and is equal to the

computation + filter delays. The delay until valid data is

available (the DVALID status bit is set) is equal to 2x the filter

delay + the computation delay.

Table 5. Configuration With Default Filter

ICLK

Frequency Filter 1 Filter 2 Filter 3 Data State Computation

Delay Filter Delay Passband

Bandwidth

Output Data

Rate (ODR)

20 MHz 4x 4x 2x Fully Filtered 1.775µS 44.4µS 250 kHz 625 kHz

20 MHz 4x 8x Bypassed Partially Filtered 2.6µS 10.8µS 140.625 kHz 625 kHz

20 MHz 4x 8x 2x Fully Filtered 2.25µS 87.6µS 125 kHz 312.5 kHz

20 MHz 4x 16x Bypassed Partially Filtered 4.175µS 20.4µS 70.3125 kHz 312.5 kHz

20 MHz 4x 16x 2x Fully Filtered 3.1µS 174µS 62.5 kHz 156.25 kHz

20 MHz 4x 32x Bypassed Partially Filtered 7.325µS 39.6µS 35.156 kHz 156.25 kHz

20 MHz 4x 32x 2x Fully Filtered 4.65µS 346.8µS 31.25 kHz 78.125 kHz

12.288MHz 4x 8x 2x Fully Filtered 3.66µS 142.6µS 76.8 kHz 192 kHz

12.288MHz 4x 16x 2x Fully Filtered 5.05µS 283.2µS 38.4 kHz 96 kHz

12.288MHz 4x 32x Bypassed Partially Filtered 11.92µS 64.45µS 21.6 kHz 96 kHz

12.288MHz 4x 32x 2x Fully Filtered 7.57µS 564.5µS 19.2 kHz 48 kHz

AD7763 Preliminary Technical Data

Rev. PrD | Page 14 of 24

AD7763 INTERFACE

Reading Data

The AD7763 uses an SPI compatible serial interface. The timing

diagram in Figure 2 shows how the AD7763 transmits its

conversion results.

The data being read from the AD7763 is clocked out using the

serial clock output, SCO. The SCO frequency is dependant on

the the state of the serial clock output rate, SCR, and the clock

divider mode chosen by the state of the clock divider bit CDIV

(see the Clocking the AD7763 section). Table 6 details the SCO

frequency for the AD7763 as a result of the states of both the

CDIV and SCR pins.

Table 6. SCO Frequency

Clock Divide

Mode

CDIV SCR SCO

Frequency

0 MCLK Divide by 1 1

1 MCLK

0 MCLK/2 Divide by 2 0

1 MCLK

An active low pulse of one SCO period on the data ready

output, DRDY, indicates a new conversion result is available at

the AD7763 serial data output,SDO.

Each bit of the new conversion result is clocked onto the SDO

line on the rising SCO edge and is valid on the falling SCO

edge. The SDO line is tri-stated when the serial data enable pin,

SDEN, is logic high.The 32-bit result consists of the 24 data bits

which, are followed by 8 status bits. These status bits are shown

in Table 7. The first three status bits. AD[2:0}, are the device

address bits. Table 15 contains descriptions of the other status

bits.

Table 7. Status Bits During Data Read

D7 D0

AD2 AD1 AD0 DValid Ovr LPwr FiltOk 0

The conversion result output on the SDO line is framed by the

frame synchronization output, FSO, which is sent logic low for

32 SCO cycles following the rising edge of the DRDY signal.

The AD7763 also features a serial data latch output, SDL, which

outputs a pulse every sixteen data bits. The SDL output offers an

alternative framing signal for serial transfers which require a

framing signal more frequent than every 32 bits.

Sharing The Serial Bus

The AD7763 functionality allows up to eight devices to share

the same serial bus, SDO. Devices sharing the serial output bus

are assigned addresses from 000 to 111.

For a part with an address of 0, the SDO line comes out of tri-

state on the first rising edge of SCO after the DRDY pulse and

returns to tri-state after the 32nd SCO falling edge plus a TBD

hold time. For the next device sharing the serial bus , address 1,

the SDO line will come out of tri-state on the 32nd SCO rising

edge for the next 32 SCO periods. This pattern will occur for

the rest of the proceeding devices sharing the serial bus.

Figure 4 shows an example lof four devices sharing the same

serial bus. Each of the devices is hardwired with a different

address form 0 to 3(ADR2:0). Device 0 outputs its serial word

on the SDO line during the first 32 SCO cycles. Device 1 then

outputs its serial word during the next 32 SCO cycles and so on

for the remaining devices 2 and 3.

To create the DRDY pulse as shown in Figure 4, (where four

devices are sharing the same serial line) the share bits of this

device, SH[2:0], should be set to 011, which, corresponds to 4

devices sharing the serial line. Each AD7763 device outputs its

own FSO signal.

The provision of two framing signals: DRDY and ,FSO ensures

that the AD7763 offers flexible data output framing options,

which, are further enhanced by the availability of the SDL

output. The user can select the framing output which bests suits

the application.

Writing To The AD7763

Figure 3 shows the AD7763 write operation. The serial writing

operation is synchronous to the SCO signal. The status of the

frame sync input, FSI , is checked on the falling edge of the SCO

signal. If the FSI line is low then the first data is latched in on

the next SCO falling edge.

The active edge of the FSI signal should be set to occur at a

position when the SCO signal is high or low and which also

allows set-up and hold time from the SCO falling edge to be

met. The width of the FSI signal may be set to between 1 and 32

SCO periods wide. A second or subsequent FSI falling edge

which occurs before 32 SCO periods have elapsed will be

ignored.

Figure 3 also shows the format for the serial data being written

to the AD7763. 32 bits are required for a write operation. The

first 16 bits are used to select the device and register address

which the data being read is intended. The second 16 bits

contain the data for the selected register. When using multiple

Preliminary Technical Data AD7763

Rev. PrD | Page 15 of 24

devices which share the same serial bus, all FSI and SDI pins

may be tied together and each device written to individually by

setting the appropriate address bits in the serial 32-bit word.

There is an exception to this in the case where all devices may

be written to at the same time by setting the ALL bit logic high.

Thus if this bit is set to logic high every device on the serial bus

will accept the data written regardless of the address bits. This

feature is particularly attractive, if, for example 4 devices were

being configured with the same user defined filter. Instead of

having to download the filter configuration four times, only one

write would be required.

Writing to AD7763 should be allowed at any time even while

reading a conversion result. It should be noted that after writing

to the devices, valid data will not be output until after the

settling time for the filter has elapsed. The DVALID status bit is

asserted at this point to indicate that the filter has settled and

that valid data is available at the output.

Reading Status and Other Registers

The AD7763 features a number of programmable registers. To

read back the contents of these registers or the status register,

the user must first write to the control register of the device

setting a bit corresponding to the register they wish to read. The

next read operation will then output the contents of the selected

relevant bits in the control register is given in the AD7763

Registers section.

AD7763 Preliminary Technical Data

Rev. PrD | Page 16 of 24

CLOCKING THE AD7763

The AD7763 requires an external low jitter clock source. This

signal is applied to the MCLK and MCLKGND pins. An

internal clock signal (ICLK) is derived from the MCLK input

signal. This ICLK controls all the internal operation of the

AD7763. The maximum ICLK frequency is 20MHz but due to

an internal clock divider, a range of MCLK frequencies can be

used. There are three possibilities available to generate the

ICLK:

1. ICLK = MCLK (CDIV = 1)

2. ICLK = MCLK / 2 (CDIV = 0)

These options are pin selected (See Table 4 Pin Function

Descriptions for further details). If the user wishes to get output

data rates equal to those used in audio systems, a 12.288 MHz

ICLK frequency can be used. As shown in Table 5, output data

rates of 192, 96kHz and 48kHz are achievable with this ICLK

frequency. As mentioned previously, this ICLK frequency can

be derived from different MCLK frequencies.

The MCLK jitter requirements depend on a number of factors

and are given by the following equation:

)(

102

dBSNR

RMSj f

OSR

×××

OSR = Over-sampling ratio = ODR

fICLK

fIN = Maximum Input Frequency

SNR(dB) = Target SNR.

Taking an example from Table 5:

ODR = 625 kHz, fICLK = 20MHz, fIN (max) = 250 kHz, SNR =

108dB

pst RMSj 6.3

10102502

)( =

××××

This is the maximum allowable clock jitter for a full-scale

250kHz input tone with the given ICLK and Output Data Rate.

Taking a second example from Table 5:

ODR = 48kHz, fICLK = 12.288MHz, fIN (max) = 19.2kHz, SNR =

120dB

pst RMSj 133

10102.192

256

)( =

××××

The input amplitude also has an effect on these jitter figures. If,

for example, the input level was 3dB down from full-scale, the

allowable jitter would be increased by a factor of √2 increasing

the first example to 2.53ps RMS. This is due to the fact that the

maximum slew rate is reduced by a reduction in amplitude.

Figure 13 and Figure 14 illustrate this point showing the

maximum slew rate of a sine wave of the same frequency but

with different amplitudes.

Figure 13. Maximum Slew Rate of Sine Wave with Amplitude of 2V Pk-Pk

Figure 14. Maximum Slew Rate of Same Frequency Sine Wave with

Amplitude of 1V Pk-Pk

Preliminary Technical Data AD7763

Rev. PrD | Page 17 of 24

DRIVING THE AD7763

The AD7763 has an on-chip differential amplifier. This

amplifier will operate with a supply voltage (AVDD3) from 3V to

5.5V. For a 4.096V reference, the supply voltage must be 5V.

To achieve the specified performance in full power mode, the

differential amplifier should be configured as a first order anti-

alias filter as shown in Figure 15. Any additional filtering

should be carried out in previous stages using low noise, high-

performance op-amps such as the AD8021.

Suitable component values for the first order filter are listed in

Table 8. Using the first row as an example would yield a 10dB

attenuation at the first alias point of 19MHz.

RIN

RFB

CFB

VIN-

VIN+

Figure 15. Differential Amplifier Configuration

Table 8. Full Power Component Values

ODR VREF R

IN R

FB C

S C

625kHz 4.096v

1kΩ 655 Ω 5.6pF 33pF

625kHz 2.5v TBD Ω TBD Ω TBD TBD pF

48kHz 4.096v

TBD Ω TBD Ω TBD TBD pF

48kHz 2.5v TBD Ω TBD Ω TBD TBD pF

Figure 16 shows the signal conditioning that occurs using the

circuit in Figure 15 with a ±2.5V input signal biased around

ground using the component values and conditions in the first

row of Table 8. The differential amplifier will always bias the

output signal to sit on the optimum common mode of VREF/2, in

this case 2.048V. The signal is also scaled to give the maximum

allowable voltage swing with this reference value. This is

calculated as 80% of VREF, i.e. 0.8 × 4.096V ≈ 3.275V peak to

peak on each input.

+2.5V

-2.5V

+2.5V

-2.5V

+2.048V

0.410V

+3.685V

VIN+

VIN-

+2.048V

0.410V

+3.685V

Figure 16. Differential Amplifier Signal Conditioning

To obtain maximum performance from the AD7763, it is

advisable to drive the ADC with differential signals. However, it

is possible to drive the AD7763 with a single ended signal once

the common mode of the signal is within the range of +0.7V to

+2.1V with VDD3 = 5V or +0.7 to +1.25V with VDD3 = 3.3V. In

this case the on-chip differential amplifier can be used to

convert the signal from single-ended to differential before being

fed into the modulator inputs. Figure 17 shows how a bipolar

single-ended signal biased around ground can be used to drive

the AD7763 with the use of an external op-amp such as the

AD8021.

RIN

RFB

CFB

VIN-

VIN+

AD8021

VIN

Figure 17. Single Ended to Differential Conversion

If using a 4.096V reference, a supply must be provided to the

reference buffer (AVDD4). If using a 2.5V reference, a 3.3V

supply must be provided to AVDD4 .

AD7763 Preliminary Technical Data

Rev. PrD | Page 18 of 24

USING THE AD7763

The following is the recommended sequence for powering up

and using the AD7763.

1. Apply Power

2. Start clock oscillator, applying MCLK

3. Ta ke RESET low for a minimum of 1 MCLK cycle

4. Wait a minimum of 2 MCLK cycles after RESET has

been released.

5. Write to Control Register 2 to power up the ADC and

the differential amplifier as required.

6. Write to Control Register 1 to set up the Output Data

Rate.

7. In circumstances where multiple parts are being

synchronized, a SYNC pulse must be applied to the

parts, otherwise no SYNC pulse is required.

Conditions for applying the SYNC pulse:

(a) The issue of a SYNC pulse to the part must

not coincide with a write to the part.

(b) The SYNC pulse should be applied a

minimum of 2.5 ICLK cycles after the CS

signal for the previous write to the part has

returned logic high.

a minimum of 2.5 ICLK cycles.

Data can now be read from the part using the default filter,

offset, gain, and over range threshold values. The

conversion data read will not be valid however until the

settling time of the filter has passed. When this has

occurred, the DVALID bit read will be set indicating that

the data is indeed valid.

The user can now download their own filter if required

(see Downloading a User-Defined Filter). Values for gain,

offset and over range threshold registers can be written or

read at this stage.

BIAS RESISTOR SELECTION

The AD7763 requires a resistor to be connected between the

RBIAS pin and AGND. The value for this resistor is dependant on

the reference voltage being applied to the device. The resistor

value should be selected to give a current of 25µA through the

resistor to ground. For a 2.5V reference voltage, the correct

resistor value is 100kΩ and for a 4.096V reference, 160kΩ.

Preliminary Technical Data AD7763

Rev. PrD | Page 19 of 24

PROGRAMMABLE FIR FILTER

As previously mentioned, the third FIR filter on the AD7763 is

user programmable. The default coefficients that are loaded on

reset are given in Table 9. This gives a frequency response

shown in Figure 18. The frequencies quoted in Figure 18 scale

directly with the Output Data Rate.

Table 9. Default Filter Coefficients

# Dec. Value Hex

Value # Dec.

Value Hex Value

0 53656736 332BCA0 24 700847 AB1AF

1 25142688 17FA5A0 25 -70922 401150A

2 -4497814 444A196 26 -583959 408E917

3 -11935847 4B62067 27 -175934 402AF3E

4 -1313841 4140C31 28 388667 5EE3B

5 6976334 6A734E 29 294000 47C70

6 3268059 31DDDB 30 -183250 402CBD2

7 -3794610 439E6B2 31 -302597 4049E05

8 -3747402 4392E4A 32 16034 3EA2

9 1509849 1709D9 33 238315 3A2EB

10 3428088 344EF8 34 88266 158CA

11 80255 1397F 35 -143205 4022F65

12 -2672124 428C5FC 36 -128919 401F797

13 -1056628 4101F74 37 51794 CA52

14 1741563 1A92FB 38 121875 1DC13

15 1502200 16EBF8 39 16426 402A

16 -835960 40CC178 40 -90524 401619C

17 -1528400 4175250 41 -63899 400F99B

18 93626 16DBA 42 45234 B0B2

19 1269502 135EFE 43 114720 1C020

20 411245 6466D 44 102357 18FD5

21 -864038 40D2F26 45 52669 CDBD

22 -664622 40A242E 46 15559 3CC7

23 434489 6A139 47 1963 7AB

The default filter should be sufficient for almost all applications.

It is a standard brick wall filter with a symmetrical impulse

response. The default filter has a length of 96, is non-aliasing

with 120dB of attenuation at Nyquist. This filter not only

performs signal anti-aliasing but also suppresses out-of-band

quantization noise produced by the A-D conversion process.

Any significant relaxation in the stop-band attenuation or

transition band width relative to the default filter may result in a

failure to meet the SNR specifications.

If a user does wish to create their own filter then the following

should be noted:

• The filter must be even, symmetrical FIR.

• The coefficients are in sign-and-magnitude format

with 26 magnitude bits and sign coded as positive=0.

• The filter length must be between 12 and 96 in steps of

12.

• As the filter is symmetrical, the number of coefficients

that must be downloaded will be half the filter length.

The default filter coefficients are an example of this

with only 48 coefficients listed for a 96-tap filter.

• Coefficients are written from the center of impulse

response (adjacent to the point of symmetry)

outwards.

• The coefficients are scaled so that the in-band gain of

the filter is equal to 134217726 with the coefficients

rounded to the nearest integer. For a low pass filter

this is the equivalent of having the coefficients sum

arithmetically (including sign) to +67108863 (0x3FF

FFFF) positive value over the half-impulse-response

coefficient set (max 48 coefficients). Any deviation

from this will result in a gain error being introduced.

Figure 18. Default Filter Frequency Response (625kHz ODR)

The procedure for downloading a user-defined filter is detailed

in the Downloading a User-Defined Filter section.

AD7763 Preliminary Technical Data

Rev. PrD | Page 20 of 24

DOWNLOADING A USER-DEFINED FILTER

As previously mentioned, the filter coefficients are 27 bits in

length; one sign and 26 magnitude bits. Since the AD7763 has a

16-bit parallel bus, the coefficients are padded with 5 MSB zeros

to generate a 32-bit word and split into two 16-bit words for

downloading. The first 16-bit word for each coefficient becomes

(00000, Sign bit, Magnitude[25:16]), while the second word

becomes (Magnitude [15:0]). To ensure that a filter is

downloaded correctly, a checksum must also be generated and

downloaded following the final coefficient. The checksum is a

16-bit word generated by splitting each 32-bit word mentioned

above into 4 bytes and summing all bytes from all coefficients

up to a maximum of 192 bytes (48 coefficients × 4 bytes). The

same checksum is generated internally in the AD7763 and

compared with the checksum downloaded. The DL_OK bit in

the Status Register is set if these two checksums agree. The

following is the procedure for downloading a user filter:

1. Write to Control Register 1 setting the DL_Filt bit and

also the correct filter length bits corresponding to the

length of the filter about to be downloaded (See Table

10).

2. Write the first half of the current coefficient data

(00000, Sign bit, Magnitude[25:16]). The first

coefficient to be written must be the one adjacent to

the point of filter symmetry.

3. Write the second half of the current coefficient data

(Magnitude [15:0]).

4. Repeat Steps 2 and 3 for each coefficient.

5. Write the 16-bit checksum.

6. There are two methods to verify that the filter

coefficients have been downloaded correctly:

a. Read the Status Register checking the

DL_OK bit.

b. Start reading data and observe the status of

the DL_OK bit.

Table 10. Filter Length Values

FLEN[3:0] Num Coeffs Filter Length

0000 Default Default

0001 6 12

0011 12 24

0101 18 36

0111 24 48

1001 30 60

1011 36 72

1101 42 84

1111 48 96

It should be borne in mind that since the user coefficients are

stored in RAM, they will be cleared after a RESET operation or

a loss of power.

EXAMPLE FILTER DOWNLOAD

The following is an example of downloading a short user

defined filter with 24-taps. The frequency response is shown in

Figure 19.

-80

-70

-60

-50

-40

-30

-20

-10

0 100 200 300 400 500 600

Frequency (kHz)

Amplitude (dB)

Figure 19. 24-Tap FIR Frequency Response

The coefficients for the filter are listed in Table 11. The

coefficients are shown from the center of symmetry outwards.

The raw coefficients were generated using a commercially

available filter design tool and scaled appropriately so their sum

equals +67108863 (0x3FF FFFF).

Table 11. 24-Tap FIR Coefficients

Coeff Raw Scaled

1 0.365481974 53188232

2 0.201339905 29300796

3 0.009636604 1402406

4 -0.075708848 -11017834

5 -0.042856209 -6236822

6 0.019944246 2902466

7 0.036437914 5302774

8 0.007592007 1104856

9 -0.021556583 -3137108

10 -0.024888355 -3621978

11 -0.012379538 -1801582

12 -0.001905756 -277343

Preliminary Technical Data AD7763

Rev. PrD | Page 21 of 24

Table 12 shows the Hex values (in sign and magnitude format)

that are downloaded to the AD7763 to realize this filter. The

table is also split into the bytes which are all summed to

produce the checksum. The checksum generated from these

coefficients is 0x0E6B.

Table 12. Filter Hex Values

Coeff Word 1 Word 2

Byte 1 Byte 2 Byte 3 Byte 4

1 03 2B 96 88

2 01 BF 18 3C

3 00 15 66 26

4 04 A8 1E 6A

5 04 5F 2A 96

6 00 2C 49 C2

7 00 50 E9 F6

8 00 10 DB

9 04 2F DE 54

10 04 37 44 5A

11 04 1B 7D 6E

12 04 04 3B 5F

What follows is a list of 16-bit words that the user would write

to the AD7763 to set up the ADC and download this filter

assuming an output data rate of 625kSPS has already been

selected.

0x0001 Address of Control Register 1

0x8079 Control Reg Data; DL Filter, Set Filter Length = 24, Set

Output Data Rate = 625kHz

0x032B First Coefficient, Word 1

0x9688 First Coefficient, Word 2

0x01BF Second Coefficient, Word 1

0x183C Second Coefficient, Word 2

… …

0x0404 Twelfth (Final) Coefficient, Word 1

0x3B5F Final Coefficient, Word 2

0x0E6B Checksum

Wait TBD xS for AD7763 to fill remaining unused coefficients

with zeros.

0x0001 Address of Control Register

0x0879 Control Reg Data; Set Read Status and maintain filter

length and decimation settings.

Read contents of Status Register. Check Bit 7 (DL_OK) to

determine that the filter was downloaded correctly.

AD7763 Preliminary Technical Data

Rev. PrD | Page 22 of 24

AD7763 REGISTERS

The AD7763 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter

configuration, the clock divider etc. There are also digital gain, offset and over-range threshold registers. Writing to these registers

involves writing the register address first, then a 16-bit data word. Register Addresses, details of individual bits and default values are

given here.

Table 13. Control Register 1 (Address 0x0001, Default Value 0x001A)

MSB LSB

Filt

Ovr

Gain

Off

Stat 0 SYNC FLEN3 FLEN2 FLEN1 FLEN0 BYP F3 BYP F1 DEC2 DEC1 DEC0

Bit Mnemonic Comment

15 DL Filt8 Download Filter. Before downloading a user defined filter, this bit must be set. The Filter Length bits must also be set at

this time. The write operations that follow will be interpreted as the user coefficients for the FIR filter until all the

coefficients and the checksum have been written.

14 RD Ovr8,9 Read Overrange. If this bit has been set, the next read operation will output the contents of the Overrange Threshold

13 RD Gain8,9 Read Gain. If this bit has been set, the next read operation will output the contents of the digital Gain Register.

12 RD Off8,9 Read Offset. If this bit has been set, the next read operation will output the contents of the digital Offset Register.

11 RD Stat8,9 Read Status. If this bit has been set, the next read operation will output the contents of the Status Register.

10 0

9 SYNC8 Synchronize. Setting this bit will initiate in internal synchronisation routine. Setting this bit simultaneously on multiple

devices will synchronize all filters.

8-5 FLEN3:0 Filter Length Bits. These bits must be set when the DL Filt bit is set and before a user defined filter is downloaded.

4 BYP F3 Bypass Filter 3. If this bit is a 0, Filter 3 (Programmable FIR) will be bypassed.

3 BYP F1 Bypass Filter 1. If this bit is a 0, Filter 1 will be bypassed. This should only occur when the user requires unfiltered

modulator data to be output.

2-0 DEC2:0 Decimation Rate. These bits set the decimation rate of Filter 2. All zeros implies that the filter is bypassed. A value of 1

corresponds to 2x decimation, a value of 2 corresponds to 4x and so on up to the maximum value of 5, corresponding

to 32x decimation.

8 Bits 15-9 are all self clearing bits.

9 Only one of the bits may be set in any write operation as they all determine the contents of the next operation.

Table 14. Control Register 2 (Address 0x0002, Default Value 0x009B)

MSB LSB

0 0 0 0 0 0 0 0 0 0 0 0 PD LPWR 1 D1PD

Bit Mnemonic Comment

3 PD Power Down. Setting this bit powers down the AD7763 reducing the power consumption to TBD µW.

2 LPWR Low Power. If this bit is set, the AD7763 is operating in a low power mode. The power consumption is reduced for a 3dB

reduction in noise performance.

1 Write a ‘1’ to this bit.

0 D1PD Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier.

Preliminary Technical Data AD7763

Rev. PrD | Page 23 of 24

Table 15. Status Register (Read Only)

MSB LSB

PA RT

DIE

0 DVALID LPWR OVR DL

Filter

Filter BYP F3 BYP F1 DEC2 DEC1 DEC0

Bit Mnemonic Comment

15,14 PART1:0 Part Number. These bits will be constant for the AD7763.

13-11 DIE2:0 Die Number. These bits will reflect the current AD7763 die number for identification purposes within a system.

10 DVALID Data Valid. This bit corresponds to the DVALID bit in the status word output in the second 16-bit read operation.

9 LPWR Low Power. If the AD7763 is operating in Low Power Mode, this bit is set to a 1.

8 OVR If the current analog input exceeds the current overrange threshold, this bit will be set.

7 DL OK When downloading a user filter to the AD7763, a checksum is generated. This checksum is compared to the one

downloaded following the coefficients. If these checksums agree, this bit is set.

6 Filter OK

When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter. This

generated checksum is compared to the one downloaded. If they match, this bit is set.

5 U Filter If a user-defined filter is in use, this bit is set.

4 BYP F3 Bypass Filter 3. If Filter 3 is bypassed by setting the relevant bit in Control Register 1, this bit is also set.

3 BYP F1 Bypass Filter 1. If Filter 1 is bypassed by setting the relevant bit in Control Register 1, this bit is also set.

2-0 DEC2:0 Decimation Rate. These correspond to the bits set in Control Register 1.

NON BIT-MAPPED REGISTERS

Offset Register (Address 0x0003, Default Value 0x0000)

The Offset Register uses 2’s Complement notation and is scaled such that 0x7FFF (maximum positive value) and 0x8000 (maximum

negative value) correspond to an offset of +0.78125% and -0.78125% respectively. Offset correction is applied after any gain correction.

Using the default gain value of 1.25 and assuming a reference voltage of 4.096V, the offset correction range is approximately ±25mV.

Gain Register (Address 0x0004, Default Value 0xA000)

The Gain Register is scaled such that 0x8000 corresponds to a gain of 1.0. The default value of this register is 1.25 (0xA000). This gives a

full scale digital output when the input is at 80% of VREF. This ties in with the maximum analog input range of ±80% of VREF Pk-Pk.

Over Range Register (Address 0x0005, Default Value 0xCCCC)

The Over Range register value is compared with the output of the first decimation filter to obtain an overload indication with minimum

propagation delay. This is prior to any gain scaling or offset adjustment. The default value is 0xCCCC which corresponds to 80% of VREF

(the maximum permitted analog input voltage) Assuming VREF = 4.096V, the bit will then be set when the input voltage exceeds

approximately 6.55v pk-pk differential. Note that the over-range bit is also set immediately if the analog input voltage exceeds 100% of

VREF for more than 4 consecutive samples at the modulator rate.

AD7763 Preliminary Technical Data

Rev. PrD | Page 24 of 24

OUTLINE DIMENSIONS

BOTTOM

VIEW

7.0 (0.276) BSC SQ

5.25 (0.207)

5.10 (0.201) SQ

4.95 (0.195)

0.60 (0.024)

0.42 (0.017)

0.24 (0.009)

0.50 (0.020)

0.40 (0.016)

0.30 (0.012)

PIN 1

INDICATOR

TOP

VIEW

6.75 (0.266)

BSC SQ

5.5 (0.217)

REF

0.25 (0.010)

MIN

0.60 (0.024)

0.42 (0.017)

0.24 (0.009)

0.70 (0.028) MAX

0.65 (0.026) NOM0.05 (0.002)

0.01 (0.0004)

0.0 (0.0)

0.20 (0.008)

REF

0.50 (0.020)

BSC

12°MAX

0.90 (0.035) MAX

0.85 (0.033) NOM

0.30 (0.012)

0.23 (0.009)

0.18 (0.007)

Figure 20. 48-Lead Frame Chip Scale Package [LFCSP] (CP-48)—Dimensions shown in millimeters

4964

12.0(0.47) BSC

10.0(0.39) BSC

0.50 (0.02)

BSC

0.22 ± 0.05

(0.0087 ± 0.002)

SEATING

PLANE

1.60 (0.063) MAX

0.60 ± 0.15

(0.024 ± 0.006) 12o

TYP

3.5o ± 3.5o

0.15(0.006)

0.05(0.002)

TOP VIEW 6.0(0.235)

BSC

Figure 21. 64-Lead Thin Quad Flat Pack (Exposed Paddle) [TQFP] (SV-64)—Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7763BCP –40°C to +85°C Lead Frame Chip Scale Package CP-48

AD7763BSV –40°C to +85°C Thin Quad Flat Pack, Exposed Paddle SV-64

registered trademarks are the property of their respective owners.

Printed in the U.S.A.

PR05476-0-4/05(PrD)