Product Folder Sample & Buy Support & Community Tools & Software Technical Documents bq24257: Not Recommended For New Designs bq24257 bq24258 SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 2 bq24257, bq24258 2-A Single Input I C, Standalone Switch-Mode Li-Ion/LiFePO4 Battery Charger with Integrated Current-Sense Resistor 1 1 Features * * * * * * * * * * * * * * * * High-efficiency Switch-mode Charger with Integrated Current Sense Resistor BC1.2 D+, D- Detection with Dead Battery Provision (DBP) Pin-to-Sync with External USBPHI USB Charging Compliant Selectable Input Current Limit of 100 mA, 150 mA, 500 mA, 900 mA. 1.5 A, and 2 A Watchdog Timer with Disable Bit Integrated 4.9-V, 50-mA LDO Complete System Level Protection - Input UVLO, Input Overvoltage Protection (OVP), Battery OVP, Sleep Mode, VIN_DPM - Input Current Limit - Charge Current Limit - Thermal Regulation and Thermal Shutdown - Voltage Based, JEITA Compatible NTC Monitoring Input - Safety Timer In Host Mode, Programmable VBATREG, ICHG, ILIM, VIN_DPM, VOVP and safety timer in host mode (after I2CTM Communication and Before Watchdog Timer Times Out) In Standalone Mode, Resistor Programmable ICHG, ILIM, and VIN_DPM in Standalone Mode (before I2CTM Communication and After Watchdog Timer Times Out) 20-V Maximum Input Voltage Rating 10.5-V Maximum Operating Input Voltage Low RDS(on) Integrated Sense Resistor for up to 2A Charging Rate Open Drain Status Outputs Synchronous Fixed-frequency PWM Controller Operating at 3 MHz for Small Inductor Support AnyBoot Robust Battery Detection Algorithm Charge Time Optimizer for Improved Charge Times at any Given Charge Current 3 Description The bq2425x is a highly integrated single-cell Li-Ion battery charger with integrated current sense resistor targeted for space-limited, portable applications with high capacity batteries. The single cell charger has a single input that operates from either a USB port or AC wall adapter for a versatile solution. BC1.2 compatible D+, D- detection allows for recognition of CDP, DCP, SDP, and non-standard USB adapters. The use of an accessory dead battery provision (DBP) pin allows for the system to sync a dead battery state in order to enable or disable the BC1.2 detection in the event of an external USB-PHI. The bq24257 has two modes of operation: 1) I2C mode, and 2) Standalone mode. In I2C mode, the host can adjust the charge parameters and monitor the status of the charger operation. In Standalone mode, the external resistor sets the input current limit, charge current limit, and the input DPM level. This mode also serves as the default settings when a DCP adapter is present. The bq24257 enters host mode while the I2C registers are accessed and the watchdog timer has not expired (if enabled). Device Information(1) PART NUMBER PACKAGE bq24257 bq24258 (Product Preview) BODY SIZE (NOM) QFN (24) 4.15 mm x 4.15 mm YFF (30) 2.027 mm x 2.427 mm QFN (24) 4.15 mm x 4.15 mm YFF (30) 2.027 mm x 2.427 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic for bq24257 CPMID 1F PMID IN VBUS DD+ GND SW LO 1.0PH CIN CBOOT 33 nF 2.2PF VDPM 3 MHz PWM BOOT PGND D- CSIN 1PF D+ Rsns LDO BAT 1 PF System Load VGPIO 22PF 2 Applications * * * * Mobile Phones, Smart Phones MP3 Players Handheld Devices Portable Media Player LDO SCL SCL SDA SDA Host GPIO1 TS TEMP PACK+ + STAT PACK- GPIO2 /CE GPIO3 /PG ILIM ISET 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description(cont.) .................................................. Device and Documentation Support.................... 1 1 1 2 2 2 9.6 Typical Characteristics ............................................ 11 10 Detailed Description ........................................... 14 10.1 10.2 10.3 10.4 10.5 Overview ............................................................... Functional Block Diagram ..................................... Feature Description............................................... Device Functional Modes...................................... Register Maps ....................................................... 14 15 16 29 31 6.1 Trademarks ............................................................... 2 6.2 Electrostatic Discharge Caution ................................ 3 11 Application and Implementation........................ 37 Device Comparison Table..................................... 3 Pin Configuration and FunctionsYFF package status from preview to final. ................................. 3 Specifications......................................................... 5 12 Power Supply Recommendations ..................... 41 13 Layout................................................................... 41 9.1 9.2 9.3 9.4 9.5 14 Mechanical, Packaging, and Orderable Information ........................................................... 42 ABSOLUTE MAXIMUM RATINGS .......................... Handling Ratings ...................................................... RECOMMENDED OPERATING CONDITIONS ....... Thermal Information ................................................. ELECTRICAL CHARACTERISTICS ......................... 5 5 6 6 7 11.1 Application Information.......................................... 37 11.2 Typical Application ............................................... 38 13.1 Layout Guidelines ................................................. 41 13.2 Layout Example .................................................... 41 13.3 Device and Documentation Support ..................... 42 4 Revision History Changes from Original (February 2013) to Revision A * Changed Changed from a Product Brief to full data sheet..................................................................................................... 1 Changes from Revision A (March 2013) to Revision B * Page Page Changed Changed the Product Preview data sheet .............................................................................................................. 1 Changes from Revision B (#IMPLIED) to Revision C Page * Changed datasheet to meet superior datasheet standards. ................................................................................................. 2 * Changed YFF package status from preview to final. ............................................................................................................ 3 5 Description(cont.) The bq24258 has only one mode of operation which is the Standalone. In this mode, the external resistor sets the input current limit, charge current limit, and the input DPM level. This mode also serves as the default settings when a DCP adapter is present. The EN1, EN2, and EN3 pin are available in the bq24258 spin to support USB 3.0 compliance. The battery is charged in four phases: trickle charge, pre-charge, constant current and constant voltage. In all charge phases, an internal control loop monitors the device junction temperature and reduces the charge current if the internal temperature threshold is exceeded. Additionally, a voltage-based, JEITA compatible battery pack thermistor monitoring input (TS) is included that monitors battery temperature for safe charging. 6 Device and Documentation Support 6.1 Trademarks I2C is a trademark of NXP B.V. Corporation. All other trademarks are the property of their respective owners. 2 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 6.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 7 Device Comparison Table DEVICE DEFAULT OVP D+/D- or EN1, EN2, EN3 DEFAULT VOREG VLOWV TS or DBP Termination (1) CHEM I2C ADDRESS DEFAULT USB ILIM bq24257 6.5 V D+/D- 4.2 V 3V TS 10% Li / LiPo Yes 0x6A 100mA bq24258 (Product Preview) 10.5 V EN1, EN2, EN3 4.2 V 3V TS 10% LiFePO4 No 0x6A N/A (2) (1) (2) Default behavior unless changed via I2C. Selectable via the EN1, EN2, EN3 pins. 8 Pin Configuration and Functions B C CSIN PGND BAT CSIN SW IN SW SW PGND IN IN PMID PGND 5 IN CSIN 4 BOOT BAT BAT 3 ILIM 2 VDPM A 1 LDO 30-Pin DSBGA, 24-Pin QFN YFF, RGE Package (Top View) 24 23 22 21 20 19 /CE 1 18 SW D+ 2 17 SW D- 3 16 PGND AGND 4 15 PGND SDA 5 14 CSIN SCL 6 13 CSIN bq24257 D E ISET /PG D- /CE D+ SCL STAT VDPM PMID BOOT TS ISET BAT BAT PMID IN ILIM 12 BOOT LDO 11 ILIM PGND 10 /PG SDA 9 VDPM TS 24 23 22 21 20 19 STAT F 8 LDO 7 bq24257 WCSP A B C 1 2 3 4 5 BAT CSIN PGND SW IN BAT BAT CSIN CSIN PGND SW PGND SW IN IN /CE 1 18 SW NC 2 17 SW EN3 3 16 PGND AGND 4 15 PGND EN1 5 14 CSIN EN2 6 13 CSIN PMID E /PG EN2 STAT VDPM BOOT F TS EN1 PGND LDO ILIM 7 8 9 10 11 12 BAT /CE BAT PGND TS EN3 ISET ISET /PG D STAT bq24258 bq24258 WCSP Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 3 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com Pin Functions PIN NAME bq24257 bq24257 YFF IN A5,B5,C5 PMID 4 bq24258 (Product Preview) bq24258 (Product Preview) I/O DESCRIPTION RGE YFF RGE 19 A5,B5,C5 19 I Input power supply. IN is connected to the external DC supply (AC adapter or USB port). Bypass IN to PGND with >2-F ceramic capacitor D5 20 D5 20 I Connection between blocking FET and high-side FET. Connect a 1-F capacitor from PMID to PGND as close to the PMID and PGND pins as possible SW A4,B4,C4 17-18 A4,B4,C4 17-18 O Inductor Connection. Connect to the switching side of the external inductor. BOOT E5 21 E5 21 I High-Side MOSFET Gate-Driver Supply. Connect a 0.033-F ceramic capacitor (voltage rating > 15 V) from BOOT to SW to supply the gate drive for the highside MOSFETs. PGND A3,B3,C3, F3 15-16 A3,B3,C3, D3,F3 15-16 CSIN A2,B2,C2 13-14 A2,B2,C2 13-14 I System Voltage Sense and SMPS output filter connection. Connect CSIN to the system output at the output bulk capacitors. Bypass CSIN locally with at least 1 F. BAT A1,B1,C1 11-12 A1,B1,C1 11-12 I/O Battery Connection. Connect to the positive terminal of the battery. Additionally, bypass BAT with at least 20-F capacitor to GND. TS F1 9 F1 9 I Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from LDO to GND. The NTC is connected from TS to GND. The TS function provides four thresholds for JEITA or PSE compatibility. See the NTC Monitor section for more details on operation and selecting the resistor values. VDPM E4 23 E4 23 I Input DPM Programming Input. Connect a resistor divider between IN and GND with VDPM connected to the center tap to program the Input Voltage based Dynamic Power Management threshold (VIN_DPM). The input current is reduced to maintain the supply voltage at VIN_DPM. The reference for the regulator is 1.2 V. Short pin to GND if external resistors are not desired--this sets a default of 4.68 V for the input DPM threshold. ISET D1 10 D1 10 I Charge Current Programming Input. Connect a resistor from ISET to GND to program the fast charge current. ILIM F5 22 F5 22 I Input Current Limit Programming Input. Connect a resistor from ILIM to GND to program the input current limit for IN. The current limit is programmable from 0.5 A to 2 A. ILIM has no effect on the USB input. If an external resistor is not desired, short to GND for a 2-A default setting. CE D4 1 D4 1 I Charge Enable Active-Low Input. Connect CE to a high logic level to place the battery charger in standby mode. EN1 -- -- F2 5 I EN2 -- -- E2 6 I Input Current Limit Configuration Inputs. Use EN1, EN2, and EN3 to control the maximum input current and enable USB compliance. See Table 1 for programming details. EN3 -- -- D2 3 I PG E1 8 E1 8 O Power Good Open Drain Output. PG is pulled low when a valid supply is connected to IN. A valid supply is between VBAT + VSLP and VOVP. If no supply is connected or the supply is out of this range, PG is high impedance. STAT E3 7 E3 7 O Status Output. STAT is an open-drain output that signals charging status and fault interrupts. STAT pulls low during charging. STAT is high impedance when charging is complete or the charger is disabled. When a fault occurs, a 256-s pulse is sent out as an interrupt for the host. STAT is enabled/disabled using the EN_STAT bit in the control register. STAT indicates recharge cycles. Connect STAT to a logic rail using an LED for visual indication or through a 10-k resistor to communicate with the host processor. Power Ground terminal. Connect to the ground plane of the circuit. For QFN only, connect to the thermal pad of the device. NC -- -- -- 2 SCL E2 6 -- -- Not connected SDA F2 5 D+ D3 2 -- -- I D- D2 3 -- -- I LDO F4 24 F4 24 O AGND -- 4 -- 4 I I2C Interface Clock. Connect SCL to the logic rail through a 10-k resistor. I/O I2C Interface Data. Connect SDA to the logic rail through a 10-k resistor. BC1.2 compatible D+/D- Based Adapter Detection. Detects DCP, SDP, and CDP. Also complies with the unconnected dead battery provision clause. D+ and D- are connected to the D+ and D- outputs of the USB port at power up. Also includes the detection of AppleTM and TomTomTM adapters where a 500mA input current limit is enabled. LDO output. LDO is regulated to 4.9 V and drives up to 50 mA. Bypass LDO with a 1-F ceramic capacitor. LDO is enabled when VUVLO < VIN < 19 V. Analog Ground for QFN only. Connect to the thermal pad and the ground plane of the circuit. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 9 Specifications 9.1 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Pin voltage range (with respect to PGND) MIN MAX IN -1.3 20 V SW -0.7 12 V PMID, BOOT -0.3 20 V CSIN, BAT, EN1,EN2, EN3, LDO, SCL, SDA, STAT, D+, D-, CE, ISET, ILIM, VDPM -0.3 7 V -0.3 BOOT relative to SW Output current (continuous) Output sink current UNIT 5 V IN 2 A CSIN, BAT 4 A STAT 5 mA Operating free-air temperature range -40 85 C Junction temperature, TJ -40 125 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 9.2 Handling Ratings Tstg Storage temperature range MIN MAX UNIT -65 150 C Lead temperature (soldering, 10 s) V(ESD) (1) (2) Electrostatic discharge 300 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 2 500 kV V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 5 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com 9.3 RECOMMENDED OPERATING CONDITIONS All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified pin. Consult Packaging Section of the data book for thermal limitations and considerations of packages. VIN MIN MAX IN voltage range 4.35 18 IN operating voltage range (bq24258) 4.35 10.5 IN operating voltage range (bq24257) 4.35 6.5 UNITS (1) V IIN Input current 2 A ICHG Current in charge mode, BAT 2 A IDISCHG Current in discharge mode, BAT RISET Charge current programming resistor range RILIM Input current limit programming resistor range TJ Operating junction temperature range, TJ (1) 4 A 75 105 0 125 C The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight layout minimizes switching noise. 9.4 Thermal Information THERMAL METRIC bq24257, bq24258 bq24257, bq24258 QFN YFF 24 PINS 30 PINS RJA Junction-to-ambient thermal resistance 32.9 76.5 RJC(top) Junction-to-case (top) thermal resistance 32.8 0.2 RJB Junction-to-board thermal resistance 10.6 44.0 JT Junction-to-top characterization parameter 0.3 1.6 JB Junction-to-board characterization parameter 10.7 43.4 RJC(bot) Junction-to-case (bottom) thermal resistance 2.3 n/a 6 Submit Documentation Feedback UNIT C/W Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 9.5 ELECTRICAL CHARACTERISTICS bq24257 App Circuit, VUVLO < VIN < VOVP AND VIN > VBAT+VSLP, TJ = 0C - 125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CURRENTS VUVLO < VIN < VOVP and VIN > VBAT + VSLP, PWM switching, CE enable IIN IBAT Supply current from IN 13 mA VUVLO < VIN < VOVP and VIN > VBAT + VSLP, PWM switching, CE disable Battery discharge current in high impedance SYSOFF mode , (BAT, SW,CSIN) 5 0C< TJ < 85C, High-Z Mode 170 225 A 0C< TJ < 85C, VBAT = 4.2 V, VIN = 0 V or 5V, High-Z Mode 16 22 A 1 A m 0C< TJ < 85C, VBAT = 4.2 V, VIN = 0V, SYSOFF Mode BATTERY CHARGER RSNS Internal battery charger MOSFET onresistance I2C mode VBATREG Measured from BAT to CSIN, VBAT = 4.2V (WCSP) 20 30 Measured from BAT to CSIN, VBAT = 4.2V (QFN) 30 40 Operating in voltage regulation, Programmable range SA mode TJ = 25C Voltage regulation accuracy TJ = 0C to 125C 3.5 4.44 V 4.2 -0.5% 0.5% -0.75% 0.75% Fast charge current range VLOWV VBAT < VBATREG 500 2000 Fast charge current accuracy I2C mode -7% +7% ICHG_LOW Low charge current Setting Set via I2C 297 330 363 mA KISET Programmable fast charge current factor 232.5 250 267.5 A ICHG ICHG = mA KISET RISET (0.5 A ICHG < 2 A) VISET Maximum ISET pin voltage (in regulation) RISET-SHORT Short circuit resistance threshold 0.42 Battery voltage rising bq24257 VLOWV Hysteresis for VLOWV IPRECHG Pre-charge current (VBATUVLO < VBAT < VLOWV) Ipre-charge is percentile of the external fast charge settings. Battery under voltage lockout threshold VBAT rising VBAT_UVLO 40 55 75 2.9 3 3.1 Battery voltage falling VBATSHRT Battery voltage rising Hysteresis for VBATSHRT Battery voltage falling IBATSHRT Trickle charge current (VBAT < VBATSHRT) tDGL(BATSHRT) Deglitch time for trickle charge tp precharge transition Termination current threshold ITERM Termination current threshold tolerance tDGL(TERM) Deglitch time for charge termination 10 12 2.37 2.5 2.63 1.9 Termination Current on SA only Both rising and falling, 2-mV overdrive, tRISE, tFALL = 100 ns Recharge threshold voltage Below VBATREG Deglitch time VBAT falling below VRCH, tFALL = 100 ns V 200 mV 32 ms 2 35 2.1 V mV 50 mA 256 us 10 %ICHG -10% VRCH % ICHG 100 25 tDGL(RCH) V mV 8 Deglitch time for pre-charge to fast charge transition Battery short threshold 100 Battery UVLO hysteresis tDGL(LOWV) V 10% 64 70 115 ms 160 32 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 mV ms 7 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com ELECTRICAL CHARACTERISTICS (continued) bq24257 App Circuit, VUVLO < VIN < VOVP AND VIN > VBAT+VSLP, TJ = 0C - 125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BATTERY CHARGER LiFePO4 (bq24258) VREG-OVCHG Over charge voltage regulation 3.76 3.8 3.84 V VFLT-CHG Float charge regulation 3.46 3.5 3.54 V VOVCHG Overcharge comparator for LiFePo 3.65 3.7 3.75 VBAT rising VOVCHG-HYS tDGL(OVCHG) VBAT falling Deglitch on the overcharge comparator V 300 mV 32 ms BATTERY DETECTION VBATREG_HI Battery detection high regulation voltage Same as VBATREG VBATREG V VBATREG_LO Battery detection low regulation voltage 360 mV offset from VBATREG VBATREG - 480mV V VBATDET_HI Battery detection comparator VBATREG = VBATREG_HI VBATREG - 120 mV V VBATDET_LO Battery detection comparator VBATREG = VBATREG_LO VBATREG + 120 mV V IDETECT Battery detection sink current) Always on during battery detection 7.5 mA tDETECT Battery detection time For both VBATREG_HI and VBATREG_LO 32 ms Tsafe Safety timer accuracy -10% 10% INPUT PROTECTION IIN Input current limiting IIN_LIMIT = 100 mA 90 95 100 IIN_LIMIT = 150 mA 135 142.5 150 IIN_LIMIT = 500 mA 450 475 500 IIN_LIMIT = 900 mA 810 860 910 IIN_LIMIT = 1500 mA 1400 1475 1550 IIN_LIMIT = 2000 mA 1850 1950 2050 ILIM = IIN_LIMIT = External ILIM Maximum input current limit programmable range for IN input KILIM Maximum input current factor for IN input VILIM Maximum ILIM pin voltage (in regulation) RILIM-SHORT Short circuit resistance threshold VREF_DPM VDPM_SHRT VUVLO tDGL(SLP) VOVP 8 240 55 270 2000 mA 300 A 83 V 105 SA mode 4.2 10 V I2C mode 4.2 4.76 V 2% VIN_DPM threshold accuracy Both I2C and SA mode -2% DPM regulation voltage External resistor setting only 1.15 VIN_DPM short threshold If VDPM is shorted to ground, VIN_DPM threshold will use internal default value IC active threshold voltage VIN rising IC active hysteresis VIN falling from above VUVLO Sleep-mode entry threshold, VSUPPLYVSLP RILIM 0.42 VIN_DPM threshold range VIN_DPM KILIM 500 ILIM = 500 mA to 2 A mA 1.2 1.25 0.3 3.15 3.35 V V 3.5 175 V mV VIN falling 0 50 100 mV Sleep-mode exit hysteresis VIN rising 40 100 160 mV Deglitch time for supply rising above VSLP+VSLP_EXIT Rising voltage, 2-mV over drive, tRISE = 100ns Input supply OVP threshold voltage (bq24258) IN rising IN_OVP -200mV IN_OVP IN_OVP +200mV Input supply OVP threshold voltage (bq24257) IN rising IN_OVP -200mV IN_OVP IN_OVP +200mV VOVP hysteresis IN falling from VOVP 100 6.8 VBAT Submit Documentation Feedback 32 ms V mV Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 ELECTRICAL CHARACTERISTICS (continued) bq24257 App Circuit, VUVLO < VIN < VOVP AND VIN > VBAT+VSLP, TJ = 0C - 125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Deglitch time for IN Rising above VOVP IN rising voltage, tRISE = 100ns Battery OVP threshold voltage VBAT threshold over VBATREG to turn off charger during charge VBATOVP hysteresis Lower limit for VBAT falling from above VBOVP 1 BOVP Deglitch Battery entering/exiting BOVP 1 RON(BLK) Internal blocking MOSFET onresistance Measured from IN to PMID (WCSP and QFN) RON(HS) Internal high-side MOSFET onresistance RON(LS) Internal low-side MOSFET onresistance ICbC Cycle-by-cycle current limit fOSC Oscillator frequency DMAX Maximum duty cycle DMIN Minimum duty cycle tDGL(OVP) VBOVP tDGL(BOVP) MAX UNIT 32 102.5 105 ms 107.5 % VBATREG ms PWM CONVERTER TSHTDWN TREG 60 100 m Measured from PMID to SW (WCSP and QFN) 100 150 m Measured from SW to PGND (WCSP and QFN) 110 165 m 2.6 3.2 3.8 A 2.7 3 3.3 MHz 95% 0% Thermal trip 150 Thermal hysteresis 10 Thermal regulation threshold Charge current begins to cut off VLDO LDO output voltage VIN = 5.5V, ILDO = 0 to 50 mA ILDO Maximum LDO output current VLDO LDO dropout voltage (VIN - VLDO) C 125 LDO 4.65 4.95 5.25 V 50 VIN = 5 V, ILDO = 50 mA mA 200 300 30 30.4 mV BATTERY-PACK NTC MONITOR VHOT High temperature threshold VTS falling VHYS(HOT) Hysteresis on high threshold VTS VWARM Warm temperature threshold VTS falling VHYS(WARM) Hysteresis on warm temperature threshold VTS rising VCOOL Cool temperature threshold VTS rising VHSY(COOL) Hysteresis on cool temperature threshold VTS falling VCOLD Low temperature threshold VTS rising VHYS(COLD) Hysteresis on low threshold VTS falling VTS_DIS TS disable threshold tDGL(TS) Deglitch time on TS change 29.6 rising 1 37.9 38.3 38.7 %VLDO 1 56.5 56.5 56.9 %VLDO 1 59.6 60 60.4 1 70 %VLDO 73 %VLDO %VLDO 32 ms INPUTS (DBP, EN1, EN2, EN3, CE, SCL, SDA) VIH Input high threshold VIL Input low threshold 1 V 0.4 V STATUS OUTPUTS (STAT, PG, CHG) VOL Low-level output saturation voltage IO = 5 mA, sink current IIH High-level leakage current Hi-Z and 5 V applies 0.4 V 1 uA TIMERS tSAFETY tWATCH-DOG 45 min safety timer 2700 s 6 hr safety timer 21600 s 9 hr safety timer 32400 s Watch dog timer 50 s Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 9 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com ELECTRICAL CHARACTERISTICS (continued) bq24257 App Circuit, VUVLO < VIN < VOVP AND VIN > VBAT+VSLP, TJ = 0C - 125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT D+, D- DETECTION IDP_SRC D+ current source for DCD DCD 7 13 A RDM_DWN D- pull-down resistance for DCD DCD 14.25 24.8 k VDP_LOW D+ low comparator threshold for DCD DCD 0.85 0.9 0.95 V VDP_SRC D+ source voltage for primary detection Primary Detection 0.5 0.6 0.7 V IDP_SRC_PD D+ source voltage output current for primary detection Primary Detection 200 IDM_SINK D- sink current for primary detection Primary Detection 50 100 150 A VDAT_REF Primary detection threshold Primary Detection 250 325 400 mV VLGC Primary detection threshold Primary Detection 0.85 0.9 0.95 V VDM_SRC D- source voltage for Secondary Detection Secondary Detection 0.5 0.6 0.7 V IDM_SRC_PD D- source voltage output current for secondary detection Secondary Detection 200 IDP_SINK D+ sink current for secondary detection Secondary Detection 50 100 150 A VDAT_REF Secondary detection threshold Secondary Detection 250 325 400 mV VATT_LO Apple/TomTom detection low threshold Apple, TomTom Detection 1.8 1.85 1.975 V VATT_HI Apple/TomTom detection high threshold Apple, TomTom Detection 3.2 3.5 4.05 V CI Input capacitance ID_LKG 10 Leakage current into D+/D- A A D- , switch open 4.5 D+, switch open 4.5 pF pF D-, switch open -1 1 A D+, switch open -1 1 A Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 9.6 Typical Characteristics Figure 1. Battery Detection Figure 2. Battery Removal 88 4.350 ICHG = 2 A VIN = 5 V VREG = 4.2 V 86 4.340 4.335 82 VSYS-REG (V) Efficiency (%) 84 4.345 80 78 76 4.330 4.325 4.320 4.315 74 4.310 72 4.305 bq24257 70 4.300 2.9 3.1 3.3 3.5 3.7 3.9 4.1 VBAT (V) 4.3 0.0 1.0 1.5 2.0 2.5 ISYS (A) Figure 3. Efficiency vs. Battery Voltage C004 Figure 4. System Voltage Regulation vs. Load Current 100 100 95 95 90 90 85 85 Efficiency (%) Efficiency (%) 0.5 C001 80 75 70 65 80 75 70 65 60 V VIN ==55V VIN 60 V VIN ==55V VIN 55 VIN ==77V V VIN 55 VIN ==77V V VIN VIN ==10 V VIN 10V 50 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Output Current (mA) VIN ==10 V VIN 10V 50 0 200 400 Figure 5. Efficiency vs. Output Current 600 800 1000 1200 1400 1600 1800 2000 Output Current (mA) C002 C003 Figure 6. Efficiency vs. Output Current Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 11 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com Typical Characteristics (continued) 20 16 18 14 16 Input Current (mA) 18 IBAT ( A) 12 10 8 6 4 CE EN CE DIS 14 12 10 8 6 2 4 0 2 0 2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VBAT (V) 5.0 0 5 10 15 20 Input Voltage (V) C007 25 C008 Figure 8. Input IQ with Charge DIS and EN Figure 7. VBAT IQ vs. IBAT 500 450 Input Current ( A) 400 350 300 250 200 ICHG = 1 A ILIM = 1.5 A ISYS = 0 A VBAT = 3.6 V 150 100 50 0 0 5 10 15 20 Input Voltage (V) 25 C009 Figure 9. Input IQ with Charge Enable and Hz Figure 10. Startup ICHG = 1 A ILIM = 1 A VBAT = 3.9 V VOVP = 10.5 V ICHG = 2 A ILIM = 0.5 A ISYS = 0 A VBAT = 3.6 V VDPM = 4.36 V Figure 11. Input OVP Event with INT 12 Submit Documentation Feedback Figure 12. VDPM Startup, 4.2 V Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com bq24257 bq24258 SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 Typical Characteristics (continued) ICHG = 1 A ISYS = 0 A VBAT = 3.3 V VIN = 5.2 V Figure 13. 1.0-H CCM Operation Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 13 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com 10 Detailed Description 10.1 Overview The bq24257 is a highly-integrated, single-cell, Li-Ion battery charger with integrated current sense resistors targeted for space-limited, portable applications with high-capacity batteries. The single-cell charger has a single input that operates from either a USB port or AC wall adapter for a versatile solution. The bq24257 device has two modes of operation: 1. I2C Mode 2. Standalone Mode In I2C mode, the host adjusts the charge parameters and monitors the status of the charger operation. In standalone mode, the external resistor sets the input-current limit, and charge current limit. Standalone mode also serves as the default settings when a DCP adapter is present. It enters host mode while the I2C registers are accessed and the watchdog timer has not expired (if enabled). The battery is charged in four phases: trickle charge, pre-charge, constant current and constant voltage. In all charge phases, an internal control loop monitors the device junction temperature and reduces the charge current if the internal temperature threshold is exceeded. 14 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 10.2 Functional Block Diagram PMID Q1 LDO LDO IN Charge Pump Q2 VREF_CBCLIM ILIM _ + BOOT CbC Comparator IIN_LIM Amp _ VDPM + VREF_INLIM VIN_DPM Amp + VREF_DPM PWM LOOP SELECT COMPENSATION DRIVER _ Host SW + VDPM_DAC _ V LDO I2C Only Q3 TJ PGND + 125C ICHG Amp _ ISET + VBATREG Amp Sleep Comparator _ CSIN _ + VREF_BATREG VREF_ICHG VBAT +VSLP + VREF_TERM EN2 / D- + EN1 / D+ LDO Termination Comparator Input current limit decoder / D+ and DDecoder Q4 Recharge Comparator + Batt Detect Or Precharge Curent Source VBATREG 0.12V VBAT BAT SCL I2C Controller SDA Charge Pump CHARGE CONTROLLER / PG - BATSHORT Comparator STAT , + VBAT VBATSHRT Supplement Comparator V SYS + DISABLE VBAT V BSUP VLDO + /CE TS -10C + TS 0C + TS 10 C + TS 45 C + TS 60C TS Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 15 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com 10.3 Feature Description 10.3.1 EN1, EN2, EN3 Pins If the D+, D- detection pins are not used (bq24257), input current limit can be programmed through the host. The EN1, EN2, and EN3 pins are available in the bq24258 spin to support USB 3.0 compliance. When the input current limit pins change state, the VIN_DPM threshold changes as well. See Table 1 for details: Table 1. EN1, and EN2 Truth Table (1) (1) 16 EN3 EN2 EN1 INPUT CURRENT LIMIT VINDPM THRESHOLD 0 0 0 500mA 4.36V 0 0 1 Externally programmed by ILIM (up to 2.0A) Externally programmed VDPM 0 1 0 100mA 4.36V 0 1 1 Input Hi-Z None 1 0 0 900mA 4.36V 1 0 1 Externally programmed by ILIM (up to 2.0 A) Externally programmed VDPM 1 1 0 150mA 4.36V 1 1 1 Input Hi-Z None If EN3 = 0, it will be USB 2.0 compliant; If EN3 = 1, USB 3.0 compliant. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com bq24257 bq24258 SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 10.3.2 I2C and Stand Alone Operation The bq24257 series offers a unique feature when compared to traditional host mode chargers--the default input current limit, output current limit and VIN_DPM parameters can be set via external resistors. In traditional host mode chargers, the default parameters are programmed during manufacturing to set the I2C registers at a specific default. If an end application calls for an alternate default setting, the traditional charger is left with the only option of changing the parameters at the manufacturing stage. This may not always be acceptable. Figure 14 illustrates the behavior of the bq24257 when transitioning between I2C mode and stand alone mode (except for the bq24257). Battery or Input is Inserted No VIN or VBAT GOOD? Yes i2c command received? No ILIM=EN1/EN2 VDPM=External Default ISET=External Default Yes ILIM=Register Value VDPM=Register Value ISET=Register Value No 32s Watchdog Expired? Yes Figure 14. I2C and Stand Alone Mode Handoff Once the battery or input is inserted and above the good thresholds, the device will determines if an I2C command has been received in order to discern whether to operate from the I2C registers or the external settings. Note that the bq24257 does not have EN1/EN2 pins and therefore the input current limit will be based on the D+/D- results. When in host mode (I2C operation), the device will enter stand alone operation once the watchdog timer expires. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 17 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com 10.3.2.1 External Settings: ISET, ILIM and VIN_DPM The fast charge current resistor (RISET) can be set by using the following formula: K 250 RISET = ISET = IFC IFC (1) Where IFC is the desired fast charge current setting in Amperes. The input current limit resistor (RILIM) can be set by using the following formula: K 270 RILIM = ILIM = IIC IIC (2) Where IIC is the desired input current limit in Amperes. Based on the application diagram reference designators, the resistor R1 and R2 can be calculated as follows to set VIN_DPM: R + R2 R + R2 VIN _ DPM = VREF _ DPM 1 = 1.2 1 R2 R2 (3) VIN_DPM should be chosen first along with R1. Choosing R1 first will ensure that R2 will be greater than the resistance chosen. This is the case since VIN_DPM should be chosen to be greater than 2x VREF_DPM. If resistors are not desired for BOM count reduction, the VDPM and the ILIM pins can be shorted to set the internal defaults. However, the ISET resistor must be populated as this will be interpreted as a fault. Table 2 summarizes the settings when the ILIM, ISET, and VIN_DPM pins are shorted to GND. Table 2. ILIM, VDPM, and ISET Short Behaviors 18 PIN SHORTED BEHAVIOR ILIM Input current limit = 2 A VDPM VIN_DPM = 4.68 V ISET Fault--charging suspended Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com bq24257 bq24258 SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 10.3.3 BC1.2 D+/D- Detection The bq24257 includes a fully BC1.2 compatible D+/D- source detection. This detection supports the following types of ports: * DCP (dedicated charge port) * CDP (charging downstream port) * SDP (standard downstream port) * AppleTM/TomTomTM ports This D+/D- detection algorithm does not support ACA (accessory charge adapter) identification, but the input current will default to 500mA when a charge port is attached to the ACA and bq24257 is connected to the OTG port. The D+/D- detection algorithm is only active when the device is in standalone mode (e.g. the host is not communicating with the device and the watch dog timer has expired). However, when the device is in host mode (that is, host is communicating via I2C to the device) writing a `1' to register 0x04 bit location 4 (DPDM_EN) forces the device to perform a D+/D- detection on the next power port insertion. This allows the D+/D- detection to be enabled in both host mode and default mode. The D+/D- detection algorithm has 5 primary states. These states are termed the following: 1. Data Contact Detect 2. Primary Detection 3. Secondary Detection 4. Non-standard Adapter Detection (for AppleTM / TomTomTM) 5. Detection Configuration The DCD state determines if the device has properly connected to the D+/D- lines. If the device is not in host mode and VBUS is inserted (or DPDM_EN is true) the device will enter the DCD state and enable the appropriate algorithm. If the DCD timer expires, the device will enter the Non-standard Adapter Detection (for AppleTM / TomTomTM) state. Otherwise it will enter the Primary Detection state. When entering the Primary Detection state, the appropriate algorithm is enabled to determine whether to enter the secondary detection state for DCP and CDP or the secondary detection state for SDP/Non-Standard adaptors. The non-standard adapter detection state for AppleTM / TomTomTM tests for the unique conditions for these nonstandard adapters. If the algorithm passes the unique conditions found with these adapters, it will proceed to the Detection Configuration state. Otherwise it will revert back to the primary detection state. The secondary detection state determines whether the input port is a DCP, CDP, SDP, or other non-standard adapters. If the Primary Detection state indicated that the input port is either a DCP or CDP, the device will enable the appropriate algorithm to differentiate between the two. If the Primary Detection state indicated that the input port is either a SDP or non-standard adapter, the device will enable the appropriate algorithm to differentiate between these two ports. Once complete, the device will continue to the Detection Configuration state. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 19 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 DCP Settings www.ti.com No VBAT > VBATGD? Yes Turn on V DP_SRC And keep it on until CLR_VDP is set to `1' in i2c DCP External ILIM Start 6 hr timer Non Standard Adapter SDP Settings CDP Settings VBAT > VBATGD Yes No Turn on VDP_SRC And keep it on until CLR_VDP is set to `1' CDP and weak battery CDP and good battery SDP and weak battery SDP and good battery Apple/TT or Non-Standard IILIM=100mA Start 45 min timer IILIM=1500mA Start 6 hr timer IILIM=100mA Start 45 min timer Hi-Z mode IILIM=0.5A Start 6 hr timer Detection Done. Set detection status in register Figure 15. Detection Configuration State The detection configuration state sets the input current limit of the device along with the charge timer. The exception to the CDP and the SDP settings are due to the Dead Battery Provision (DBP) clause for unconnected devices. This clause states that the device can pull a maximum of 100mA when not connected due to a dead battery. During the battery wakeup time, the device sources a voltage on the D+ pin in order to comply with the DBP clause. Once the battery is good, the system can clear the D+ pin voltage by writing a `1' to address 0x07 bit position 4 (CLR_VDP). The device must connect to the host within 1sec of clearing the D+ pin voltage per the DPB clause. A summary of the input current limits and timer configurations for each charge port type are found in Table 3. Table 3. D+, D- Detection Results per Charge Port Type 20 CHARGE PORT TYPE INPUT CURRENT LIMIT CHARGE TIMER DCP External ILIM 6 hours 45 minutes CDP Dead Battery 100 mA CDP Good Battery 1500 mA 6 hours SDP Dead Battery 100 mA 45 minutes SDP Good Battery Hi-Z N/A Non-Standard 500 mA 6 hours Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com bq24257 bq24258 SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 10.3.4 Transient Response The bq2425x includes an advanced hybrid switch mode control architecture. When the device is regulating the charge current (fast-charge), a traditional voltage mode control loop is used with a Type-3 compensation network. However, the bq2425x switches to a current mode control loop when the device enters voltage regulation. Voltage regulation occurs in two charging conditions: 1) Battery voltage regulation (IBAT < ICHG), and 2) Charge Done. This architecture allows for superior transient performance when regulating the voltage due to the simplification of the compensation when using current mode control. The below transient response plot illustrates a 0 A to 2-A load step with 4.7 ms full cycle and 12% duty cycle. A 3.9 V Li-Ion battery is used. The input voltage is set to 5 V, charge current is set to 0.5 A and the input current is limited to 0.5 A. . Note that a high line impedance input supply was used to indicate a realistic input scenario (adapter and cable). This is illustrated by the change in VIN seen at the input of the IC. The figure shows a ringing at both the input voltage and the input current. This is caused by the input current limit speed up comparator. Figure 16. 2A Load step Transient Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 21 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 10.3.5 www.ti.com AnyBoot Battery Detection The bq24257 includes a sophisticated battery detection algorithm used to provide the system with the proper status of the battery connection. The AnyBoot battery algorithm also guarantees the detection of voltage based battery protectors that may have a long closure time (due to the hysteresis of the protection switch and the cell capacity). The AnyBoot battery detection algorithm is utilizes a dual-voltage based detection methodology where the csin rail will switch between two primary voltage levels. The period of the voltage level shift is 64ms and therefore the power supply rejection of the down-system electronics will see this shift as essentially DC. The AnyBoot algorithm has essentially 3 states. The 1st state is used to determine if the device has terminated with a battery attached. If it has terminated due to the battery not being present, then the algorithm moves to the 2nd and 3rd states. The 2nd and 3rd states shift the csin voltage level between 4.2V and 3.72V. In each state there are comparator checks to determine if a battery has been inserted. The two states guarantees the detection of a battery even if the voltage of the cell is at the same level of the comparator thresholds. The algorithm will remain in states 2 and 3 until a battery has been inserted. The flow diagram details for the Anyboot algorithm are shown in Figure 17. 22 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com bq24257 bq24258 SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 Enter Battery Detection BATREG = Vreg setting - 480mV No VBAT > BATREG+120mV? Yes Yes Battery Detected, STAT register updated, and PTM mode aborted (if enabled) Yes Battery Detected, STAT register updated and Exit Battery Detection Yes Battery Detected, STAT register updated and Exit Battery Detection 32ms Timer Expired? No No 25ms Timer Expired? Yes BATREG = 4.2V No VBAT < 4.08V? Yes 32ms Timer Expired? No No 25ms Timer Expired? Yes ONLY ON FIRST LOOP ITERATION "No Battery" Condition BATREG = 4.2V Update STAT Registers and send Fault Pulse Yes EN_PTM=1 and NVM_EN_PTM=1? Enter PTM mode Exit Battery Detection No BATREG = 3.72V No VBAT > 3.84V? Yes 32ms Timer Expired? No No 25ms Timer Expired? Yes Figure 17. AnyBoot Battery Detection Flow Diagram Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 23 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com 10.3.5.1 Input Voltage Based DPM During normal charging process, if the input power source is not able to support the programmed or default charging current, the supply voltage deceases. Once the supply drops to VIN_DPM, the input current limit is reduced down to prevent the further drop of the supply. When the IC enters this mode, the charge current is lower than the set. This feature ensures IC compatibility with adapters with different current capabilities without a hardware change. 10.3.5.2 Sleep Mode The bq2425x enters the low-power sleep mode if the voltage on VIN falls below sleep-mode entry threshold, VBAT + VSLP, and VIN is higher than the under-voltage lockout threshold, VUVLO. This feature prevents draining the battery during the absence of VIN. When VIN < VBAT + VSLP, the bq2425x turns off the PWM converter, turns on the battery FET, sends a single 256 s pulse is sent on the STAT output and the FAULT/STAT bits of the status registers are updated in the I2C. Once VIN > VBAT + VSLP with the hysteresis, the FAULT bits are cleared and the device initiates a new charge cycle. 10.3.5.3 Hiz Mode Set the HZ_MODE bit to 1 to put the device in Hiz mode. In Hiz, the charger device is in low-power standby mode and the switch mode controller is disabled. 10.3.5.4 Input Over-Voltage Protection The bq2425x provides over-voltage protection on the input that protects downstream circuitry. The built-in input over-voltage protection to protect the device and other components against damage from over voltage on the input supply (Voltage from VIN to PGND). When VIN > VOVP, the bq2425x turns off the PWM converter, turns the battery FET, sends a single 256 s pulse is sent on the STAT output and the FAULT/STAT bits of the status registers and the battery/supply status registers are updated in the I2C. Once the OVP fault is removed, the FAULT bits are cleared and the device returns to normal operation. The OVP threshold for the bq2425x is programmable from 6.5 V to 10.5 V using VOVP bits in register #7. 24 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com bq24257 bq24258 SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 10.3.5.5 NTC Monitor (contact the local TI representative for function availability) The bq24257 includes the integration of an NTC monitor pin that complies with the JEITA specification (PSE also available upon request). The voltage based NTC monitor allows for the use of any NTC resistor with the use of the circuit shown below: LDO R2 TS NTC R3 Figure 18. Voltage Based NTC Circuit The use of R3 is only necessary when the NTC does not have a beta near 3500K. When deviating from this beta, error will be introduced in the actual temperature trip thresholds. The trip thresholds are summarized below which are typical values provided in the specification table. Table 4. Ratiometric TS Trip Thresholds for JEITA Compliant Charging VHOT 30.0% VWARM 38.3% VCOOL 56.5% VCOLD 60% When sizing for R2 and R3, it is best to solve two simultaneous equations that ensure the temperature profile of the NTC network will cross the VHOT and VCOLD thresholds. The accuracy of the VWARM and VCOOL thresholds will depend on the beta of the chosen NTC resistor. The two simultaneous equations are shown below: %VCOLD ae R3 RNTC o TCOLD / c c R3 + RNTC / TCOLD o = e 100 ae R3 RNTC o TCOLD c / + R2 c R3 + RNTC / TCOLD e o %VHOT ae R3 RNTC o THOT / c c R3 + RNTC / THOT o = e 100 ae R3 RNTC o THOT c / + R2 c R3 + RNTC / THOT e o (4) Where the NTC resistance at the VHOT and VCOLD temperatures must be resolved as follows: b 1 -1 TCOLD To RNTC TCOLD RNTC THOT = Ro e ( 1 -1 THOT To =Ro e ( ) ) (5) To be JEITA compliant, TCOLD must be 0C and THOT must be 60C. If an NTC resistor is chosen such that the beta is 4000K and the nominal resistance is 10k, the following R2 and R3 values result from the above equations: R2 = 5 k R3 = 9.82 k Figure 19 illustrates the temperature profile of the NTC network with R2 and R3 set to the above values. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 25 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com Example NTC Network Profile of %LDO vs. TEMP 60 Tcool LDO Percent (%) 55 50 45 40 Twarm 35 30 0 10 20 30 40 50 60 Temperature (C) Figure 19. Voltage Based NTC Circuit Temperature Profile For JEITA compliance, the TCOOL and TWARM levels are to be 10C and 45C respectively. However, there is some error due to the variation in beta from 3500K. As shown above, the actual temperature points at which the NTC network crosses the VCOOL and VWARM are 13C and 47C respectively. This error is small but should be considered when choosing the final NTC resistor. Once the resistors are configured, the internal JEITA algorithm will apply the below profile at each trip point for battery voltage regulation and charge current regulation. Charge Programmed VBAT_REG 4.10 V max 4.06 V typ No Charge No Charge Programmed ICHG (1C) Charge 0.5C No Charge No Charge TS_DIS VCOLD VCOOL VWARM VHOT Figure 20. JEITA Profile for Voltage and Current Regulation Loops 26 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 10.3.6 Production Test Mode To aid in end mobile device product manufacturing, the bq24257 includes a Production Test Mode (PTM), where the device is essentially a DC-DC buck converter. In this mode the input current limit to the charger is disabled and the output current limit is limited only by the inductor cycle-by-cycle current (e.g. 3.5A). The PTM mode can be used to test systems with high transient loads such as GSM transmission without the need of a battery being present. As a means of safety, the Anyboot algorithm will determine if a battery is not present at the output prior to enabling the PTM mode. If a battery is present and the software attempts to enter PTM mode, the device will not enable PTM mode. 10.3.7 Safety Timer At the beginning of charging process, the bq24257 starts the safety timer. This timer is active during the entire charging process. If charging has not terminated before the safety timer expires, the IC enters suspend mode where charging is disabled. The safety timer time is selectable using the I2C interface. A single 256s pulse is sent on the STAT output and the FAULT/ bits of the status registers are updated in the I2C. This function prevents continuous charging of a defective battery if the host fails to reset the safety timer. The safety timer runs at 2x the normal rate under the following conditions: Pre-charge mode, during thermal regulation where the charge current is reduced, during TS fault where the charge current reduced due to temperature rise on the battery, input current limit. The safety timer is suspended during OVP, TS fault where charge is disabled, thermal shut down, and sleep mode. 10.3.8 Fault Modes The bq2425x family includes several hardware fault detections. This allows for specific conditions that could cause a safety concern to be detected. With this feature, the host can be alleviated from monitoring unsafe charging conditions and also allows for a "fail-safe" if the host is not present. Table 5 summarizes the faults that are detected and the resulting behavior. Table 5. Fault Condition Fault Condition Charger Behavior Safety Timer Behavior Suspended Input OVP ICHG Disabled Input UVLO ICHG Disabled Reset Sleep (VIN < VBAT) ICHG Disabled Suspended TS Fault (Batter Over Temp) ICHG Disabled Suspended Thermal Shutdown ICHG Disabled Suspended Timer Fault ICHG Disabled Reset No Battery ICHG Disabled Suspended ISET Short ICHG Disabled Suspended Input Fault and LDO Low ICHG Disabled Suspended Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 27 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com 10.3.9 Watchdog Timer In addition to the safety timer, the bq24257 contains a 50-second watchdog timer that monitors the host through the I2C interface. Once a write is performed on the I2C interface, a watchdog timer is reset and started. The watchdog timer can be disabled by writing "0" on WD_EN bit of register #1. Writing "1" on that bit enables it and reset the timer. If the watchdog timer expires, the IC enters DEFAULT mode where the default charge parameters are loaded and charging continues. The I2C may be accessed again to re-initialize the desired values and restart the watchdog timer as long as the safety timer has not expired. Once the safety timer expires, charging is disabled. 10.3.10 Thermal Regulation and Thermal Shutdown During the charging process, to prevent overheat of the chip, bq2425x monitors the junction temperature, TJ, of the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TREG. The charge current is reduced when the junction temperature increases about above TREG. Once the charge current is reduced, the system current is reduced while the battery supplements the load to supply the system. This may cause a thermal shutdown of the IC if the die temperature rises too. At any state, if TJ exceeds TSHTDWN, bq2425x suspends charging and disables the buck converter. During thermal shutdown mode, PWM is turned off, all timers are suspended, and a single 256 s pulse is sent on the STAT output and the FAULT/STAT bits of the status registers are updated in the I2C. A new charging cycle begins when TJ falls below TSHTDWN by approximately 10C. 28 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 10.4 Device Functional Modes The bq24257 family provides a switch-mode buck regulator with output non-power path and a charge controller to provide optimum performance over the full battery charge cycle. The control loop for the buck regulator has 6 primary feedback loops that can set the duty cycle: 1. Constant Current (CC) 2. Constant Voltage (CV) 3. Input Current (IILIM) 4. Input Voltage (VIN_DPM) 5. Die Temperature 6. Cycle by Cycle Current The feedback with the minimum duty cycle is chosen as the active loop. The bq24257 supports a precision Li-Ion or Li-Polymer charging system for single-cell applications. The bq24257 includes an integrated charge sense resistor for highly accurate charge current sensing while reducing the external BOM requirements. Figure 21 below illustrates a typical charge profile. Trickle Charge Precharge Current Regulation Phase (CC) Voltage Regulation Phase (CV) Termination VBATREG ICHG ICHG VCSIN VBAT VLOWV VBATSHRT IPRECHG ITERM IBATSHRT Charging on Charge done Figure 21. Li-ion Battery Charge Profile The bq24258 supports an advanced Lithium-Iron-Phosphate (LiFePO4) algorithm. This allows for the charger to source the charge current up to the VREG-OVCHG level before entering the float charge region. See Figure 22 below for the charge profile characteristics: Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 29 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com Device Functional Modes (continued) Trickle Charge Precharge VBATREG (3.8V) VOVRCHG (3.7V) VFLTCHG (3.5V) Current Regulation Phase (CC) Discharge Float Charge ICHG ICHG VCSIN VBAT VLOWV VBATSHRT IPRECHG IBATSHRT Figure 22. LiFePO4 Battery Charge Profile 30 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com bq24257 bq24258 SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 10.5 Register Maps Register #1 Memory location: 00, Reset state: x0xx xxxx BIT * * * * NAME Read/Write FUNCTION B7(MSB) WD_FAULT Read only Read: 0 - No fault 1 - WD timeout if WD enabled B6 WD_EN Read/Write 0 - Disable 1 - Enable (also resets WC timer) B5 STAT_1 Read only B4 STAT_0 Read only B3 FAULT_3 Read only B2 FAULT_2 Read only B1 FAULT_1 Read only B0(LSB) FAULT_0 Read only 00 - 01 - 10 - 11 - Ready Charge in progress Charge done Fault 0000 - 0001 - 0010 - 0011 - 0100 - 0101 - 0110 - 0111 - 1000 - 1001 - 1010 - Normal Input OVP Input UVLO Sleep Battery Temperature (TS) Fault Battery OVP Thermal Shutdown Timer Fault No Battery connected ISET short Input Fault & LDO Low WD_FAULT - `0' indicates no watch dog fault has occurred, where a `1' indicates a fault has previously occurred. WD_EN - Enables or disables the internal watch dog timer. A `1' enables the watch dog timer and a `0' disables it. STAT - Indicates the charge controller status FAULT - Indicates the faults that have occurred. If multiple faults occurred, they can be read by sequentially addressing this register (e.g. reading the register 2 or more times). Once all faults have been read and the device is in a non-fault state, the fault register will show "Normal". Regarding the "Input Fault & LDO Low" , the IC will indicates this fault if the LDO is low and at the same time the input is below UVLO or coming out of UVLO with LDO still low. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 31 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com Register #2 Memory location: 01, Reset state: 1010 1100 BIT * * * * * 32 NAME Read/Write FUNCTION Write: 1 - Reset all registers to default values 0 - No effect B7(MSB) Reset Write only B6 IIN_ILIMIT_2 Read/Write B5 IIN_ILIMIT_1 Read/Write B4 IIN_ILIMIT _0 Read/Write B3 EN_STAT Read/Write 0 - Disable STAT function 1 - Enable STAT function B2 EN_TERM Read/Write 0 - Disable charge termination 1 - Enable charge termination B1 CE Read/Write 0 - Charging is enabled 1 - Charging is disabled B0(LSB) HZ_MODE Read/Write 0 - Not high impedance mode 1 - High impedance mode 000 - USB2.0 host with 100mA current limit 001 - USB3.0 host with 150mA current limit 010 - USB2.0 host with 500mA current limit 011 - USB3.0 host with 900mA current limit 100 - Charger with 1500mA current limit 101 - Charger with 2000mA current limit 110 - External ILIM current limit(5) 111- No input current limit with internal clamp at 3A (PTM MODE) IIN_LIMIT - Sets the input current limit level. When in host mode this register sets the regulation level. However, when in standalone mode (e.g. no I2C writes have occurred after power up or the WD timer has expired) the external resistor setting for IILIM sets the regulation level. EN_STAT - Enables and disables the STAT pin. When set to a `1' the STAT pin is enabled and function normally. When set to a `0' the STAT pin is disabled and the open drain FET is in HiZ mode. EN_TERM - Enables and disables the termination function in the charge controller. When set to a `1' the termination function will be enabled. When set to a `0' the termination function will be disabled. When termination is disabled, there are no indications of the charger terminating (i.e. STAT pin or STAT registers). CE - The charge enable bit which enables or disables the charge function. When set to a `0', the charger operates normally. When set to a `1', the charger is disabled. HZ_MODE - Sets the charger IC into low power standby mode. When set to a `1', the switch mode controller is disabled. When set to a `0', the charger operates normally. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com bq24257 bq24258 SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 Register #3 Memory location: 02, Reset state: 1000 1111 BIT NAME Read/Write FUNCTION B7(MSB) VBATREG_5 (1) Read/Write Battery Regulation Voltage: 640mV (default 1) B6 VBATREG_4 (1) Read/Write Battery Regulation Voltage: 320mV (default 0) B5 VBATREG_3 (1) Read/Write Battery Regulation Voltage: 160mV (default 0) B4 VBATREG_2 (1) Read/Write Battery Regulation Voltage: 80mV (default 0) B3 VBATREG_1 (1) Read/Write Battery Regulation Voltage: 40mV (default 1) B2 VBATREG_0 (1) Read/Write Battery Regulation Voltage: 20mV (default 1) USB_DET_1/EN1 Read Only USB_DET_0/EN0 Read Only Return USB detection result or pin EN1/EN0 status - 00 - DCP detected / EN1=0, EN0=0 01 - CDP detected / EN1=0, EN0=1 10 - SDP detected / EN1=1, EN0=0 11 - Apple/TT or non-standard adaptor detected/EN1=1, EN0=1 (4)(5) B1 B0(LSB) (1) * * Charge voltage range is 3.5V--4.44V with the offset of 3.5V and step of 20mV (default 4.2V) VBATREG - Sets the battery regulation voltage USB_DET/EN - Provides status of the D+/D- detection results for spins that include the D+/D- pins or the state of EN1/EN2 for spins that include the EN1/EN2 pins. Register #4 Memory location: 03, Reset state: 0000 0000 BIT Read/Write FUNCTION B7(MSB) ICHG_4 (1) (2) Read/Write Charge current 800mA - (default 0) B6 ICHG_3 (1) (2) Read/Write Charge current: 400mA - (default 0) B5 ICHG_2 (1) (2) Read/Write Charge current: 200mA - (default 0) B4 ICHG_1 (1) (2) Read/Write Charge current: 100mA - (default 0) B3 ICHG_0 (1) (2) Read/Write Charge current: 50mA - (default 0) ITERM_2 (3) Read/Write Termination current sense threshold: 100mA (default 0) B1 ITERM_1 (3) Read/Write Termination current sense threshold: 50mA (default 0) B0(LSB) ITERM_0 (3) Read/Write Termination current sense threshold: 25mA (default 0) B2 (1) (2) (3) * * NAME Charge current offset is 500mA and default charge current is 500mA (maximum is 2.0A) When all bits are 1's, it is external ISET charging mode Termination threshold voltage offset is 50mA. The default termination current is 50mA if ICHG is selected from I2C. Otherwise, termination is set to 10% in external I_set mode with +/-10% accuracy. ICHG - Sets the charge current regulation ITERM - Sets the current level at which the charger will terminate Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 33 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com Register #5 Memory location: 04, Reset state: xx00 x010 BIT NAME Read/Write B7(MSB) LOOP_STATUS1 (1) Read Only B6 LOOP_STATUS0 (1) Read Only B5 LOW_CHG Read/Write 0 - Normal charge current set by 03h 1 - Low charge current setting 330mA (default 0) B4 DPDM_EN Read/Write 0 - Bit returns to 0 after D+/D- detection is performed 1 - Force D+/D- detection (default 0) B3 CE_STATUS Read Only 0 - CE low 1 - CE high B2 VINDPM_2 (2) Read/Write Input VIN-DPM voltage: 320mV (default 0) B1 (2) Read/Write Input VIN-DPM voltage: 160mV (default 1) VINDPM_0 (2) Read/Write Input VIN-DPM voltage: 80mV (default 0) B0(LSB) (1) (2) * * * * 34 VINDPM_1 FUNCTION 00 - 01 - 10 - 11 - No loop is active that slows down timer VIN_DPM regulation loop is active Input current limit loop is active Thermal regulation loop is active LOOP_STATUS bits show if there are any loop is active that slow down the safety timer. If a status occurs, these bits announce the status and do not clear until read. If more than one occurs, the first one is shown VIN-DPM voltage offset is 4.20V and default VIN_DPM threshold is 4.36V. LOOP_STATUS - Provides the status of the active regulation loop. The charge controller allows for only one loop to regulate current at a time. LOW_CHG - When set to a `1', the charge current is reduced 330mA independent of the charge current setting in register 0x03. When set to `0', the charge current is set by register 0x03. DPDM_EN - Forces a D+/D- detection routine to be executed once a `1' is written. This is independent of the input being supplied. CE_STATUS - Provides the status of the CE pin level. If the CE pin is forced high, this bit returns a `1'. If the CE pin is forced low, this bit returns a `0'. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com bq24257 bq24258 SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 Register #6 Memory location: 05, Reset state: 101x 1xxx * * * * BIT NAME Read/Write B7(MSB) 2XTMR_EN Read/Write 0 - Timer not slowed at any time 1 - Timer slowed by 2x when in thermal regulation, VIN_DPM or DPPM (default 1) FUNCTION B6 TMR_1 Read/Write B5 TMR_2 Read/Write Safety Timer Time Limit 00 - 0.75 hour fast charge 01 - 6 hour fast charge (Default 01) 10 - 9 hour fast charge 11 - Disable safety timers B4 SYSOFF Read/Write 0 - SYSOFF disabled 1 - SYSOFF enabled B2 TS_STAT2 Read only B1 TS_STAT1 Read only B0(LSB) TS_STAT0 Read only TS Fault Mode: 000 - Normal, No TS fault 100 - TS temp < TCOLD (Charging suspended for JEITA and Standard TS) 101 - TFREEZE < TS temp < TCOLD (Charging at 3.9V and 100mA and only for PSE option only) 110 - TS temp < TFREEZE (Charging suspended for PSE option only) 111 - TS open (TS disabled) 2xTMR_EN - When set to a `0', the 2x Timer function is enabled and allows for the timer to be extended if a condition occurs where the charge current is reduced (that is, VIN_DPM, thermal regulation, and so on). When set to a `1', this function is disabled and the normal timer will always be executed independent of the current reduce conditions. SYSOFF - When set to a `1' and the input is removed, the leakage from the BAT pin will be changed to less than 1A. Note that this disconnects the battery from the IC. When set to a `0', this function is disabled. TS_EN - Enables and disables the TS function. When set to a `1' the TS function is disabled otherwise it is enabled. Only applies to spins that have a TS pin. TS_STAT - Provides status of the TS pin state for spins that have a TS pin. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 35 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com Register #7 Memory location: 06, Reset state: 1110 0000 for the bq24258 and 0010 0000 for the bq24257. BIT NAME Read/Write B7(MSB) VOVP_2 Read/Write B6 VOVP_1 Read/Write FUNCTION OVP voltage: 000 - 6.0V; 001 - 6.5V; 010 - 7.0V; 011 - 8.0V 100 - 9.0V; 101 - 9.5V; 110 - 10.0V; 111 -10.5V B5 VOVP_0 Read/Write B4 CLR_VDP Read/Write 0 - Keep D+ voltage source on during DBP charging B3 FORCE_BATDET Read/Write 0 - Enter the battery detection routine only if TERM is true or EN_PTM is true B2 FORCE_PTM Read/Write 0 - PTM mode is disabled 1 - PTM mode is enabled if OTP_EN_PTM=1 B1 N/A Read/Write B0(LSB) N/A Read/Write 1 - Turn off D+ voltage source to release D+ line 1 - Enter the battery detection routine * * * * 36 VOVP - Sets the OVP level CLR_VDP - When the D+/D- detection has finished, some cases require the D+ pin to force a voltage of 0.6V. This bit allows the system to clear the voltage prior to any communication on the D+/D- pins. A `1' clears the voltage at the D+ pin if present. FORCE_BATDET - Forces battery detection and provides status of the battery presence. A logic `1' enables this function. FORCE_PTM - Puts the device in production test mode (PTM) where the input current limit is disabled. Note that a battery must not be present prior to using this function. Otherwise the function will not be allowed to execute. A logic `1' enables the PTM function. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com bq24257 bq24258 SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 11 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 11.1 Application Information The bq24257EVM-150 evaluation module (EVM) is a complete charger moudule for evaluating the bq24257. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 37 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com 11.2 Typical Application Bq24257 and bq24258 devices are highly-integrated, single cell, Li-Ion battery chargers with integrated current sense resistors targeted for space-limited, portable applications with high-capacity batteries. They are featured with a high-efficiency switch-mode charger. They have integrated power FETs able to charge at up to a 2-A charging rate, and an integrated 50-mA LDO. In I2C mode, the bq24257 device has programmable battery charge voltage (VBATREG), charge current(ICHG), input current limit(ILIM), and input over-voltage protection threshold (VOVP). CPMID 1F LO 1.0PH PMID IN VBUS DD+ GND SW CIN CBOOT 33 nF 2.2PF VDPM 3 MHz PWM BOOT PGND D- CSIN 1PF D+ Rsns LDO BAT 1 PF System Load VGPIO 22PF LDO SCL SCL SDA SDA TS TEMP PACK+ + Host GPIO1 STAT PACK- GPIO2 /CE GPIO3 /PG ILIM ISET Figure 23. bq24257 Typical Application Circuit 38 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 Typical Application (continued) 11.2.1 Design Requirements Use the following typical application design procedure to select external components values for the bq24257 device. Table 6. Design Parameters SPECIFICATION Input DC voltage, VIN Input current Charge current Output regulation voltage TEST CONDITION Recommended input voltage range MAX UNIT 4.35 MIN TYP 10.5 V 2 A 0.5 2 A Recommended input current range Fast charge current range Standalone mode or I2C default mode 4.2 V 2 Output regulation voltage LDO I C host mode: operating in voltage regulation, programmable range LDO output voltage 3.5 4.44 4.9 V V 11.2.2 Detailed Design Procedure 11.2.2.1 Components Selection The inductor selection depends on the application requirements. The bq24257 and bq24258 are designed to operate at around 1 H. The value has an effect on efficiency, and the ripple requirements, stability of the charger, package size, and DCR of the inductor. The 1H inductor provides a good tradeoff between size and efficiency and ripple. Once the inductance has been selected, the peak current is needed in order to choose the saturation current rating of the inductor. Make sure that the saturation current is always greater than or equal to the calculated IPEAK. The following equation can be used to calculate the current ripple: IL = {VBAT (VIN - VBAT)}/(VIN x s x L) (6) Then use current ripple to calculate the peak current as follows: IPEAK = Load x (1 + IL/2) (7) In this design example, the regulation voltage is set to 4.2V, the input voltage is 5V and the inductance is selected to be 1H. The maximum charge current that can be used in this application is 1A and can be set by I2C command. The peak current is needed in order to choose the saturation current rating of the inductor. Using equation 6 and 7, IL is calculated to be 0.224A and the inductor peak current is 1.112A. A 1F CSIN cap is needed and 22F BAT cap is needed on the output trace. The default settings for external fast charge current and external setting of current limit are chosen to be IFC=500mA and ILIM=1A. RISET and RILIM need to be calculated using equation 1 and 2 in the data sheet. The fast charge current resistor (RISET) can be set as follows: RISET=250/0.5A=500 The input current limit resistor (RILIM) can be set as follows: RILIM= 270/1A=270 The external settings of VIN_DPM can be designed by calculating R1 and R2 according to equation 3 in this data sheet and the typical application circuit. VIN_DPM should be chosen first along with R1. VIN_DPM is chosen to be 4.48V and R1 is set to 274K in this design example. Using equation 3, the value of R2 is calculated to be 100 k. In this design example, the application needs to be JEITA compliant. Thus, TCOLD must be 0C and THOT must be 60C. If an NTC resistor is chosen such that the beta is 4500K and the nominal resistance is 13K, the calculated R3 and R4 values are 5K and 8.8K respectively. These results are obtained from equation 4 and 5 in this data sheet. Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 39 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com 11.2.3 Application Curves ICHG = 1 A ILIM = 1.5 A ISYS = 0 A VBAT = 3.6 V ICHG = 2 A ILIM = 0.5 A ISYS = 0 A VBAT = 3.6 V VDPM = 4.36 V Figure 25. VDPM Startup, 4.2 V Figure 24. Startup ICHG = 1 A ISYS = 0 A VBAT = 3.3 V VIN = 5.2 V Figure 26. 1.0-H CCM Operation 40 Figure 27. 2-A Load Step Transient Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 bq24257: Not Recommended For New Designs www.ti.com bq24257 bq24258 SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 12 Power Supply Recommendations The devices are designed to operate from an input voltage range between 4.35V and 10.5V. This input supply must be well regulated. If the input supply is located more than a few inches from the bq24257 charger, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. 13 Layout 13.1 Layout Guidelines 1. Place the BOOT, PMID, IN, BAT, and LDO capacitors as close as possible to the IC for optimal performance. 2. Connect the inductor as close as possible to the SW pin, and the SYS/CSIN cap as close as possible to the inductor minimizing noise in the path. 3. Place a 1-F PMID capacitor as close as possible to the PMID and PGND pins, making the high frequency current loop area as small as possible. 4. The local bypass capacitor from SYS/CSIN to GND must be connected between the SYS/CSIN pin and PGND of the IC. This minimizes the current path loop area from the SW pin through the LC filter and back to the PGND pin. 5. Place all decoupling capacitors close to their respective IC pins and as close as possible to PGND (do not place components such that routing interrupts power-stage currents). All small control signals must be routed away from the high-current paths. 6. To reduce noise coupling, use a ground plane if possible, to isolate the noisy traces from spreading its noise all over the board. Put vias inside the PGND pads for the IC. 7. The high-current charge paths into IN, Micro-USB, BAT, SYS/CSIN, and from the SW pins must be sized appropriately for the maximum charge current to avoid voltage drops in these traces. 8. For high-current applications, the balls for the power paths must be connected to as much copper in the board as possible. This allows better thermal performance because the board conducts heat away from the IC. 13.2 Layout Example Figure 28. Recommended bq2425x PCB Layout for WCSP Package Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 41 bq24257 bq24258 bq24257: Not Recommended For New Designs SLUSBG0C - FEBRUARY 2013 - REVISED OCTOBER 2014 www.ti.com 13.3 Device and Documentation Support 13.3.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 7. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY bq24257 Click here Click here Click here Click here Click here bq24258 Click here Click here Click here Click here Click here 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 42 Submit Documentation Feedback Copyright (c) 2013-2014, Texas Instruments Incorporated Product Folder Links: bq24257 bq24258 PACKAGE OPTION ADDENDUM www.ti.com 10-Sep-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) BQ24257RGER NRND VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ24257 BQ24257RGET NRND VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ24257 BQ24257YFFR NRND DSBGA YFF 30 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24257 BQ24257YFFT NRND DSBGA YFF 30 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24257 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Sep-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Jun-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device BQ24257RGER Package Package Pins Type Drawing VQFN RGE 24 BQ24257RGET VQFN RGE BQ24257YFFR DSBGA YFF BQ24257YFFT DSBGA YFF SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 30 3000 180.0 8.4 2.09 2.59 0.78 4.0 8.0 Q1 30 250 180.0 8.4 2.09 2.59 0.78 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Jun-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ24257RGER VQFN RGE 24 3000 367.0 367.0 35.0 BQ24257RGET VQFN RGE 24 250 210.0 185.0 35.0 BQ24257YFFR DSBGA YFF 30 3000 182.0 182.0 20.0 BQ24257YFFT DSBGA YFF 30 250 182.0 182.0 20.0 Pack Materials-Page 2 GENERIC PACKAGE VIEW RGE 24 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204104/H PACKAGE OUTLINE VQFN - 1 mm max height RGE0024H PLASTIC QUAD FLATPACK- NO LEAD A 4.1 3.9 B 4.1 3.9 PIN 1 INDEX AREA 1 MAX C SEATING PLANE 0.05 0.00 0.08 C (0.2) TYP 2X 2.5 12 7 20X 0.5 6 13 25 2X 2.5 SYMM 1 PIN 1 ID (OPTIONAL) 18 24X 0.30 0.18 24 19 SYMM 24X 0.48 0.28 0.1 0.05 C A B C 4219016 / A 08/2017 NOTES: 1. 2. 3. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. This drawing is subject to change without notice. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT VQFN - 1 mm max height RGE0024H PLASTIC QUAD FLATPACK- NO LEAD (3.825) ( 2.7) 19 24 24X (0.58) 24X (0.24) 1 18 20X (0.5) 25 SYMM (3.825) 2X (1.1) TYP 6 13 (R0.05) 12 7 2X(1.1) SYMM LAND PATTERN EXAMPLE SCALE: 20X 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND METAL SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK SOLDER MASK DEFINED SOLDER MASK DETAILS 4219016 / A 08/2017 NOTES: (continued) 4. 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN VQFN - 1 mm max height RGE0024H PLASTIC QUAD FLATPACK- NO LEAD (3.825) 4X ( 1.188) 19 24 24X (0.58) 24X (0.24) 1 18 20X (0.5) SYMM (3.825) (0.694) TYP 6 13 (R0.05) TYP METAL TYP 25 7 SYMM 12 (0.694) TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 78% PRINTED COVERAGE BY AREA SCALE: 20X 4219016 / A 08/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.. www.ti.com PACKAGE OUTLINE YFF0030 DSBGA - 0.625 mm max height SCALE 4.500 DIE SIZE BALL GRID ARRAY B E A BUMP A1 CORNER D C 0.625 MAX SEATING PLANE BALL TYP 0.30 0.12 0.05 C 1.6 TYP SYMM F D: Max = 2.418 mm, Min =2.357 mm E D 2 TYP SYMM E: Max = 2.018 mm, Min =1.957 mm C B A 0.4 TYP 0.3 30X 0.2 0.015 C A B 1 2 3 4 5 0.4 TYP 4219433/A 03/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com EXAMPLE BOARD LAYOUT YFF0030 DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP 30X ( 0.23) 1 2 3 4 5 A (0.4) TYP B C SYMM D E F SYMM LAND PATTERN EXAMPLE SCALE:25X ( 0.23) METAL 0.05 MAX 0.05 MIN ( 0.23) SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4219433/A 03/2016 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com EXAMPLE STENCIL DESIGN YFF0030 DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP (R0.05) TYP 30X ( 0.25) 1 2 3 4 5 A (0.4) TYP METAL TYP B C SYMM D E F SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X 4219433/A 03/2016 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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