A1280XLPQ160I - Actel Corporation

May 1995

1-103

1200XL

Field Programmable Gate Arrays

Features

• Up to 8000 Gate Array Gates

(20,000 PLD equivalent gates)

• Replaces up to 200 TTL Packages

• Replaces up to eighty 20-Pin PAL

Packages

• Design Library with over 500 Macro Functions

• Single-Module Sequential Functions

• Wide-Input Combinatorial Functions

• Up to 1232 Programmable Logic Modules

• Up to 998 Flip-Flops

• Datapath Performance at 135 MHz

• 16-Bit Accumulator Performance to 50 MHz

• 10 ns Clock-Out speeds

• Two In-Circuit Diagnostic Probe Pins Support Speed

Analysis to 50 MHz

• Two High-Speed, Low-Skew Clock Networks

• I/O Drive to 10 mA

• Nonvolatile, User Programmable

• Fabricated in 0.6 micron CMOS technology

Product Family Profile

Device A1225XL A1240XL A1280XL

Capacity

Gate Array Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Packages

20-Pin PAL Equivalent Packages

2,500

6,250

4,000

10,000

100

8,000

20,000

200

Logic Modules

S-Modules

C-Modules

451

231

220

684

348

336

1,232

624

608

Flip-Flops (maximum) 382 568 998

Routing Resources

Horizontal Tracks/Channel

V ertical Tracks/Channel

PLICE Antifuse Elements

250,000

400,000

750,000

User I/Os (maximum) 83 104 140

Packages

100 PQFP

100 VQFP

84 PLCC

100 CPGA

144 PQFP

176 TQFP

84 PLCC

132 CPGA

160 PQFP

176 TQFP

84 PLCC

176 CPGA

Performance

16-Bit Prescaled Counters

16-Bit Loadable Counters

16-Bit Accumulators

135 MHz

87 MHz

47 MHz

130 MHz

83 MHz

45 MHz

110 MHz

75 MHz

42 MHz

Notes:

1. See product plan on page 1-105 for package availability.

2. Performance is based on ‘–1’ speed devices at commercial worst-case operating conditions using PREP Benchmarks (mean

frequency results), Suite #1, Version 1.2, dated 3-28-93, any analysis is not endorsed by PREP.

1200XL DB DS Page 103 Tuesday, October 3, 1995 8:36 AM

1-104

Description

The 1200XL family, Actel’s fourth family of field

programmable gate arrays (FPGAs), is targeted as a

VALUE family, offering very low costs and mid-to-high

range performance. The 1200XL family is based on

Actel’s patented channeled array architecture and consists

of two-module types: combinatorial (C-modules) and

combinatorial- sequential (S-modules). The 1200XL

family is pin and functionally compatible with the ACT 2

family, and is design compatible with the ACT 1 and

ACT 3 families. The 1200XL family provides significant

performance enhancements in comparison to the ACT 2

family while offering a lower cost solution. The devices

are implemented in 0.65 micron two-level metal CMOS

technology and employ Actel’s patented PLICE antifuse

technology.

The 1200XL family is supported by Actel’s Designer and

Designer Advantage Systems, allowing logic design

implementation with minimum effort. The systems offer

Microsoft

Windows

™

and X Window

™

graphical user

interfaces and integrate with the resident CAE system to

provide a complete gate array design environment:

schematic capture, simulation, fully automatic placement

and routing, timing verification and device programming.

The systems also include the ACTmap™ optimization and

synthesis tool, and the ACTgen™ Macro Builder, a

powerful macro function generator for counters, adders,

and other structured blocks. The systems are available for

386/486/Pentium PCs and for HP

™

, and Sun

™

workstations running Viewlogic

, Mentor Graphics

, and

OrCAD™ tools.

Performance versus ACT 2

The 1200XL family has been enhanced for performance in

comparison to the ACT 2 family. The I/O modules have

been redesigned to improve pin-to-pin and clock-out

delays. The clock distribution networks have been

enhanced to improve both propagation delays and skews

for highly loaded designs. Finally, the family is

implemented in 0.65 micron CMOS technology, resulting

in much faster performance.

Ordering Information

A1225A A1225A-2 A1225XL A1225XL-1

Clock-Out (pad-pad, 64 loads) 24.0 ns 18.0 ns 12.0 ns 10.0 ns

Pin-Pin (1 level, FO = 1) 28.3 ns 21.2 ns 15.5 ns 13.2 ns

PREP Datapath (#1) 75 MHz 105 MHz 115 MHz 135 MHz

PREP Accumulator (#6) 28 MHz 37 MHz 40 MHz 47 MHz

PREP State Machine (#3) 32 MHz 43 MHz 51 MHz 60 MHz

Application (Temperature Range)

C = Commercial (0 to +70°C)

I = Industrial (–40 to +85°C)

P ackage Type

PL = Plastic J-Leaded Chip Carrier

PQ = Plastic Quad Flatpack

TQ = Thin (1.4 mm) Quad Flatpack

VQ = Very Thin (1.0 mm) Quad Flatpack

Speed Grade

Blank = Standard Speed

–1 = Approximately 15% faster than Standard

Part Number

A1225 = 2500 Gates

A1240 = 4000 Gates

A1280 = 8000 Gates

Package Lead Count

A1280 – TQ 176 C

1XL

Sub Family

1200XL DB DS Page 104 Tuesday, October 3, 1995 8:36 AM

1200XL Field Programmable Gate Arrays

1-105

Product Plan

Applications: C = Commercial Availability:

✔

= Available * Speed Grade: –1 = Approx. 15% faster than Standard

I = Industrial P = Planned

— = Not Planned

Note:

1. Please consult Actel representatives for current availability.

Device Resources

Speed Grade* Application

Std –1 C I

A1225XL Device

84-pin Plastic Leaded Chip Carrier (PL)

100-pin Plastic Quad Flatpack (PQ)

100-pin Very Thin (1.0 mm) Quad Flatpack

A1240XL Device

84-pin Plastic Leaded Chip Carrier (PL)

144-pin Plastic Quad Flatpack (PQ)

176-pin Thin (1.4 mm) Quad Flatpack

A1280XL Device

84-pin Plastic Leaded Chip Carrier (PL)

160-pin Plastic Quad Flatpack (PQ)

176-pin Thin (1.4 mm) Quad Flatpack

✔

User I/Os

Device Series Logic Modules Gates PQFP PLCC TQFP VQFP

160-pin 144-pin 100-pin 84-pin 176-pin 100-pin

A1225XL 451 2500 — — 83 72 — 83

A1240XL 684 4000 — 104 — 72 104 —

A1280XL 1232 8000 125 — — 72 140 —

1200XL DB DS Page 105 Tuesday, October 3, 1995 8:36 AM

1-106

Pin Description

CLKA Clock A (Input)

TTL Clock input for clock distribution networks. The

Clock input is buffered prior to clocking the logic

modules. This pin can also be used as an I/O.

CLKB Clock B (Input)

TTL Clock input for clock distribution networks. The

Clock input is buffered prior to clocking the logic

modules. This pin can also be used as an I/O.

DCLK Diagnostic Clock (Input)

TTL Clock input for diagnostic probe and device

programming. DCLK is active when the MODE pin is

HIGH. This pin functions as an I/O when the MODE pin

is LOW.

GND Ground

LOW supply voltage.

I/O Input/Output (Input, Output)

The I/O pin functions as an input, output, three-state, or

bidirectional buffer. Input and output levels are compatible

with standard TTL and CMOS specifications. Unused I/O

pins are automatically driven LOW by the ALS software.

MODE Mode (Input)

The MODE pin controls the use of multifunction pins

(DCLK, PRA, PRB, SDI). When the MODE pin is HIGH,

the special functions are active. When the MODE pin is

LOW, the pins function as I/Os.

NC No Connection

This pin is not connected to circuitry within the device.

PRA Probe A (Output)

The Probe A pin is used to output data from any

user-defined design node within the device. This

independent diagnostic pin is used in conjunction with the

Probe B pin to allow real-time diagnostic output of any

signal path within the device. The Probe A pin can be used

as a user-defined I/O when debugging has been

completed. The pin’s probe capabilities can be

permanently disabled to protect programmed design

confidentiality. PRA is active when the MODE pin is

HIGH. This pin functions as an I/O when the MODE pin

is LOW.

PRB Probe B (Output)

The Probe B pin is used to output data from any

user-defined design node within the device. This

independent diagnostic pin is used in conjunction with the

Probe A pin to allow real-time diagnostic output of any

signal path within the device. The Probe B pin can be used

as a user-defined I/O when debugging has been

completed. The pin’s probe capabilities can be

permanently disabled to protect programmed design

confidentiality. PRB is active when the MODE pin is

HIGH. This pin functions as an I/O when the MODE pin

is LOW.

SDI Serial Data Input (Input)

Serial data input for diagnostic probe and device

programming. SDI is active when the MODE pin is

HIGH. This pin functions as an I/O when the MODE pin

is LOW.

5 V Supply Voltage

HIGH supply voltage.

Programming Voltage

Supply voltage used for device programming. This pin

must be connected to GND during normal operation.

Programming Voltage

Supply voltage used for device programming. This pin

must be connected to V

during normal operation.

Programming Voltage

Supply voltage used for device programming. This pin

must be connected to V

during normal operation.

1200XL Architecture

This section of the data sheet is meant to familiarize the

user with the architecture of 1200XL family devices. A

generic description of the family will be presented first,

followed by a detailed description of the logic blocks, the

routing structure, the antifuses, and the special function

circuits. Diagrams for the ACT 2 devices are provided at

the end of the data sheet. The additional circuitry required

to program and test the devices will not be covered.

1200XL DB DS Page 106 Tuesday, October 3, 1995 8:36 AM

1-107

1200XL Field Programmable Gate Arrays

Array Topology

The 1200XL family architecture is composed of five key

building blocks: Logic modules, I/O modules, Routing

Tracks, Global Clock Networks, and Probe Circuits. The

basic structure is similar for all devices in the family,

differing only in the number of rows, columns, or I/Os (see

Table 1).

The logic and I/O modules are arranged in a

two-dimensional array (Figure 1). There are three types of

modules: Logic, I/O, and Bin. Logic and I/O modules are

available as user resources. Bin modules are used during

testing and are not available to users.

Logic Modules

Logic modules are classified into two types: combinatorial

(C-modules) and sequential (S-modules) (see Figures 2

and 3). The C-module is an enhanced version of the ACT

1 family logic module optimized to implement high fanin

combinatorial macros, such as 5-input AND, and 5-input

OR. The full ACT 2 combinatorial logic module is

available for use as the CM8 hard macro. The S-module is

designed to implement high-speed flip-flop functions

within a single module. S-modules also include

combinatorial logic, which allows an additional level of

logic to be implemented without additional propagation

delay. C-modules and S-modules are arranged in pairs

called module-pairs. Module-pairs are arranged in

alternating pairs (shown in Figure 1) and make up the bulk

of the array. This arrangement allows the placement

software to support two-module macros of four types

Table 1 •

Array Sizes

Device Rows Columns Logic I/O

A1225XL 13 46 451 83

A1240XL 14 62 684 104

A1280XL 18 82 1232 140

Figure 1 •

A1280XL Simplified Floor Plan

•••

I I S S C C S S C C S S C C S S C C S S C C S S C C S S C C S S S S C C S S C C S S C I I

•••

010 3020 70 80

I I S S C C S S C C S S C C S S C C S S C C S S C C S S C C S S •••

010 3020 C C S S C C S S C C S I I

70 80

I I S S C C S S C C S S C C S S C C S S C C S S C C S S C C S S •••

010 3020

I I S S C C S S C C S S C C S S C C S S C C S S C C S S C C S S •••

010 3020

II S S C C S S C C S S C C S S C C S S C C S S C C S S C C S S •••

010 3020

I I S S C C S S C C S S C C S S C C S S C C S S C C S S C C S S •••

010 3020

I I S S C C S S C C S S C C S S C C S S C C S S C C S S C C S S •••

010 3020

I I S S C C S S C C S S C C S S C C S S C C S S C C S S C C S S •••

010 3020

I I S S C C S S C C S S C C S S C C S S C C S S C C S S C C S S •••

010 3020

•••

010 3020 70 80

S = Sequential Module

C = Combinatorial Module

I = I/O Module

B = Binning Module (Actel use only)

I IIIIIIIIIIIIIII IIIIII

•••

010 3020 70 80

0I IIIIIIIIIIIIIII IIIIII

CSSCCSSCCSII

70 80

C C S S C C S S C C S I I

70 80

CC S S C C S S C C S I I

70 80

C C S S C C S S C C S I I

70 80

C C S S C C S S C C S I I

70 80

C C S S C C S S C C S I I

70 80

C C S S C C S S C C S I I

70 80

1200XL DB DS Page 107 Tuesday, October 3, 1995 8:36 AM

1-108

(CC, CS, SC, and SS). I/O modules are arranged around

the periphery of the array.

The combinatorial module (shown in Figure 2)

implements the following function:

Y = !S1 * !S0 * D00 + !S1 * S0 * D01 * S1 * !S0 * D10 +

S1 * S0 * D11

where:

S0 = A0 * B0

S1 = A1 + B1

The sequential module implements this same function Y

(except that S0 = A0 only, since the B0 input is used for

reset), followed by a sequential block. The sequential

block can implement either a D-type flip-flop or a

transparent latch. It can also be fully transparent so that the

S-modules can be used to implement purely combinatorial

functions. The function of the sequential module is

determined by the macro selection from the design library

of hard macros. Allowable S-module implementations are shown in Figure 3.

Figure 2 •

C-module Implementation

D11

D01

D00

D10 Y OUT

S1 S0

Up to 8-input function

Figure 3 •

S-module Implementations

D11

D01

D00

D10 YOUT

S1 S0

Up to 7-input function plus D-type ﬂip-ﬂop with clear

CLK

CLR

D11

D01

D00

D10 YOUT

S1 S0

Up to 7-input function plus latch

GATE

YOUT

Up to 4-input function plus latch with clear

GATE

CLR

D11

D01

D00

D10 Y OUT

S1 S0

Up to 8-input function (same as C-module)

1200XL DB DS Page 108 Tuesday, October 3, 1995 8:36 AM

1-109

1200XL Field Programmable Gate Arrays

I/Os

The I/O architecture consists of pad drivers located near

the bonding pads and I/O modules located in the array.

Top/bottom I/O modules are located in the top and bottom

rows respectively. Side I/O modules occupy the leftmost

two columns and the rightmost two columns of the array.

The function of all I/O modules is identical, but the

top/bottom I/O modules have a different routing interface

to the array than the side I/O modules. I/Os implement a

variety of user functions determined by library macro

selection.

Special Purpose I/Os

Certain I/O pads are temporarily used for programming

and testing the device. During normal user operation, these

special I/O pads are identical to other I/O pads. The

following special I/O pads and their functions are shown

in Table 2.

Two other pads, CLKA and CLKB, also differ from

normal I/Os in that they can be used to drive the global

clock networks. Power, Ground, and Programming pads

are not considered I/O functions. Their function is

summarized as follows:

I/O Pads

I/O pads are located on the periphery of the die and consist

of the bonding pad, the high-drive CMOS drivers, and the

TTL level-shifter inputs. Each I/O pad is associated with a

specific I/O module. Connections from the I/O pad to the

I/O module are made using the signals DATAOUT,

DATAIN, and EN (shown in Figure 4).

I/O Modules

There are two types of I/O modules: side and top/bottom.

The I/O module schematic is shown in Figure 5. In the

side I/O modules, there are two inputs supplying the data

to be output from the chip UO1 and UO2. (UO stands for

user output.) Two are used so that the router can choose to

take the signal from either the routing channel above or the

routing channel below the I/O module. The top/bottom I/O

modules interact with only one channel and therefore have

Table 2 •

Special I/O Pads

SDI Serial Data In

DCLK Serial Data Clock In

PRA Probe A Output

PRB Probe B Output

Power

GND Circuit Ground

, V

KS,

Programming Pads

MODE Program/Debug Control

only one UO input.

The EN input enables the tristate output buffer. The global

signals INEN and OUTEN (Figures 4 and 5) are used to

disable the inputs and outputs during certain test modes.

Latches are provided in the input and output path. When

GOUT is high, the latch is transparent. The latch can be

used as the second stage of a rising-edge flip-flop. GIN is

the reverse of GOUT. When GIN is high, the input data is

latched; when it is low, the input latch becomes

transparent.

Figure 4 •

I/O Pad Signals

Figure 5 •

I/O Module

SELECT

SDATA

DATAIN

DATAOUT

PAD

SEL

D0 Y

OUTEN

(global)

DATAOUT

DATAIN

INEN

(global)

GIN

SEL

D1 Y

GOUT

U01

U02

SEL

1200XL DB DS Page 109 Tuesday, October 3, 1995 8:36 AM

1-110

The output of the module, Y, is used for data being input

to the chip. Side I/O modules have a dedicated output

segment for Y extending into the routing channels above

and below (similar to logic modules). Side I/O modules

may also connect to the array through nondedicated Long

Vertical Tracks (LVTs). Top/Bottom I/O modules have no

dedicated output segment. Signals coming into the chip

from the top or bottom must be routed using F-fuses and

LVTs (F-fuses and LVTs are explained in detail in the

routing section). I/O signals connected to I/O modules on

either the top or bottom of the array may incur a delay

penalty over signals connected to I/O modules on the

sides.

Hard Macros

Designing within the Actel design environment is

accomplished using a building block approach. Over 350

logic function macros are provided in the 1200XL design

library. Hard macro logic functions range from simple SSI

gates such as AND, NOR, and Exclusive OR to more

complex functions such as flip-flops with 4:1 Multiplexed

Data inputs. Hard macros are implemented in the ACT 2

architecture by using one or more C-modules or

S-modules. Over 200 of the macros are implemented in a

single module, while several two-module macros are also

available. Two-module hard macros always utilize a

module-pair, either SS, CC, CS, or SC. Because one- and

two-module macros have small propagation delay

variances, their performances can be predicted very

accurately. Hard macro propagation delays are specified in

the data sheet. Soft macros comprise multiple hard macros

connected together to form complex functions. These

functions range from MSI functions to 16-bit counters and

accumulators. A large number of TTL equivalent hard and

soft macros are also provided. Soft macro delays are not

specified in the data sheet.

Routing Structure

The 1200XL architecture uses Vertical and Horizontal

routing tracks to interconnect the various logic and I/O

modules. These routing tracks are metal interconnects that

may either be of continuous length or broken into pieces

called segments. Segments can be joined together at the

ends using antifuses to increase their lengths up to the full

length of the track.

Horizontal Routing

Horizontal channels are located between the rows of

modules and are composed of several routing tracks. The

horizontal routing tracks within the channel are divided

into one or more segments. The minimum horizontal

segment length is the width of a module-pair, and the

maximum horizontal segment length is the full length of

the channel. Any segment that spans more than one-third

the row length is considered a long horizontal segment. A

typical channel is shown in Figure 6. Nondedicated

horizontal routing tracks are used to route signal nets.

Dedicated routing tracks are used for the global clock

networks and for power and ground tie-off tracks.

Vertical Routing

Other tracks run vertically through the module. Vertical

tracks are of three types: input, output, and long. Vertical

tracks are also divided into one or more segments. Each

segment in an input track is dedicated to the input of a

particular module. Each segment in an output track is

dedicated to the output of a particular module. Long

segments are uncommitted and can be assigned during

routing. Each output segment spans four channels (two

above and two below), except near the top and bottom of

the array where edge effects occur. LVTs contain either

one or two segments. An example of vertical routing

tracks and segments is shown in Figure 7.

Antifuse Structures

An antifuse is a “normally open” structure as opposed to

the normally closed fuse structure used in PROMs or

PALs. The use of antifuses to implement a Programmable

Logic Device results in highly testable structures as well

as efficient programming algorithms. The structure is

highly testable because there are no preexisting

connections; therefore, temporary connections can be

made using pass transistors. These temporary connections

can isolate individual antifuses to be programmed as well

as isolate individual circuit structures to be tested. This can

be done both before and after programming. For example,

all metal tracks can be tested for continuity and shorts

between adjacent tracks, and the functionality of all logic

modules can be verified.

1200XL DB DS Page 110 Tuesday, October 3, 1995 8:36 AM

1200XL Field Programmable Gate Arrays

1-111

Figure 6 •

Horizontal Routing Tracks and Segments

Figure 7 •

Vertical Routing Tracks and Segments

MODULE ROW

CLK0

NVCC

SIGNAL

(LHT)

SIGNAL

NVSS

CLK1

TRACK

SEGMENT |

MODULE ROW

VERTICLE INPUT

SEGMENT

S-MODULE C-MODULE

MODULE ROW

CHANNEL

LVTS

S-MODULE C-MODULE

1200XL DB DS Page 111 Tuesday, October 3, 1995 8:36 AM

1-112

Antifuse Connections

Four types of antifuse connections are used in the routing

structure of the 1200XL array. (The physical structure of

the antifuse is identical in each case; only the usage

differs.) The four types are:

Examples of all four antifuse connections are shown in

Figures 6 and 7.

XF Cross-connected antifuse Most intersections of horizontal and vertical tracks have an XF that

connects the perpendicular tracks.

HF Horizontally connected antifuses Adjacent segments in the same horizontal tracks are connected

end-to-end by an HF.

VF Vertically connected antifuse Some long vertical tracks are divided into two segments. Adjacent long

segments are connected end-to-end by a VF.

FF “Fast-Fuse” antifuse The FF connects a module output directly to a long vertical track.

Antifuse Programming

The 1200XL family uses the PLICE antifuse developed by

Actel. The PLICE element is programmed by placing a

high voltage (~17 V) across the element and supplying

current (~5 mA) for a short duration (<1 ms). In the

1200XL architecture, most antifuses are programmed to

~500 ohms resistance, except for the F-fuses which are

programmed to ~250 ohms. The programming circuits are

transparent to the user.

Clock Networks

Two low-skew, high fanout clock distribution networks

are provided in the 1200XL architecture (Figure 8). These

networks are referred to as CLK0 and CLK1. Each

network has a clock module (CLKMOD) that selects the

source of the clock signal and may be driven as follows:

1. externally from the CLKA pad

2. externally from the CLKB pad

3. internally from the CLKIN A input

4. internally from the CLKINB input

The clock modules are located in the top row of I/O

modules. Clock drivers and a dedicated horizontal clock

track are located in each horizontal routing channel.

The user controls the clock module by selecting one of two

clock macros from the macro library. The macro

CLKBUF is used to connect one of the two external clock

pins to a clock network, and the macro CLKINT is used to

connect an internally generated clock signal to a clock

network. Since both clock networks are identical, the user

does not care whether CLK0 or CLK1 is being used.

The clock input pads may also be used as normal I/Os,

bypassing the clock networks.

Module Interface

Connections to logic and I/O modules are made through

vertical segments that connect to the module inputs and

outputs. These vertical segments lie on vertical tracks that

span the entire height of the array.

Module Input Connections

The tracks dedicated to Module inputs are segmented by

pass transistors in each module row. During normal user

operation, the pass transistors are inactive (off), which

isolates the inputs of a module from the inputs of the

module directly above or below it. During certain test

modes, the pass transistors are active (on) to verify the

continuity of the metal tracks. Vertical input segments

span only one channel. Inputs to the array modules come

either from the channel above or the channel below. The

logic modules are arranged so that half of the inputs are

connected to the channel above and half of the inputs to

segments in the channel below (Figure 9).

Figure 8 •

Clock Networks

CLKB

CLKA

FROM

PADS

CLOCK

DRIVERS

CLKMOD

CLKINB

CLKINA

S1 INTERNAL

SIGNAL

CLKO(17)

CLKO(16)

CLKO(15)

CLKO(2)

CLKO(1)

CLOCK TRACKS

1200XL DB DS Page 112 Tuesday, October 3, 1995 8:36 AM

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1200XL Field Programmable Gate Arrays

Module Output Connections

Module outputs have dedicated output segments. Output

segments extend vertically two channels above and two

channels below, except at the top or bottom of the array.

Output segments twist, as shown in Figure 9, so that only

four vertical tracks are required.

LVT Connections

Outputs may also connect to nondedicated segments

(LVTs). Each module-pair in the array shares three LVTs

that span the length of column as shown in Figure 9. Any

module in the column pair can connect to one of the LVTs

in the column using an FF connection. The FF connection

uses antifuses connected directly to the driver stage of the

module output, bypassing the isolation transistor. FF

antifuses are programmed at a higher current level than

HF, VF, or XF antifuses to produce a lower resistance

value.

Antifuse Connections

In general, every intersection of a vertical segment and a

horizontal segment contains an unprogrammed antifuse

(XF-type). One exception is in the case of the clock

networks.

Clock Connections

To minimize loading on the clock networks, only a subset

of inputs has fuses on the clock tracks. Only a few of the

C-module and S-module inputs can be connected to the

clock networks. To further reduce loading on the clock

network, only a subset of the horizontal routing tracks can

connect to the clock inputs of the S-module. Both of these

are illustrated in Figure 10.

Programming and Test Circuits

The array of logic and I/O modules is surrounded by test

and programming circuits controlled by the external pins:

MODE, SDI, and DCLK. When MODE is low (GND), the

device is in normal or user mode. When MODE is high

), the device is placed into one of several

programming or test states. The SDI pin (when MODE is

high) is used to input serial data to the Mode Register and

various address registers surrounding the array. Data is

clocked into these registers using the DCLK pin. The

registers are connected as a long series of shift registers as

shown in Figure 11. The Mode register determines the test

or programming state of the device. Many of the test

modes are used during wafer sort and final test at the

factory. Other test modes are used during programming

with the Activator

2, and some of the modes are

available only after programming. The Actionprobe

function is one such function available to users.

Figure 9 •

Logic Module Routing Interface

Y+1

A1 D10 D11

B1 B0 D01 D00

LVTs

Y+2 Y+1

Y-1

Y-2

C-MODULES

S-MODULES

D10 B0 A0 D11 A1 B1 D01

A0 Y

Y+2

Y-1

Y-2

1200XL DB DS Page 113 Tuesday, October 3, 1995 8:36 AM

1-114

Figure 10 •

Fuse Deletion on Clock Networks

Figure 11 •

1200XL Shift Register

MODULE

C1 C2

CLK0

CLK1 Clock

Tracks

Normal

Routing

Tracks

Antifuses

Deleted

SDI

DCLK

MODE

MODE REGISTER

Y1<0> Y1 REGISTER Y1<c>

Y2<0> Y2 REGISTER Y2<c>

MODULE ARRAY

OTHER REGISTERS

X1<0> X1 REGISTER X1<r>

X2<0> X2 REGISTER X2<r>

1200XL DB DS Page 114 Tuesday, October 3, 1995 8:36 AM

1-115

1200XL Field Programmable Gate Arrays

Actionprobe

If a device has been successfully programmed and the

security fuse has not been programmed, any internal logic

or I/O module output can be observed using the

Actionprobe circuitry and the PRA and/or PRB pins. The

Actionprobe diagnostic system provides the software and

hardware required to perform real-time debugging. The

software automatically performs the following functions.

A pattern of

ones

and

zeros

is shifted into the device from

the SDI pin at each positive edge transition of DCLK. The

complete sequence contains 10 bits of counter, 21 bits of

Mode Register, n bits of zeros (filler of unused fields,

where n depends on the particular device type), R bits of

X2, C bits of Y2, R bits of X1, C bits of Y1, and a stop bit

(“0” or “1”). After the stop bit has been shifted in, DCLK

is left high. X1 and Y1 represent the (X,Y) location in the

array for the Actionprobe output, PRA.

X2 and Y2 represent the (X,Y) location in the array for the

Actionprobe output, PRB. R and C are the row and

column size as defined in Table 1. The filler bits, counter

pattern, and Mode Register pattern are shown in Table 3.

Addressing for rows and columns is active high; that is,

unselected rows and columns are “zeros” and the selected

row and column is “high.” The timing sequence is shown

in Figure 12. The recommended frequency is 10 MHz

with 10 ns setup and hold times allowing for SDI and

DCLK transitions. The selected module output will be

present at the PRA or PRB output approximately 20 ns

after the stop-bit transition.

For example: Selecting PRA for A1280 results in the following bit stream.

0011011111_000000110001111100000_

(433 zeros)_X2<0>…X2<17>_Y2<81>…Y2<0>_X1<0>…X1<0>…X1<17>_Y1<0>…Y1<81>_0,

where “_” is used for clarity only

Table 3 •

Bit Stream Definitions for Actionprobe Diagnostics

Device Probe_Mode Filler (n) Counter_Pattern Mode_Register_Pattern # of clocks

A1225XL Probe A only 308 1101011010 000000110001111100000 458

A1225XL Probe B only 308 1101011010 000000101001111100000 458

A1225XL Probe A and B 308 1101011010 000000111001111100000 458

A1240XL Probe A only 361 1111000001 000000110001111100000 545

A1240XL Probe B only 361 1111000001 000000101001111100000 545

A1240XL Probe A and B 361 1111000001 000000111001111100000 545

A1280XL Probe A only 443 0011011111 000000110001111100000 675

A1280XL Probe B only 443 0011011111 000000101001111100000 675

A1280XL Probe A and B 443 0011011111 000000111001111100000 675

Figure 12 •

Timing Waveforms

FILLER ZEROS

STOP

BIT NEXT

LOAD

MODE

DCLK

SDI

LOAD COUNTER LOAD MODE REG X, Y ADDRESS PROBING

1200XL DB DS Page 115 Tuesday, October 3, 1995 8:36 AM

1-116

Absolute Maximum Ratings

Free air temperature range

Notes:

1. Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

Exposure to absolute maximum rated conditions for extended

periods may affect device reliability. Device should not be

operated outside the Recommended Operating Conditions.

2. V

= V

, except during device programming.

3. V

= V

, except during device programming.

4. V

= GND, except during device programming.

5. Device inputs are normally high impedance and draw

extremely low current. However, when input voltage is greater

than VCC + 0.5 V or less than GND – 0.5 V, the internal

protection diode will be forward biased and can draw

excessive current.

Symbol Parameter Limits Units

VCC DC Supply Voltage2,3,4 –0.5 to +7.0 V

VIInput V oltage –0.5 to VCC +0.5 V

VOOutput Voltage –0.5 to VCC +0.5 V

IIO I/O Source/Sink

Current5±20 mA

TSTG Storage Temperature –65 to +150 °C

Recommended Operating Conditions

Note:

1. Ambient temperature (TA) is used for commercial and

industrial; case temperature (TC) is used for military.

Parameter Commercial Industrial Military Units

Temperature

Range10 to

+70 –40 to

+85 –55 to

+125 °C

Power Supply

Tolerance ±5±10 ±10 %VCC

Electrical Specifications

Notes:

1. Only one output tested at a time. VCC = min.

2. Not tested, for information only.

3. Includes worst-case 176 CPGA package capacitance. VOUT = 0 V, f = 1 MHz.

4. All outputs unloaded. All inputs = VCC or GND, typical ICC = 1 mA. ICC limit includes IPP and ISV during normal operation.

5. VOUT , VIN = VCC or GND.

Symbol Parameter Commercial Industrial Military Units

Min. Max. Min. Max. Min. Max.

VOH1(IOH = –10 mA) 2 2.4 V

(IOH = –6 mA) 3.84 V

(IOH = –4 mA) 3.7 3.7 V

VOL1(IOL = 10 mA) 2 0.5 V

(IOL = 6 mA) 0.33 0.40 0.40 V

VIL –0.3 0.8 –0.3 0.8 –0.3 0.8 V

VIH 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V

Input Transition Time tR, tF2500 500 500 ns

CIO I/O Capacitance2, 3 10 10 10 pF

Standby Current, ICC4 (typical = 1 mA) 2 10 20 mA

Leakage Current5–10 10 –10 10 –10 10 µA

1200XL DB DS Page 116 Tuesday, October 3, 1995 8:36 AM

1-117

1200XL Field Programmable Gate Arrays

Package Thermal Characteristics

The device junction to case thermal characteristic is θjc,

and the junction to ambient air characteristic is θja. The

thermal characteristics for θja are shown with two

different air flow rates.

Maximum junction temperature is 150°C.

A sample calculation of the absolute maximum power

dissipation allowed for a PQFP 160-pin package at

commercial temperature is as follows:

Notes:

1. Maximum Power Dissipation for PQFP packages are 1.6 Watts (100-pin), 2.2 Watts (144-pin), and 2.4 Watts (160-pin).

2. Maximum Power Dissipation for PLCC packages is 2.2 Watts.

3. Maximum Power Dissipation for VQFP packages is 1.9 Watts.

4. Maximum Power Dissipation for TQFP packages is 2.5 Watts.

Package T ype Pin Count θja

Still Air θja

300 ft/min Units

Ceramic Pin Grid Array 100

132

176

°C/W

Plastic Quad Flatpack1100

144

160

°C/W

Plastic Leaded Chip Carrier284 37 28 °C/W

Very Thin Quad Flatpack3100 43 35 °C/W

Thin Quad Flatpack4176 32 25 °C/W

Max. junction temp.

(

° C) – Max. commercial temp.

ja ( °

C/W)

----------------------------------------------------------------------------------------------------------------------------- 150

C – 70

C/W

--------------------------------- 2 .6 W==

General Power Equation

P = [I

standby + I

active] * V

+ I

* V

* N

+ I

* (V

– V

) * M

Where:

standby is the current flowing when no inputs or

outputs are changing.

active is the current flowing due to CMOS

switching.

, I

are TTL sink/source currents.

, V

are TTL level output voltages.

N equals the number of outputs driving TTL loads to

M equals the number of outputs driving TTL loads to

An accurate determination of N and M is problematic

because their values depend on the family type, design

details, and on the system I/O. The power can be divided

into two components: static and active.

Static Power Component

Actel FPGAs have small static power components that

result in lower power dissipation than PALs or PLDs. By

integrating multiple PALs/PLDs into one FPGA, an even

greater reduction in board-level power dissipation can

be achieved.

The power due to standby current is typically a small

component of the overall power. Standby power is

calculated below for commercial, worst case conditions.

Power

2 mA 5.25 V 10.5 mW

The static power dissipation by TTL loads depends on the

number of outputs driving high or low and the DC load

current. Again, this number is typically small. For

instance, a 32-bit bus sinking 4 mA at 0.33 V will generate

42 mW with all outputs driving low and 140 mW with all

outputs driving high. The actual dissipation will average

somewhere between as I/Os switch states with time.

Active Power Component

Power dissipation in CMOS devices is usually dominated

by the active (dynamic) power dissipation. This

component is frequency dependent, a function of the logic

and the external I/O. Active power dissipation results from

charging internal chip capacitances of the interconnect,

unprogrammed antifuses, module inputs, and module

outputs, plus external capacitance due to PC board traces

and load device inputs. An additional component of the

active power dissipation is the totem-pole current in the

CMOS transistor pairs. The net effect can be associated

with an equivalent capacitance that can be combined with

frequency and voltage to represent active power

dissipation.

1200XL DB DS Page 117 Tuesday, October 3, 1995 8:36 AM

1-118

Equivalent Capacitance

The power dissipated by a CMOS circuit can be expressed

by Equation 1.

Power (

W) = C

* V

CC2

* F (1)

Where:

is the equivalent capacitance expressed in picofarads

(pF).

is power supply in volts (V).

F is the switching frequency in megahertz (MHz).

Equivalent capacitance is calculated by measuring

ICCactive at a specified frequency and voltage for each

circuit component of interest. Measurements have been

made over a range of frequencies at a fixed value of VCC.

Equivalent capacitance is frequency independent so that

the results may be used over a wide range of operating

conditions. Equivalent capacitance values are shown

below.

Values for Actel FPGAs

Modules (C

EQM

) 5.2

Input Buffers (C

EQI

) 11.6

Output Buffers (C

EQO

) 23.8

Routed Array Clock Buffer Loads (C

EQCR

) 3.5

To calculate the active power dissipated from the complete

design, the switching frequency of each part of the logic

must be known. Equation 2 shows a piece-wise linear

summation over all components.

Power = V

CC2

* [(m x

EQM

* f

)

Modules

(n *

EQI

* f

)

Inputs

+ (p * (

EQO

+ C

) * f

)

outputs

0.5 * (q

1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 +

0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 (2)

Where:

m = Number of logic modules switching at

frequency fm

n = Number of input buffers switching at frequency

p = Number of output buffers switching at

frequency fp

q1= Number of clock loads on the first routed array

clock

q2= Number of clock loads on the second routed

array clock

r1= Fixed capacitance due to first routed array clock

r2= Fixed capacitance due to second routed array

clock

CEQM = Equivalent capacitance of logic modules in pF

CEQI = Equivalent capacitance of input buffers in pF

CEQO = Equivalent capacitance of output buffers in pF

CEQCR= Equivalent capacitance of routed array clock in

CL= Output load capacitance in pF

fm= Average logic module switching rate in MHz

fn= Average input buffer switching rate in MHz

fp= Average output buffer switching rate in MHz

fq1 = Average first routed array clock rate in MHz

fq2 = Average second routed array clock rate in MHz

Fixed Capacitance Values for Actel FPGAs

(pF)

Determining Average Switching Frequency

To determine the switching frequency for a design, you

must have a detailed understanding of the data input

values to the circuit. The following guidelines are meant to

represent worst-case scenarios so that they can be

generally used to predict the upper limits of power

dissipation. These guidelines are as follows:

Device Type r1

routed_Clk1 r2

routed_Clk2

A1225XL 106 106

A1240XL 134 134

A1280XL 168 168

Logic Modules (m) = 80% of

combinatorial

modules

Inputs switching (n) = # of inputs/4

Outputs switching (p) = # outputs/4

First routed array clock loads (q1) = 40% of sequential

modules

Second routed array clock loads

(q2)= 40% of sequential

modules

Load capacitance (CL) = 35 pF

Average logic module switching

rate (fm)= F/10

Average input switching rate (fn) = F/5

Average output switching rate (fp) = F/10

Average first routed array clock

rate (fq1)=F

Average second routed array

clock rate (fq2)= F/2

1200XL DB DS Page 118 Tuesday, October 3, 1995 8:36 AM

1200XL Field Programmable Gate Arrays

1-119

1200XL Timing Model*

*Values shown for A1225XL-1 at worst-case commercial conditions. † Input Module Predicted Routing Delay

Output DelaysInternal DelaysInput Delays

tINH = 0.0 ns

tINSU = 0.4 ns

I/O Module

tINGL = 3.0 ns

tINYL = 1.4 ns tIRD2 = 3.6 ns†

Combinatorial

Logic Module

tPD = 3.0 ns

Sequential

Logic Module

I/O Module

tRD1 = 0.9 ns tDLH = 4.3 ns

I/O Module

ARRAY

CLOCKS

FMAX = 135 MHz

Combin-

atorial

Logic

included

in tSUD

DQDQ

tOUTH = 0.0 ns

tOUTSU = 0.4 ns

tGLH = 4.8 ns

tDLH = 4.3 ns

tENHZ = 6.1 ns

tRD1 = 0.9 ns

tCO = 3.0 ns

tSUD = 0.4 ns

tHD = 0.0 ns

tRD4 = 2.3 ns

tRD8 = 3.5 ns

Predicted

Routing

Delays

tCKH = 5.8 ns

FO = 256

tRD2 = 1.4 ns

tLCO = 10 ns (64 loads, pad-pad)

1200XL DB DS Page 119 Tuesday, October 3, 1995 8:36 AM

1-120

Parameter Measurement

Output Buffer Delays

AC Test Loads

Input Buffer Delays Module Delays

To AC test loads (shown below)PAD

TRIBUFF

In VCC GND

50%

PAD

VOL

VOH

1.5 V

tDLH

50%

1.5 V

tDHL

EVCC GND

50%

PAD VOL

1.5 V

tENZL

50%

10%

tENLZ

EVCC GND

50%

PAD

GND

VOH

1.5 V

tENZH

50%

90%

tENHZ

VCC

Load 1

(Used to measure propagation delay) Load 2

(Used to measure rising/falling edges)

35 pF

To the output under test VCC GND

35 pF

To the output under test

R to VCC for tPLZ/tPZL

R to GND for tPHZ/tPZH

R = 1 kΩ

PAD Y

INBUF

PAD 3 V 0 V

1.5 V

GND

VCC

50%

tINYH

1.5 V

50%

tINYL

S, A or B

GND

VCC

50%

tPLH

GND

VCC

50%

50% 50%

VCC

50% 50%

tPHL

tPLH

1200XL DB DS Page 120 Tuesday, October 3, 1995 8:36 AM

1200XL Field Programmable Gate Arrays

1-121

Sequential Module Timing Characteristics

Flip-Flops and Latches

Note: D represents all data functions involving A, B, and S for multiplexed flip-flops.

(Positive edge triggered)

CLK CLR

PRE Y

G, CLK

PRE, CLR

tWCLKA

tWASYN

tHD

tSUENA

tSUD

tRS

tWCLKI

tCO

tHENA

1200XL DB DS Page 121 Tuesday, October 3, 1995 8:36 AM

1-122

Sequential Timing Characteristics (continued)

Input Buffer Latches

Output Buffer Latches

PAD

CLK

DATA

CLK

tINH

CLKBUF

tINSU

tSUEXT

tHEXT

IBDL

DATA

tOUTSU

tOUTH

PAD

OBDLHS

1200XL DB DS Page 122 Tuesday, October 3, 1995 8:36 AM

1-123

1200XL Field Programmable Gate Arrays

Predictable Performance:

Tight Delay Distributions

Propagation delay between logic modules depends on the

resistive and capacitive loading of the routing tracks, the

interconnect elements, and the module inputs being

driven. Propagation delay increases as the length of

routing tracks, the number of interconnect elements, or the

number of inputs increases.

From a design perspective, the propagation delay can be

statistically correlated or modeled by the fanout (number

of loads) driven by a module. Higher fanout usually

requires some paths to have longer routing tracks.

The 1200XL family delivers a very tight fanout delay

distribution. This tight distribution is achieved in two

ways: by decreasing the delay of the interconnect elements

and by decreasing the number of interconnect elements per

path.

Actel’s patented PLICE antifuse offers a very low

resistive/capacitive interconnect. The 1200XL family’s

antifuses, fabricated in 0.6 micron lithography, offer

nominal levels of 100 ohms resistance and 7.0 femtofarad

(fF) capacitance per antifuse.

The 1200XL fanout distribution is also tight due to the low

number of antifuses required for each interconnect path.

The 1200XL family’s proprietary architecture limits the

number of antifuses per path to a maximum of four, with

90% of interconnects using two antifuses.

Timing Characteristics

Timing characteristics for 1200XL devices fall into three

categories: family dependent, device dependent, and

design dependent. The input and output buffer

characteristics are common to all 1200XL family

members. Internal routing delays are device dependent.

Design dependency means actual delays are not

determined until after placement and routing of the user’s

design is complete. Delay values may then be determined

by using the ALS Timer utility or performing simulation

with post-layout delays.

Critical Nets and Typical Nets

Propagation delays are expressed only for typical nets,

which are used for initial design performance evaluation.

Critical net delays can then be applied to the most

time-critical paths. Critical nets are determined by net

property assignment prior to placement and routing. Up to

6% of the nets in a design may be designated as critical,

while 90% of the nets in a design are typical.

Long Tracks

Some nets in the design use long tracks. Long tracks are

special routing resources that span multiple rows,

columns, or modules. Long tracks employ three and

sometimes four antifuse connections. This increases

capacitance and resistance, resulting in longer net delays

for macros connected to long tracks. Typically, up to 6%

of nets in a fully utilized device require long tracks. Long

tracks contribute approximately 4 ns to 8 ns delay. This

additional delay is represented statistically in higher

fanout (FO=8) routing delays in the data sheet

specifications section.

Timing Derating

A best case timing derating factor of 0.45 is used to reflect

best case processing. Note that this factor is relative to the

“standard speed” timing parameters, and must be

multiplied by the appropriate voltage and temperature

derating factors for a given application.

Table 4 • Logic Module + Routing Delay, by Fanout (ns)

(Worst-Case Commercial Conditions)

Family FO=1 FO=2 FO=3 FO=4 FO=8

A1225XL-1 3.9 4.4 4.8 5.3 6.5

A1240XL-1 4.2 4.4 4.9 5.6 6.8

A1280XL-1 4.4 5.0 5.5 6.0 8.7

1200XL DB DS Page 123 Tuesday, October 3, 1995 8:36 AM

1-124

Timing Derating Factor (Temperature and Voltage)

Timing Derating Factor for Designs at Typical Temperature (TJ = 25°C)

and Voltage (5.0 V)

Temperature and Voltage Derating Factors

(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)

Note: This derating factor applies to all routing and propagation delays.

Industrial Military

Min. Max. Min. Max.

(Commercial Minimum/Maximum Speciﬁcation) x 0.69 1.11 0.67 1.23

(Commercial Maximum Speciﬁcation) x 0.85

–55 –40 0 25 70 85 125

4.50 0.75 0.79 0.86 0.92 1.06 1.11 1.23

4.75 0.71 0.75 0.82 0.87 1.00 1.05 1.16

5.00 0.69 0.72 0.80 0.85 0.97 1.02 1.13

5.25 0.68 0.69 0.77 0.82 0.95 0.98 1.09

5.50 0.67 0.69 0.76 0.81 0.93 0.97 1.08

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

4.50 4.75 5.00 5.25 5.50

Derating Factor

Voltage (V)

125°C

85°C

70°C

25°C

0°C

–40°C

–55°C

Junction Temperature and Voltage Derating Curves

(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)

1200XL DB DS Page 124 Tuesday, October 3, 1995 8:36 AM