AN394 - STMicroelectronics

1/10June 1998

AN394

APPLICATION NOTE

MICROWIRE EEPROM COMMON I/O OPERATION

Within STMicroelectronics’ broad spectrum of different types of serial access EEPROM product, the MI-

CROWI RE® family is based on a 4-wire interface. The four line s consist of: the Clock Input (C), the Chip

Select Input (S), the Serial Data Input (D), and the Serial Data Output (Q).

Some microprocessor chips, such as ST’s mi crocontroller series, include an on-chip Serial Peripheral In-

terface (SPI). The MICROWIRE interface is ideally suited to use with these devices. However, the MICRO-

WIRE EEPROM devices can also be used with any gener al purpose microcontroller, provi ded that care is

taken no t to allow signal conflicts to result. This document discusses how to avoid such conflicts when

tying the D and Q lines together as a single bus.

While command s, address es or data are being shifted into the D serial input of the EE PROM device, the

Q out put is h eld i n t he high im pedance state. It should be possibl e, therefore, t o tie th e D and Q pi ns to -

gether to prov ide a com mo n D/Q bus , as depic ted in Figu re 1. The device c an, indeed , operate correctl y

in this con figuration, provided that appropriate design rules are followed.

The potentially troublesome situations are during commands which activate the Q output (such as

READ,WRI TE, ERA SE, WRAL and ERAL). This document considers these cases, and recommends the

most conservative solut ion to each problem. In order to provide t he designer wi th a safe design guide, all

calculations are based on worst case values, as found in the data sheets for these EEPROM devices.

Figure 1. Typical Application of t he Common-D/Q Approach

READ INSTRUCTION

The D dr iver and the Q receiver, in Figure 1, can be di sc rete logic, or par t of a microcontroller I/O port, or

any equival ent circuitr y. The READ com man d and its ad dress bits are clocked i nto t he c hi p, th rough the

D pin, on the rising edges of the C clock. Each bit must be kept valid for a minimum hol d time (tDVCH) as

specified in the data sheet for the memory device. The device holds t he Q pin in the high impedance state

during most of the input operation. However, as Figure 2 shows, the Q pin is taken out of this state at the

EEPROM Device

Data In

Driver Enable

(active low)

Common D/Q Bus

Data Out

Q Receiver

Clock In

Chip Select In

D Driver

Ai02419

AN394 - APPLICATION NOTE

2/10

start of the la st ad dress bit (A0) of the instruction (signalled by t he rising edge of C), and s tarts to out put

the leading zero that pr ecedes the 16-bit data string. The data sheets specify the maximum delay (tCHQL)

between the rising edge of C and th e leading zero data bit.

Figure 2. Timing Sequence for a Read Instructi on

Since the D driver must remain enabled with the A0 bit for a minimum of tDVCH (the ho ld time), a bus

conflict occurs whenever the A0 bit is a “1”, as it would be for all odd addressed registers). The conse-

quenc es are:

– A low impedance path is created between Vc c and ground through the D driver and the on-chip Q output

buffer (as depicted in Figure 3). This short-circuit may produc e glitches on t he power supply which can

disturb all the circuits on the board.

– The l ogic level on the D/Q bus is not well -defined: the potential divider chain, s o created, c an end up

producing a voltage level anywhere between Vcc and 0 V. Thus access to the odd addressed registers

will probably be impossible.

Figure 3. Short-Circuit Created Betwe en Vcc and Grou nd

Ai02420

Bus Conflict

1 0 A5 A4 A3 A2 A1 A0

0D15 D14 D13 D12 D11 D10 D9

High Impedance

Ai02424

EEPROM Device

A0="1" Common D/Q Bus

D Driver

Low Impedance Path

Output

Buffer

VCC

3/10

AN394 - APPLICATION NOTE

This problem c an be avoided by inserting a current limiting resistor in the current sink path. Figure 4 shows

some possible locations for thi s resistor. However, the best location is between the Q output and the D/ Q

bus for the following reasons:

– During the overl ap time, only the D dri ver is providing usef ul information. The Q driver simply outputs a

con stant zero. By p lacing th e resistor in this pos ition, the D driver ov errides the Q driver at set ting the

logic level on the D/Q bus, thereby allowing the last address bit to be presented on the D pin for the

specified hold time (tDVCH).

– The R resistor slows down the propagation time of the Q o utpu t signals on the D/Q bus , as di scu ssed

later in this document. In this position, the resistor only slows down the transmission of the 16 bits of

data during a READ operation. If R were in series with the D driver, all operations would be slowed

down.

Figure 4. Possible Locations for the Current Limiting Resistor

The R resistor does not have any effect as long as Q is in its high impedance s tate. During the execut ion

of a RE AD instruction, R sin ks s ome c urrent f rom the D driver during the short overlap t ime. Then the D

driver is disabled and Q output takes control of the D/Q bus through the R resistor.

Because of the bus capacit ance, C, the si gnals are distorted, as shown in Fi gure 5 (on the next page): t he

rising and fal ling edges of the Q output are transformed into exponential curves whose shape depends on

the time constant RC.

Ai02421

EEPROM Device

A0="1"

Recommended

Location

D Driver

Output

Buffer

VCC

Not Recommended

Locations

(If D driver is an

open collector type)

AN394 - APPLICATION NOTE

4/10

Figure 5. Expon ential Charge and Discharg e of the Bus Capacitance

As a consequence, the logi c level on the D/Q bus is not stable until some t i me after the risi ng edge of the

C clock. The delay in reading the bus should be at least 3xRC.

In a typical dat a sheet for a 5 V device, VOH(min) = 2.4 V and VOL(max) = 0.4 V, so giving a voltage swing

of 2 V. Using the 3xRC approximation, the D/Q bus levels will be:

– logical “1” = 2.3 V minimum after a delay of 3xRC

– logical “0” = 0.5 V maximum after the C rising edge

It might be neces sa ry to reduce the C clock frequen cy, w hen shifting the 16 data bits out from the EEP-

ROM during a READ operation, by an amount that is directly related to the RC time co nstant of the D/Q

bus. Al l other operations can be perf ormed at the nominal clock rate.

Figures 6, 7, 8 show so me experi men tal exampl es, plotted from the oscilloscope, with different values of

R and C. In the last example, the maximum clock frequency is: 1/(3xRC) = 100 kHz, assuming that the D/

Q bus is sampled by the Q recei ver circuitry just before the rising edge of the C clock.

Ai02422

0 RC 2xRC 3xRC

63%

RC = Time Constant

86%

95%

0 RC 2xRC 3xRC

13%

37%

% of the

Voltage Swing

5/10

AN394 - APPLICATION NOTE

Figure 6. Oscil loscope Pl ot, R = 10 kΩ, C = 100 pF, RC = 1 µs

Figure 7. Oscil loscope Pl ot, R = 5 kΩ, C = 100 p F, RC = 500 ns

Ai02425

10 µS

C clock

D/Q bus

Q output

D driver enable

(1 = disabled)

AO bit

is '1'

Q output

a '0' bit

D/Q bus is now driven by Q

D driver is disabled here

AN394 - APPLICATION NOTE

6/10

Figure 8. Oscil loscope Pl ot, R = 10 kΩ, C = 330 pF, RC = 3.3 µs

In order to avoid over reducing the clock frequency, the following techniques can be used to minimize the

R and C values:

■To min imize the bus capac itance:

– the EEP ROM device should be position as close as possibl e to the D-driver/Q-receiver circuitry (the ca-

paci t ance is proportional to t he surface area of the bus line).

– As few devi ces as possible shoul d share t he D/Q bus (the capacitance is proportional to the number of

input gates connected to t he bus).

■To minimize the resistor value:

– Find, from the data s heet, the m aximum current that the D dri ver can source, and divide this value into

the value of Vcc.

– Find t he m aximum transient current that the power supply c an source without glitches bei ng i ntroduced

on to the power lines, and divide this value into the value of Vcc .

– It is up to the designer to decide the best trade-off , based upon his specific application’s requirements,

but t he resistor value should not be less than the higher of the two values calculated above.

INTERFACE WITH CMOS CIRCUITS

The MICROW IRE EEPRO M specification makes these devices compa tible with TTL input/output levels.

When i nte rfacing t hese devices to CMOS circui ts, however, some precaut ion s m us t be taken, to ens ure

the correct interpretation of the logic levels.

Since the output-high level is close to VCC, and the output-low level is c lose to 0 V, there are no difficulties

in driving the D, S and C inputs of the EEPROM devices.

For the Q outpu t, though , the m inimum output-high level i s spec ified as being 2.4 V , which is lower than

the minim um input-high level of CMOS (3.5 V for Vcc = 5 V). A common pra ctice is to conne ct a pull-up

resistor, Rp, between the Q output and Vcc.

This sol ution works well wh en D and Q are separat e. However, it rai ses som e dif ficulties when D and Q

are tied together.

Ai02427

C clock

D/Q bus

Q output

D driver enable

(1 = disabled)

10 µS

7/10

AN394 - APPLICATION NOTE

When the Q output is at a “zero” lev el (VOL= 0.4 V), during the overlap period, the R and Rp resistors form

a potent ial divider chai n, as shown in Figure 9. Rp must have a resistance greater than 5 times t hat of R.

This means that the “zero” level on the D/Q bus is: 0.4 V + (5 V -0.4 V) x R / (R + Rp) = 1.17 V. Although

this value is 330 mV below the 1.5 V maximum input-low level for CMOS, it does mean losing the wide

noise margin that is traditionally associated with the CMOS specification.

Fi gure 9. D/Q Bus Con figu ration wit h Pull - up R esi stor ( R p)

For a high t o low transition, the Q on-chip output buf fer has to dischar ge the bus capacitance through t he

R resistor and t o sink some current from Vcc through the Rp resistor. The new time constant , when com-

pared to that c alculated earli er in this document , is reduced by 17%, because of the parallel combinati on

of R and Rp. However, the steady low level is not 0.4 V, as had been assumed f or TTL levels, but 1.17 V,

as calculat ed above for Rp = 5xR. Despite this smaller time constant, the voltage swing between high and

low is grea ter in t his case, as described later in this document, so i t is advisabl e t o keep the same del ay

(3xRC) between the C clock rising edge and the first sampl ing of the data line.

A greater problem is faced during the low to high transition, though. At first, the bus capacitance is charged

by the Q output through R, and from the Vcc power supply via Rp, again leading to a time constant for Rp

connec ted in parallel with R. But once the D/Q bus reaches the Q output voltage level, the Q on-chip buffer

automat ically turns off, and the Rp resistor remains the only contributor to the charge of th e bus capa ci-

tance. This results in a much highe r time constant: RpxC =5xRC.

For the worst case output-high level for Q (VOH= 2.4 V), combined with the minimum input-high level for

CMOS, the chargi ng delay, after the Q driver cuts out, needs t o be at least 0.55xRpC: that is, 2.75xRC.

This is still assuming Vcc = 5 V, and allowing for a noise margin of 300 or 400 mV .

As a result , the minim um delay be tween the rising edge of C and the sampli ng of the D/Q bus should be

2 or 3 times longer tha n the one we have found for the TTL levels (without Rp), and t he clo ck frequ ency

must be reduced acc ordingly. (A typical oscilloscope plot is shown in Figure 10).

It is possible to avoid this situation by using a TTL-compatible CMOS device as the Q receiver circuit, and

thereby to remove the need for the Rp resistor. Suitable devices include:

■mem bers of the 74HCTXXX family

■a CMOS microcontroller that provides an opti on for “ TTL input levels” on its I/O ports, such as the ST9

series.

Ai02423

EEPROM Device

Data In

D Driver

(CMOS)

Output

Buffer

VCC

Driver Enable

(active low)

Data Out

Q Receiver

(CMOS)

AN394 - APPLICATION NOTE

8/10

Figure 10. Oscil loscope Plot, R = 10 kΩ, C = 100 pF, Rp = 50 kΩ

PROGRAMMING MO DE: ACKNOWLEDGEMENT OF READY/BUSY STAT US

Duri ng a self-time d progr am min g cycle , MICROWIRE EEPRO M device s us e the Q output to indi ca te th e

ready/busy stat us of the chip. This occurs during the ex ecution of commands such as: W RITE, ERASE,

WRAL and ERA L.

The self-timed programming cycle begins with the falling edge of S, at the end of a programming com-

mand. The S pin must be kept l ow f or a minimum of tSLSH (as described in the data sheet). T he Q output

remains in its high impedance state as long as S is low. If S is brought high for cloc king-in a new command,

Q comes out of its high impedance state, and indicates the Ready/Busy status of the chip (0 = Busy,

1 = Ready).

Figure 11. Ackno wledg ement of the Ready/Busy S ignal on the Q Output

Ai02428

C clock

D/Q bus

Q output

D driver enable

(1 = disabled)

10 µS

Ai02429

C clock

D/Q bus

D driver enable

(1 = disabled)

10 µS

9/10

AN394 - APPLICATION NOTE

In app lications where D and Q are tied together, this may again create bus c onflicts . Therefore, it i s rec -

omm ended that this status sig nal be c ancelle d as s oon a s poss ible: this can be achieved very sim pl y by

applying a single clock pul se on the C input while S i s high, as depi cted in Figure 11.

The operation is scheduled as foll ows:

– shift the write command into the chip

– bring S low for the minimum period of tSLSH

– bring S high

– moni tor the D/Q bus until a high level (Ready) is detected

–clock C once

– bring S low

– th e ch ip is now re ady to accept t he ne xt instruct ion

It shoul d also be noted that, on power-up, the Ready/B usy status be ini tially in the active state. Therefore,

it is recommended t o clock C once (with S = 1) prior to t he issue of the f ir st command.

IMPROVING ON THE CALCULATIONS IN T HIS DOCUMENT

This document has discussed how MICROWIRE devices can be used in a configuration in which the D

and Q lines are tied together as a single bus. For safety, and for generality, the worst case and most con-

servative conditions hav e been assumed in all calculations.

In particular circum stances, however, it might be possible for the designer to do better than this. In the

designer’s own particular application, it might be reasonable to rule out some worst-c ase situations as nev-

er occ urring, and to adapt the calculati ons accordi ngly.

AN394 - APPLICATION NOTE

10/10

If you have any qu estions or suggestions concerning the matters raised in this document, please send

them to the following electronic mail address:

apps.eeprom@st.com

Please rem em ber to include your name, company , location, telephon e numbe r and fax numbe r.

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no respo nsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by i m plicati on or otherwi se under any patent or patent rights o f STMicroelec t ronics. Speci fications mention ed in thi s publi cation are subject

to ch ange without notice. This publica tion supersedes and replaces al l informati on previ ously supp l ie d. STM i croel ectron i cs products are not

authorized for us e as cri t i cal com ponents in l i fe support de vices or s ys tems without ex press wr i tt en a pproval of STMi croelect ronic s.

The ST l ogo is a re gi stered trade m ark of STMi croel ectro ni cs.

All other nam es are th e propert y of their respect ive owners.

STMicro electronics GROUP OF COMPANIES

Austra lia - Brazil - Chi na - Fra nce - Germ any - Ita l y - J apan - Korea - Malaysia - M al ta - Mor occo - The Nether l ands - Singapo r e - Spain -

Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.