SP000014559 - INFINEON TECHNOLOGIES AG

Wireless Components

ASK/FSK Transmitter 31 5 MHz

TDK 5101 Version 1.0

Specification October 2002

Preliminary

Edition 31.10.2001

Published by Infineon Technologies AG,

Balanstraße 73,

815 41 Mü nc he n

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Revision History

Current Version: Version 1.0 as of 31.10.2002

Previous Version: Version 0.1 as of February 2002

Page

(in previous

Version)

Page

(in current

Version)

Subjects (major changes since last revision)

4-4 4-4 BOM of 50 Ohm-Output Testboard defined

4-7 4-5 ... 4-13 Ohm-Output Testboard Measurement results added

Application Hints on the Power Amplifier added

5-2 5-2 ESD-specification added

5-3, 5-6 5-3, 5-6 VCO-frequency range specified

5-4, 5-7 5-4, 5-7 Tolerances of Lcosc specified

Value of Iclkout co rrec ted

5-5, 5-8 5-5, 5-8 Tolerances of output power specified

Product Info

Wireless Components

Specific ati on, Oc tob er 2002

Package

TDK 5101

Product Info

General Description The TDK 5101 is a single chip ASK/

FSK transmitter for the frequency band

31 1-317 MHz. The IC offers a high level

of integration and needs only a few

extern al components . The device co n-

tains a fully integrated PLL synthesizer

and a h igh ef fi cien cy powe r am pli fie r to

drive a loop antenna. A special circuit

design and an unique power amplifier

design are used to save current con-

sumption and therefore to save battery

life. Additionally features like a power

down mode, a low power detect and a

divided clock output are implemented.

The IC can be used for both ASK and

FSK modulation.

Features ■fully integrated frequency synthe-

sizer

■VCO without external components

■high efficiency power amplifier

■frequency range 311 ... 317 MHz

■ASK/FSK modulation

■low supply current (typically 7mA)

■voltage supply range 2.1 ... 4 V

■temperature range -40 ... +125°C

■power down mode

■low voltage sensor

■programmable divided clock output

for µC

■low external component count

Applications ■Keyless entry systems

■Remote control systems

■Alarm systems

■Communication systems

Ordering Information

Type Ordering Code Package

TDK 5101 Q67100-H2062 P-TSSOP-16

available on tape and reel

2Product Description

2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Contents of this Chapter

Product Description

2 - 2

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

2.1 Overview

The TDK 5101 is a single chip ASK/FSK transmitter for the frequency band 31 1-

317 MHz. The IC offers a high level of integration and needs only a few external

components. The device contains a fully integrated PLL synthesizer and a high

efficiency power amplifier to drive a loop antenna. A special circuit design and

an unique power amplifier design are used to save current consumption and

therefore to save battery life. Additional features like a power down mode, a low

power detect and a divided clock output are implemented. The IC can be used

for both ASK and FSK modulation.

2.2 Applications

■Keyless entry systems

■Remote control systems

■Alarm systems

■Communication systems

2.3 Features

■fully integrated frequency synthesizer

■VCO without external components

■high efficiency power amplifier

■frequency range 311 MHz ... 317 MHz

■ASK/FSK modulation

■low supply current (typically 7 mA)

■voltage supply range 2.1 V ... 4 V

■temper ature ra nge -40°C ... 125°C

■power down mode

■low voltage sensor

■programmable divided clock out put for µC

■low external component count

Product Description

2 - 3

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

2.4 Package Outlines

Figure 2-1 P-TSSOP-16

3Functional Description
 
1 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3 Functional Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
4 Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
4.1 PLL Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
4.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
4.3 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
4.4 Low Power Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
4.5 Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
4.5.1 Power Down Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10
4.5.2 PLL Enable Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
4.5.3 Transmit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10
4.5.4 Power mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
4.6 Recommended timing diagrams for ASK- and FSK-Modulation . .3-12
Contents of this Chapter

Functional Description

3 - 2

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

3.1 Pin Configuration

Pin_config.wmf

Figure 3-1 IC Pin Configur atio n

Table 3-1

Pin No. Symbol Function

1PDWN Power Down Mode Control

2LPD Low Power Detect Output

3VS Voltage Supply

4LF Loop Filter

5GND Ground

6ASKDTA Amplitude Shift Keying Data Input

7FSKDTA Frequency Shift Keying Data Input

8CLKOUT Clock Driver Output

9CLKDIV Clock Divider Control

10 COSC Crystal Oscillator Input

11 FSKOUT Frequency Shift Keying Switch Output

12 FSKGND Frequency Shift Keying Ground

13 PAGND Power Amplifier Ground

14 PAOUT Power Amplifier Output

15 FSEL Frequency Range Selection: Has to be shorted to

ground for 315 MHz operation

16 CSEL Crystal Frequency Selection: Has to be left open

CSEL

FSEL

PAOUT

PAGND

FSKGND

FSKOUT

COSC

CLKDIV

PDWN

LPD

GND

ASKDTA

FSKDTA

CLKOUT

TDK 5101

Functional Description

3 - 3

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

3.2 Pin Definitions and Functions

Table 3-2

No. Symbol Interface Schematic1) Function

1PDWN Disable pin for the complete transmitter cir-

cuit.

A logic low (PDWN < 0.7 V) turns off all

transmitter functions.

A logic high (PDWN > 1.5 V) gives access to

all transmitter functions.

PDWN input will be pulled up by 40 µA inter-

nally by setting FSKDTA or ASKDTA to a

logic high-state.

2LPD This pin provides an output indicating the

low-voltage state of the supply voltage VS.

VS < 2.15 V will set LPD to the low-state.

An internal pull-up current of 40 µA gives the

output a high-state at supply voltages above

2.15 V.

3VS This pin is the positive supply of the trans-

mitter electronics.

An RF bypass capacitor should be con-

nected directly to this pin and returned to

GND (pin 5) as short as possible.

150 k

Ω

5 k

Ω

250 k

Ω

"ON"

∗

(ASKDTA+FSKDTA)

300

Ω

40 µA

Functional Description

3 - 4

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

4LF Output of the charge pump and input of the

VCO control voltage.

The loop bandwidth of the PLL is 150 kHz

when only the internal loop filter is used.

The loop bandwidth may be reduced by

applying an external RC network referencing

to the positive supply VS (pin 3).

5GND General ground connection.

6ASKDTA Digital amplitude modulation can be

imparted to the Power Amplifier through this

pin.

A logic high (ASKDTA > 1.5 V or open)

enables the Power Amplifier.

A logic low (ASKDTA < 0.5 V)

disable s the Powe r Am pli fi er .

7FSKDTA Digital frequency modulation can be

imparted to the Xtal Oscillator by this pin.

The VCO-frequency varies in accordance to

the frequency of the reference oscillator.

A logic high (FSKDTA > 1.5V or open)

sets the FSK switch to a high impedance

state.

A logic low (FSKDTA < 0.5 V)

closes the FSK switch

from FSKOUT (pin 11) to FSKGND (pin 12).

A capacitor can be switched to the reference

crystal network this way. The Xtal Oscillator

frequency will be shifted giving the designed

FSK frequency deviation.

10 k

Ω

35 k

Ω

15 pF

140 pF

+1.2 V

90 k

Ω

50 pF 30

60 k

Ω

+1.1 V

+1.2 V

90 k

Ω

60 k

Ω

+1.1 V

Functional Description

3 - 5

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

8CLKOUT Clock output to supply an external device.

An external pull-up resistor has to be added

in accordance to the driving requirements of

the external device.

A clock frequency of 2.46 MHz is selected

by a logic low at CLKDIV input (pin9).

A clock frequency of 615 kHz is selected by

a logic high at CLKDIV input (pin9).

9CLKDIV This pin is used to select the desired clock

division rate for the CLKOUT signal.

A logic low (CLKDIV < 0.2 V) applied to this

pin selects the 2.46 MHz output signal at

CLKOUT (pin 8).

A logic high (CLKDIV open) applied to this

pin selects the 615 kHz output signal at

CLKOUT (pin 8).

10 COSC This pin is connected to the reference oscil-

lator circuit.

The reference oscillator is working as a neg-

ative impedance converter. It presen ts a

negative resistance in series to an induc-

tance at the COSC pin.

11 FSKOUT This pin is connected to a switch to

FSKGND (pin 12).

The switch is closed when the signal at

FSKDTA (pin 7) is in a logic low state.

The switch is open when the signal at

FSKDTA (pin 7) is in a logic high state.

FSKOUT can switch an additional capacitor

to the reference crystal network to pull the

crystal fr eque nc y by an amou nt res ul tin g in

the desired FSK frequency shift of the trans-

mitter output frequency.

12 FSKGND Ground connection for FSK modulation out-

put FSKOUT.

300

Ω

+1.2 V

60 k

Ω

60 k

Ω

+0.8 V

6 k

Ω

100

200 µA

1.5 k

Ω

Functional Description

3 - 6

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

13 PAGND Ground connection of the power amplifier.

The RF ground return path of the power

amplifier output PAOUT (pin 14) has to be

concentrated to this pin.

14 PAOUT RF output pin of the transmitter.

A DC path to the positive supply VS has to

be supplied by the antenna matching net-

work.

15 FSEL This pin has to be short ed to ground to

select the 315 MHz transmitter frequency

range.

A logic low (FSEL < 0.5 V) applied to this pin

sets the transmitter to the 315 MHz fre-

quency ra nge .

A logic high (FSEL open) applied to this pin

sets the transmitter to the 630 MHz fre-

quency ra nge .

16 CSEL This pin is used to select the desired refer-

ence freque nc y.

A logic high (CSEL open) applied to this pin

sets th e inte rnal fr equ ency divi der to ac cep t

a reference frequency of 9.84 MHz.

1) Indicated voltages and currents apply for PLL Enable Mode and Transmit Mode.

In Power Down Mode, the values are zero or high-ohmic.

+1.2 V

90 k

Ω

30 k

Ω

+1.1 V

+1.2 V

60 k

Ω

60 k

Ω

+0.8 V

Functional Description

3 - 7

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

3.3 Functional Block diagram

Funct_Block_Diagram.wmf

Figure 3-2 Functional Block diagram

XTAL

Osc

:2/8

:4/16

PD :128/64 VCO :1/2 Power

AMP

Low voltage

Sensor 2.2V

Power

Supply

7135 2

6154168

GND

FSK

DATA

INPUT

POWER

DOWN

MODE V

GND LOW POWER

DETECT

OUTPUT

POWER

AMPLIFIER

OUTPUT

POWER

AMPLIFIER

GND

POWER

AMPLIFIER

ASK

DATA

INPUT

434/868

MHz

LOOP

FILTER

CRYSTAL

6.78/13.56

CLKOUT

6.78/13.56

MHz

CLKDIV

ASK

DATA

INPUT

Functional Description

3 - 8

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

3.4 Functional Blocks

3.4.1 PLL Synthesizer

The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator

(VCO), an asynchronous divider chain, a phase detector, a charge pump and a

loop filter. It is fully implemented on chip. The tuning circuit of the VCO consist-

ing of spiral inductors and varactor diodes is on chip, too. Therefore no addi-

tional external components are necessary. The nominal center frequency of the

VCO is 630 MHz. The oscillator signal is fed both, to the synthesizer divider

chain and to the power amplifier. The overall division ratio of the asynchronous

divider chain is 64. The phase detector is a Type IV PD with charge pump. The

passive loop filter is realized on chip. In all 315 MHz applications, the FSEL pin

is shorted to ground (logic low) and the CSEL pin is not connected (logic high).

3.4.2 Crystal Oscillator

The crystal oscillator operates at 9.84 MHz. Frequencies of 615 kHz or 2.46

MHz are available at the clock output CLKOUT (pin 8) to drive the clock input

of a micro controller.

The frequency at CLKOUT (pin 8) is controlled by the signal at CLKDIV (pin 9)

To achieve FSK transmission, the oscillator frequency can be detuned by a

fixed amount by switching an external capacitor via FSKOUT (pin 11).

The condition of the switch is controlled by the signal at FSKDTA (pin 7).

Table 3-3 CLKDIV (pin 9) CLKOUT Frequency

Low1)

1) Low: Voltage at pin < 0.2 V

2.46 MHz

Open2)

2) Open: Pin open

615 kHz

Table 3-4 FSKDTA (pin7) FSK Switch

Low1)

1) Low: Voltage at pin < 0.5 V

CLOSED

Open2), High3)

2) Open: Pin open

3) High: Voltage at pin > 1.5 V

OPEN

Functional Description

3 - 9

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

3.4.3 Power Amplifier

For operation at 315 MHz, the power amplifier is fed with the VCO frequency

divided by 2. It is possible to feed the power amplifier directly from the voltage

controlled oscillator. This is controlled by FSEL (pin 15) as described in the

table below.

In all 315 MHz applications, the pin FSEL is connected to ground.

The Power Amplifier can be switched on and off

by the signal at ASKDTA (pin 6).

The Power Amplifier has an Open Collector output at PAOUT (pin 14) and

requires an external pull-up coil to provide bias. The coil is part of the tuning and

matching LC circuitry to get best performance with the external loop antenna.

To achieve the best power amplifier efficiency, the high frequency voltage swing

at PAOUT (pin 14) should be twice the supply voltage.

The power amplifier has its own ground pin PAGND (pin 13) in order to reduce

the amount of coupling to the other circuits.

3.4.4 Low Power Detect

The supply voltage is sensed by a low power detector. When the supply voltage

drops below 2.15 V, the output LPD (pin 2) switches to the low-state. To mini-

mize the external component count, an internal pull-up current of 40 µA gives

the output a high-state at supply voltages above 2.15 V.

The output LPD (pin 2) can either be connected to ASKDTA (pin 6) to switch off

the PA as soon as the supply voltage drops below 2.15 V or it can be used to

inform a micro-controller to stop the transmission after the current data packet.

Table 3-5 FSEL (pin 15) Radiated Frequency Band

Low1)

1) Low: Voltage at pin < 0.5 V

315 MHz

Open2)

2) Open: Pin open

630 MHz

Table 3-6 ASKD TA (pin 6) Power Amplifier

Low1)

1) Low: Voltage at pin < 0.5 V

OFF

Open2), High3)

2) Open: Pin open

3) High: Voltage at pin > 1.5 V

Functional Description

3 - 10

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

3.4.5 Power Modes

The IC provides three power modes, the POWER DOWN MODE, the PLL

ENABLE MODE and the TRANSMIT MODE.

3.4.5.1 Power Down Mode

In the POWER DOWN MODE the complete chip is switched off.

The current consumption is typically 0.3 nA at 3 V 25°C.

This current doubles every 8°C. The values for higher temperatures are

typically 14 nA at 85°C and typically 600 nA at 125°C.

3.4.5.2 PLL Enable Mode

In the PLL ENABLE MODE the PLL is switched on but the power amplifier is

turned off to avoid undesired power radiation during the time the PLL needs to

settle. The turn on time of the PLL is determined mainly by the turn on time of

the crystal oscillator and is less than 1 msec when the specified crystal is used.

The current consumption is typically 3.5 mA.

3.4.5.3 Transmit Mode

In the TRANSMIT MODE the PLL is switched on and the power amplifier is

turned on too.

The current consumption of the IC is typically 7 mA when using a proper trans-

forming network at PAOUT, see Figure 4-1.

3.4.5.4 Power mode control

The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin 1).

When the bias circuitry is powered up, the pins ASKDTA and FSKDTA are

pulled up inte rn all y.

Forcing the voltage at the pins low overrides the internally set state.

Alternatively, if the voltage at ASKDTA or FSKDTA is forced high externally, the

PDWN pin is pulled up internally via a current source. In this case, it is not nec-

essary to connect the PDWN pin, it is recommended to leave it open.

The principle schematic of the power mode control circuitry is shown in

Figure 3-5.

Functional Description

3 - 11

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

Power_Mode.wmf

Figure 3-5 Power mode control circuitry

Table 3-7 provides a listing of how to get into the different power modes

Other combinations of the control pins PDWN, FSKDTA and ASKDTA are not

recommended.

Table 3-7

PDWN FSKDTA ASKDTA MODE

Low1)

1) Low: Voltage at pin < 0.7 V (PDWN)

Voltage at pin < 0.5 V (FSKDTA, ASKDTA)

Low, Open Low, Open POWER DOWN

Open2)

2) Open: Pin open

Low Low

High3)

3) High: Voltage at pin > 1.5 V

Low, Open, High Low PLL ENABLE

Open High Low

High Low, Open, High Open, High

TRANSMITOpen High Open, High

Open Low, Open, High High

Bias

Source

FSKDTA

ASKDTA

PDWN

FSKOUT

PAOUT

Bias Voltage

120 k

Ω

PLL

FSK

120 k

Ω

315

MHz

Functional Description

3 - 12

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

3.4.6 Recommended timing diagrams for ASK- and FSK-Modulation

ASK Modulation using FSKDTA and ASKDTA, PDWN not connected

ASK_mod.wmf

Figure 3-6 ASK Modulation

FSK Modulation using FSKDTA and ASKDTA, PDWN not connected

FSK_mod.wmf

Figure 3-7 FSK Modulation

FSKDTA

High

Low

ASKDTA

min. 1 msec.

DATA

Open, High

Low

Modes: TransmitPLL EnablePower Down

FSKDTA

High

Low

ASKDTA

min. 1 msec.

DATA

High

Low

Modes: TransmitPLL EnablePower Down

Functional Description

3 - 13

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

Alternative ASK Modulation, FSKDTA not connected.

Alt_ASK_mod.wmf

Figure 3-8 Alternative ASK Modulation

Alternative FSK Modulation

Alt_FSK_mod.wmf

Figure 3-9 Alternative FSK Modulation

PDWN

High

Low

ASKDTA

min. 1 msec.

DATA

Open, High

Low

Modes: TransmitPLL EnablePower Down

FSKDTA

min. 1 msec.

DATA

Open, High

Low

Modes: TransmitPLL EnablePower Down

PDWN

High

Low

to t

ASKDTA

Open, High

Low

to t

4Applications

4.1 50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.2 50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.3 Bill of material (50 Ohm-Output Testboard) . . . . . . . . . . . . . . . . . . . . 4-4

4.4 50 Ohm-Output Testboard: Measurement results . . . . . . . . . . . . . . . 4-5

4.5 Application Hints on the crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 4-6

4.6 Design hints on the buffered clock output (CLKOUT). . . . . . . . . . . . . 4-8

4.7 Application Hints on the Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . 4-9

Contents of this Chapter

Applications

4 - 2

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

4.1 50 Ohm-Output Testboard Schematic

50ohm_test_v5.wmf

Figure 4-1 50 Ω-Output testboard schematic

R1 C5

X1SMA

TDK5101

VCC

R3F

R3A

X2SMA

ASK FSK

0.615 (2.46)

MHz

Applications

4 - 3

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

4.2 50 Ohm-Output Testboard Layout

Figure 4-2 Top Side of TDK 5101-Testboard with 50 Ω-Output.

It is the same testboard as for the TDA 5100.

Figure 4-3 Bottom Side of TDK 5101-Testboard with 50 Ω-Output.

It is the same testboard as for the TDA 5100.

Applications

4 - 4

TDK 5101

Wireless Components

Specific ati on, Oc tob er 2002

4.3 Bill of material (50 Ohm-Output Testboard)

Table 4-1 Bill of material

Part ASK 315 MHz FSK 315 MHz Specification

R1 4.7 kΩ4.7 kΩ0805, ± 5%

R2 12 kΩ0805, ± 5%

R3A 15 kΩ0805, ± 5%

R3F 15 kΩ0805, ± 5%

R4 open open 0805, ± 5%

C1 47 nF 47 nF 0805, X7R, ± 10%

C2 33 pF 33 pF 0805, COG, ± 5%

C3 5.6 pF 5.6 pF 0805, COG, ± 0.1 pF

C4 330 pF 330 pF 0805, COG, ± 5%

C5 1 nF 1 nF 0805, X7R, ± 10%

C6 8.2 pF 8.2 pF 0805, COG, ± 0.1 pF

C7 0 Ω Ju mp er 47 pF 0805, COG, ± 5%

0805, 0Ω Jumper

C8 22 pF 22 pF 0805, COG, ± 5%

L1 150 nH 150 nH TOKO LL2012-J

L2 56 nH 56 nH TOKO LL2012-J

Q1 9843.75 kHz,

CL=12pF 9843.75 kHz,

CL=12pF Tokyo Denpa TSS-3B

9843. 75 kHz

Spec.No. 10-5 022 1

IC1 TDK 5101 TDK 5101

T1 Push-button Push-button replaced by a short

B1 Battery clip Battery clip HU2031-1, RENATA

X1 SMA-S SMA-S SMA standing

X2 SMA-S SMA-S SMA standing

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Pout over tem peratur e TDK5101 315 M Hz

0,00

1,00

2,00

3,00

4,00

5,00

6,00

7,00

8,00

9,00

-50 0 50 100 150

T [°C]

Pout [dBm ]

4, 0 V

3, 0 V

2, 1 V

2, 0 V

1, 9 V

I s over t emperature TDK5101 315 MHz

5,5

6,5

7,5

8,5

-50050100150

T [°C]

Is [mA ]

4, 0 V

3, 0 V

2, 1 V

2, 0 V

1, 9 V

4.4 50 Ohm-Output Testboard: Measurement results

Note the specified operating range: 2.1 V to 4.0 V and −40°C to +125°C.

Pout_over_Temp_315.wmf

Figure 4-4 Pout over Tempera ture of the 50Ω-testboard with TDK5101 at 315 MHz

is_over_temp_315.wmf

Figure 4-5 Is over temperature of the 50Ω-testboard with TDK5101 at 315 MHz

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4.5 Application Hints on the crystal oscillator

As mentioned before, the crystal oscillator achieves a turn on time less than

1 msec . To achi eve thi s, a NIC os cill ator ty pe is imp lemen ted in th e TDK 510 1.

The input impedance of this oscillator is a negative resistance in series to an

inductance. Therefore the load capacitance of the crystal CL (specified by the

crystal supplier) is transformed to the capacitance Cv.

CL: crystal load capacitance for nominal frequency

ω: angular frequency

L: inductance of the crystal oscillator

Example for the ASK-Mode:

Referring to the application circuit, in ASK-Mode the capacitance C7 is replaced

by a short to ground. Assume a crystal frequency of 9.84 MHz and a crystal load

capacitance of CL = 12 pF. The inductance L at 9.84 MHz is about 4.4 µH.

Therefore C6 is calculated to 10 pF.

-R L f, CL Cv

(1)

Cv =

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Example for the FSK-Mode:

FSK modulation is achieved by switching the load capacitance of the crystal as

shown below.

The frequency deviation of the crystal oscillator is multiplied with the divider

factor N of the Phase Locked Loop to the output of the power amplifier . In case

of small frequency deviations (up to +/- 1000 ppm), the two desired load

capacitances can be calculated with the formula below.

CL: crystal load capacitance for nominal frequency

C0: shunt capacitance of the crystal

f: frequency

ω: ω = 2πf: angular frequency

N: division ratio of the PLL

df: peak freque nc y dev iat ion

Because of the inductive part of the TDK 5101, these values must be corrected

by formula 1). The value of Cv± can be calculated.

-R L f, CL Cv1 Cv2

COSC

FSKOUT

FSKDTA

Csw

)

1)0(2

)

1)0(2

CCLC

fN fCCLC

fN f

CCL

CL +

∆

=±

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If the FSK switch is closed, Cv- is equal to Cv1 (C6 in the application diagram).

If the FSK switch is open, Cv2 (C7 in the application diagram) can be calculated.

Csw: parallel capacitance of the FSK switch (3 pF incl. layout parasitics)

Remark: These calculations are only approximations. The necessary values

depend on the layout also and must be adapted for the specific

application board.

The 50Ω-Output testboard shows an FSK-deviation of +/- 22.5 kHz, typically.

4.6 Design hints on the buffered clock output (CLKOUT)

The CLKOUT pin is an open collector output. An external pull up resistor (RL)

should be connected between this pin and the positive supply voltage. The

value of RL is depending on the clock frequency and the load capacitance CLD

(PCB board plus input capacitance of the microcontroller). RL can be calculated

to:

Remark: To achieve a low current consumption and a low

spurious radiation, the largest possible RL should be chosen.

1)( )1()(1

72 CvCv CswCvCvCvCsw

CCv −+ +∗+−∗

Table 4-2 fCLKOUT=

615 kHz fCLKOUT=

2.46 MHz

CLD[pF]RL[kOhm]CLD[pF]RL[kOhm]

539 5 10

10 18 10 4.7

20 10 20 2.2

CLDfCLKOUT

RL *8*

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4.7 Appli cation Hints on the Power-Amp lifi er

The power amplifier operates in a high efficient class C mode. This mode is

characterized by a pulsed operation of the power amplifier transistor at a current

flow angle of θ<<π. A frequency selective network at the amplifier output

passes the fundamental frequency component of the pulse spectrum of the

collecto r current to the load. Th e load and its reson ance transform ation to the

collecto r of the power amplifier can be gener alized by the equival ent circuit of

Figure 4- 6. The tank c ircuit L//C//R L in parallel to the output im pedance of the

transistor should be in resonance at the operating frequency of the transmitter.

Equivalent_power_wmf.

Figure 4-6 Equivalent power amplifier tank circuit

The optim um load at the collecto r of the power amplifie r for “critical” operati on

under idealized conditions at resonance is:

The th eoretic al value of RLC for an RF output power of Po= 5 dBm (3.16 mW) is:

“Critical” operation is characterized by the RF peak voltage swing at the

collector of the PA transistor to just reach the supply voltage VS.

The high degree of efficiency under “critical” operating conditions can be

explained by the low power losses at the transistor. During the conducting

phase of the tran sistor, its collector voltage is very sma ll. This wa y the power

loss of the transi s tor, e qua l to iC*uCE , is minimiz ed. This i s parti cu la rl y true for

small current flow angles of θ<<π.

In practice the RF-satu ration voltage of the PA transistor and other parasitics

redu ce the “critical” RLC.

LC P

Ω== 1423

00316

.0*2 32

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The output power Po is reduced by operating in an “overcritical” mode

characterised by RL > RLC.

The power efficiency (and the bandwidth) increase when operating at a slightly

higher RL, as shown in Figure 4-7.

The collector efficiency E is defined as

The d ia gr am of Fi gu r e 4-7 w as measur ed direct l y at the PA-out p ut a t V S = 3 V.

Losses in the matching circuitry decrease the output power by about 1.5 dB. As

can be s een from th e diagram, 70 0 Ω is t he opti mu m i mp eda nc e fo r op erati on

at 3 V. F or an a pprox im ati on o f ROPT an d POUT a t oth e r su ppl y v ol tages thos e

2 formulas can be used:

and

Power_E_vs_RL.wmf

Figure 4-7 Output power Po (mW) and collector efficiency E vs. load resistor RL.

The DC collector current Ic of the power amplifier and the RF output power Po

vary wi th the l oad resist or RL. This is typical for overcritical operation of class C

amplifiers. The collector current will show a characteristic dip at the resonance

frequency for this type of “overcritical” operation. The depth of this dip will

increase with higher values of RL.

IVP

OPT VR ~

OPTOUT RP ~

0 1000 2000 3000

RL [Ohm]

10*E

0*E

o [mW]

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As Figure 4-8 shows, detuning beyond the bandwidth of the matching circuit

results in a significant increase of collector current of the power amplifier and in

some loss of output power. This diagram shows the data for the circuit of the

test board at the frequency of 315 MHz. The effective load resistance of this

circuit i s RL = 700 Ω, which is the optimum impedance for operation at 3 V. This

will lead to a dip of the collector current of approx. 40%.

pout_vs_frequ.wmf

Figure 4-8 Output power and collector current vs. frequency

C3, L2-C2 and C8 are the main matching components which are used to

transform the 50 Ω load at the SMA-RF-connector to a higher impedance at the

PA-output (700 Ω @ 3 V). L1 c an be use d for so me finetuni ng of the r esona nt

frequency but should not become too small in order to keep its losses low.

The transformed impedance of 700+j0 Ω at the PA-output-pin can be verified

with a network analyzer using the following measurement procedure:

1. Calibrate your network analyzer.

2. Connect some short, low-loss 50 Ω cable to your network analyzer with an

open end on one side. Semirigid cable works best.

3. Use the „Port Extension“ feature of your network analyzer to shift the refer-

ence plane of your network analyzer to the open end of the cable.

4. Connect the center-conductor of the cable to the solder pad of the pin „PA“

of the IC. The outer conductor has to be grounded. Very short connections

have to be used. Do not remove the IC or any part of the matching-compo-

nents!

5. Screw a 50 Ω dummy-load on the RF-I/O-SMA-connector

6. Be sure that your network analyzer is AC-coupled and turn on the power

supply of the IC. The TDK5101 must not be in Transmit-Mode.

7. Measure the S-parameter S11

420 430 440 450

f [MHz]

Ic [ mA ]

Po [dBm]

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Plot0.pcx

Figure 4-9 Sparam_measured_200M

Above you can see the measurement of the evalboard with a span of 100 MHz.

The evalboard has been optimized for 3 V. The load is about 700+j0 Ω at

the transmit frequency.

A tuning-free realization requires a careful design of the components within the

matching network. A simple linear CAE-tool will help to see the influence of

tolerances of matching components.

Suppression of spurious harmonics may require some additional filtering within

the antenna matching circuit. The total spectrum of a typical 50 Ω-Output

testboard can be summarized as:

Table 4-3

Frequency Output Power

315 MHz Testboa rd

315 MHz +5 dBm

315 MHz − 9.84 MHz −72 dBc

315 MHz + 9.84 MHz −74 dBc

2nd harmonic −49 dBc

3rd harmonic −43 dBc

5Reference

5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.3.1 AC/DC Characteristics at 3V, 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.3.2 AC/DC Characteristics at 2.1 V ... 4.0 V, -40°C ... +125°C. . . . . . . . . 5-6

Contents of this Chapter

Reference

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5.1 Absolute Maximum Ratings

The AC / DC characteristic limits are not guaranteed. The maximum ratings

must not be exceeded under any circumstances, not even momentarily and

individually, as permanent damage to the IC may result.

Ambient Temperature under bias: TA=-40°C to +125°C

Note: All voltages referred to ground (pins) unless stated otherwise.

Pins 5, 12 and 13 are grounded.

5.2 Operating Range

Within the operational range the IC operates as described in the circuit

description.

Table 5-1

Parameter Symbol Limit Values Unit Remarks

Min Max

Junction Temperature TJ-40 150 °C

Storage Temper ature Ts-40 125 °C

Thermal Resistance RthJA 230 K/W

Supply voltage VS-0.3 4.0 V

Voltage at any pin

excluding pin 14 Vpins -0.3 VS + 0.3 V

Voltage at pin 14 Vpin14 -0.3 2 * VS VNo ESD-Diode to

Current into pin 11 Ipin11 -10 10 mA

ESD integrity, all pins VESD -1 +1 kV JEDEC Standard

JESD22-A114-B

ESD integrity, all pins

excluding pin 14 VESD -2 +2 kV JEDEC Standard

JESD22-A114-B

Table 5-2

Parameter Symbol Limit Values Unit Test Conditions

Min Max

Supply voltage VS2.1 4.0 V

Ambient temperature TA-40 125 °C

Reference

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5.3 AC/DC Characteristics

5.3. 1 AC/D C Cha rac te ristics at 3V, 25°C

Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25°C

Parameter Symbol Limit Values Unit Test Conditions

Min Typ Max

Current consumption

Power down mode IS PDWN 0.3 100 nA V (Pins 1, 6 and 7)

< 0.2 V

PLL enable mode IS PLL_EN 3.5 4.2 mA

Transmit mo de IS TRANSM 79mA Load tank see

Figure 4-1 and 4-2

Power Down Mode Control (Pin 1)

Power down mode VPDWN 00.7 VV

ASKDTA < 0.2 V

VFSKDTA < 0.2 V

PLL enable mode VPDWN 1.5 VSVV

ASKDTA < 0.5 V

Transmit mo de VPDWN 1.5 VSVV

ASKDTA > 1.5 V

Input bi as current PDWN IPDWN 30 µA VPDWN = VS

Low Power Detect Output (Pin 2)

Internal pull up current I LPD1 30 µA VS = 2.3 V ... VS

Input current low voltage I LPD2 1mA VS = 1.9 V ... 2.1 V

Loop Filter (Pin 4)

VCO tuning voltag e VLF VS - 1.4 VS - 0.7 Vf

VCO = 630 MHz

Output frequency range

315 MHz-band fOUT, 315 305 315 325 MHz VFSEL = 0 V

fOUT = fVCO / 2

ASK Modulation Data Input (Pin 6)

ASK Transmit disabled VASKDTA 00.5 V

ASK Transmit enabled VASKDTA 1.5 VSV

Input bias current ASKDTA IASKDTA 30 µA VASKDTA = VS

Input bias current ASKDTA IASKDTA -20 µA VASKDTA = 0 V

ASK data rate fASKDTA 20 kHz

Reference

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Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25°C

Parameter Symbol Limit Values Unit T est Conditi ons

Min Typ Max

FSK Modulation Data Input (Pin 7)

FSK Switch on VFSKDTA 00.5 V

FSK Switch off VFSKDTA 1.5 VSV

Input bias current FSKDTA IFSKDTA 30 µA VFSKDTA = VS

Input bias current FSKDTA IFSKDTA -20 µA VFSKDTA = 0 V

FSK data rate fFSKDTA 20 kHz

Clock Driver Output (Pin 8)

Output current (High) ICLKOUT 5µA VCLKOUT = VS

Saturation Voltage (Low)1) VSATL 0.56 VI

CLKOUT = 1 mA

Clock Divider Control (Pin 9)

Setting Clock D riv er outpu t

frequency fCLKOUT=2.46 MHz VCLKDIV 00.2 V

Setting Clock D riv er outpu t

frequency fCLKOUT=615 kHz VCLKDIV V pin open

Input bias cu rrent CLKDIV ICLKDIV 30 µA VCLKDIV = VS

Input bias cu rrent CLKDIV ICLKDIV -20 µA VCLKDIV = 0 V

Crystal Oscillator Input (Pin 10)

Load capacitance CCOSCmax 5pF

Serial Resistance of the crys-

tal 100 Ωf = 9.84 MHz

Input inductance of the

COSC pin 3.4 4.4 5.4 µH f = 9.84 MHz

FSK Switch Output (Pin 11)

On resista nce RFSKOUT 220 ΩVFSKDTA = 0 V

On capacitance CFSKOUT 6pF VFSKDTA = 0 V

Off resistance RFSKOUT 10 kΩVFSKDTA = VS

Off capacitance CFSKOUT 1.5 pF VFSKDTA = VS

Reference

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Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25°C

Parameter Symbol Limit Values Unit T est Conditi ons

Min Typ Max

Power Amplifier Output (Pin 14)

Output Power2)

transformed to 50 Ohm POUT315 456dBm fOUT = 315 MHz

VFSEL = 0 V

Frequency Range Selection (Pin 15)

Transmit frequency 315 MHz VFSEL 00.5 V

Input bi as current FSE L IFSEL 30 µA VFSEL = VS

Input bi as current FSE L IFSEL -20 µA VFSEL = 0 V

Crystal Frequency Selection (Pin 16)

Crystal frequency 9.84 MHz VCSEL V p in ope n

Input bi as current CSEL ICSEL 50 µA VCSEL = VS

Input bi as current CSEL ICSEL -25 µA VCSEL = 0 V

1) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA

2) Power amplifier in overcritical C-operation.

Matching circuitry as used in the 50 Ohm-Output Testboard.

Tolerances of the passive elements not taken into account.

Reference

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5.3.2 AC/DC Characteristics at 2.1 V ... 4.0 V, -40°C ... +125°C

Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -40°C ... +125°C

Parameter Symbol Limit Values Unit Test Condit ions

Min Typ Max

Current consumption

Power down mode IS PDWN 4µA V (Pins 1, 6, and 7)

< 0.2 V

PLL enable mode IS PLL_EN 3.5 4.6 mA

Transmit mo de IS TRANSM 79.5mA Load tank see

Figure 4-1 and 4-2

Power Down Mode Control (Pin 1)

Power down mode VPDWN 00.5 VV

ASKDTA < 0.2 V

VFSKDTA < 0.2 V

PLL enable mode VPDWN 1.5 VSVV

ASKDTA < 0.5 V

Transmit mo de VPDWN 1.5 VSVV

ASKDTA > 1.5 V

Input bi as current PDWN IPDWN 38 µA VPDWN = VS

Low Power Detect Output (Pin 2)

Internal pull up current I LPD1 30 µA VS = 2.3 V ... VS

Input current low voltage I LPD2 0.5 mA VS = 1.9 V ... 2.1 V

Loop Filter (Pin 4)

VCO tuning voltag e VLF VS - 1.85 VS - 0.45 Vf

VCO = 630 MHz

Output frequency range 1)

315 MHz-band fOUT, 315 311 315 317 MHz VFSEL = 0 V

fOUT = fVCO / 2

ASK Modulation Data Input (Pin 6)

ASK Transmit disabled VASKDTA 00.5 V

ASK Transmit enabled VASKDTA 1.5 VSV

Input bias current ASKDTA IASKDTA 33 µA VASKDTA = VS

Input bias current ASKDTA IASKDTA -20 µA VASKDTA = 0 V

ASK data rate fASKDTA 20 kHz

1) The output-frequency range can be increased by limiting the temperature and supply voltage

range.

Minimum fOUT − 1 MHz => Minimum Tamb + 10°C

Maximum fOUT + 1 MHz => Maximum Tamb − 10°C

Maximum fOUT + 1 MHz => Minimum VS + 50 mV, max. + 20 MHz.

Reference

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Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -40°C ... +125°C

Parameter Symbol Limit Values Unit Test Conditions

Min Typ Max

FSK Modulation Data Input (Pin 7)

FSK Switch on VFSKDTA 00.5 V

FSK Switch off VFSKDTA 1.5 VSV

Input bias current FSKDTA IFSKDTA 35 µA VFSKDTA = VS

Input bias current FSKDTA IFSKDTA -20 µA VFSKDTA = 0 V

FSK data rate fFSKDTA 20 kHz

Clock Driver Output (Pin 8)

Output current (High) ICLKOUT 5µA VCLKOUT = VS

Saturation Voltage (Low)1) VSATL 0.5 VI

CLKOUT = 0.6 mA

Clock Divider Control (Pin 9)

Setting Clock D riv er outpu t

frequency fCLKOUT=2.46 MHz VCLKDIV 00.2 V

Setting Clock D riv er outpu t

frequency fCLKOUT=615 kHz VCLKDIV V pin open

Input bias cu rrent CLKDIV ICLKDIV 30 µA VCLKDIV = VS

Input bias cu rrent CLKDIV ICLKDIV -20 µA VCLKDIV = 0 V

Crystal Oscillator Input (Pin 10)

Load capacitance CCOSCmax 5pF

Serial Resistance of the crys-

tal 100 Ωf = 9.84 MHz

Input inductance of the

COSC pin 3.2 4.6 6.3 µH f = 9.84 MHz

FSK Switch Output (Pin 11)

On resista nce RFSKOUT 280 ΩVFSKDTA = 0 V

On capacitance CFSKOUT 6pF VFSKDTA = 0 V

Off resistance RFSKOUT 10 kΩVFSKDTA = VS

Off capacitance CFSKOUT 1.5 pF VFSKDTA = VS

1) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA

Reference

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Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -40°C ... +125°C

Parameter Symbol Limit Values Unit Test Conditions

Min Typ Max

Power Amplifier Output (Pin 14)

Output Power 1) at 315 MHz

transformed to 50 Ohm.

VFSEL = 0 V

POUT, 315 -0.5 2.2 dBm VS = 2.1 V

POUT, 315 0.5 57dBm VS = 3.0 V

POUT, 315 1.5 7.4 dBm VS = 4.0 V

Frequency Range Selection (Pin 15)

Transmit frequency 315 MHz VFSEL 00.5 V

Input bi as current FSE L IFSEL 35 µA VFSEL = VS

Input bi as current FSE L IFSEL -20 µA VFSEL = 0 V

Crystal Frequency Selection (Pin 16)

Crystal frequency 9.84 MHz VCSEL V pin ope n

Input bi as current CSEL ICSEL 55 µA VCSEL = VS

Input bi as current CSEL ICSEL -25 µA VCSEL = 0 V

1) Matching circuitry as used in the 50 Ohm-Output Testboard.

Tolerances of the passive elements not taken into account.

Range @ 2.1 V, +25°C: 2.2 dBm +/- 0.7 dBm

Typ. temperature dependency at 2.1 V: +0.3 dBm@-40°C and -1.4 dBm@+125°C, reference +25°C

Range @ 3.0 V, +25°C: 5.0 dBm +/- 1.0 dBm

Typ. temperature dependency at 3.0 V: +0.4 dBm@-40°C and -1.9 dBm@+125°C, reference +25°C

Range @ 4.0 V, +25°C: 7,4 dBm +/- 2.0 dBm

Typ. temperature dependency at 4.0 V: +0.6 dBm@-40°C and -3.1 dBm@+125°C, reference +25°C

A smaller load impedance reduces the supply-voltage dependency.

A higher load impedance reduces the temperature dependency.