Standard Products UT8Q512K32E 16 Megabit RadTolerant SRAM MCM Data Sheet June 28, 2011 INTRODUCTION The UT8Q512K32E RadTolerant product is a high-performance 2M byte (16Mbit) CMOS static RAM multi-chip module (MCM), organized as four individual 524,288 x 8 bit SRAMs with a common output enable. Memory expansion is provided by an active LOW chip enable (En), an active LOW output enable (G), and three-state drivers. This device has a powerdown feature that reduces power consumption by more than 90% when deselected. FEATURES 25ns maximum (3.3 volt supply) address access time MCM contains four (4) 512Kx8 industry-standard asynchronous SRAMs; the control architecture allows operation as 8, 16, 24 or 32-bit data width TTL compatible inputs and output levels, three-state bidirectional data bus Typical radiation performance - Total dose: 50krads - SEL Immune >110 MeV-cm2/mg - SEU LETTH(0.25) = >52 MeV-cm2/mg - Saturated Cross Section , 2.8E-8 cm2/bit - <1.1E-9 errors/bit-day, Adams 90% geosynchronous heavy ion Writing to each memory is accomplished by taking chip enable (En) input LOW and write enable (Wn) inputs LOW. Data on the eight I/O pins (DQ0 through DQ7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip enable (En) and output enable (G) LOW while forcing write enable (Wn) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. Packaging: - 68-lead dual cavity ceramic quad flatpack (CQFP) (11.0 grams) The input/output pins are placed in a high impedance state when the device is deselected (En HIGH), the outputs are disabled (G HIGH), or during a write operation (En LOW and Wn LOW). Perform 8, 16, 24 or 32 bit accesses by making Wn along with En a common input to any combination of the discrete memory die. Standard Microcircuit Drawing 5962-01533 - QML Q and Vcompliant part E3 W3 E2 W2 E1 W1 W0 E0 A(18:0) G 512K x 8 512K x 8 DQ(31:24) or DQ3(7:0) DQ(23:16) or DQ2(7:0) 512K x 8 DQ(15:8) or DQ1(7:0) Figure 1. UT8Q512K32E SRAM Block Diagram 1 512K x 8 DQ(7:0) or DQ0(7:0) DEVICE OPERATION NC A0 A1 A2 A3 A4 A5 E2 VSS E3 W0 A6 A7 A8 A9 A10 VDD The UT8Q512K32E has three control inputs called Chip Enable (En), Write Enable (Wn), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). En Chip Enable controls device selection, active, and standby modes. Asserting En enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. Wn controls read and write operations. During a read cycle, G must be asserted to enable the outputs. 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 1 2 3 4 5 Top View 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 DQ0(2) DQ1(2) DQ2(2) DQ3(2) DQ4(2) DQ5(2) DQ6(2) DQ7(2) VSS DQ0(3) DQ1(3) DQ2(3) DQ3(3) DQ4(3) DQ5(3) DQ6(3) DQ7(3) Table 1. Device Operation Truth Table VDD A11 A12 A13 A14 A15 A16 E0 G E1 A17 W1 W2 W3 A18 NC NC DQ0(0) DQ1(0) DQ2(0) DQ3(0) DQ4(0) DQ5(0) DQ6(0) DQ7(0) VSS DQ0(1) DQ1(1) DQ2(1) DQ3(1) DQ4(1) DQ5(1) DQ6(1) DQ7(1) G Wn En I/O Mode Mode X1 X 1 3-state Standby X 0 0 Data in Write 1 1 0 3-state Read2 0 1 0 Data out Read Figure 2. 25ns SRAM Pinout (68) Notes: 1. "X" is defined as a "don't care" condition. 2. Device active; outputs disabled. PIN NAMES READ CYCLE A(18:0) DQn(7:0) En Address Data Input/Output Chip Enable Wn Write Enable G Output Enable VDD Power VSS Ground A combination of Wn greater than VIH (min) and En less than VIL (max) defines a read cycle. Read access time is measured from the latter of Chip Enable, Output Enable, or valid address to valid data output. SRAM Read Cycle 1, the Address Access in figure 4a, is initiated by a change in address inputs while any chip are enabled with G asserted and Wn deasserted. Valid data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as Chip Enable and Output Enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV). SRAM read Cycle 2, the Chip Enable - Controlled Access in figure 4b, is initiated by En going active while G remains asserted, Wn remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0). SRAM read Cycle 3, the Output Enable - Controlled Access in figure 4c, is initiated by G going active while En is asserted, Wn is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied. 2 WRITE CYCLE TYPICAL RADIATION HARDNESS A combination of Wn less than VIL(max) and En less than VIL(max) defines a write cycle. The state of G is a "don't care" for a write cycle. The outputs are placed in the high-impedance state when either G is greater than VIH(min), or when Wn is less than VIL(max). The UT8Q512K32E SRAM incorporates features which allows operation in a limited radiation environment. Table 2. Radiation Hardness Design Specifications1 Write Cycle 1, the Write Enable-controlled Access in Figure 5a, is defined by a write terminated by Wn going high, with En still active. The write pulse width is defined by tWLWH when the write is initiated by Wn, and by tETWH when the write is initiated by En. Unless the outputs have been previously placed in the highimpedance state by G, the user must wait tWLQZ before applying data to the nine bidirectional pins DQ(7:0) to avoid bus contention. Total Dose 50 krad(Si) Heavy Ion Error Rate2 <1.1E-9 Errors/Bit-Day Notes: 1. The SRAM will not latchup during radiation exposure under recommended operating conditions. 2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of Aluminum. Write Cycle 2, the Chip Enable-controlled Access in Figure 5b, is defined by a write terminated by the latter of En going inactive. The write pulse width is defined by tWLEF when the write is initiated by Wn, and by tETEF when the write is initiated by the En going active. For the Wn initiated write, unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention. 3 ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS) SYMBOL PARAMETER LIMITS VDD DC supply voltage -0.5 to 7.0V VI/O Voltage on any pin -0.5 to 7.0V TSTG Storage temperature -65 to +150C PD Maximum power dissipation TJ Maximum junction temperature2 +150C Thermal resistance, junction-to-case 10C/W DC input current 10 mA JC II 1.0W (per byte) Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDD Positive supply voltage 3.0 to 3.6V TC Case temperature range (W) Screen - 40C to 105C VIN DC input voltage 0V to VDD 4 DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* -40C to +105C (VDD = 3.3V + 0.3V) SYMBOL PARAMETER CONDITION MIN MAX VIH High-level input voltage (TTL) VIL Low-level input voltage (TTL) 0.8 V VOL1 Low-level output voltage IOL = 6mA, VDD = 3.0V (TTL) 0.4 V VOL2 Low-level output voltage IOL = 200A,VDD = 3.0V (CMOS) 0.08 V VOH1 High-level output voltage IOH = -4mA,VDD = 3.0V (TTL) VOH2 High-level output voltage IOH = 200A,VDD = 3.0V (CMOS) CIN1 Input capacitance = 1MHz @ 0V 45 pF CIO1 Bidirectional I/O capacitance = 1MHz @ 0V 25 pF IIN Input leakage current VIN = VDD and VSS, VDD = VDD (max) -2 2 A IOZ Three-state output leakage current VO = VDD and VSS VDD = VDD (max) G = VDD (max) -2 2 A Short-circuit output current VDD = VDD (max), VO = VDD VDD = VDD (max), VO = 0V -90 90 mA IDD(OP) Supply current operating @ 1MHz (per byte) Inputs: VIL = 0.8V, VIH = 2.0V IOUT = 0mA VDD = VDD (max) 40 mA IDD1(OP) Supply current operating @40MHz (per byte) Inputs: VIL = 0.8V, VIH = 2.0V IOUT = 0mA VDD = VDD (max) 70 mA IDD2(SB)4 Supply current standby @0MHz (per byte) Inputs: VIL = VSS IOUT = 0mA E1 = VDD - 0.5, VDD = VDD (max) VIH = VDD - 0.5V -40C & 25C 9 mA 105C 24 mA IOS2, 3 2.0 UNIT Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 4. Post-radiation limit based off of high temperature limit. 5 V 2.4 V VDD -.010 V AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)* -40C to +105C (VDD = 3.3V + 0.3V) SYMBOL PARAMETER MAX MIN UNIT tAVAV1 Read cycle time tAVQV Read access time tAXQX2 Output hold time 3 ns tGLQX2 G-controlled Output Enable time 3 ns tGLQV G-controlled Output Enable time (Read Cycle 3) 10 ns tGHQZ2 G-controlled output three-state time 10 ns tETQX2,3 En-controlled Output Enable time tETQV3 tEFQZ1,2,4 25 ns 25 3 ns ns En-controlled access time 25 ns En-controlled output three-state time 10 ns Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Functional test. 2. Three-state is defined as a 500mV change from steady-state output voltage. 3. The ET (chip enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters. 4. The EF (chip enable false) notation refers to the rising edge of En. SEU immunity does not affect the read parameters. High Z to Active Levels Active to High Z Levels VH - 300mV VLOAD + 300mV } VLOAD { { } VLOAD - 300mV VL + 300mV Figure 3. 3.3-Volt SRAM Loading 6 tAVAV A(18:0) DQn(7:0) Previous Valid Data Valid Data tAVQV tAXQX Assumptions: 1. En and G < VIL (max) and Wn > VIH (min) Figure 4a. SRAM Read Cycle 1: Address Access A(18:0) En tETQV tETQX tEFQZ DQn(7:0) DATA VALID Assumptions: 1. G < VIL (max) and Wn > VIH (min) Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access tAVQV A(18:0) tGHQZ tGLQX DATA VALID Qn(7:0) tGLQV ssumptions: En < VIL (max) and Wn > VIH (min) Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access 7 AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)* -40C to +105C (VDD = 3.3V + 0.3V) SYMBOL PARAMETER MIN MAX UNIT tAVAV1 Write cycle time 25 ns tETWH Chip Device Enable to end of write 20 ns tAVET Address setup time for write (En - controlled) 0 ns tAVWL Address setup time for write (Wn - controlled) 0 ns tWLWH Write pulse width 20 ns tWHAX Address hold time for write (Wn - controlled) 0 ns tEFAX Address hold time for Chip Device Enable (En - controlled) 0 ns tWLQZ2 Wn - controlled three-state time 10 tWHQX2 Wn - controlled Output Enable time 4 ns tETEF Chip Device Enable pulse width (En - controlled) 20 ns tDVWH Data setup time 15 ns tWHDX Data hold time 2 ns tWLEF Chip Device Enable controlled write pulse width 20 ns tDVEF Data setup time 15 ns tEFDX Data hold time 2 ns tAVWH Address valid to end of write 20 ns tWHWL1 Write disable time 5 ns Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Functional test performed with outputs disabled (G high). 2. Three-state is defined as 500mV change from steady-state output voltage. 8 ns A(18:0) tAVAV2 En tAVWH tETWH tWHWL Wn tWLWH tAVWL tWHAX Qn(7:0) tWLQZ Dn(7:0) tWHQX APPLIED DATA Assumptions: 1. G < VIL (max). If G > VIH (min) then Qn(7:0) will be in three-state for the entire cycle. 2. G high for tAVAV cycle. tDVWH tWHDX Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access 9 tAVAV3 A(18:0) tETEF tAVET tEFAX En or tAVET En Wn tETEF tEFAX tWLEF Dn(7:0) APPLIED DATA tWLQZ tDVEF Qn(7:0) tEFDX Assumptions & Notes: 1. G < VIL (max). If G > VIH (min) then Qn(7:0) will be in three-state for the entire cycle. 2. Either En scenario above can occur. 3. G high for tAVAV cycle. Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access CMOS 90% VDD-0.05V 10% 0.5V 10% < 5ns < 5ns Input Pulses Notes: 1. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = VDD/2). Figure 6. AC Test Loads and Input Waveforms 10 DATA RETENTION MODE VDR > 2.0V VDD 3.0V 3.0V tR tEFR EN VDD = VDR Figure 7. Low VDD Data Retention Waveform DATA RETENTION CHARACTERISTICS (Pre-Radiation) *(VDD2 = VDD2 (min), 1 Sec DR Pulse) SYMBOL VDR IDDR 1 tEFR tR1 1 PARAMETER VDD1 for data retention Data retention current (per byte) TEMP MINIMUM MAXIMUM UNIT -- 2.0 -- V -40oC & 25oC -- 9 mA 24 mA 105oC Chip deselect to data retention time -- 0 -- ns Operation recovery time -- tAVAV -- ns Notes: *Post-radiation performance guaranteed at 25oC per MIL-STD-883 Method 1019. 1. E n= VDR all other inputs = VDR or VSS 11 PACKAGING Figure 8. 68-Lead Ceramic Quad Flatpack Notes: 1. All exposed metallized areas are gold plated over nickel per MIL-PRF-38535. 2. The lids are electrically connected to VSS. 3. Packages may be shipped with repaired leads as shown. 4. Coplanarity requirements do not apply in repaired area. 5. Letter designations are to cross reference to MIL-STD-1835. 6. Lead true position tolerances and coplanarity are not measured. 7. Capacitor pads are sized to fit CDR32 (1206) capacitors. 12 ORDERING INFORMATION 512K32 16Megabit SRAM MCM: UT8Q512K32E - * * * Lead Finish: (note 1) (C) = Gold Screening: (Notes 2 & 3) (P) = Prototype flow (W) = -40oC to +105oC Package Type: (S) = 68-lead dual cavity CQFP Device Type: - = 25ns access time, 3.3V operation Aeroflex Core Part Number Notes: 1. Gold lead finish only. 2. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at 25oC. Radiation neither tested nor guaranteed. 3. Extended Industrial Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -40C to +105C. Radiation neither tested nor guaranteed. 13 512K32 16Megabit SRAM MCM: SMD 14 5962 - 01533 ** * * * Lead Finish: (Note 1) (C) = Gold Case Outline: (Y) = 68-lead dual cavity CQFP Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type 02 = 25 ns access time, 3.3V operation, (-40oC to +105oC) Drawing Number: 01533 Total Dose: (Note 2) (D) = 1E4 (10krad(Si)) (P) = 3E4 (30krad(Si)) (L) = 5E4 (50krad(Si)) Federal Stock Class Designator: No Options Notes: 1. Lead finish is "C" (Gold) only. 2.Total dose radiation must be specified when ordering. 15 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com Aeroflex Colorado Springs, Inc., reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 16 Aeroflex Colorado Springs Application Note AN-MEM-002 Low Power SRAM Read Operations Table 1: Cross Reference of Applicable Products Manufacturer Part Number SMD # Device Type Internal PIC Number:* 4M Asynchronous SRAM UT8R128K32 5962-03236 01 & 02 WC03 4M Asynchronous SRAM UT8R512K8 5962-03235 01 & 02 WC01 16M Asynchronous SRAM UT8CR512K32 5962-04227 01 & 02 MQ08 16M Asynchronous SRAM UT8ER512K32 5962-06261 05 & 06 WC04/05 4M Asynchronous SRAM UT8Q512E 5962-99607 05 & 06 WJ02 4M Asynchronous SRAM UT9Q512E 5962-00536 05 & 06 WJ01 16M Asynchronous SRAM UT8Q512K32E 5962-01533 02 & 03 QS04 16M Asynchronous SRAM UT9Q512K32E 5962-01511 02 & 03 QS03 32M Asynchronous SRAM UT8ER1M32 5962-10202 01 - 04 QS16/17 64M Asynchronous SRAM UT8ER2M32 5962-10203 01 - 04 QS09/10 128M Asynchronous SRAM UT8ER4M32 5962-10204 01 - 04 QS11/12 40M Asynchronous SRAM UT8R1M39 5962-10205 01 & 02 QS13 80M Asynchronous SRAM UT8R2M39 5962-10206 01 & 02 QS14 160M Asynchronous SRAM UT8R4M39 5962-10207 01 & 02 QS15 Product Name: * PIC = Aeroflex's internal Product Identification Code 1.0 Overview The purpose of this application note is to discuss the Aeroflex SRAMs low power read architecture and to inform users of the affects associated with the low power read operations. 2.0 Low Power Read Architecture The aforementioned Aeroflex designed SRAMs all employ an architecture which reduces power consumption during read accesses. The architecture internally senses data only when new data is requested. A request for new data occurs anytime the chip enable device pin is asserted, or any of the device address inputs transition states while the chip enable is asserted. A trigger is generated and sent to the sensing circuit anytime a request for new data is observed. Since several triggers could occur simultaneously, these triggers are wire-ORed to result in a single sense amplifier activity for the read request. This design method results in less power consumption than designs that continually sense data. Aeroflex's low power SRAMs listed above activate the sensing circuit for approximately 5ns whenever and access is requested, thereby, significantly reducing active power. Creation Date: 8/19/11 Page 1 of 5 Modification Date: 4/24/13 Aeroflex Colorado Springs Application Note AN-MEM-002 2.1 The SRAM Read Cycles. The data sheets for all the devices noted in Table #1 discuss three methods for performing a read operation. The two most common methods for reading data are an Address Access and a Chip Enabled-Controlled Access. The third access discussed is the Output Enable-Controlled Access. The sequence at which control lines and address inputs are toggled determines which cycle is considered relevant. As discussed in section 2.0, an assertion of chip enable or any address transition while chip enable is asserted, initiates a read cycle. If the device chip enable is asserted prior to any address input transitions, then the read access is considered an Address Access. By keeping the device enabled and repeatedly switching address locations, the user retrieves all data of interest. A Chip Enable-Controlled Access occurs when the address signals are stable prior to asserting the chip enable. The Output Enabled-Controlled Access requires that either an Address Access or Chip Enable-Controlled Access has already been performed and the data is waiting for the Output Enable pin to assert, driving data to the device I/O pins. The subsequent read cycle verbiage and diagrams are based on the Aeroflex UT8R512K8 data sheet. The number of control, input, and I/O pins will vary across the products listed in Table 1. The basic design family functionality for read operations is common among all the devices. 2.1.0 Address Access Read Cycle The Address Access is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as chip enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV). tAVAV A(18:0) DQ(7:0) Previous Valid Data Valid Data tAVQV Assumptions: 1. E1 and G < VIL (max) and E2 and W > VIH (min) tAXQX Note: No time references are relevant with respect to Chip Enable(s). Chip Enable(s) is assumed to be asserted. SRAM Read Cycle 1: Address Access Creation Date: 8/19/11 Page 2 of 5 Modification Date: 4/24/13 Aeroflex Colorado Springs Application Note AN-MEM-002 2.1.1 Chip Enable-Controlled Read Cycle The Chip Enable-controlled Access is initiated by E1 and E2 going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0). A(18:0) E1 low or E2 high tETQV tETQX DQ(7:0) tEFQZ DATA VALID Assumptions: 1. G < VIL (max) and W > VIH (min) Note: No specification is given for address set-up time with respect to chip enable assertion. The read cycle description states that addresses are to remain stable for the entire cycle. Address set-up time relative to chip enable is assumed to be 0ns minimum. SRAM Read Cycle 2: Chip Enable Access 2.1.1 Output Enabled-Controlled Read Cycle The Output Enable-controlled Access is initiated by G going active while E1 and E2 are asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied. tAVQV A(18:0) G tGHQZ tGLQX DATA VALID DQ(7:0) tGLQV Assumptions: 1. E1 < VIL (max) , E2 > and W > VIH (min) SRAM Read Cycle 3: Output Enable Access 3.0 Low Power Read Architecture Timing Consideration The low power read architecture employed by Aeroflex designed SRAMs results in significant power reduction, especially in applications with longer than minimum read cycle times. However, this type of architecture is responsive to excessive input signal skew when device addressing and chip enable assertion occur simultaneously. Signal skew of greater than 4-5ns between all of the read triggering activities is sufficient to start another read cycle. Creation Date: 8/19/11 Page 3 of 5 Modification Date: 4/24/13 Aeroflex Colorado Springs Application Note AN-MEM-002 3.1 Simultaneous Control and Address Switching Simultaneous switching of controls and address pins, alone, is not a problem; excessive skew between them is the concern. Consider the application where several SRAM devices are connected to the same memory bus. The address bus is commonly connected to all the devices, but the chip enable pin is singularly connected to each individual SRAM. This configuration results in a loading difference between the address inputs and the chip enable. This lightly loaded chip enable propagates to the memory more quickly than the heavily loaded address lines. The oscilloscope capture of Figure #1 is the actual timing of an application which had intermittent data errors due to address transitions lagging chip enable. Address Signal (Ax) Chip Enable (/E) Timing shown from VIL (yellow trace /CS) and VIH (pink for address signal) as delta X = 6ns. Even at actual internal gate switching point (~ VDD/2), the skew is still around 6ns. Figure #1 SRAM Signal Capture The signal transitions in the scope plot of Figure #1 appear to be fairly coincidental. A closer look however, reveals the chip enable signal actually starts and reaches VIL approximately 6ns before the address signal reaches VIH. Even at one half VDD (closer to actual logical gate switching of the inputs), the delta in signal times is still approximately 6ns. Simultaneous switching of controls and address inputs is not recommended for a couple of reasons. The first is the previously described signal skew sensitivity between controls and/or address inputs. The second reason is that activating all the controls and address inputs simultaneously results in peak instantaneous current consumption. This condition causes maximum strain to the power decoupling. Chip Enable activates address decoding circuits, address switching introduces input buffer switching current, and output enable assertion turns on all the device output drivers. Peforming all three simultaneously results in worst case transient current demand by the memory. 3.1.0 Technical Overview of Skew Sensitivity Recall from section 2.0 that any activity requesting new data causes a read trigger. The triggers are wire-ORed together. In order to meet the faster access times demanded by today's applications, the ORed trigger only exists during the first 4-5ns of the read cycle. Since the slowest of the address transitions occurs more than 5ns after the initiation of the read activity, a second read activity is initiated. The sensing circuit does not have time to normalize before the second read activity has started. For this reason a Chip Enable-Controlled read cycle requires that address inputs remain stable for the entire cycle. Infrequent and random sensing errors can result if the bit columns are continually pulled to one state then quickly requested to sense the opposite state. Another effect of the low power read architecture that differs from previous generation designs (those that continually sense for data) is that the bit line will not be sensed again until another read triggering event occurs. If another read trigger event (chip enable assertion and/or address change) does no occur for a particular address, the incorrect data remains at the outputs. Creation Date: 8/19/11 Page 4 of 5 Modification Date: 4/24/13 Aeroflex Colorado Springs Application Note AN-MEM-002 4.0 Summary and Conclusion The Aeroflex SRAMs in Table #1 all employ a low power consumption read architecture. Power is conserved by sensing data only when new data is requested. A request occurs anytime chip enable is asserted or any address input signal transitions while chip enable is asserted. The data sheets for the SRAMs listed in Table #1 do not explicitly define the case of simultaneous switching of address and control signals during read operations. Data sheet read cycle descriptions indicate that control inputs are established prior to address changes, and address inputs are stable prior to control assertions. Simultaneous switching of addresses and controls is tolerable, when the skew between all input signals is < 4ns. For designs that must employ the simultaneous activation of address and control signals, two important issues should be considered by the designer. The first is the input signal skew sensitivity of the low power read architecture discussed by this application note. The second is the instantaneous current consumption that results from simultaneous access methods. Aeroflex recommends the use of only one read access method at a time. If multiple read accesses (simultaneous chip enable assertion and address switching) cannot be avoided, then Aeroflex recommends that the chip enable signal be delayed until all addresses have completed transitions. Creation Date: 8/19/11 Page 5 of 5 Modification Date: 4/24/13