1
FEATURES
25ns maximum (3.3 volt supply) address access time
MCM contains four (4) 512Kx8 industry-standard
asynchronous SRAMs; the control architecture allows
operation as 8, 16, 24 or 32-bit data width
TTL compatible inputs and output levels, three-state
bidirectional data bus
Typical radiation performance
- Total dose: 50krads
- SEL Immune >110 MeV-cm2/mg
- SEU LETTH(0.25) = >52 MeV-cm2/mg
- Saturated Cross Section , 2.8E-8 cm2/bit
- <1.1E-9 errors/bit-day , Adams 90% geosynchronous
heavy ion
Packaging:
- 68-lead dual cavity ceramic quad flatpack (CQFP)
(11.0 grams)
Standard Microcircuit Drawing 5962-01533
- QML Q and Vcompliant part
INTRODUCTION
The UT8Q512K32E RadTolerant product is a high-performance
2M byte (16Mbit) CMOS static RAM multi-chip module
(MCM), organized as four individual 524,288 x 8 bit SRAMs
with a common output enable. Memory expansion is provided
by an active LOW chip enable (En), an active LOW output
enable (G), and three-state drivers. This device has a power-
down feature that reduces power consumption by more than 90%
when deselected.
W riting to each memory is accomplished by taking chip enable
(En) input LOW and write enable (Wn) inputs LOW. Data on
the eight I/O pins (DQ0 through DQ7) is then written into the
location specified on the address pins (A0 through A18). Reading
from the device is accomplished by taking chip enable (En) and
output enable (G) LOW while forcing write enable (Wn) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
Perform 8, 16, 24 or 32 bit accesses by making Wn along with
En a common input to any combination of the discrete memory
die.
Standard Products
UT8Q512K32E 16 Megabit RadTolerant SRAM MCM
Data Sheet
June 28, 2011
512K x 8 512K x 8 512K x 8 512K x 8
DQ(31:24)
or
DQ3(7:0)
DQ(23:16)
or
DQ2(7:0)
DQ(15:8)
or
DQ1(7:0)
DQ(7:0)
or
DQ0(7:0)
G
A(18:0)
W3
E3 E2E1 E0
W2 W1W0
Figure 1. UT8Q512K32E SRAM Block Diagram
2
PIN NAMES
DEVICE OPERATION
The UT8Q512K32E has three control inputs called Chip Enable
(En), Write Enable (Wn), and Output Enable (G); 19 address
inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). En
Chip Enable controls device selection, active, and stand by
modes. Asserting En enables the device, causes IDD to rise to its
active value, and decodes the 19 address inputs to select one of
524,288 words in the memory. Wn controls read and write
operations. During a read cycle, G must be asserted to enable
the outputs.
Table 1. Device Operation Truth Table
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of Wn greater than VIH (min) and En less than
VIL (max) defines a read cycle. Read access time is measured
from the latter of Chip Enable, Output Enable, or valid address
to valid data output.
SRAM Read Cycle 1, the Address Access in figure 4a, is
initiated by a change in address inputs while any chip are enabled
with G asserted and Wn deasserted. Valid data appears on data
outputs DQ(7:0) after the specified tAVQV is satisf ied . Outputs
remain active throughout the entire cycl e. As long as Chip
Enable and Output Enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (tAVAV).
SRAM read Cycle 2, the Chip Enable - Controlled Access in
figure 4b, is initiated by En going active while G remains
asserted, Wn remains deasserted, and the addresses remain
stable for the entire cycle. After the specified tETQV is satisfied,
the eight-bit word addressed by A(18:0) is accessed and appears
at the data outputs DQ(7:0).
SRAM read Cycle 3, the Output Enable - Controlled Access in
figure 4c, is initiated by G going active while En is asserted, Wn
is deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
A(18:0) Address Wn Write Enable
DQn(7:0) Data Input/Output GOutput Enable
En Chip Enable VDD Power
VSS Ground
G Wn En I/O Mode Mode
X1X 1 3-state Standby
X 0 0 Data in Write
1 1 0 3-state Read2
0 1 0 Data out Read
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Top View
DQ0(0)
DQ1(0)
DQ2(0)
DQ3(0)
DQ4(0)
DQ5(0)
DQ6(0)
DQ7(0)
VSS
DQ0(1)
DQ1(1)
DQ2(1)
DQ3(1)
DQ4(1)
DQ5(1)
DQ6(1)
DQ7(1)
NC
A0
A1
A2
A3
A4
A5
E2
VSS
E3
W0
A6
A7
A8
A9
A10
VDD
VDD
A11
A12
A13
A14
A15
A16
E0
G
E1
A17
W1
W2
W3
A18
NC
NC
DQ0(2)
DQ1(2)
DQ2(2)
DQ3(2)
DQ4(2)
DQ5(2)
DQ6(2)
DQ7(2)
VSS
DQ0(3)
DQ1(3)
DQ2(3)
DQ3(3)
DQ4(3)
DQ5(3)
DQ6(3)
DQ7(3)
Figure 2. 25ns SRAM Pinout (68)
3
WRITE CYCLE
A combination of Wn less than VIL(max) and En less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than VIH(min), or when Wn is less
than VIL(max).
Write Cycle 1, the Write Enable-controlled Access in Figure 5a,
is defined by a write terminated by Wn going high, with En still
active. The write pulse width is defined by tWLWH when the write
is initiated by Wn, and by tETWH when the write is initiated by
En. Unless the outputs have been previously placed in the high-
impedance state by G, the user must wait tWLQZ before applying
data to the nine bidirectional pins DQ (7: 0) to avoid bus
contention.
W rite Cycle 2, the Chip Enable-controlled Access in Figure 5b,
is defined by a write terminated by the latter of En going inactive.
The write pulse width is defined by tWLEF when the write is
initiated by Wn, and by tETEF when the write is initiated by the
En going active. For the Wn initiated write, unless the out puts
have been previously placed in the high-impedance state by G,
the user must wait tWLQZ before applying data to the eight
bidirectional pins DQ(7:0) to avoid bus cont enti on.
TYPICAL RADIATION HARDNESS
The UT8Q512K32E SRAM incorporates features which allows
operation in a limited radiation environment.
Table 2. Radiation Hardness
Design Specifications1
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
Total Dose 50 krad(Si)
Heavy Ion
Error Rate2<1.1E-9 Errors/Bit-Day
4
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only , and functional operatio n of the device
at these or any other conditions beyon d limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS
VDD DC supply voltage -0.5 to 7.0V
VI/O Voltage on any pin -0.5 to 7.0V
TSTG Storage temperature -65 to +150C
PDMaximum power dissipation 1.0W (per byte)
TJMaximum junctio n temperature2+150C
JC Thermal resistance, junction-to-case 10C/W
IIDC input current ±10 mA
SYMBOL PARAMETER LIMITS
VDD Positive supply voltage 3.0 to 3.6V
TCCase temperature range (W) Screen - 40C to 105C
VIN DC input voltage 0V to VDD
5
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
-40C to +105C (VDD = 3.3V + 0.3V)
Notes:
* Post-radiation pe rfo rm ance guaranteed at 25C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. Post-radiation limit based off of high temperature limit.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltage (TTL) 2.0 V
VIL Low-level input voltage (TTL) 0.8 V
VOL1 Low-level output voltage IOL = 6mA, VDD = 3.0V (TTL) 0.4 V
VOL2 Low-level output voltage IOL = 200A,VDD = 3.0V (CMOS) 0.08 V
VOH1 High-level output voltage IOH = -4mA,VDD = 3.0V (TTL) 2.4 V
VOH2 High-level output voltage IOH = 200A,VDD = 3.0V (CMOS) VDD -.010 V
CIN1Input capacitance = 1MHz @ 0V 45 pF
CIO1Bidirectional I/O capacitance = 1MHz @ 0V 25 pF
IIN Input leakage current VIN = VDD and VSS, VDD = VDD (max) -2 2 A
IOZ Three-state output leakage current VO = VDD and VSS
VDD = VDD (max)
G = VDD (max)
-2 2 A
IOS2, 3 Short-circuit output current VDD = VDD (max), VO = VDD
VDD = VDD (max), VO = 0V
-90 90 mA
IDD(OP) Supply current operating
@ 1MHz
(per byte)
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
40 mA
IDD1(OP) Supply current operating
@40MHz
(per byte)
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
70 mA
IDD2(SB)4Supply current standby
@0MHz
(per byte)
Inputs: VIL = VSS
IOUT = 0mA
E1 = VDD - 0.5, VDD =
VDD (max)
VIH = VDD - 0.5V
-40C &
25C9mA
105C24mA
6
AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*
-40C to +105C (VDD = 3.3V + 0.3V)
Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019.
1. Functional test.
2. Three-state is defined as a 500mV change from steady-state output voltage.
3. The ET (chip enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters.
4. The EF (chip enable false) notation ref ers to the rising edge of En. SEU immunity does not affect the read parameters.
SYMBOL PARAMETER MIN MAX UNIT
tAVAV1Read cycle time 25 ns
tAVQV Read access time 25 ns
tAXQX2Output hold time 3ns
tGLQX2G-controlled Output Enable tim e 3ns
tGLQV G-controlled Output Enable time (Read Cycle 3) 10 ns
tGHQZ2G-controlled output three-state time 10 ns
tETQX2,3 En-controlled Output Enable time 3ns
tETQV3En-controlled access time 25 ns
tEFQZ1,2,4 En-controlled output th ree-state time 10 ns
{
{}
}
VLOAD + 300mV
VLOAD - 300mV
VLOAD
VH - 300mV
VL + 300mV
Active to High Z LevelsHigh Z to Active Levels
Figure 3. 3.3-Volt SRAM Loading
7
Assumptions:
1. En and G < VIL (max) and Wn > VIH (min)
A(18:0)
DQn(7:0)
Figure 4a. SRAM Read Cycle 1: Address Access
tAVAV
tAVQV
tAXQX
Previous Valid Data Valid Data
Assumptions:
1. G < VIL (max) and Wn > VIH (min)
A(18:0)
Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access
En
DATA VALID
tEFQZ
tETQV tETQX
DQn(7:0)
8
AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)*
-40C to +105C (VDD = 3.3V + 0.3V)
Notes:
* Post-radiation performan c e guaranteed at 25C per MIL-STD-883 Method 1019.
1. Functional test performed with outputs disab l ed (G high).
2. Three-state is defined as 500mV change from steady- state output voltage.
SYMBOL PARAMETER MIN MAX UNIT
tAVAV1Write cyc le time 25 ns
tETWH Chip Device Enable to end of write 20 ns
tAVET Address setup time for write (En - controlled) 0 ns
tAVWL Address setup time for write (Wn - controlled) 0 ns
tWLWH Write pulse width 20 ns
tWHAX Address hold time for write (Wn - controlled) 0 ns
tEFAX Address hold time for Chip Device Enable (En - controlled) 0 ns
tWLQZ2Wn - controlled three-state time 10 ns
tWHQX2Wn - controlled Output Enable time 4 ns
tETEF Chip Device Enable pulse width (En - controlled) 20 ns
tDVWH Data setup time 15 ns
tWHDX Data hold time 2 ns
tWLEF Chip Device Enable controlled write pulse width 20 ns
tDVEF Data setup time 15 ns
tEFDX Data hold time 2 ns
tAVWH Address valid to end of write 20 ns
tWHWL1Write disable time 5 ns
9
Assumptions:
1. G < VIL (max). If G > VIH (min) then Qn(7:0) will be
in three-state for the entire cycle.
2. G high for tAVAV cycle.
Wn
tAVWL
Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access
A(18:0)
Qn(7:0)
En
tAVAV2
Dn(7:0) APPLIED DATA
tDVWH tWHDX
tETWH
tWLWH tWHAX
tWHQX
tWLQZ
tAVWH
tWHWL
10
tEFDX
Assumptions & Notes:
1. G < VIL (max). If G > VIH (min) then Qn(7:0) will be in three-state for the entire cycle.
2. Either En scenario above can occur.
3. G high for tAVAV cycle.
A(18:0)
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access
Wn
En
Dn(7:0) APPLIED DATA
En
Qn(7:0) tWLQZ
tETEF
tWLEF
tDVEF
tAVAV3
tAVET
tAVET
tETEF
tEFAX
tEFAX
or
Notes:
1. Measurement of data output occu rs at the low to high or high to low
transition mid-point (i.e., CMOS input = VDD/2).
90%
Figure 6. AC Test Loads and Input Waveforms
Input Pulses
10%
< 5ns < 5ns
CMOS
0.5V
VDD-0.05V
10%
11
DATA RETENTION CHARACTERISTICS (Pre-Radiation) *(VDD2 = VDD2 (min), 1 Sec DR Pulse)
Notes:
*Post-radiation performance guaranteed at 25oC per MIL-STD-883 Method 1019.
1. E n= VDR all other inputs = VDR or VSS
VDD
DATA RETENTION MODE
tR
3.0V
3.0V VDR > 2.0V
Figure 7. Low VDD Data Retention Waveform
tEFR
EN VDD = VDR
SYMBOL PARAMETER TEMP MINIMUM MAXIMUM UNIT
VDR VDD1 for data retention -- 2.0 -- V
IDDR 1 Data retention current
(per byte) -40oC & 25oC
105oC
-- 9
24
mA
mA
tEFR1Chip deselect to data retention time -- 0 -- ns
tR1Operation recovery time -- tAVAV -- ns
12
PACKAGING
Figure 8. 68-Lead Ceramic Quad Flatpack
Notes:
1. All exposed metallized areas are gold plated over nickel per MIL-PRF-38535.
2. The lids are electrically connected to VSS.
3. Packages may be ship p ed w ith repaired leads as shown.
4. Coplanarity requirements do not apply in r epaired area.
5. Letter designations are to cross refer en c e to MIL-STD-1835.
6. Lead true position tolerances and coplanarity are not measured.
7. Capacitor pads are sized to fit CDR32 (1206) capacitors.
13
ORDERING INFORMATION
512K32 16Megabit SRAM MCM:
Device Type:
- = 25ns access time, 3.3V operation
Package Type:
(S) = 68-lead dual cavity CQFP
Screening: (Notes 2 & 3)
(P) = Prototype flow
(W) = -40oC to +105oC
Lead Finish: (note 1)
(C) = Gold
Notes:
1. Gold lead finish only.
2. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at 25oC. Radiation neither tested nor guaranteed.
3. Extended Industrial T emperature Range flow per Aeroflex Colorado Springs M anufacturing Flows Document. Devices are tested at -40C to +105C.
Radiation neither tested nor guaranteed.
UT8Q512K32E - * * *
Aeroflex Core Part Number
14
512K32 16Megabit SRAM MCM: SMD
15
5962 - 01533 ** ** *
Notes:
1. Lead finish is "C" (Gold) only.
2.Tota l dose radiation must be specified when orde ring.
Federal Stoc k Class Designator: No Options
Total Dose: (Note 2)
(D) = 1E4 (10krad(Si))
(P) = 3E4 (30krad(Si))
(L) = 5E4 (50krad(Si))
Drawing Number: 01533
Device Type
02 = 25 ns access time, 3.3V operation, (-40oC to +105oC)
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Case Outline:
(Y) = 68-lead dual cavity CQFP
Lead Finish: (Note 1)
(C) = Gold
16
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www.aeroflex.com info-ams@aeroflex.com
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Aeroflex Colorado Springs, Inc., reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights,
trademark rights, or any other of the intellectual rights of
Aeroflex or of third parties.
Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
Aeroflex Colorado Springs Application Note AN-MEM-002
Creation Date: 8/19/11 Page 1 of 5 Modification Date: 4/24/ 13
Low Power SRAM Read Operations
* PIC = Aeroflex’s internal Product Identification Code
1.0 Overview
The purpose of this application note is to discuss the Aeroflex SRAMs low power read architecture and to inform users of the
affects associa ted with the low pow e r read operations.
2.0 Low Power Read Architecture
The aforementioned Aeroflex designed SRAMs all employ an architecture which reduces power consump tion during read
accesses. The architecture internally senses data only when new data is requested. A request for new data occurs anytime the
chip enable device pin is asserted, or any of the device address inputs transition states while the chip enable is asserted. A trig-
ger is generated and sent to the sensing circuit anytime a request for new data is observed. Since several triggers could occur
simultaneously, these triggers are wire-ORed to result in a single sense amplifier activity for the read request. This design
method results in less power consumption than designs that continually sense data. Aeroflex’ s low power SRAMs listed above
activate the sensing circuit for approximately 5ns whenever and access is requested, thereby, significantly reducing active
power.
Table 1: Cross Reference of Applicable Products
Product Name: Manufacturer
Part Number SMD # Device Type Internal PIC
Number:*
4M Asynchronous SRAM UT8R128K32 5962-03236 01 & 02 WC03
4M Asynchronous SRAM UT8R512K8 5962-03235 01 & 02 WC01
16M Asynchronous SRAM UT8CR512K32 5962-04227 01 & 02 MQ08
16M Asynchronous SRAM UT8ER512K32 5962-06261 05 & 06 WC04/05
4M Asynchronous SRAM UT8Q512E 5962-99607 05 & 06 WJ02
4M Asynchronous SRAM UT9Q512E 5962-00536 05 & 06 WJ01
16M Asynchronous SRAM UT8Q512K32E 5962-01533 02 & 03 QS04
16M Asynchronous SRAM UT9Q512K32E 5962-01511 02 & 03 QS03
32M Asynchronous SRAM UT8ER1M32 5962-10 202 01 - 04 QS16/17
64M Asynchronous SRAM UT8ER2M32 5962-10 203 01 - 04 QS09/10
128M Asynchronous SRAM UT8ER4M32 5962-10204 01 - 04 QS11/12
40M Asynchronous SRAM UT8R1M39 5962-10 205 01 & 02 QS13
80M Asynchronous SRAM UT8R2M39 5962-10 206 01 & 02 QS14
160M Asynchronous SRAM UT8R4M39 5962-10207 01 & 02 QS15
Aeroflex Colorado Springs Application Note AN-MEM-002
Creation Date: 8/19/11 Page 2 of 5 Modification Date: 4/24/ 13
2.1 The SRAM Read Cycles.
The data sheets for all the devices noted in Table #1 discuss three methods for performing a read operation. The two most com-
mon methods for reading data are an Address Access and a Chip Enabled-Controlled Access. The third access discussed is the
Output Enable-Controlled Access. The sequence at which control lines and address inputs are toggled determines which cycle
is considered relevant. As discussed in section 2.0, an assertion of chip enable or any address transition while chip enable is
asserted, initiates a read cycle. If the device chip enable is asserted prior to any address input transitions, then the read access
is considered an Address Access. By keeping the device enabled and repeatedly switching address locations, the user retrieves
all data of interest. A Chip Enable-Controlled Access occurs when the address signals are stable prior to asserting the chip
enable. The Output Enabled-Controlled Access requires that either an Address Access or Chip Enable-Controlled Access has
already been performed and the data is waiting for the Output Enable pin to assert, driving data to the device I/O pins.
The subsequent read cycle verbiage and diagrams are based on the Aeroflex UT8R512K8 data sheet. The number of control,
input, and I/O pins will vary across the products listed in Table 1. The basic design family functionality for read operations is
common among all the devices.
2.1.0 Address Access Read Cycle
The Address Access is initiated by a change in address inputs while the chip is enabled with G asserted and W deas serted. Valid
data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain activ e throughout the entire cycle.
As long as chip enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle
time (tAVAV).
Assumptions:
1. E1 and G < VIL (max) and E2 and W > VIH (min)
A(18:0)
DQ(7:0)
SRAM Read Cycle 1: Address Access
tAVAV
tAVQV
tAXQX
Previous Valid Data Valid Data
Note: No time references are relevant with respect to Chip Enable(s). Chip Enable(s) is assumed to be asserted.
Aeroflex Colorado Springs Application Note AN-MEM-002
Creation Date: 8/19/11 Page 3 of 5 Modification Date: 4/24/ 13
2.1.1 Chip Enable-Controlled Read Cycle
The Chip Enable-controlled Access is initiated by E1 and E2 going active while G remains asserted, W remains deasserted, and
the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0)
is accessed and appears at the data outputs DQ(7:0).
2.1.1 Output Enabled-Controlled Read Cycle
The Output Enable-controlled Access is initiated by G going active while E1 and E2 are asserted, W is deasserted, and the
addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied.
3.0 Low Power Read Architecture Timing Consideration
The low power read architecture employed by Aeroflex designed SRAMs results in significant power reduction, especially in
applications with longer than mini mum read cycle times. However, this type of architecture is responsi ve to excessive input
signal skew when device addressing and chip enable assertion occur simultaneously. Signal skew of greater than 4-5ns
between all of the read triggering activities is sufficient to start another read cycle.
Assumptions:
1. G < VIL (max) and W > VIH (min)
A(18:0)
SRAM Read Cycle 2: Chip Enable Access
E1 low or
E2 high
DATA VALID
tEFQZ
tETQV tETQX
DQ(7:0)
Note: No specification is given for address set-up time with respect to chip enable assertion. The read cycle descri ption states that
addresses are to remain stable for the entire cycle. Address set-up time relative to chip enable is assumed to be 0ns minimum.
SRAM Read Cycle 3: Output Enable Access
A(18:0)
DQ(7:0)
G
tGHQZ
Assumptions:
1. E1 < VIL (max) , E2 > and W > VIH (min)
tGLQV
tGLQX
tAVQV
DATA VALID
Aeroflex Colorado Springs Application Note AN-MEM-002
Creation Date: 8/19/11 Page 4 of 5 Modification Date: 4/24/ 13
3.1 Simultaneous Control and Address Switching
Simultaneous switching of controls and address pins, alone, is not a problem; excessive skew between them is the concern.
Consider the application where several SRAM devices are connected to the same memory bus. The address bus is commonly
connected to all the devices, but the chip enable pin is singularly connected to each individual SRAM. This configuration
results in a loading difference between the address inputs and the chip enable. This lightly loaded chip enable propagates to the
memory more quickly than the heavily loaded address lines. The oscilloscope capture of Figure #1 is the actual timing of an
application which had intermittent data errors due to address transitions lagging chip enable.
Figure #1 SRAM Signal Capture
The signal transitions in the scope plot of Figure #1 appear to be fairly coincidental. A closer look however, reveals the chip
enable signal actually starts and reaches VIL approximately 6ns before the address signal reaches VIH. Even at one half VDD
(closer to actual logical gate switch ing of the inp uts), the del ta in signal tim es is still approximately 6ns.
Simultaneous switching of controls and address inputs is not recommended for a couple of reasons. The first is the previously
described signal skew sensitivity between controls and /or address inputs. The second reason is that activating all the controls
and address inputs simultaneously result s in peak instantaneous current consumpti on. This condition causes maximum strain
to the power decoupling. Chip Enable activates address decoding circuits, address switching introduces input buffer switching
current, and output enable assertion turns on all the device output drivers. Peforming all three simultaneously results in worst
case transient current demand by the memory.
3.1.0 Technical Overview of Skew Sensitivity
Recall from section 2.0 that any activity requesting new data causes a read trigger. The triggers are wire-ORed together. In
order to meet the faster access times demanded by today’s applications, the ORed trigger only exists during the first 4-5ns of
the read cycle. Since the slowest of the address transitions occurs more than 5ns after the initiation of the read activity, a sec-
ond read activity is initiated. The sensing circuit does not have time to norm alize before the second read activity has started.
For this reason a Chip Enable-Controlled read cycle requires that address inputs remain stable for the entire cycle. Infrequent
and random sensing errors can result if the bit columns are continually pulled to one state th en quickly requested to sense the
opposite state. Another effect of the low power read architecture that differs from previous generation designs (those that con-
tinually sense for data) is that the bit line wi ll not be sensed again unti l anot her read triggering event occurs. If another read
trigger event (chip enable assertion and/or address change) does no occur for a particular address, the incorrect data remains at
the outputs.
Timing shown from VI L (yellow t race /CS) and VIH (pink f or address signal) as de lta X =
6ns. Even at actual internal gate switching point (~ VDD/2), the skew is still around 6ns.
Chip Enable (/E)
Address Signal (A x)
Aeroflex Colorado Springs Application Note AN-MEM-002
Creation Date: 8/19/11 Page 5 of 5 Modification Date: 4/24/ 13
4.0 Summary and Conclusion
The Aeroflex SRAMs in Table #1 all employ a low power consumption read architecture. Power is conserved by sensing data
only when new data is requested. A request occurs anytime chip enable is asserted or any addr ess input signal transitions while
chip enable is asserted. The data sheets for the SRAMs listed in Table #1 do not explicitly define the case of simultaneous
switching of address and control signals during read operations. Data sheet read cycle descriptions indicate that control inputs
are established prior to address changes, and address inputs are stable prior to contro l assertions. Simultaneous switching of
addresses and controls is tolerable, when the skew between all input signals is < 4ns. For designs that must employ the simul-
taneous activation of address and control signals, two important issues should be considered by the designer. The first is the
input signal skew sensitiv ity of the low power read architecture discussed by this application note. The second is the instanta-
neous current consumption that results from simultaneous access methods. Aeroflex recommends the use of only one read
access method at a time. If multiple read accesses (simultaneous chip enable assertion and address switching) cannot be
avoided, then Aeroflex recommends that the chip enable signal be delayed until all addresses have completed transitions.