Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator AD9554 Data Sheet FEATURES APPLICATIONS Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.8262 synchronous Ethernet slave clocks Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8261 Auto/manual holdover and reference switchover Adaptive clocking allows dynamic adjustment of feedback dividers for use in OTN mapping/demapping applications Quad digital phase-locked loop (DPLL) architecture with four reference inputs (single-ended or differential) 4 x 4 crosspoint allows any reference input to drive any PLL Input reference frequencies from 2 kHz to 1000 MHz Reference validation and frequency monitoring: 2 ppm Programmable input reference switchover priority 20-bit programmable input reference divider 8 differential clock outputs with each differential pair configurable as HCSL, LVDS-compatible, or LVPECLcompatible Output frequency range: 430 kHz to 941 MHz Programmable 18-bit integer and 24-bit fractional feedback divider in digital PLL Programmable loop bandwidths from 0.1 Hz to 4 kHz Optional off-chip EEPROM to store power-up profile 72-lead (10 mm x 10 mm) LFCSP package Network synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Cable infrastructure Data communications Professional video GENERAL DESCRIPTION The AD9554 is a low loop bandwidth clock translator that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9554 generates an output clock synchronized to up to four external input references. The digital PLL (DPLL) allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9554 continuously generates a low jitter output clock even when all reference inputs have failed. The AD9554 operates over an industrial temperature range of -40C to +85C. If a smaller device is needed, the AD9554-1 is a version of this device with one output per PLL. If a single or dual DPLL version of this device is needed, refer to the AD9557 or AD9559, respectively. FUNCTIONAL BLOCK DIAGRAM STATUS AND CONTROL PINS REFERENCE INPUT MONITOR AND MUX STABLE SOURCE Q0_A DIVIDER SERIAL INTERFACE (SPI OR I2C) P0 DIVIDER DIGITAL PLL 0 ANALOG PLL 0 DIGITAL PLL 1 ANALOG PLL 1 DIGITAL PLL 2 ANALOG PLL 2 DIGITAL PLL 3 ANALOG PLL 3 CLOCK MULTIPLIER Q0_B DIVIDER Q1_A DIVIDER P1 DIVIDER Q1_B DIVIDER Q2_A DIVIDER P2 DIVIDER Q2_B DIVIDER P3 DIVIDER AD9554 Q3_A DIVIDER Q3_B DIVIDER 12132-001 EXTERNAL EEPROM (OPTIONAL) Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. 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Technical Support www.analog.com AD9554 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital PLL (DPLL) Core .......................................................... 35 Applications ....................................................................................... 1 Loop Control State Machine ..................................................... 38 General Description ......................................................................... 1 System Clock (SYSCLK) ................................................................ 39 Functional Block Diagram .............................................................. 1 SYSCLK Inputs ........................................................................... 39 Revision History ............................................................................... 4 SYSCLK Multiplier ..................................................................... 39 Specifications..................................................................................... 5 Output Analog PLL (APLL) .......................................................... 41 Supply Voltage ............................................................................... 5 APLL Configuration .................................................................. 41 Supply Current .............................................................................. 5 APLL Calibration ....................................................................... 41 Power Dissipation ......................................................................... 6 Clock Distribution.......................................................................... 42 System Clock Inputs (XOA, XOB) ............................................. 6 Clock Dividers ............................................................................ 42 Reference Inputs ........................................................................... 7 Output Amplitude and Power-Down ...................................... 42 Reference Monitors ...................................................................... 8 Clock Distribution Synchronization........................................ 43 Reference Switchover Specifications .......................................... 8 Status and Control .......................................................................... 44 Distribution Clock Outputs ........................................................ 9 Multifunction Pins (M0 to M9) ............................................... 44 Time Duration of Digital Functions ........................................ 11 IRQ Function .............................................................................. 44 Digital PLL (DPLL_0, DPLL_1, DPLL_2, and DPLL_3) ...... 11 Watchdog Timer ......................................................................... 45 Analog PLL (APLL_0, APLL_1, APLL_2, and APLL_3) ...... 11 EEPROM ..................................................................................... 45 Digital PLL Lock Detection ...................................................... 12 Serial Control Port ......................................................................... 49 Holdover Specifications ............................................................. 12 SPI/I2C Port Selection................................................................ 49 Serial Port Specifications--Serial Port Interface (SPI) Mode12 SPI Serial Port Operation .......................................................... 49 2 Serial Port Specifications--I C Mode ...................................... 13 I2C Serial Port Operation .......................................................... 52 Logic Inputs (RESET, M9 to M0)............................................. 14 Programming the Input/Output Registers .................................. 55 Logic Outputs (M9 to M0) ........................................................ 14 Buffered/Active Registers .......................................................... 55 Jitter Generation ......................................................................... 15 Write Detect Registers ............................................................... 55 Absolute Maximum Ratings.......................................................... 16 Autoclear Registers..................................................................... 55 ESD Caution ................................................................................ 16 Register Access Restrictions...................................................... 55 Pin Configuration and Function Descriptions ........................... 17 Thermal Performance .................................................................... 56 Typical Performance Characteristics ........................................... 21 Power Supply Partitions................................................................. 57 Input/Output Termination Recommendations .......................... 24 VDD Supplies ............................................................................. 57 Getting Started ................................................................................ 25 VDD_SP Supply ......................................................................... 57 Chip Power Monitor and Startup ............................................. 25 Register Map ................................................................................... 58 Multifunction Pins at Reset/Power-Up ................................... 25 Register Map Bit Descriptions ...................................................... 70 Device Register Programming Using a Register Setup File .. 25 Serial Control Port Configuration (Register 0x0000 to Register 0x0001) ......................................................................... 70 Register Programming Overview ............................................. 30 Theory of Operation ...................................................................... 33 Overview...................................................................................... 33 Reference Input Physical Connections .................................... 34 Reference Monitors .................................................................... 34 Reference Input Block ................................................................ 34 Clock Part Family ID (Register 0x0003 to Register 0x0006) 71 SPI Version (Register 0x000B).................................................. 71 Vendor ID (Register 0x000C to Register 0x000D) ................ 71 IO_Update (Register 0x000F) ................................................... 71 User Scratchpad (Register 0x00FE to Register 0x00FF) ....... 71 Reference Switchover ................................................................. 35 Rev. D | Page 2 of 116 Data Sheet AD9554 General Configuration (Register 0x0100 to Register 0x010E) .......................................................................................................72 DPLL_2 Settings for Reference Input D (REFD) (Register 0x0667 to Register 0x0673)........................................................ 88 IRQ Mask (Register 0x010F to Register 0x011F)....................73 DPLL_3 Controls (Register 0x0700 to Register 0x071E) ...... 88 System Clock (Register 0x0200 to Register 0x0208) ..............75 APLL_3 Configuration (Register 0x0730 to Register 0x0733) ....................................................................................................... 88 Reference Input A (Register 0x0300 to Register 0x031E) ......76 Reference Input B (Register 0x0320 to Register 0x033E) ......78 Reference Input C (Register 0x0340 to Register 0x035E) ......78 Reference Input D (Register 0x0360 to Register 0x037E) .....78 DPLL_0 Controls (Register 0x0400 to Register 0x041E).......78 APLL_0 Configuration (Register 0x0430 to Register 0x0434) .......................................................................................................80 Output PLL_0 (APLL_0) Sync and Clock Distribution (Register 0x0434 to Register 0x043E).......................................81 DPLL_0 Settings for Reference Input A (REFA) (Register 0x0440 to Register 0x044C) .......................................................83 DPLL_0 Settings for Reference Input B (REFB) (Register 0x044D to Register 0x0459).......................................................84 DPLL_0 Settings for Reference Input C (REFC) (Register 0x045A to Register 0x0466) .......................................................85 PLL_3 Output Sync and Clock Distribution (Register 0x0734 to Register 0x073E) ..................................................................... 88 DPLL_3 Settings for Reference Input A (REFA) (Register 0x0740 to Register 0x074C) ....................................................... 88 DPLL_3 Settings for Reference Input B (REFB) (Register 0x074D to Register 0x0759) ...................................................... 88 DPLL_3 Settings for Reference Input C (REFC) (Register 0x075A to Register 0x0766) ....................................................... 88 DPLL_3 Settings for Reference Input D (REFD) (Register 0x0767 to Register 0x0773)........................................................ 88 Digital Loop Filter Coefficients (Register 0x0800 to Register 0x0817) ......................................................................................... 89 Common Operational Controls (Register 0x0A00 to Register 0x0A0E) ........................................................................................ 90 IRQ Clearing (Register 0x0A05 to Register 0x0A14) ............ 92 DPLL_0 Settings for Reference Input D (REFD) (Register 0x0467 to Register 0x0473) ........................................................86 PLL_0 Operational Controls (Register 0x0A20 to Register 0x0A24) ........................................................................................ 95 DPLL_1 Controls (Register 0x0500 to Register 0x051E).......87 PLL_1 Operational Controls (Register 0x0A40 to Register 0x0A44) ........................................................................................ 97 APLL_1 Configuration (Register 0x0530 to Register 0x0533) .......................................................................................................87 PLL_1 Output Sync and Clock Distribution (Register 0x0534 to Register 0x053E) .....................................................................87 DPLL_1 Settings for Reference Input A (REFA) (Register 0x0540 to Register 0x054C) .......................................................87 DPLL_1 Settings for Reference Input B (REFB) (Register 0x054D to Register 0x0559).......................................................87 DPLL_1 Settings for Reference Input C (REFC) (Register 0x055A to Register 0x0566) .......................................................87 DPLL_1 Settings for Reference Input D (REFD) (Register 0x0567 to Register 0x0573) ........................................................87 DPLL_2 Controls (Register 0x0600 to Register 0x061E).......87 APLL_2 Configuration (Register 0x0630 to Register 0x0633) .......................................................................................................87 PLL_2 Output Sync and Clock Distribution (Register 0x0634 to Register 0x063E) .....................................................................88 DPLL_2 Settings for Reference Input A (REFA) (Register 0x0640 to Register 0x064C) .......................................................88 DPLL_2 Settings for Reference Input B (REFB) (Register 0x064D to Register 0x0659).......................................................88 DPLL_2 Settings for Reference Input C (REFC) (Register 0x065A to Register 0x0666) .......................................................88 PLL_2 Operational Controls (Register 0x0A60 to Register 0x0A64) ........................................................................................ 97 PLL_3 Operational Controls (Register 0x0A80 to Register 0x0A84) ........................................................................................ 97 Voltage Regulator (Register 0x0B00 to Register 0x0B01)...... 97 Status ReadBack (Register 0x0D00 to Register 0x0D05)....... 97 IRQ Monitor (Register 0x0D08 to Register 0x0D16) ............ 99 PLL_0 Read Only Status (Register 0x0D20 to Register 0x0D2A) .....................................................................................102 PLL_1 Read Only Status (Register 0x0D40 to Register 0x0D4A) .....................................................................................104 PLL_2 Read Only Status (Register 0x0D60 to Register 0x0D6A) .....................................................................................104 PLL_3 Read Only Status (Register 0x0D80 to Register 0x0D8A) .....................................................................................104 EEPROM Control (Register 0x0E00 to Register 0x0E03) ...104 EEPROM Storage Sequence (Register 0x0E10 to Register 0x0E61) .......................................................................................105 Outline Dimensions ......................................................................116 Ordering Guide .........................................................................116 Rev. D | Page 3 of 116 AD9554 Data Sheet REVISION HISTORY 3/2017--Rev. C to Rev. D Changes to Chip Power and Startup Section .............................. 25 Changes to Figure 26 ...................................................................... 26 10/2016--Rev. B to Rev. C Changes to Multifunction Pins at Reset/Power-Up Section and Table 21 ..................................................................................... 25 Changes to Figure 29 ...................................................................... 29 Changes to the Important Update to EEPROM Programing Sequence Section ............................................................................ 48 Changes to Table 71 and Table 73 ................................................ 82 6/2016--Rev. A to Rev. B Changes to Device Register Programming Using a Register Setup File Section ........................................................................... 25 Added Figure 26 to Figure 29; Renumbered Sequentially ........ 26 Added Note 1, Table 69 .................................................................. 81 Changes to Bit 1 Description, Table 98 ........................................ 90 8/2014--Rev. 0 to Rev. A Changes to Applications and General Description Sections ...... 1 Added Output Frequency of 0.430 MHz (Min) and 941 MHz (Max); Table 8 ................................................................ 10 Added Bandwidth (fREF = 19.44 MHz; fOUT = 156.25 MHz; fLOOP = 50 Hz) Parameters; Table 18 ............................................. 15 Changes to Figure 3 ........................................................................ 21 Changes to Figure 24 Caption....................................................... 24 Changes to Table 21 and Device Register Programming Using a Register Setup File Section ............................................................ 25 Changes to Overview Section ....................................................... 30 Changes to DPLL Overview Section and Figure 27 .................. 32 Changes to System Clock (SYSCLK) Section ............................. 35 Changes to APLL Calibration Section ......................................... 37 Changes to P Dividers and Output Amplitude and Power-Down Sections .................................................................... 38 Changes to EEPROM Overview Section and Figure 32............ 41 Changes to Second Paragraph of Serial Port Control Section.. 45 Changes to Write Section, Address Ascension Section and Table 25 ............................................................................................ 46 Changes to Data Transfer Process Section .................................. 48 Changes to Write Detect Registers Section ................................. 51 Changes to Table 32 ....................................................................... 54 Changes to Table 47 ....................................................................... 71 Changes to Table 61 and Table 62 ................................................ 74 Changes to Table 68 ....................................................................... 76 Changes to Table 71 ....................................................................... 78 Changes to Table 76 ....................................................................... 79 Changes to Table 78 and Table 79 ................................................ 80 Changes to Table 100 ..................................................................... 87 Changes to Table 118 ..................................................................... 94 Changes to Table 121 ..................................................................... 96 Changes to Table 126 ..................................................................... 99 Changes to Table 155 ................................................................... 110 4/2014--Revision 0: Initial Version Rev. D | Page 4 of 116 Data Sheet AD9554 SPECIFICATIONS Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for VDD = 1.8 V, TA = 25C, unless otherwise noted. SUPPLY VOLTAGE Table 1. Parameter SUPPLY VOLTAGE for 1.8 V OPERATION VDD_SP VDD SUPPLY VOLTAGE for 1.5 V OPERATION VDD_SP VDD Min Typ Max Unit 1.47 1.71 1.8 1.8 2.625 1.89 V V 1.47 1.47 1.5 1.5 2.625 1.53 V V SUPPLY CURRENT The test conditions for the maximum (max) supply current are at the maximum supply voltage found in Table 1. The test conditions for the typical (typ) supply current are at the typical supply voltage found in Table 1. The test conditions for the minimum (min) supply current are at the minimum supply voltage found in Table 1. Table 2. Parameter SUPPLY CURRENT FOR TYPICAL CONFIGURATION IVDD_SP IVDD SUPPLY CURRENT FOR ALL BLOCKS RUNNING CONFIGURATION IVDD_SP IVDD Min Typ Max Unit 0.01 430 0.04 520 0.1 575 mA mA Test Conditions/Comments Typical values are for the Typical Configuration parameter listed in Table 3; valid for both 1.5 V and 1.8 V operation Maximum values are for the All Blocks Running parameter listed in Table 3; valid for both 1.5 V and 1.8 V operation 0.01 615 0.04 745 0.1 780 mA mA Rev. D | Page 5 of 116 AD9554 Data Sheet POWER DISSIPATION Typical (typ) values apply for VDD = 1.8 V and maximum (max) values for VDD = 1.89 V. Table 3. Parameter POWER DISSIPATION Typical Configuration Min Typ Max Unit Test Conditions/Comments 0.94 1.1 W All Blocks Running 1.3 1.47 W Full Power-Down 174 mW 190 mW System clock: 49.152 MHz crystal; four DPLLs active; two 19.44 MHz input references in differential mode; four ac-coupled output drivers in 21 mA mode at 644.53125 MHz System clock: 49.152 MHz crystal; four DPLLs active, four 19.44 MHz input references in differential mode; eight ac-coupled output drivers in 28 mA mode at 750 MHz Measured using the Typical Configuration parameter (see Table 3) and then setting the full power down bit Typical configuration; table values show the change in power due to the indicated operation Power delta computed relative to the typical configuration; the blocks powered down include one reference input, one DPLL, one APLL, one P divider, two channel dividers, and one output driver in 21 mA mode 22.5 24.6 14.3 mW mW mW 70 48 23.6 mW mW mW Incremental Power Dissipation Complete DPLL/APLL On/Off Input Reference On/Off Differential (Normal Mode) Differential (DC-Coupled LVDS) Single-Ended Output Distribution Driver On/Off 28 mA Mode (at 644.53 MHz) 21 mA Mode (at 644.53 MHz) 14 mA mode (at 644.53 MHz) fREF = 19.44 MHz fREF = 19.44 MHz fREF = 19.44 MHz SYSTEM CLOCK INPUTS (XOA, XOB) Table 4. Parameter SYSTEM CLOCK MULTIPLIER PLL Output Frequency Range Min Phase Frequency Detector (PFD) Rate Frequency Multiplication Range SYSTEM CLOCK REFERENCE INPUT PATH Input Frequency Range System Clock Input Doubler Disabled System Clock Input Doubler Enabled Minimum Input Slew Rate Self-Biased Common-Mode Voltage Input High Voltage Input Low Voltage Differential Input Voltage Sensitivity Typ Max Unit Test Conditions/Comments 2250 2415 MHz Voltage controlled oscillator (VCO) range can place limitations on nonstandard system clock input frequencies 10 8 300 241 MHz 10 16 250 268 150 MHz MHz V/s V V V mV p-p 0.72 0.9 0.5 250 Assumes valid system clock and PFD rates System clock input must be ac-coupled System Clock Input Doubler Duty Cycle System Clock Input = 20 MHz to 150 MHz System Clock Input = 16 MHz to 20 MHz 43 47 50 50 57 53 % % Rev. D | Page 6 of 116 Minimum limit imposed for jitter performance Internally generated For ac-coupled single-ended operation For ac-coupled single-ended operation Minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed 1.14 V; single-ended input can be accommodated by ac grounding complementary input; 800 mV p-p recommended for optimal jitter performance Amount of duty-cycle variation that can be tolerated on the system clock input to use the doubler Data Sheet AD9554 Parameter Input Capacitance Input Resistance CRYSTAL RESONATOR PATH Crystal Resonator Frequency Range Input Capacitance Maximum Crystal Motional Resistance Min Typ 3 5 12 Max Unit pF k Test Conditions/Comments Single-ended to ground, each pin 50 MHz pF Fundamental mode, AT cut crystal Single-ended to ground, each pin 3 100 REFERENCE INPUTS Table 5. Parameter DIFFERENTIAL MODE Frequency Range Sinusoidal Input LVPECL Input LVDS Input Minimum Input Slew Rate DPLL Loop Bandwidth = 50 Hz DPLL Loop Bandwidth = 4 kHz Common-Mode Input Voltage Differential Input Voltage Sensitivity fIN < 400 MHz fIN = 400 MHz to 750 MHz fIN = 750 MHz to 1000 MHz Differential Input Voltage Hysteresis Input Resistance Input Capacitance Minimum Pulse Width High LVPECL LVDS Minimum Pulse Width Low LVPECL LVDS DC-COUPLED LVDS MODE Frequency Range Minimum Input Slew Rate DPLL Loop Bandwidth = 50 Hz DPLL Loop Bandwidth = 4 kHz Common-Mode Input Voltage Differential Input Voltage Sensitivity Differential Input Voltage Hysteresis Input Resistance Input Capacitance Minimum Pulse Width High Minimum Pulse Width Low Min Typ 10 0.002 0.002 Max Unit 475 1000 700 MHz MHz MHz 40 50 V/s V/s V 0.64 400 500 1000 55 16 9 2100 2100 2100 100 mV p-p mV p-p mV p-p mV k pF 460 560 ps ps 460 560 ps ps Test Conditions/Comments AC couple inputs in differential mode Assumes an LVDS minimum of 494 mV p-p differential amplitude Minimum limit imposed for jitter performance Maximum loop bandwidth is fPFD/50 Internally generated self-bias voltage Peak-to-peak differential voltage swing across pins required to ensure switching between logic levels as measured with a differential probe; instantaneous voltage on either pin must not exceed 1.3 V Equivalent differential input resistance Single-ended to ground, each pin Intended for dc-coupled LVDS 10.24 MHz 0.002 10.24 MHz 1.375 1200 V/s V/s V mV Minimum limit imposed for jitter performance 40 150 1.125 400 55 21 7 25 25 100 mV k pF ns ns Rev. D | Page 7 of 116 Maximum loop bandwidth is fPFD/50 Differential voltage across pins required to ensure switching between logic levels; instantaneous voltage on either pin must not exceed the supply rails AD9554 Data Sheet Parameter SINGLE-ENDED MODE Frequency Range (CMOS) Minimum Input Slew Rate DPLL Loop Bandwidth = 50 Hz DPLL Loop Bandwidth = 4 kHz Input Voltage High, VIH Input Voltage Low, VIL Input Resistance Input Capacitance Minimum Pulse Width High Minimum Pulse Width Low Min Typ 0.002 Max Unit 300 MHz Test Conditions/Comments DC-coupled Minimum limit imposed for jitter performance 40 175 VDD - 0.5 V/s V/s V V k pF ns ns 0.5 30 5 1.5 1.5 Maximum loop bandwidth is fPFD/50 REFERENCE MONITORS Table 6. Parameter REFERENCE MONITORS Reference Monitor Loss of Reference Detection Time Frequency Out-of Range Limits Validation Timer Min Typ Max Unit Test Conditions/Comments 1.15 DPLL PFD period 2 105 f/fREF (ppm) 0.001 65.535 sec Nominal phase detector period = R/fREF, where R is the frequency division factor determined by the R divider, and fREF is the frequency of the active reference Programmable (lower bound subject to quality of the system clock [SYSCLK]); SYSCLK accuracy must be less than the lower bound Programmable in 1 ms increments REFERENCE SWITCHOVER SPECIFICATIONS Table 7. Parameter MAXIMUM OUTPUT PHASE PERTURBATION (PHASE BUILD-OUT SWITCHOVER) Min Typ Max Unit 20 20 130 130 ps ps 10 DPLL PFD period 50 Hz DPLL Loop Bandwidth Peak Steady State Time Required to Switch to a New Reference Phase Build-Out Switchover Rev. D | Page 8 of 116 Test Conditions/Comments Assumes a jitter-free reference; satisfies Telcordia GR-1244-CORE requirements; base loop filter selection bit set to 1b or all active references High phase margin mode; 19.44 MHz to 174.70308 MHz; DPLL bandwidth = 50 Hz; 49.152 MHz signal generator used for system clock source Calculated using the nominal phase detector period (NPDP = R/fREF); the total time required is the time plus the reference validation time, plus the time required to lock to the new reference Data Sheet AD9554 DISTRIBUTION CLOCK OUTPUTS Table 8. Parameter 14 mA (HCSL-, LVDS-COMPATIBLE) MODE Min Typ Max Unit Output Frequency 0.430 941 MHz Continuous Output Frequency Range 0.430 781 MHz Maximum Output Frequency PLL0 to PLL3 Using Unique VCO Frequencies PLL0, PLL1, and PLL2 PLL3 Rise/Fall Time (20% to 80%)1 Duty Cycle Up to fOUT = 750 MHz Up to fOUT = 941 MHz Up to fOUT = 1250 MHz Differential Output Voltage Swing Without 100 Termination Resistor With 100 Termination Resistor Across Outputs Common-Mode Output Voltage Reference Input-to-Output Delay Variation over Temperature Static Phase Offset Variation from Active Reference to Output over Voltage Extremes 21 mA MODE 941 MHz 1250 MHz 1187 125 45 44 50 50 50 190 55 56 MHz ps Test Conditions/Comments Unless otherwise stated, specifications dccoupled with no output termination resistor; when ac-coupled, LVDS-compatible amplitudes are achieved with a 100 resistor across the output pair; HCSL-compatible amplitudes achieved with no termination resistor across the output pair; output current setting: 14 mA Frequency range all four PLLs can generate using unique VCO frequencies; frequencies outside this range are possible on some of the PLLs, but can result in increased VCO coupling due to multiple PLLs using the same VCO frequency All four PLLs can generate this range at the same time while using unique VCO frequencies Maximum frequency all four PLLs can generate using unique VCO frequencies Limited by 1250 MHz maximum input frequency to channel divider (Q divider) Limited by 4748 MHz maximum VCO frequency % % % Differential voltage swing between output pins; measured with output driver static; peak-to-peak differential output amplitude 2x this level with driver toggling; see Figure 11 for output amplitude vs. output frequency 635 294 840 390 1000 463 mV mV 310 420 600 525 mV fs/C 75 Output driver static; no termination resistor DPLL locked to same input reference at all times; stable system clock source (noncrystal) fs/mV Output Frequency 0.430 941 MHz Continuous Output Frequency Range 0.430 781 MHz Maximum Output Frequency PLL0 to PLL3 Using Unique VCO Frequencies PLL0, PLL1, and PLL2 941 MHz 1250 MHz PLL3 Rise/Fall Time (20% to 80%)1 1187 125 190 Rev. D | Page 9 of 116 MHz ps Unless otherwise stated, specifications dc-coupled with 50 output termination resistor to ground; output current setting = 21 mA Frequency range all four PLLs can generate using unique VCO frequencies; frequencies outside this range are possible on some of the PLLs, but can result in increased VCO coupling due to multiple PLLs using the same VCO frequency All four PLLs can generate this range at the same time while using unique VCO frequencies Maximum frequency all four PLLs can generate using unique VCO frequencies Limited by 1250 MHz maximum input frequency to channel divider (Q divider) Limited by 4748 MHz maximum VCO frequency AD9554 Parameter Duty Cycle Up to fOUT = 750 MHz Up to fOUT = 941 MHz Up to fOUT = 1250 MHz Differential Output Voltage Swing No External Termination Resistor With 50 Termination Resistor to Ground on Each Leg Common-Mode Output Voltage Data Sheet Min Typ Max Unit 45 44 50 50 50 55 56 % % % Differential voltage swing between output pins; measured with output driver static; peak-to-peak differential output amplitude 2x this level with driver toggling; see Figure 13 for output amplitude vs. output frequency 779 413 1180 625 1510 800 mV mV 206 312 400 mV Reference Input-to-Output Delay Variation over Temperature Static Phase Offset Variation from Active Reference to Output over Voltage Extremes 28 mA (LVPECL-COMPATIBLE) MODE 600 fs/C 75 fs/mV 0.430 941 MHz Continuous Output Frequency Range 0.430 781 MHz Maximum Output Frequency PLL0 to PLL3 Using Unique VCO Frequencies PLL0, PLL1, and PLL2 Common-Mode Output Voltage Reference Input-to-Output Delay Variation over Temperature Static Phase Offset Variation from Active Reference to Output over Voltage Extremes Output driver static with 50 resistor to ground on each leg DPLL locked to same input reference at all times; stable system clock source (noncrystal) Specifications for dc-coupled, 50 termination resistor from each leg to ground; ac coupling used in most applications; output current setting = 28 mA; in this mode, user must have either a 50 resistor from each leg to ground, or a 100 resistor across the differential pair Output Frequency PLL3 Rise/Fall Time (20% to 80%)1 Duty Cycle Up to fOUT = 750 MHz Up to fOUT = 941 MHz Up to fOUT = 1250 MHz Differential Output Voltage Swing Test Conditions/Comments 941 MHz 1250 MHz 1187 185 45 44 280 MHz ps 55 56 540 50 50 50 830 1020 % % % mV 275 415 510 mV 600 fs/C 75 fs/mV Rev. D | Page 10 of 116 Frequency range all four PLLs can be generated using unique VCO frequencies; frequencies outside this range are possible on some of the PLLs, but can result in increased VCO coupling due to multiple PLLs using the same VCO frequency Frequency range for each PLL such that all four PLLs are using unique VCO frequencies with no frequency gaps Maximum frequency all four PLLs can generate using unique VCO frequencies Limited by 1250 MHz maximum input frequency to channel divider (Q divider) Limited by 4748 MHz maximum VCO frequency Differential voltage swing between output pins; measured with output driver static; peak-to-peak differential output amplitude 2x this level with driver toggling; see Figure 10 for output amplitude vs. output frequency Output driver static; 50 external termination resistor from each leg to ground DPLL locked to same input reference at all times; stable system clock source (noncrystal) Data Sheet AD9554 Parameter OUTPUT TIMING SKEW Between OUT0A, OUT0A and OUT0B, OUT0B Between OUT1A, OUT1A and OUT1B, OUT1B Between OUT2A, OUT2A and OUT2B, OUT2B Between OUT3A, OUT3A and OUT3B, OUT3B 1 Min Typ Max Unit -60 -60 -60 -60 -6 -6 -6 -6 +48 +48 +48 +48 ps ps ps ps Test Conditions/Comments Independent of output driver mode; rising edge only; any divide value; negative value means OUTxB is ahead of OUTxA The listed values are for the slower edge (rising or falling). TIME DURATION OF DIGITAL FUNCTIONS Table 9. Parameter TIME DURATION OF DIGITAL FUNCTIONS EEPROM to Register Download Time Min Register to EEPROM Upload Time Power-Down Exit Time Typ Max Unit Test Conditions/Comments 30 ms Varies 51 ms ms Uses default EEPROM storage sequence (see Register 0x0E10 to Register 0x0E6F) assuming full 400 kHz throughput from EEPROM Value dependent on write throughput of the external EEPROM Time from power-down exit to system clock stable (including the system clock stability timer default of 50 ms); does not include time to validate input references or lock the DPLL Mx refers to Pin M0 though Pin M9 1 1 10 Mx Pin to RESET Rising Edge Setup Time Mx Pin to RESET Rising Edge Hold Time RESET Falling Edge to Mx Pin High-Z Time ns ns ns DIGITAL PLL (DPLL_0, DPLL_1, DPLL_2, AND DPLL_3) Table 10. Parameter DIGITAL PLL Phase Frequency Detector (PFD) Input Frequency Range Loop Bandwidth Phase Margin Closed Loop Peaking Min Typ Max Unit 2 200 kHz 0.1 45 <0.1 4000 89 Hz Degrees dB Test Conditions/Comments Programmable design parameter; note that (fPFD/loop bandwidth) 50 Programmable design parameter Programmable design parameter; device can be programmed for <0.1 dB peaking in accordance with Telcordia GR-253-CORE jitter transfer ANALOG PLL (APLL_0, APLL_1, APLL_2, AND APLL_3) Table 11. Parameter ANALOG PLL0 (APLL_0) VCO Frequency Range Phase Frequency Detector (PFD) Input Frequency Range Loop Bandwidth Phase Margin ANALOG PLL1 (APLL_1) VCO Frequency Range Phase Frequency Detector (PFD) Input Frequency Range Loop Bandwidth Phase Margin Min Typ Max Unit 320 3132 350 MHz MHz 2424 240 68 3232 320 240 68 Test Conditions/Comments The AD9554 evaluation software finds the optimal value for this setting based on user input. kHz Degrees 3905 350 MHz MHz kHz Degrees Rev. D | Page 11 of 116 The AD9554 evaluation software finds the optimal value for this setting based on user input. AD9554 Data Sheet Parameter ANALOG PLL2 (APLL_2) VCO Frequency Range Phase Frequency Detector (PFD) Input Frequency Range Loop Bandwidth Phase Margin ANALOG PLL3 (APLL_3) VCO Frequency Range Phase Frequency Detector (PFD) Input Frequency Range Loop Bandwidth Phase Margin Min Typ Max Unit 320 5650 350 MHz MHz 4842 240 68 4040 320 Test Conditions/Comments The AD9554 evaluation software finds the optimal value for this setting based on user input. kHz Degrees 4748 350 240 68 MHz MHz The AD9554 evaluation software finds the optimal value for this setting based on user input. kHz Degrees DIGITAL PLL LOCK DETECTION Table 12. Parameter PHASE LOCK DETECTOR Threshold Programming Range Threshold Resolution FREQUENCY LOCK DETECTOR Threshold Programming Range Threshold Resolution Min Typ 10 Max Unit Test Conditions/Comments 224 - 1 ps ps Reference-to-feedback phase difference 224 - 1 ps ps Reference-to-feedback period difference Max Unit Test Conditions/Comments ppm Excludes frequency drift of SYSCLK source; excludes frequency drift of input reference prior to entering holdover; compliant with GR-1244 Stratum 3 1 10 1 HOLDOVER SPECIFICATIONS Table 13. Parameter HOLDOVER SPECIFICATIONS Initial Frequency Accuracy Min Typ <0.01 SERIAL PORT SPECIFICATIONS--SERIAL PORT INTERFACE (SPI) MODE Table 14. Parameter CS Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance Min Typ Max VDD_SP - 0.4 Unit 1 1 3 V V A A pF 1 1 2 V V A A pF 0.4 Test Conditions/Comments Valid for VDD_SP = 1.5 V, VDD_SP = 1.8 V, and VDD_SP = 2.5 V No internal pull-up or pull-down resistor VDD_SP - 0.4 0.4 Rev. D | Page 12 of 116 Data Sheet Parameter SDIO As an Input Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance As an Output Output Logic 1 Voltage Output Logic 0 Voltage SDO Output Logic 1 Voltage Output Logic 0 Voltage High-Z Leakage Current TIMING SCLK Clock Rate, 1/tCLK Pulse Width High, tHIGH Pulse Width Low, tLOW SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO and SDO, tDV CS to SCLK Setup, tS CS to SCLK Hold, tC CS Minimum Pulse Width High AD9554 Min Typ Max VDD_SP - 0.4 0.4 1 1 2 VDD_SP - 0.2 Test Conditions/Comments V V A A pF 0.1 V V 1 mA load current 1 mA load current 0.1 100 V V A 1 mA load current 1 mA load current VDD_SP - 0.2 6 Unit Valid for VDD_SP = 1.5 V, VDD_SP = 1.8 V, and VDD_SP = 2.5 V 50 5 8 1.5 0 8 0 0 1.5 MHz ns ns ns ns ns ns ns ns SERIAL PORT SPECIFICATIONS--I2C MODE Table 15. Parameter SDA, SCL (AS INPUTS) Min Input Logic 1 Voltage Input Logic 0 Voltage Input Current Hysteresis of Schmitt Trigger Inputs SDA (AS OUTPUT) Output Logic 0 Voltage Output Fall Time from VIH Minimum to VIL Maximum TIMING SCL Clock Rate Bus-Free Time Between a Stop and Start Condition, tBUF Repeated Start Condition Setup Time, tSU; STA Repeated Hold Time Start Condition, tHD; STA Stop Condition Setup Time, tSU; STO Low Period of the SCL Clock, tLOW High Period of the SCL Clock, tHIGH SCL/SDA Rise Time, tR SCL/SDA Fall Time, tF 0.7 x VDD_SP Max Unit 0.3 x VDD_SP +10 V V A For VIN = 10% to 90% of VDD 0.2 250 V ns IOUT = 3 mA 10 pF Cb 400 pF 400 1.3 kHz s 0.6 s 0.6 s 0.6 1.3 0.6 20 + 0.1 x Cb 20 + 0.1 x Cb s s s ns ns -10 0.015 x VDD 20 + 0.1 x Cb Typ 300 300 Rev. D | Page 13 of 116 Test Conditions/Comments Valid for VDD_SP = 1.5 V, VDD_SP = 1.8 V, and VDD_SP = 2.5 V After this period, the first clock pulse is generated AD9554 Data Sheet Parameter Data Setup Time, tSU; DAT Data Hold Time, tHD; DAT Capacitive Load for Each Bus Line, Cb Min 100 100 Typ Max Unit ns ns pF 400 Test Conditions/Comments LOGIC INPUTS (RESET, M9 TO M0) Table 16. Parameter RESET PIN Input High Voltage (VIH) Input Low Voltage (VIL) Input Current (IINH, IINL) Input Capacitance (CIN) LOGIC INPUTS (M9 to M0) Input High Voltage (VIH) Input Low Voltage (VIL) Input Current (IINH, IINL) Input Capacitance (CIN) Min Typ Max Unit 0.5 125 V V A pF 0.6 25 V V A pF VDD_SP -0.5 85 3 Test Conditions/Comments Valid for VDD_SP = 1.5 V, VDD_SP = 1.8 V, and VDD_SP = 2.5 V Valid for VDD = 1.5 V, and VDD = 1.8 V VDD - 0.5 15 5 LOGIC OUTPUTS (M9 TO M0) Table 17. Parameter LOGIC OUTPUTS (M9 to M0) Output High Voltage (VOH) Output Low Voltage (VOL) Min Typ Max Unit 0.2 V V VDD - 0.2 Test Conditions/Comments VDD = 1.5 V and VDD = 1.8 V IOH = 1 mA using high drive strength (see Register 0x011E) IOL = 1 mA Rev. D | Page 14 of 116 Data Sheet AD9554 JITTER GENERATION Jitter Generation (Random Jitter)--49.152 MHz Crystal for System Clock Input Table 18. Parameter JITTER GENERATION fREF = 19.44 MHz; fOUT = 622.08 MHz; fLOOP = 50 Hz Bandwidth 5 kHz to 20 MHz 12 kHz to 20 MHz 20 kHz to 80 MHz 50 kHz to 80 MHz 4 MHz to 80 MHz fREF = 19.44 MHz; fOUT = 644.53 MHz; fLOOP = 50 Hz Bandwidth 5 kHz to 20 MHz 12 kHz to 20 MHz 20 kHz to 80 MHz 50 kHz to 80 MHz 4 MHz to 80 MHz fREF = 19.44 MHz; fOUT = 693.48 MHz; fLOOP = 50 Hz Bandwidth 5 kHz to 20 MHz 12 kHz to 20 MHz 20 kHz to 80 MHz 50 kHz to 80 MHz 4 MHz to 80 MHz fREF = 19.44 MHz; fOUT = 156.25 MHz; fLOOP = 50 Hz Bandwidth 5 kHz to 20 MHz 12 kHz to 20 MHz 20 kHz to 80 MHz 50 kHz to 80 MHz 4 MHz to 80 MHz fREF = 19.44 MHz; fOUT = 174.703 MHz; fLOOP = 50 Hz Bandwidth 5 kHz to 20 MHz 12 kHz to 20 MHz 20 kHz to 80 MHz 50 kHz to 80 MHz 4 MHz to 80 MHz fREF = 25 MHz; fOUT = 161.1328 MHz; fLOOP = 100 Hz Bandwidth 5 kHz to 20 MHz 12 kHz to 20 MHz 20 kHz to 80 MHz 50 kHz to 80 MHz 4 MHz to 80 MHz Min Typ Max Unit 381 375 380 365 116 fs rms fs rms fs rms fs rms fs rms 388 381 385 368 106 fs rms fs rms fs rms fs rms fs rms 433 427 432 419 120 fs rms fs rms fs rms fs rms fs rms 420 414 461 449 260 fs rms fs rms fs rms fs rms fs rms 398 393 439 427 231 fs rms fs rms fs rms fs rms fs rms 385 379 423 412 250 fs rms fs rms fs rms fs rms fs rms Rev. D | Page 15 of 116 Test Conditions/Comments System clock doubler enabled; high phase margin mode enabled; all PLLs are running with same output frequency; in cases where the four PLLs have different jitter, the higher jitter is listed; there is not a significant jitter difference between driver modes AD9554 Data Sheet ABSOLUTE MAXIMUM RATINGS ESD CAUTION Table 19. Parameter 1.8 V Supply Voltage (VDD) Serial Port Supply Voltage (VDD_SP) Maximum Digital Input Voltage Range Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 2V 2.75 V -0.5 V to VDD + 0.5 V -65C to +150C -40C to +85C 300C 115C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. D | Page 16 of 116 Data Sheet AD9554 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 OUT3B VDD VDD LDO_3 LF_3 M9 M8 M7 XOA XOB VDD M6 M5 LF_2 LDO_2 VDD VDD OUT2B PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD9554 TOP VIEW (Not to Scale) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 OUT2B VDD OUT2A OUT2A VDD M2 REFC REFC VDD VDD REFB REFB M1 VDD OUT1A OUT1A VDD OUT1B NOTES 1. THE EXPOSED PADDLE IS THE GROUND CONNECTION ON THE CHIP. IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. 12132-002 OUT0B VDD VDD LDO_0 LF_0 M4 VDD SDO SDIO/SDA SCLK/SCL CS VDD_SP RESET LF_1 LDO_1 VDD VDD OUT1B 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 OUT3B VDD OUT3A OUT3A VDD M3 REFD REFD VDD VDD REFA REFA M0 VDD OUT0A OUT0A VDD OUT0B Figure 2. Pin Configuration Table 20. Pin Function Descriptions Pin No. 1 Mnemonic OUT3B Input/ Output O 2, 5, 9, 10, 14, 17, 20, 21, 25, 34, 35, 38, 41, 45, 46, 50, 53, 56, 57, 62, 70, 71 3 VDD I OUT3A O 4 OUT3A O 6, 13, 42, 49 M3, M0, M1, M2 I/O 7 REFD I Pin Type HCSL, LVDScompatible, LVPECLCompatible Power Description PLL3 Complementary Output 3B. Complementary signal to the output provided on Pin 72 (OUT3B). HCSL, LVDScompatible, LVPECLcompatible HCSL, LVDScompatible, LVPECLcompatible 1.5 V/1.8 V CMOS PLL3 Output 3A. This HCSL output can be configured as a LVDS- or LVPECLcompatible output. LVPECL and LVDS levels can be achieved by ac coupling and using the Thevenin equivalent termination as described in the Input/Output Termination Recommendations section. PLL3 Complementary Output 3A. Complementary signal to the output provided on Pin 3 (OUT3A). Differential input 1.5 V or 1.8 V Power Supply. See the Power Supply Partitions section for information about the recommended grouping of the power supply pins. Configurable Input/Output Pins. These pins are used for status and control of the AD9554. These pins are also used at power-up and reset to control the optional external EEPROM. See the Multifunction Pins at Reset/Power-Up section for more information about the internal 100 k pull-up or pull-down resistors. These pins are on the VDD power domain (Pin 9, Pin 10, Pin 45, and Pin 46), and the logic high voltage for this pin matches the voltage of the VDD pins. Reference D Input. This internally biased input is typically ac-coupled; when configured in this manner, it can accept any differential signal with singleended swing up to the VDD power supply. If dc-coupled, the input can be LVDS or single-ended CMOS provided that VIH VDD. Rev. D | Page 17 of 116 AD9554 Data Sheet Pin No. 8 Mnemonic REFD Input/ Output I 11 REFA I Differential input 12 REFA I Differential input 15 OUT0A O 16 OUT0A O 18 OUT0B O 19 OUT0B O 22 LDO_0 I HCSL, LVDScompatible, LVPECLcompatible HCSL, LVDScompatible, LVPECLcompatible HCSL, LVDScompatible, LVPECLcompatible HCSL, LVDScompatible, LVPECLcompatible LDO bypass 23 LF_0 I/O 24 M4 I/O 26 SDO O CMOS 27 SDIO/SDA I/O CMOS 28 SCLK/SCL I CMOS 29 CS I CMOS 30 VDD_SP I Power 31 RESET I 1.5 V/1.8 V/ 2.5 V CMOS Pin Type Differential input Loop filter for APLL_0 1.5 V/1.8 V CMOS Description Complementary Reference D Input. Complementary signal to the input provided on Pin 7 (REFD). This pin can be left floating if REFD is a single-ended input or if REFD is not used. Complementary Reference A Input. Complementary signal to the input provided on Pin 12 (REFA). This pin can be left floating if REFA is a single-ended input or if REFA is not used. Reference A Input. This internally biased input is typically ac-coupled; when configured in this manner, it can accept any differential signal with singleended swing up to the VDD power supply. If dc-coupled, the input can be LVDS or single-ended CMOS provided that VIH VDD. PLL0 Complementary Output 0A. Complementary signal to the output provided on Pin 16 (OUT0A). PLL0 Output 0A. This HCSL output can be configured as a LVDS- or LVPECLcompatible output. LVPECL and LVDS levels can be achieved by ac-coupling and using the Thevenin equivalent termination as described in the Input/Output Termination Recommendations section. PLL0 Complementary Output 0B. Complementary signal to the output provided on Pin 19 (OUT0A). PLL0 Output 0B. This HCSL output can be configured as a LVDS- or LVPECLcompatible output. LVPECL and LVDS levels can be achieved by ac-coupling and using the Thevenin equivalent termination as described in the Input/Output Termination Recommendations section. APLL_0 Loop Filter Voltage Regulator. Connect a 0.22 F capacitor from this pin to ground. This pin is also the ac ground reference for the integrated APLL_0 external loop filter. Loop Filter Node for the APLL_0. Connect an external 15 nF capacitor from this pin to Pin 22 (LDO_0). Configurable Input/Output Pin. This pin is used for status and control of the AD9554. At power-up and reset this pin controls whether or not the M1 and M2 pins are used for the serial port connection to the optional external EEPROM. See the Multifunction Pins at Reset/Power-Up section for more information about internal 100 k pull-up or pull-down resistors. This pin is on the VDD power domain, and the logic high voltage for this pin matches the voltage of the VDD pins. Serial Data Output (SDO). In 4-wire SPI mode, this pin is used for reading serial data. The VIH/VOH of this pin tracks the VDD_SP power supply, which can be 1.5 V, 1.8 V, or 2.5 V. In SPI mode, this is the serial data input/output (SDIO) pin. In 4-wire SPI mode, data is written via this pin. In 3-wire SPI mode, data reads and writes both occur on this pin. In I2C mode, this is the serial data pin (SDA) pin. There is no internal pull-up/pull-down resistor on this pin. The VIH/VOH of this pin tracks the VDD_SP power supply, which can be 1.5 V, 1.8 V, or 2.5 V. In SPI mode, this is the serial programming clock (SCLK) pin. In I2C mode, this is the serial clock pin (SCL). The VIH/VOH of this pin tracks the VDD_SP power supply, which can be 1.5 V, 1.8 V, or 2.5 V. Chip Select in SPI Mode (CS). Active low input. When programming a device in SPI, this pin must be held low. In systems where more than one AD9554 is present, this pin enables individual programming of each AD9554. This pin has an internal 10 k pull-up resistor. The VIH of this pin tracks the VDD_SP power supply, which can be 1.5 V, 1.8 V, or 2.5 V. Serial Port Power Supply. The power supply can be 1.5 V, 1.8 V, or 2.5 V. If this pin is at the same voltage as VDD, it can be connected to VDD pins. Chip Reset. When this active low pin is asserted, the chip goes into reset. This pin has an internal 50 k pull-up resistor. The VIH of this pin tracks the VDD_SP power supply, which can be 1.5 V, 1.8 V, or 2.5 V. Rev. D | Page 18 of 116 Data Sheet AD9554 Pin No. 32 Mnemonic LF_1 Input/ Output I/O 33 LDO_1 I 36 OUT1B O 37 OUT1B O 39 OUT1A O 40 OUT1A O 43 REFB I 44 REFB I Differential input 47 REFC I Differential input 48 REFC I Differential input 51 OUT2A O 52 OUT2A O 54 OUT2B O 55 OUT2B O 58 LDO_2 I HCSL, LVDScompatible, LVPECLcompatible HCSL, LVDScompatible, LVPECLcompatible HCSL, LVDScompatible, LVPECLcompatible HCSL, LVDScompatible, LVPECLcompatible LDO bypass 59 LF_2 I/O Pin Type Loop filter for APLL_1 LDO bypass HCSL, LVDScompatible, LVPECLcompatible HCSL, LVDScompatible, LVPECLcompatible HCSL, LVDScompatible, LVPECLcompatible HCSL, LVDScompatible, LVPECLcompatible Differential input Loop filter for APLL_2 Description Loop Filter Node for the APLL_1. Connect an external 15 nF capacitor from this pin to Pin 33 (LDO_1). APLL_1 Loop Filter Voltage Regulator. Connect a 0.22 F capacitor from this pin to ground. This pin is also the ac ground reference for the integrated APLL_1 external loop filter. PLL1 Output 1B. This HCSL output can be configured as a LVDS- or LVPECLcompatible output. LVPECL and LVDS levels can be achieved by ac-coupling and using the Thevenin equivalent termination as described in the Input/Output Termination Recommendations section. PLL1 Complementary Output 1B. Complementary signal to the output provided on Pin 36 (OUT1B). PLL1 Output 1A. This HCSL output can be configured as a LVDS- or LVPECLcompatible output. LVPECL and LVDS levels can be achieved by ac-coupling and using the Thevenin equivalent termination as described in the Input/Output Termination Recommendations section. PLL1 Complementary Output 1A. Complementary signal to the output provided on Pin 39 (OUT1A). Reference B Input. This internally biased input is typically ac-coupled; when configured in this manner, it can accept any differential signal with singleended swing up to the VDD power supply. If dc-coupled, the input can be LVDS or single-ended CMOS provided that VIH VDD. Complementary Reference B Input. Complementary signal to the input provided on Pin 43 (REFB). This pin can be left floating if REFB is a single-ended input, or if REFB is not used. Complementary Reference C Input. Complementary signal to the input provided on Pin 48 (REFC). This pin can be left floating if REFC is a single-ended input, or if REFC is not used. Reference C Input. This internally biased input is typically ac-coupled; when configured in this manner, it can accept any differential signal with singleended swing up to the VDD power supply. If dc-coupled, the input can be LVDS or single-ended CMOS provided that VIH VDD. PLL2 Complementary Output 2A. Complementary signal to the output provided on Pin 52 (OUT2A). PLL2 Output 2A. This HCSL output can be configured as a LVDS- or LVPECLcompatible output. LVPECL and LVDS levels can be achieved by ac-coupling and using the Thevenin equivalent termination as described in the Input/Output Termination Recommendations section. PLL2 Complementary Output 2B. Complementary signal to the output provided on Pin 55 (OUT2B). PLL2 Output 2B. This HCSL output can be configured as a LVDS- or LVPECLcompatible output. LVPECL and LVDS levels can be achieved by ac-coupling and using the Thevenin equivalent termination as described in the Input/Output Termination Recommendations section. APLL_2 Loop Filter Voltage Regulator. Connect a 0.22 F capacitor from this pin to ground. This pin is also the ac ground reference for the integrated APLL_2 external loop filter. Loop Filter Node for the APLL_2. Connect an external 15 nF capacitor from this pin to Pin 58 (LDO_2). Rev. D | Page 19 of 116 AD9554 Data Sheet Input/ Output I/O Pin No. 60, 61, 65, 66, 67 Mnemonic M5, M6, M7, M8, M9 Pin Type 1.5 V/1.8 V CMOS 63 XOB I Differential input 64 XOA I Differential input 68 LF_3 I/O 69 LDO_3 I Loop filter for APLL_3 LDO bypass 72 OUT3B O 0 EPAD GND HCSL, LVDScompatible, LVPECLcompatible Exposed pad Description Configurable Input/Output Pins. These pins are used for status and control of the AD9554. These pins are also used at power-up and reset to determine the serial port and address. See the Multifunction Pins at Reset/Power-Up section for more information about the internal 100 k pull-up or pull-down resistors. These pins are on the VDD digital power domain (Pin 62), and the logic high voltage for this pin matches the voltage of the VDD pins. Complementary System Clock Input. Complementary signal to XOA. XOB contains internal dc biasing and must be ac-coupled with a 0.1 F capacitor except when using a crystal. When a crystal is used, connect the crystal across XOA and XOB. System Clock Input. XOA contains internal dc biasing and must be ac-coupled with a 0.1 F capacitor except when using a crystal. When a crystal is used, connect the crystal across XOA and XOB. Single-ended CMOS is also an option, but a spur may be introduced if the duty cycle is not 50%. When using XOA as a single-ended input, connect a 0.1 F capacitor from XOB to ground. Loop Filter Node for the APLL_3. Connect an external 15 nF capacitor from this pin to Pin 69 (LDO_3). APLL_3 Loop Filter Voltage Regulator. Connect a 0.22 F capacitor from this pin to ground. This pin is also the ac ground reference for the integrated APLL_3 external loop filter. PLL3 Output 3B. This HCSL output can be configured as a LVDS- or LVPECLcompatible output. LVPECL and LVDS levels can be achieved by ac-coupling and using the Thevenin equivalent termination as described in the Input/Output Termination Recommendations section. The exposed pad is the ground connection on the chip. It must be soldered to the analog ground of the printed circuit board (PCB) to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. Rev. D | Page 20 of 116 Data Sheet AD9554 TYPICAL PERFORMANCE CHARACTERISTICS fR = input reference clock frequency, fOUT = output clock frequency, fSYS = SYSCLK input frequency, and VDD at 1.8 V. -60 INTEGRATED RMS JITTER (12kHz TO 20MHz): 414fs -70 PHASE NOISE (dBc/Hz): 10Hz -82 100Hz -97 1kHz -114 10kHz -125 100kHz -129 1MHz -138 10MHz -153 FLOOR -155 -100 PHASE NOISE (dBc/Hz) -90 -110 -120 -130 -110 -120 -130 -140 -150 10 100 1k 10k 100k 1M 10M 100M -160 1k 10k 100k 1M 10M 100M -60 -90 -100 -110 -120 -130 -90 -100 -110 -120 -130 -140 -140 -150 -150 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) -160 12132-302 10 PHASE NOISE (dBc/Hz): 10Hz -80 100Hz -96 1kHz -113 10kHz -125 100kHz -128 1MHz -137 10MHz -154 FLOOR -155 -80 PHASE NOISE (dBc/Hz) -80 INTEGRATED RMS JITTER (12kHz TO 20MHz): 393fs -70 PHASE NOISE (dBc/Hz): 10Hz -69 100Hz -84 1kHz -102 10kHz -113 100kHz -113 1MHz -127 10MHz -146 FLOOR -152 10 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) Figure 4. Absolute Phase Noise (Output Driver = 21 mA Mode), fR = 19.44 MHz, fOUT = 622.08 MHz, DPLL Loop Bandwidth = 50 Hz, fSYS = 49.152 MHz Crystal 12132-307 INTEGRATED RMS JITTER (12kHz TO 20MHz): 375fs -70 Figure 7. Absolute Phase Noise (Output Driver = 21 mA Mode), fR = 19.44 MHz, fOUT = 174.703 MHz, DPLL Loop Bandwidth = 1 kHz, fSYS = 49.152 MHz Crystal -60 INTEGRATED RMS JITTER (12kHz TO 20MHz): 381fs -70 -90 -100 -110 -120 -130 -90 -100 -110 -120 -130 -140 -140 -150 -150 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) Figure 5. Absolute Phase Noise (Output Driver = 21 mA Mode), fR = 19.44 MHz, fOUT = 644.53125 MHz, DPLL Loop Bandwidth = 50 Hz, fSYS = 49.152 MHz Crystal -160 12132-303 10 PHASE NOISE (dBc/Hz): 10Hz -80 100Hz -96 1kHz -114 10kHz -125 100kHz -129 1MHz -139 10MHz -154 FLOOR -155 -80 PHASE NOISE (dBc/Hz) -80 INTEGRATED RMS JITTER (12kHz TO 20MHz): 379fs -70 PHASE NOISE (dBc/Hz): 10Hz -67 100Hz -84 1kHz -102 10kHz -113 100kHz -116 1MHz -128 10MHz -147 FLOOR -152 10 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M 12132-308 -60 -160 100 Figure 6. Absolute Phase Noise (Output Driver = 21 mA Mode), fR = 19.44 MHz, fOUT = 693.482991 MHz, DPLL Loop Bandwidth = 50 Hz, fSYS = 49.152 MHz Crystal -60 -160 10 FREQUENCY OFFSET (Hz) Figure 3. Absolute Phase Noise (Output Driver = 21 mA Mode), fR = 19.44 MHz, fOUT = 156.25 MHz, DPLL Loop Bandwidth = 50 Hz, fSYS = 49.152 MHz Crystal PHASE NOISE (dBc/Hz) -100 -150 FREQUENCY OFFSET (Hz) PHASE NOISE (dBc/Hz) -90 -140 -160 PHASE NOISE (dBc/Hz): 10Hz -63 100Hz -84 1kHz -101 10kHz -112 100kHz -116 1MHz -124 10MHz -144 FLOOR -151 -80 12132-309 PHASE NOISE (dBc/Hz) -80 INTEGRATED RMS JITTER (12kHz TO 20MHz): 427fs -70 12132-304 -60 Figure 8. Absolute Phase Noise, fR = 19.44 MHz, fOUT = 161.1328125 MHz, DPLL Loop Bandwidth = 100 Hz, fSYS = 49.152 MHz Crystal Rev. D | Page 21 of 116 AD9554 Data Sheet -80 -90 -100 -110 -120 -130 -140 -160 10 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) 12132-008 -150 1.6 WITH 100 TERMINATION RESISTOR (REQUIRED) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 100 200 300 400 500 600 700 OUTPUT FREQUENCY (MHz) 800 900 1000 Figure 10. Peak-to-Peak Differential Amplitude vs. Output Frequency, 28 mA Mode (LVPECL-Compatible Mode) with 100 Termination Resistor (Required) 1.0 0.8 0.6 0.4 0.2 0 0 100 200 300 400 500 600 700 800 900 1000 Figure 12. Single-Ended Peak-to-Peak Amplitude vs. Output Frequency, 21 mA Mode (No Termination) 3.0 2.5 NO TERMINATION RESISTOR 2.0 1.5 100 TERMINATION RESISTOR 1.0 0.5 0 0 100 200 300 400 500 600 700 OUTPUT FREQUENCY (MHz) 800 900 1000 Figure 13. Peak-to-Peak Differential Amplitude vs. Output Frequency, 21 mA Mode 1.0 1.8 0.8 1.6 0.6 NO TERMINATION RESISTOR (HCSL) 1.4 0.4 100 TERMINATION (LVDS COMPATIBLE) 0.8 0.2 0 -0.2 0.6 -0.4 0.4 -0.6 0.2 -0.8 0 0 -1.0 100 200 300 400 500 600 700 OUTPUT FREQUENCY (MHz) 800 900 1000 Figure 11. Peak-to-Peak Differential Amplitude vs. Output Frequency, 14 mA Mode 0 1 2 3 TIME (ns) 4 5 12132-400 1.0 OUTPUT (V) 1.2 12132-318 PEAK-TO-PEAK DIFFERENTIAL AMPLITUDE (V) 1.2 OUTPUT FREQUENCY (MHz) PEAK-TO-PEAK DIFFERENTIAL AMPLITUDE (V) 1.8 1.4 12132-316 PEAK-TO-PEAK DIFFERENTIAL AMPLITUDE (V) Figure 9. Absolute Phase Noise (Output Driver = 14 mA Mode), fR = 2 kHz, fOUT = 125 MHz, DPLL Loop Bandwidth = 100 Hz, fSYS = 49.152 MHz Crystal SINGLE-ENDED, NO TERMINATION 1.6 12132-312 PHASE NOISE (dBc/Hz): OFFSET LEVEL 10Hz -79 100Hz -82 1kHz -110 10kHz -127 100kHz -131 1MHz -141 10MHz -153 FLOOR -154 1.8 12132-317 INTEGRATED RMS JITTER (12kHz TO 20MHz): 408fs -70 PHASE NOISE (dBc/Hz) SINGLE-ENDED PEAK-TO-PEAK AMPLITUDE (V) -60 Figure 14. Output Waveform, 28 mA LVPECL-Compatible Mode (400 MHz) with 100 Termination Resistor Rev. D | Page 22 of 116 1.2 NO TERMINATION 100 TERMINATION 1.0 0.8 0.6 0.4 OUTPUT (V) 0.2 0 -0.2 -0.4 -0.6 -0.8 0 1 2 3 4 5 TIME (ns) -1.2 0 3 0.5 0 0.4 -3 0.3 25 0.1 0 -0.1 -0.2 -9 -12 -15 -18 -0.3 -21 -0.4 -24 -0.5 -27 1 2 3 4 5 TIME (ns) Figure 16. Output Waveform, 14 mA LVDS-Compatible Mode (400 MHz) with 100 Termination at Load 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 -30 10 12132-402 0 LOOP BW = 100Hz LOOP BW = 2kHz LOOP BW = 4kHz 100 1k 10k OFFSET FREQUENCY (Hz) 100k 12132-129 LOOP GAIN (dB) OUTPUT (V) 20 -6 0.2 Figure 19. Closed-Loop Transfer Function for 100 Hz, 2 kHz, and 4 kHz Loop Bandwidth Settings; High Phase Margin Loop Filter Setting; Figure Compliant with Telcordia GR-253 Jitter Transfer Test for Loop Bandwidths <2 kHz (Note that the bandwidth register setting is the point where the open-loop gain = 0 dB.) 3 NO TERMINATION 100 TERMINATION 0 -3 LOOP GAIN (dB) -6 -9 -12 -15 -18 -21 LOOP BW = 100Hz PEAKING: 1.3dB. -3dB: 112Hz -24 LOOP BW = 2kHz PEAKING: 1.1dB. -3dB: 2.4kHz -27 0 5 10 15 20 TIME (ns) Figure 17. Output Waveform, 21 mA Mode (100 MHz) 25 -30 12132-403 OUTPUT (V) 15 Figure 18. Output Waveform, 14 mA Mode (100 MHz) 0.6 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 10 TIME (ns) Figure 15. Output Waveform, 21 mA Mode (400 MHz) with 100 Termination at Load -0.6 5 12132-404 -1.0 LOOP BW = 4kHz. PEAKING: 1.1dB. -3dB: 5.3kHz 10 100 10k 1k OFFSET FREQUENCY (Hz) 100k 12132-230 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 AD9554 12132-401 OUTPUT (V) Data Sheet Figure 20. Closed-Loop Transfer Function for 100 Hz, 2 kHz, and 4 kHz Loop Bandwidth Settings; Normal Phase Margin Loop Filter Setting (Note that the bandwidth register setting is the point where the open-loop gain = 0 dB.) Rev. D | Page 23 of 116 AD9554 Data Sheet INPUT/OUTPUT TERMINATION RECOMMENDATIONS 0.1F Z0 = 50 15pF XOA Z0 = 50 XOB 15pF Figure 21. Destination Self-Biased Differential Receiver; Use 14 mA Mode for LVDS-Compatible Amplitude or 28 mA for LVPECL-Compatible Amplitudes (100 resistor must be as close to the destination receiver as possible.) Figure 24. System Clock Input (XOA/XOB) in Crystal Mode (The recommended CLOAD = 10 pF is shown. The values of 15 pF shunt capacitors shown here must equal 2 x (CLOAD - CSTRAY), where CSTRAY is typically 2 pF to 5 pF.) Z0 = 50 AD9554 3.3V CMOS TCXO HCSL HIGH IMPEDANCE DIFFERENTIAL RECEIVER SINGLE-ENDED (NOT COUPLED) 14mA MODE 12132-131 Figure 22. DC-Coupled HCSL Receiver 82 3.3V LVPECL SINGLE-ENDED (NOT COUPLED) 28mA MODE 0.1F Z0 = 50 127 127 12132-132 AD9554 82 0.1F XOA 150 0.1F XOB Figure 25. System Clock Input (XOA, XOB) When Using a TCXO/OCXO with 3.3 V CMOS Output VS = 3.3V Z0 = 50 330 AD9554 Z0 = 50 0.1F AD9554 12132-133 0.1F 10MHz TO 50MHz FUNDAMENTAL AT-CUT CRYSTAL WITH 10pF LOAD CAPACITANCE (C LOAD) 12132-134 100 12132-130 SINGLE-ENDED (NOT CLOSELYCOUPLED) AD9554 DOWNSTREAM DEVICE WITH HIGH IMPEDANCE INPUT AND INTERNAL DC BIAS Figure 23. Interfacing the HCSL Driver to a 3.3 V LVPECL Input (This method incorporates impedance matching and dc-biasing for bipolar LVPECL receivers. If the receiver is self-biased, the termination scheme shown in Figure 21 is recommended.) Rev. D | Page 24 of 116 Data Sheet AD9554 GETTING STARTED CHIP POWER MONITOR AND STARTUP The AD9554 monitors the voltage on the power supplies at power-up. The VDD pins provide power to the internal voltage regulators to provide a 1.2 V supply to the chip. When the internal 1.2 V supply is greater than 0.96 V 0.1 V, the device generates a 25 ms reset pulse. The power-up reset pulse is internal and independent of the RESET pin. This internal power-up reset sequence eliminates the need for the user to provide external power supply sequencing. The M0 pin to M8 pin values are latched 25 ms after the internal reset pulse, and the M0 to M9 multifunction pins behave as high impedance digital inputs and continue to do so until otherwise programmed. Activating the RESET pin initiates the same sequence with respect to the multifunction pins. Wait a minimum of 25 ms before programming the device to ensure that the power-on reset (POR) has completed. MULTIFUNCTION PINS AT RESET/POWER-UP The AD9554 Mx pins (where x is 0 through 9) have internal 100 k pull-up/pull-down resistors, except for M1 and M2, and the Mx pin defaults are detailed in Table 21. Note that M0, M5, M6, and M7, are not mentioned in Table 21 for they are not used for the EEPROM function. Table 21. Mx Pin Function at Startup Mx Pin M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 1 Startup Function IC address select EEPROM SCL EEPROM SDA Load EEPROM at startup EEPROM IC enabled on M2 and M1 pins SPI/IC select IC address select IC address select EEPROM fast IC mode None Internal Resistor 100 k pull-down None High (Logic 1) Refer to Table 22 Not applicable Not applicable Loaded EEPROM Low (Logic 0) Refer to Table 22 Not applicable Not applicable Do not load EEPROM1 100 k pull-down IC mode on M2 and M1 pins Normal Mx pin function on M1and M21 100 k pull-down 100 k pull-up 100 k pull-down 100 k pull-up IC SPI1 Refer to Table 22 Refer to Table 22 400 kHz1 Refer to Table 22 Refer to Table 22 100 kHz 100 k pull-down Not applicable Not applicable1 None 100 k pull-down Table 22. SPI/I2C Serial Port Setup M7 Don't care Don't care M6 0 1 M5 0 0 M0 Don't care Don't care 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 SPI/IC Address Not applicable Analog Devices, Inc., unified SPI (default) IC, 1101000 (0x68) IC, 1101001 (0x69)1 IC, 1101010 (0x6A) IC, 1101011 (0x6B) IC, 1101100 (0x6C) IC, 1101101 (0x6D) IC, 1101110 (0x6E) IC, 1101111 (0x6F) If M5 is high, the IC power-on default is via internal pull-up/pull-down resistors. By pulling M5 high, the user selects IC mode; the default IC address is 0x69. DEVICE REGISTER PROGRAMMING USING A REGISTER SETUP FILE The evaluation software contains a programming wizard and a convenient graphical user interface (GUI) that assists the user in determining the optimal configuration for the DPLLs, APLLs, and SYSCLK based on the desired input and output frequencies. It generates a register setup file with a .STP extension that is easily readable using a text editor. The user can configure PLL_0 through PLL_3 independently. To do so, program the common registers (such as the system clock and reference inputs) first. Next, the registers that are unique to PLL_0, PLL_1, PLL_2, or PLL_3 can be configured independently. After using the evaluation software to create the setup file, use the sequence shown in Figure 26 through Figure 29 to program the AD9554. Power-on default via a 100 k internal pull-up/pull-down resistor. M1 and M2 do not have internal pull-up/pull-down resistors. Rev. D | Page 25 of 116 AD9554 Data Sheet START USER POWER SUPPLIES INITIALIZATION AND POWER-ON RESET WAIT APPLY VDD (ALL DOMAINS) VDD SETTLED? NO YES POR: WAIT 25ms REFERENCE INPUT(S) CAN BE APPLIED ANY TIME HEREAFTER. RST_COUNT = RST_COUNT + 1 RST_COUNT = 0 ISSUE A CHIP LEVEL RESET (PIN OR SOFT RESET) CHIP LEVEL RESET LOOP SOFT WARE GENERATED AD9554 SETUP FILE* WRITE REGISTER CONTENT FROM SETUP FILE WRITE: REGISTER 0x00F = 0x01 SUBPROCESS: SYSTEM CLOCK INITIALIZATION i=0 NO RST_COUNT > 0 NO YES APLL_x ENABLED RAISE FLAG FOR DEBUGGING. READ: REGISTER 0xD00 TO REGISTER 0xD8A YES SUBPROCESS: ANALOG PLL_x INITIALIZATION i=i+1 NO i>3 YES *THE USER MUST ENSURE THAT THE AD9554 SETUP FILE INCLUDES WRITES TO REGISTER 0x0FFF, REGISTER 0x1488, REGISTER 0x1588, REGISTER 0x1688, AND REGISTER 0x1788. Figure 26. Main Process--Initialization Rev. D | Page 26 of 116 12132-100 END Data Sheet AD9554 START SYSTEM CLOCK RECALIBRATION LOOP CAL_COUNT = 0 WRITE: REGISTER 0xA00[2] = 0 VCO CALIBRATION OPERATION NO WRITE: REGISTER 0x00F = 0x01 CAL_COUNT > 1 YES END (TO RST_COUNT CHECK) WRITE: REGISTER 0xA00[2] = 1 WRITE: REGISTER 0x00F = 0x01 CAL_COUNT = CAL_COUNT + 1 SYSTEM CLOCK LOCKED AND STABLE POLLING LOOP START TIMEOUT CLOCK: TIME = 0 NO REGISTER 0xD01[1:0] = 0x3 NO TIMEOUT CLOCK: TIME > SYSCLK_TO* YES YES *SYSCLK_TO IS A CALCULATED TIMEOUT VALUE. IT IS 100ms AND SYSTEM CLOCK VALIDATION TIME (REGISTER 0x206 TO REGISTER 0x208: DEFAULT = 50ms) Figure 27. Subprocess--System Clock Initialization Rev. D | Page 27 of 116 12132-101 END AD9554 Data Sheet START APLL RECALIBRATION LOOP1 CAL_COUNT = 0 VCO CALIBRATION OPERATION WRITE: CAL REG BIT 1 = 0 APLL ALL 0 1 2 3 CAL REG 0xA00 0xA20 0xA40 0xA60 0xA80 LOCK REG 0xD00 2 0xD20 0xD40 0xD60 0xD80 SYNC REG 0xA00 0xA20 0xA40 0xA60 0xA80 NO WRITE: REGISTER 0x00F = 0x01 CAL_COUNT > 1 YES END (TO RST_COUNT CHECK) WRITE: CAL REG BIT 1 = 1 WRITE: REGISTER 0x00F = 0x01 CAL_COUNT = CAL_COUNT + 1 START TIMEOUT CLOCK: TIME = 0 APLL LOCK DETECT POLLING LOOP NO LOCK REG BIT 3 = 1 NO TIMEOUT CLOCK: TIME > 200ms YES YES ENSURE THAT CAL REG BIT 1 = 0 FOR ALL CALIBRATION REGISTERS (0xA00, 0xA20, 0xA40, 0xA60, 0xA80) WRITE: SYNC REG BIT 2 = 1 DISTRIBUTION SYNCHRONIZATION OPERATION WRITE: REGISTER 0x00F = 0x01 WRITE: SYNC REG BIT 2 = 0 WRITE: REGISTER 0x00F = 0x01 END THAT THE CALIBRATE ALL AND SOFT SYNC ALL BITS IN REGISTER 0x0A00 CAN BE USED IF THE USER WANTS TO CALIBRATE OR SYNC ALL FOUR PLLs SIMULTANEOUSLY INSTEAD OF ONE AT A TIME. HOWEVER, THE USER MUST STILL VERIFY THAT ALL FOUR APLLs ARE LOCKED BY READING THE INDIVIDUAL APLL LOCK REGISTERS. 2REGISTER 0x0D00 CAN ONLY BE USED TO VERIFY THE LOCK STATE OF EACH APLL IF THE CORRESPONDING DPLL IS ALSO LOCKED. Figure 28. Subprocess--Analog PLL Initialization Rev. D | Page 28 of 116 12132-102 1NOTE Data Sheet AD9554 START WRITE: SYNC REG BIT 2 = 1 WRITE: REGISTER 0x00F = 0x01 WRITE NEW DPLL CONFIGURATION DISTRIBUTION SYNCHRONIZATION: DISABLE OUTxA/OUTxB TOGGLING CHANNEL 0 1 2 3 SYNC REG 0xA20 0xA40 0xA60 0xA80 SOFTWARE GENERATED AD9554 RELATED REGISTERS FOR DIFFERENT DPLL CONFIGURATIONS WRITE: REGISTER 0x00F = 0x01 OUTPUT CLOCK DISTRIBUTION SYNCHRONIZATION FOR PLL_x 12132-103 SUBPROCESS: ANALOG PLL_x INITIALIZATION END Figure 29. Main Process--Individual DPLL Reconfiguration Rev. D | Page 29 of 116 AD9554 Data Sheet REGISTER PROGRAMMING OVERVIEW System Clock Configuration This section provides a programming overview of the register blocks in the AD9554, describing what they do and why they are important. This is supplemental information only needed when loading the registers without using the .STP file. The system clock multiplier (SYSCLK) parameters are at Register 0x0200 to Register 0x0208. For optimal performance, use the following steps: The AD9554 evaluation software contains a wizard that determines the register settings based on the input and output frequencies of the user. It is strongly recommended that the evaluation software determine these settings. 1. 2. 3. Multifunction Pins (Optional) To use any of the multifunction pins for status or control, this step is required. The multifunction pin parameters are located at Register 0x0100 to Register 0x010C. Table 154 has a list of the Mx pin output functions, and Table 155 has a list of Mx pin input functions. IRQ Functions (Optional) To use the IRQ feature, this step is required. The IRQ functions are divided into five groups: common, PLL_0, PLL_1, PLL_2, and PLL_3. First, choose the events that trigger an IRQ and then set them in Register 0x010F to Register 0x011D. Next, an Mx pin must be assigned to the IRQ function. The user can choose to dedicate one Mx pin to each of the five IRQ groups, or one Mx pin can be assigned for all IRQs. The IRQ monitor registers are located at Register 0x0D08 to Register 0x0D16. If the desired bits in the IRQ mask registers at Register 0x010F to Register 0x011D are set high, the appropriate IRQ monitor bit at Register 0x0D08 to Register 0x0D16 is set high when the indicated event occurs. Individual IRQ events are cleared by using the IRQ clearing registers at Register 0x0A05 to Register 0x0A14 or by setting the clear all IRQs bit (Register 0x0A05[0]) to 1b. The default values of the IRQ mask registers are such that interrupts are not generated. The default IRQ pin (and Mx pins) mode is active high CMOS. The user can also select active low CMOS, open-drain PMOS, and open-drain NMOS independently on any of these pins. Watchdog Timer (Optional) To use the watchdog timer, this step is required. The watchdog timer control is located at Register 0x010D and Register 0x010E. The watchdog timer is disabled by default. The watchdog timer is useful for generating an IRQ at a fixed interval. The timer is reset by setting the clear watchdog timer bit in Register 0x0A05[7] to 1. The user can also program an Mx pin for the watchdog timer output. In this mode, the Mx pin generates a 40 ns pulse every time the watchdog timer expires. 4. 5. 6. Set the system clock PLL input type and divider values. Set the system clock period. It is essential to program the system clock period because many of the AD9554 subsystems rely on this value. Set the system clock stability timer. The system clock stability timer specifies the amount of time that the system clock PLL must be locked before the device declares that the system clock is stable. It is critical that the system clock stability timer be set long enough to ensure that the external source is completely stable when the timer expires. For instance, a temperature compensated crystal oscillator (TCXO) can take longer than 50 ms (the default value for the stability timer) to stabilize after power is applied. Update all registers (Register 0x000F = 0x01). To calibrate the system clock on the next IO_UPDATE, write Register 0x0A00 = 0x04. Update all registers (Register 0x000F = 0x01). Important Notes If Bit 2 in Register 0x0A00 is set independently to initiate a system clock PLL calibration, leave this bit set to 1 in all subsequent writes to Register 0x0A00. If this bit is accidentally cleared, recalibrate the system clock VCO or issue a calibrate all command by setting Bit 1 in Register 0x0A00 and by issuing an IO_UPDATE (Register 0x000F = 0x01). In addition, the system clock PLL must be locked for the digital PLL blocks to function correctly and to read back the registers updated on the system clock domain. These registers include the status registers, as well as the free running tuning word. APLL calibration and input reference monitoring and validation require that the system clock be stable. Therefore, first ensure that the system clock is stable by checking Bit 1 in Register 0x0D01 when debugging the AD9554. Reference Inputs The reference input parameters and reference dividers are common to all PLLs; there is only one reference divider (R divider) for each reference input. The register address for each reference input follows: Register 0x0300 to Register 0x031E for REFA Register 0x0320 to Register 0x033E for REFB Register 0x0340 to Register 0x035E for REFC Register 0x0360 to Register 0x037E for REFD These registers include the following settings: Rev. D | Page 30 of 116 Reference logic type (such as differential, single-ended) Reference divider (20-bit R divider value) Reference input period and tolerance Reference validation timer Phase and frequency lock detector settings Phase step threshold Data Sheet AD9554 Other reference input settings are in the following registers: Reference input enable information is found in the DPLL Feedback Dividers section. Reference power-down information is found in Register 0x0A01. Reference switching mode settings are found in Register 0x0A22 (DPLL_0), Register 0x0A42 (DPLL_1), Register 0x0A62 (DPLL_2), and Register 0x0A82 (DPLL_3). The APLL calibration and synchronization bits reside in the following registers: Register 0x0A20 (APLL_0) Register 0x0A40 (APLL_1) Register 0x0A60 (APLL_2) Register 0x0A80 (APLL_3) DPLL Feedback Dividers The DPLL control parameters are separate for DPLL_0 through DPLL_3. They reside in the following registers: Each DPLL has separate feedback divider settings for each reference input, which allows the user to have each digital PLL perform a different frequency translation. However, there is only one reference divider (R divider) for each reference input. The feedback divider register settings for DPLL_0 reside in the following registers. Feedback divider registers for the remaining three DPLLs mimic the structure of the DPLL_0 registers, but are offsets by 0x0100 registers. Digital PLL (DPLL) Controls and Settings Register 0x0400 to Register 0x041E (DPLL_0) Register 0x0500 to Register 0x051E (DPLL_1) Register 0x0600 to Register 0x061E (DPLL_2) Register 0x0700 to Register 0x071E (DPLL_3) These registers include the following settings: 30-bit free running frequency DPLL pull-in range limits DPLL closed-loop phase offset Tuning word history control (for holdover operation) Phase slew control (for controlling the phase slew rate during a closed-loop phase adjustment) Demapping control With the exception of the free running tuning word, the default values of these registers are fine for normal operation. The free running frequency of the DPLL determines the frequency that appears at the APLL input when user free run mode is selected. The correct free running frequency is required for the APLL to calibrate and lock correctly. Output PLLs (APLLs) and Output Drivers The registers that control the APLLs and output drivers reside in the following registers: Register 0x0430 to Register 0x043E (APLL_0) Register 0x0530 to Register 0x053E (APLL_1) Register 0x0630 to Register 0x063E (APLL_2) Register 0x0730 to Register 0x073E (APLL_3) These registers include the following settings: Reference priority Reference input enable (separate for each DPLL) DPLL loop bandwidth DPLL loop filter DPLL feedback divider (integer portion) DPLL feedback divider (fractional portion) DPLL feedback divider (modulus portion) Common Operational Controls The common operational controls reside at Register 0x0A00 to Register 0x0A14 and include the following: The following functions are controlled in these registers: Register 0x0440 to Register 0x44C (DPLL_0 for REFA) Register 0x044D to Register 0x459 (DPLL_0 for REFB) Register 0x045A to Register 0x466 (DPLL_0 for REFC) Register 0x0467 to Register 0x473 (DPLL_0 for REFD) DPLL_1 for REFA to DPLL_1 for REFD: Same as DPLL_0 but offset by 0x0100 registers DPLL_2 for REFA to DPLL_2 for REFD: Same as DPLL_0 but offset by 0x0200 registers DPLL_3 for REFA to DPLL_3 for REFD: Same as DPLL_0 but offset by 0x0300 registers APLL settings (feedback divider, charge pump current) Output synchronization mode Output divider values Output enable/disable (disabled by default) Output logic type Rev. D | Page 31 of 116 Simultaneous calibration and synchronization of all PLLs Global power-down Reference power-down Reference validation override IRQ clearing (for all IRQs) AD9554 Data Sheet PLL_0 Through PLL_3 Operational Controls The PLL_0 through PLL_3 operational controls are located at Register 0x0A20 to Register 0x0A84 and include the following: APLL calibration and synchronization Output driver enable and power-down DPLL reference input switching modes DPLL open-loop phase stepping control The user free run bits that enable user free run mode reside in the following registers: Register 0x0A22 = 0x01 (DPLL_0) Register 0x0A42 = 0x01 (DPLL_1) Register 0x0A62 = 0x01 (DPLL_2) Register 0x0A82 = 0x01 (DPLL_3) Generate the Output Clock APLL VCO Calibration VCO calibration ensures that the VCO has sufficient operating margin to function across the full temperature range. The user can calibrate each of the four VCOs independently of one another. When calibrating the APLL VCO, it is important to remember the following conditions: APLL VCO calibration occurs on the low to high transition of the APLL VCO calibration bit (Register 0x0A20[1] for APLL_0, Register 0x0A40[1] for APLL_1, Register 0x0A60[1] for APLL_2, and Register 0x0A80[1] for APLL_3). The VCO calibration bit is not an autoclearing bit. Therefore, this bit must be cleared (and an IO_UPDATE issued) before the APLL is recalibrated. The best way to monitor successful APLL calibration is by monitoring the APLL locked bit in the following registers: Register 0x0D20[3] for APLL_0, Register 0x0D40[3] for APLL_1, Register 0x0D60[3] for APLL_2, and Register 0x0D80[3] for APLL_3. The APLL VCO calibration does not occur until the system clock is stable. The APLL VCO must have the correct frequency from the 30-bit digitally controlled oscillator (DCO) during calibration. The free running tuning word is found in Register 0x0400 to Register 0x0403 (DPLL_0), Register 0x0500 to Register 0x0503 (DPLL_1), Register 0x0600 to Register 0x0603 (DPLL_2), and Register 0x0700 to Register 0x0703 (DPLL_3). The APLL VCO must be recalibrated any time the APLL frequency changes. If Register 0x0435 (for PLL_0), Register 0x0535 (for PLL_1), Register 0x0635 (for PLL_2), or Register 0x0735 (for PLL_3) is programmed for automatic clock distribution synchronization via the DPLL phase or frequency lock, the synthesized output signal appears at the clock distribution outputs. Otherwise, set and then clear the soft sync bit (Bit 2 in Register 0x0A20 for APLL_0, Bit 2 in Register 0x0A40 for APLL_1, Bit 2 in Register 0x0A60 for APLL_2, and Bit 2 in Register 0x0A80 for APLL_3) or use a multifunction pin input (if programmed accordingly) to generate a clock distribution sync pulse. This sync pulse causes the synthesized output signal to appear at the clock distribution outputs. Note that the sync pulse is delayed until the APLL achieves lock following APLL calibration. Generate the Reference Acquisition After the registers are programmed, the DPLLs lock to the reference input that has been manually selected (if any), or the first available reference that has the highest priority. Rev. D | Page 32 of 116 Data Sheet AD9554 THEORY OF OPERATION XOB REF OR XTAL SYSCLK MULTIPLIER x2 /2, /4, /8 LOOP FILTER SYSTEM CLOCK INPUT REFERENCE FREQUENCY RANGE: 2kHz TO 1000MHz REFA REFA A REFB REFB B /RB REFC REFC C /RC REFD REFD D /RD DPFD /RA REFERENCE MONITORS AND CROSSPOINT MUX TW CLAMP NCO_0 PFD/CP FREE RUN TUNING WORD LF /N0 FRAC0 / MOD0 /M0 VCO_0 PLL1 SAME DETAIL AS PLL0 VCO_2 RANGE = 4842MHz TO 5650MHz RESET PLL2 CONTROL INTERFACE/LOGIC AND EEPROM INTERFACE SDIO/SDA CS SAME DETAIL AS PLL0 VCO_3 RANGE = 4040MHz TO 4748MHz SDO /Q0_B OUT0B OUT0B /P0 OUT1A OUT1A OUT1B OUT1B OUT2A OUT2A OUT2B OUT2B OUT3A OUT3A OUT3B OUT3B 12132-035 M0 M1 M2 M3 M4 M5 M6 M7 M8 PLL3 M9 OUT0A OUT0A 2424MHz TO 3132MHz PLL0 SAME DETAIL AS PLL0 VCO_1 RANGE = 3232MHz TO 3905MHz SCLK/SCL /Q0_A OUTPUT FREQUENCY RANGE: 430kHz TO 941MHz XOA Figure 30. Detailed Block Diagram OVERVIEW The AD9554 provides clocking outputs that are directly related in phase and frequency to the selected (active) reference but with jitter characteristics governed by the system clock, the DCO, and the analog output PLL (APLL). The AD9554 can be thought of as four copies of the AD9557 inside one package, with a 4:4 crosspoint controlling the reference inputs. The AD9554 supports up to four reference inputs and input frequencies ranging from 2 kHz to 1000 MHz. The cores of this device are four digital phase-locked loops (DPLLs). Each DPLL has a programmable digital loop filter that greatly reduces jitter transferred from the active reference to the output, and these four DPLLs operate completely independently of each other. The AD9554 supports both manual and automatic holdover. While in holdover, the AD9554 continues to provide an output as long as the system clock is present. The holdover output frequency is a time average of the output frequency history prior to the transition to the holdover condition. The device offers manual and automatic reference switchover capability if the active reference is degraded or fails completely. The AD9554 also has adaptive clocking capability that allows the user to dynamically change the DPLL divide ratios while the DPLLs are locked. The AD9554 includes a system clock multiplier, four DPLLs, and four APLLs. The input signal goes first to the DPLL, which performs the jitter cleaning and most of the frequency translation. Each DPLL features a 30-bit DCO output that generates a signal in the range of 283 MHz to 345 MHz. The DCO output goes to the APLL, which multiplies the signal up to a range of 2.4 GHz to 5.6 GHz. This signal is then sent to the clock distribution section, which consists of a P divider cascaded with 10-bit channel dividers (divide by 1 to divide by 1024). The XOA and XOB inputs provide the input for the system clock. These pins accept a reference clock in the 10 MHz to 268 MHz range or a 10 MHz to 50 MHz crystal connected directly across the XOA and XOB inputs. The system clock provides the clocks to the frequency monitors, the DPLLs, and internal switching logic. Each APLL on the AD9554 has two differential output drivers. Each of the eight output drivers has a dedicated 10-bit programmable post divider. Each differential driver operates up to 1.25 GHz and is an HCSL driver with a 58 internal termination resistor on each leg. There are three drive strengths: Rev. D | Page 33 of 116 The 14 mA mode is used for HCSL and ac-coupled LVDS. When used as an LVDS-compatible driver, it must be accoupled and terminated with a 100 resistor across the differential pair. The 28 mA mode produces a voltage swing and is compatible with LVPECL. If LVPECL signal levels are required, the designer must ac-couple the AD9554 output. The 21 mA mode is halfway in between the two other settings. AD9554 Data Sheet The AD9554 also includes a demapping control function that allows the user to adjust each of the AD9554 output frequencies dynamically by periodically writing the actual level and desired level of a first in, first out (FIFO). These levels are intended to match the actual levels on the user system. REFERENCE INPUT PHYSICAL CONNECTIONS Four pairs of pins (REFA, REFA to REFD, REFD) provide access to the reference clock receivers. To accommodate input signals with slow rising and falling edges, both the differential and single-ended input receivers employ hysteresis. Hysteresis also ensures that a disconnected or floating input does not cause the receiver to oscillate. When configured for differential operation, the input receivers accommodate either ac- or dc-coupled input signals. If the input receiver is configured for dc-coupled LVDS mode, the input receivers are capable of accepting dc-coupled LVDS signals; however, only up to a maximum of 10.24 MHz. For frequencies greater than that, ac-couple the input clock and use ac-coupled differential mode. The receiver is internally dc biased to handle ac-coupled operation; however, there is no internal 50 or 100 termination. When configured for single-ended operation, the input receivers exhibit a pull-down load of 47 k (typical). See Register 0x0300 to Register 0x037E for the settings for the reference inputs. The use of two tolerance values provides hysteresis for the monitor decision logic. The inner tolerance applies to a previously faulted reference and specifies the largest period tolerance that a previously faulted reference can exhibit before it qualifies as unfaulted. The outer tolerance applies to an already unfaulted reference. It specifies the largest period tolerance that an unfaulted reference can exhibit before being faulted. To produce decision hysteresis, the inner tolerance must be less than the outer tolerance. That is, a faulted reference must meet tighter requirements to become unfaulted than an unfaulted reference must meet to become faulted. Reference Validation Timer Each reference input has a dedicated validation timer. The validation timer establishes the amount of time that a previously faulted reference must remain unfaulted before the AD9554 declares that it is valid. The timeout period of the validation timer is programmable via a 16-bit register (Address 0x030F and Address 0x0310 for Reference A). The 16-bit number stored in the validation register represents units of milliseconds (ms), which yields a maximum timeout period of 65,535 ms. It is possible to disable the validation timer by programming the validation timer to 0. With the validation timer disabled, the user must validate a reference manually via the manual reference validation override controls register (Register 0x0A02). Reference Validation Override Control REFERENCE MONITORS The user can also override the reference validation logic and either force an invalid reference to be treated as valid or force a valid reference to be treated as an invalid reference. These controls are in Register 0x0A02 to Register 0x0A03. The accuracy of the input reference monitors depends on a known and accurate system clock period. Therefore, the function of the reference monitors is not operable until the system clock is stable. REFERENCE INPUT BLOCK Reference Period Monitor Each reference input has a dedicated monitor that repeatedly measures the reference period. The AD9554 uses the reference period measurements to determine the validity of the reference based on a set of user provided parameters in the reference input area of the register map. See Register 0x0304 through Register 0x030E for the settings for Reference A, Register 0x0324 through Register 0x032E for the settings for Reference B, Register 0x0344 through Register 0x034E for the settings for Reference C, and Register 0x0364 through Register 0x036E for the settings for Reference D. The monitor compares the measured period of a particular reference input with the parameters stored in the profile register assigned to that same reference input. The parameters include the reference period, an inner tolerance, and an outer tolerance. A 40-bit number defines the reference period in units of femtoseconds (fs). A 20-bit number defines the inner and outer tolerances. The value stored in the register is the reciprocal of the tolerance specification. For example, a tolerance specification of 50 ppm yields a register value of 1/(50 ppm) = 1/0.000050 = 20,000 (0x04E20). Unlike the AD9557, the AD9554 separates the DPLL reference dividers from the feedback dividers. The reference input block includes the input receiver, the reference divider (R divider), and the reference input frequency monitor for each reference input. The reference input settings for REFA are grouped together in Register 0x0300 to Register 0x031E. The corresponding registers for REFB through REFD are the following: Register 0x320 to Register 0x33E, Register 0x340 to Register 0x35E, and Register 0x0360 to Register 0x037E, respectively. These registers include the following settings: Rev. D | Page 34 of 116 Reference logic type (such as differential, single-ended) Reference divider (20-bit R divider value) Reference input period and tolerance Reference validation timer Phase and frequency lock detector settings Phase step threshold Data Sheet AD9554 The reference prescaler reduces the frequency of this signal by an integer factor, R + 1, where R is the 20-bit value stored in the appropriate profile register and 0 R 1,048,575. Therefore, the frequency at the output of the R divider (or the input to the time-to-digital converter [TDC]) is as follows: fTDC An overview of the five operating modes follows: Automatic revertive mode. The device selects the highest priority valid reference and switches to a higher priority reference if it becomes available, even if the reference in use is still valid. In this mode, the user reference is ignored. Automatic nonrevertive mode. The device stays with the currently selected reference as long as it is valid, even if a higher priority reference becomes available. The user reference is ignored in this mode. Manual with automatic fallback mode. The device uses the user reference for as long as it is valid. If it becomes invalid, the reference input with the highest priority is chosen in accordance with the priority-based algorithm. Manual with holdover fallback mode. The user reference is the active reference until it becomes invalid. At that point, the device goes into holdover. Full manual mode without holdover fallback. The user reference is the active reference, regardless of whether it is valid. fR R 1 After the R divider, the signal passes to a 4:4 crosspoint that allows any reference input signal to go to any DPLL. Each DPLL on the AD9554 has an independent set of feedback dividers for each reference input. A description of these settings can be found in the Digital PLL (DPLL) Core section. The AD9554 evaluation software includes a frequency planning wizard that configures the profile parameters based on the input and output frequencies. REFERENCE SWITCHOVER An attractive feature of the AD9554 is its versatile reference switchover capability. The flexibility of the reference switchover functionality resides in a sophisticated prioritization algorithm that is coupled with register-based controls. This scheme provides the user with maximum control over the state machine that handles the reference switchover. The main reference switchover control resides in the user mode registers in the PLL_0 through PLL_3 operational controls registers. The reference switching mode bits for each DPLL include the following: Register 0x0A22[4:2] for DPLL_0 Register 0x0A42[4:2] for DPLL_1 Register 0x0A62[4:2] for DPLL_2 Register 0x0A82[4:2] for DPLL_3 The user also can force the device directly into holdover or free run operation via the user holdover and user free run bits. In free run mode, the free run frequency tuning word registers define the free run output frequency. In holdover mode, the output frequency depends on the holdover control settings (see the Holdover section). Phase Build-Out Reference Switching The AD9554 supports phase build-out reference switching, which refers to a reference switchover that completely masks any phase difference between the previous reference and the new reference. That is, there is virtually no phase change detectable at the output when a phase build-out switchover occurs. These bits allow the user to select one of the five operating modes of the reference switchover state machine that follows: DIGITAL PLL (DPLL) CORE The AD9554 contains four separate DPLL cores (one each for DPLL_0 through DPLL_3), and each core operates independently of one another. A diagram of a single core is shown in Figure 27. Many of the blocks shown in this diagram are purely digital. Automatic revertive mode Automatic nonrevertive mode Manual with automatic fallback mode Manual with holdover fallback mode Full manual mode without holdover fallback DPLL Overview SYSTEM CLOCK /N0 REF INPUT MUX FRAC0/ MOD0 FREE RUN TW DIGITAL LOOP FILTER + TUNING WORD CLAMP AND HISTORY 24-BIT/24-BIT 18-BIT INTEGER RESOLUTION TO APLL_0 FROM APLL_0 Figure 31. DPLL_0 Core Rev. D | Page 35 of 116 30-BIT NCO R DIVIDER (20-BIT) 12132-137 REF INPUT DPFD In automatic modes, a fully automatic priority-based algorithm selects the active reference. When programmed for automatic mode, the device chooses the highest priority valid reference. When two or more references have the same priority, REFA has preference over REFB, and so on in alphabetical order. However, the reference position is used as a tiebreaker only and does not initiate a reference switch. AD9554 Data Sheet Programmable Digital Loop Filter The AD9554 loop filter is a third-order digital IIR filter that is analogous to the third-order analog filter shown in Figure 28. R3 fTDC = fR/ f R C1 R 1 R2 C3 C2 This is the frequency used by the TDC inside the DPLL. A TDC samples the output of the R divider. The TDC/phase frequency detector (PFD) produces a time series of digital words and delivers them to the digital loop filter. The digital loop filter offers the following: The determination of the filter response by numeric coefficients rather than by discrete component values The absence of analog components (R/L/C) that eliminate tolerance variations due to aging The absence of thermal noise associated with analog components The absence of control node leakage current associated with analog components (a source of reference feedthrough spurs in the output spectrum of a traditional APLL) The digital loop filter produces a time series of digital words at its output and delivers them to the frequency tuning input of a - modulator. The digital words from the loop filter steer the - modulator frequency toward frequency and phase lock with the input signal (fTDC). Each DPLL includes a feedback divider that causes the digital loop to operate at an integer-plus-fractional multiple. The output of the DPLL is FRAC fOUT_DPLL fTDC (N 1) MOD where: N is the 18-bit value stored in the appropriate profile registers (Register 0x0444 to Register 0x0446 for DPLL_0 REFA). FRAC and MOD are the 24-bit numerators and denominators of the fractional feedback divider block. The fractional portion of the feedback divider can be bypassed by setting FRAC or MOD to 0. Note that there are four DPLLs. In the Register Map section and the Register Map Bit Descriptions section, N0, FRAC0, and MOD0 are used for DPLL_0, and N1, FRAC1, MOD1 are used for DPLL_1, and so on. For optimal performance, the DPLL output frequency is typically 300 MHz to 350 MHz. Note that the DPLL output frequency is the same as APLL input frequency. TDC/PFD The PFD is an all-digital block. It compares the digital output from the TDC (which relates to the active reference edge) with the digital word from the feedback block. It uses a digital code pump (rather than a conventional charge pump) to generate the error signal that steers the - modulator frequency toward phase lock. 12132-015 The start of the DPLL signal chain is the reference signal, fR, which has been divided by the R divider and then routed through the crosspoint switch to the DPLL. The frequency of this signal (fTDC) is Figure 32. Third-Order Analog Loop Filter The AD9554 has a default loop filter coefficient for two DPLL settings: nominal (70) phase margin and high (88.5) phase margin. The high phase margin setting is for applications that require <0.1 dB of closed-loop peaking. While these settings do not normally need to be changed, the user can contact Analog Devices for assistance with calculating new coefficients to tailor the loop filter to specific requirements. The AD9554 loop filter block features a simplified architecture in which the user enters the desired loop characteristics (such as loop bandwidth) directly into the DPLL registers. This architecture makes the calculation of individual coefficients unnecessary in most cases, while still offering extensive flexibility. DPLL Digitally Controlled Oscillator (DCO) Free Run Frequency The AD9554 uses a - modulator as a DCO. The DCO free run frequency can be calculated by f DCO_FREERUN f SYS 1 DCOint FTW0 230 where: fSYS is the system clock frequency. See the System Clock (SYSCLK) section for information on calculating the system clock frequency. DCOint is the DCO integer setting. The DCO integer is usually 7, and it can be found in Register 0x0404[3:0] for DPLL_0. FTW0 is the value in Register 0x0400 to Register 0x0403 for DPLL_0 (see Table 32 for corresponding values for DPLL_1 through DPLL_3). Adaptive Clocking The AD9554 supports adaptive clocking applications such as asynchronous mapping and demapping. For these applications, the output frequency can be dynamically adjusted by up to 100 ppm from the nominal output frequency without manually breaking the DPLL loop and reprogramming the device. The following registers are used in this function: Register 0x0444 to Register 0x0446 (DPLL_0 N0 divider) Register 0x0447 to Register 0x0449 (DPLL_0 FRAC0 divider) Register 0x044A to Register 0x044C (DPLL_0 MOD0 divider) Note that the register values shown are for REFA/DPLL_0. There are corresponding registers for all reference input and DPLL combinations. Rev. D | Page 36 of 116 Data Sheet AD9554 Writing to these registers requires an IO_UPDATE by writing 0x01 to Register 0x000F before the new values take effect. To make small adjustments to the output frequency, vary the FRAC (FRAC0 through FRAC3) and issue an IO_UPDATE. The advantage to using only FRAC to adjust the output frequency is that the DPLL does not briefly enter holdover. Therefore, the FRAC bit can be updated as quickly as the phase detector frequency of the DPLL. Writing to the N (N0 through N3) and MOD (M0 through M3) dividers allows larger changes to the output frequency. When the AD9554 detects a write in the N or MOD value, it automatically enters and exits holdover for a brief instant without any disturbance in the output frequency. This limits how quickly the output frequency can be adapted. It is important to note that the amount of frequency adjustment is limited to 100 ppm before the output PLL (APLL) needs a recalibration. Variations larger than 100 ppm are possible, but such variations can compromise the ability of the AD9554 to maintain lock over temperature extremes. It is also important to remember that the rate of change in output frequency depends on the DPLL loop bandwidth. DPLL Phase Lock Detector The DPLL contains an all-digital phase lock detector. The user controls the threshold sensitivity and hysteresis of the phase detector via the profile registers. The lock detector behaves in a manner analogous to water in a tub (see Figure 29). The total capacity of the tub is 4096 units, with -2048 denoting empty, 0 denoting the 50% point, and +2048 denoting full. The tub also has a safeguard to prevent overflow. Furthermore, the tub has a low water mark at -1024 and a high water mark at +1024. To change the water level, the user adds water with a fill bucket or removes water with a drain bucket. The user specifies the size of the fill and drain buckets via the 8-bit fill rate and drain rate values in the profile registers. The water level in the tub is what the lock detector uses to determine the lock and unlock conditions. When the water level is below the low water mark (-1024), the lock detector indicates an unlock condition. Conversely, when the water level is above the high water mark (+1024), the lock detector indicates a lock condition. When the water level is between the marks, the lock detector holds its last condition. This concept appears graphically in Figure 29, with an overlay of an example of the instantaneous water level (vertical) vs. time (horizontal) and the resulting lock/unlock states. PREVIOUS STATE LOCKED UNLOCKED During any given PFD phase error sample, the lock detector either adds water with the fill bucket or removes water with the drain bucket (one or the other but not both). The decision of whether to add or remove water depends on the threshold level specified by the user. The phase lock threshold value is a 24-bit number stored in the profile registers and is expressed in picoseconds. Thus, the phase lock threshold extends from 10 ns to 16.7 s and represents the magnitude of the phase error at the output of the PFD. The phase lock detector compares each phase error sample at the output of the PFD to the programmed phase threshold value. If the absolute value of the phase error sample is less than or equal to the programmed phase threshold value, the detector control logic dumps one fill bucket into the tub. Otherwise, it removes one drain bucket from the tub. Note that it is the magnitude, relative to the phase threshold value, that determines whether to fill or drain the bucket, and not the polarity of the phase error sample. If more filling is taking place than draining, the water level in the tub eventually rises above the high water mark (+1024), which causes the lock detector to indicate lock. If more draining is taking place than filling, the water level in the tub eventually falls below the low water mark (-1024), which causes the lock detector to indicate unlock. The ability to specify the threshold level, fill rate, and drain rate enables the user to tailor the operation of the lock detector to the statistics of the timing jitter associated with the input reference signal. Note that whenever the AD9554 enters the free run or holdover mode, the DPLL phase lock detector indicates an unlocked state. However, when the AD9554 performs a reference switch, phase step detection, or loop bandwidth change, the state of the lock detector prior to the switch is preserved during the transition period. DPLL Frequency Lock Detector The operation of the frequency lock detector is identical to that of the phase lock detector. The only difference is that the fill or drain decision is based on the period deviation between the reference and feedback signals of the DPLL instead of the phase error at the output of the PFD. The frequency lock detector uses a 24-bit frequency threshold register specified in units of picoseconds. Thus, the frequency threshold value extends from 10 ps to 16.7 s. It represents the magnitude of the difference in period between the reference and feedback signals at the input to the DPLL. For example, if the divided down reference signal is 80 kHz and the feedback signal is 79.32 kHz, the period difference is approximately 107.16 ns (|1/80,000 - 1/79,320| 107.16 ns). Frequency Clamp 2048 LOCK LEVEL 1024 FILL RATE DRAIN RATE UNLOCK LEVEL -1024 -2048 Figure 33. Lock Detector Diagram 12132-017 0 The AD9554 digital PLL features a digital tuning word clamp that ensures that the digital PLL output frequency stays within a defined range. This feature is very useful to eliminate undesirable behavior in cases where the reference input clocks may be unpredictable. Rev. D | Page 37 of 116 AD9554 Data Sheet The tuning word clamp is also useful to guarantee that the APLL never loses lock by ensuring that the APLL VCO frequency stays within its tuning range. Frequency Tuning Word History The AD9554 has the ability to track the history of the tuning word samples generated by the DPLL digital loop filter output. It does so by periodically computing the average tuning word value over a user-specified interval. This average tuning word is used during holdover mode to maintain the average frequency when no input references are present. LOOP CONTROL STATE MACHINE Switchover Switchover occurs when the loop controller switches directly from one input reference to another. The AD9554 handles a reference switchover by briefly entering holdover mode, loading the new DPLL parameters, and then immediately recovering. During the switchover event, however, the AD9554 preserves the status of the lock detectors to avoid phantom unlock indications. Holdover The holdover state of the DPLL is typically used when none of the input references are present; although, the user can also manually engage holdover mode. In holdover mode, the output frequency remains constant. The accuracy of the AD9554 in holdover mode is dependent on the device programming and availability of the tuning word history. Recovery from Holdover When in holdover and a valid reference becomes available, the device exits holdover operation. The loop state machine restores the DPLL to closed-loop operation, locks to the selected reference, and sequences the recovery of all the loop parameters based on the profile settings for the active reference. Note that, if the DPLL_x user holdover bit is set, the device does not automatically exit holdover when a valid reference is available. However, automatic recovery can occur after clearing the user holdover bit. Rev. D | Page 38 of 116 Data Sheet AD9554 SYSTEM CLOCK (SYSCLK) SYSCLK INPUTS Functional Description The SYSCLK circuit provides a low jitter, stable, high frequency clock for use by the rest of the chip. The XOA and XOB pins connect to the internal SYSCLK multiplier. The SYSCLK multiplier can synthesize the system clock by connecting a crystal resonator across the XOA and XOB input pins or by connecting a low frequency clock source. The optimal signal for the system clock input is either a crystal in the 50 MHz range or an ac-coupled square wave with 800 mV p-p amplitude. SYSCLK Reference Frequency For the AD9554 to function properly, enter the system clock reference frequency into Register 0x0202 to Register 0x0205. The ability of the AD9554 to accurately measure the frequency of the reference input depends on how accurately this register setting matches the frequency on the system clock input. Choosing the SYSCLK Source There are two internal paths for the SYSCLK input signal: crystal resonator (XTAL) and nonXTAL. Using a TCXO for the system clock is a common use for the nonXTAL path. Applications requiring DPLL loop bandwidths of less than 50 Hz or high stability in holdover mode require a TCXO or oven controlled crystal oscillator (OCXO). As an alternative to the 49.152 MHz crystal for these applications, the AD9554 reference design uses a 19.2 MHz TCXO, which offers excellent holdover stability and a good combination of low jitter and low spurious content. The differential receiver connected to the XOA and XOB pins is self-biased to a dc level of ~0.6 V, and ac coupling is strongly recommended to maintain a 50% input duty cycle. When a 3.3 V CMOS oscillator is in use, it is important to ac-couple and use a voltage divider to reduce the input high voltage to a maximum of 1.14 V. The target voltage swing is 800 mV p-p. See Figure 25 for details on connecting a 3.3 V CMOS TCXO to the system clock input. The nonXTAL input path permits the user to provide an LVPECL, LVDS, CMOS, or sinusoidal low frequency clock for multiplication by the integrated SYSCLK PLL. However, when using a sinusoidal input signal, it is best to use a frequency of 20 MHz. Otherwise, the resulting low slew rate can lead to poor noise performance. Note that there is an optional 2x frequency multiplier to double the rate at the input to the SYSCLK PLL and potentially reduce the PLL in-band noise. However, to avoid exceeding the maximum PFD rate of 300 MHz, the 2x frequency multiplier is only for input frequencies less than 150 MHz. Note that using the doubler when the duty is not close to 50% results in higher spurious noise and may prevent the system clock PLL from locking. The nonXTAL path also includes an input divider (M) that is programmable for divide-by-1, -2, -4, or -8. The purpose of the divider is to allow additional flexibility in setting the system clock frequency to avoid spurs in the output clocks. The XTAL path enables the connection of a crystal resonator (typically 12 MHz to 50 MHz) across the XOA and XOB pins. An internal amplifier provides the negative resistance required to induce oscillation. The internal amplifier expects an AT cut, fundamental mode crystal with a 100 maximum motional resistance. The following crystals, listed in alphabetical order, may meet these criteria. Analog Devices does not guarantee their operation with the AD9554, nor does Analog Devices endorse one crystal supplier over another. The AD9554 reference design uses a 49.152 MHz crystal, which is high performance, low spurious content, and readily available. AVX/Kyocera CX3225SB ECS, Inc. ECX-32 Epson/Toyocom TSX-3225 Fox FX3225BS NDK NX3225SA Siward SX-3225 Suntsu SCM10B48-49.152 MHz SYSCLK MULTIPLIER The SYSCLK PLL multiplier is an integer-N design with an integrated VCO. It provides a means to convert a low frequency clock input to the desired system clock frequency, fSYS (2250 MHz to 2415 MHz). The SYSCLK PLL multiplier accepts input signals of between 10 MHz and 268 MHz. The PLL contains a feedback divider (K) that is programmable for divide values between 4 and 255. fSYS = fOSC x SYSCLK _ KDIV SYSCLK _ JDIV where: fOSC is the frequency at the XOA and XOB pins. SYSCLK_KDIV is the K divider value stored in Register 0x0200. SYSCLK_JDIV is the system clock J1 divider that is determined by setting Register 0x0201[2:1]. If the system clock doubler is used, the value of SYSCLK_KDIV must be half of its original value. The system clock multiplier features a simple lock detector that compares the time difference between the reference and feedback edges. The most common cause of the SYSCLK multiplier not locking is a non-50% duty cycle at the SYSCLK input while the system clock doubler is enabled. Rev. D | Page 39 of 116 AD9554 Data Sheet System Clock Stability Timer Because multiple blocks inside the AD9554 depend on the system clock being at a known frequency, the system clock must be stable before activating the monitors. At initial power-up, the system clock status is not known; therefore, it is reported as being unstable. After the system clock registers have been programmed and the SYSCLK VCO has been calibrated, the system clock PLL locks shortly thereafter. When the SYSCLK PLL locks, a timer runs for the duration stored in the system clock stability period registers. If the locked condition is violated any time during this waiting period, the timer is reset and halted until a locked condition is reestablished. After the specified period elapses, the internal logic of the AD9554 reports the system clock as stable. Note that any time the system clock stability timer is changed in Register 0x0206 through Register 0x0208, it is reset automatically. The system clock stability timer starts counting when the next IO_UDATE is issued (assuming that the system clock PLL is locked). Rev. D | Page 40 of 116 Data Sheet AD9554 OUTPUT ANALOG PLL (APLL) There are four output analog PLLs (APLLs) on the AD9554. They provide the frequency upconversion from the digital PLL (DPLL) outputs. The frequency ranges for each APLL are in Table 11. Each APLL also provides a noise filter on the DPLL output. The APLL reference input is the output of the DPLL. The feedback divider is an integer divider. The loop filter is partially integrated with one external 15 nF capacitor that connects to the internal LDO. In addition to the capacitor, there is an additional 0.22 F capacitor from the LDO pin to ground. The nominal loop bandwidth for all four APLLs is 240 kHz. The APLL_0 block diagram is shown in Figure 34. APLL_1 through APLL_3 are copies of APLL_0 with different VCO ranges. Each APLL_x input is connected to the respective DPLL_x output, and each APLL_x output is connected to the respective Px divider. APLL CALIBRATION Calibration of the APLLs must be performed at startup and whenever the nominal input frequency to the APLL changes by more than 100 ppm; although, the APLL maintains lock over voltage and temperature extremes without recalibration. APLL calibration at startup is normally performed during initial register loading, see the detailed instructions in the Device Register Programming Using a Register Setup File section. To recalibrate the APLL VCO after the chip has been running, first, input the new settings (if any). The user can calibrate APLL_0 without disturbing any of the other three APLLs (APLL_1, APLL_2, and APLL_3). Use the following steps to recalibrate the APLL VCO. It is important to note that an IO_UPDATE (Register 0x000F = 0x01) is needed after each of these steps. 1. INTEGER DIVIDER /M0 OUTPUT PLL (APLL_0) FROM DPLL_0 CP PFD TO P0 DIVIDER LF VCO_0 2. LF_0 CAP 23 LF_0 PIN 12132-138 LDO_0 PIN 22 Figure 34. APLL_0 Block Diagram APLL CONFIGURATION The frequency wizard that is included in the evaluation software configures the APLL, and the user must not need to make changes to the APLL settings. However, there may be special cases where the user may want to adjust the APLL loop bandwidth to meet a specific phase noise requirement. The easiest way to change the APLL loop bandwidth is to adjust the APLL charge pump current, which is controlled in the following registers: Register 0x0430 (APLL_0) Register 0x0530 (APLL_1) Register 0x0630 (APLL_2) Register 0x0730 (APLL_3) 3. 4. There is sufficient stability (68 of phase margin) in the APLL default settings to permit a broad range of adjustment without causing the APLL to be unstable. 5. Rev. D | Page 41 of 116 Ensure that the DPLL free run tuning word is set (Register 0x0A22[0] = 1b for DPLL_0, Register 0x0A42[0] = 1b for DPLL_1, Register 0x0A62[0] = 1b for DPLL_2, and Register 0x0A82[0] = 1b for DPLL_3). Clear the desired APLL calibration bit (Register 0x0A20[1] = 0b for APLL_0, Register 0x0A40[1] = 0b for APLL_1, Register 0x0A60[1] = 0b for APLL_2, and Register 0x0A80[1] = 0b for APLL_3). Alternatively, the user can write Register 0xA00 = 0x00 to clear the calibrate all bit. This allows the user to set this bit in the next step to calibrate all four VCOs at the same time. Set the desired APLL calibration bit (Register 0x0A20[1] = 1b for APLL_0, Register 0x0A40[1] = 1b for APLL_1, Register 0x0A60[1] = 1b for APLL_2, and Register 0x0A80[1] = 1b for APLL_3). Alternatively, the user can write Register 0xA00 = 0x02 to calibrate all four VCOs at the same time. To ensure that the APLLs have locked, poll the APLL lock status (Register 0x0D20[3] = 1b indicates lock for APLL_0, Register 0x0D40[3] = 1b indicates lock for APLL_1, Register 0x0D60[3] = 1b indicates lock for APLL_2, and Register 0x0D80[3] = 1b indicates lock for APLL_3). Ensure that the DPLL free run tuning word is cleared (Register 0x0A22[0] = 0b for DPLL_0, Register 0x0A42[0] = 0b for DPLL_1, Register 0x0A62[0] = 0b for DPLL_2, and Register 0x0A82[0] = 0b for DPLL_3). AD9554 Data Sheet MAX 1.25GHz CHIP RESET SYNC CHANNEL SYNC BLOCK MAX 1.25GHz /Q0_A 10-BIT INTEGER /Q0_B OUT0A OUT0A OUT0B OUT0B CHANNEL SYNC (TO Q0_A AND Q0_B) 12132-139 P0 DIVIDER FROM VCO_0 10-BIT INTEGER 430kHz TO 941MHz CLOCK DISTRIBUTION Figure 35. Clock Distribution Block Diagram from VCO_0 for the PLL_0 The AD9554 has four identical clock distribution sections for PLL_0 through PLL_3. See Figure 35 for a diagram of the clock distribution block for PLL_0. CLOCK DIVIDERS P Dividers The first block in each clock distribution section is the P divider. The P divider divides the VCO output frequency down to a frequency of 1.25 GHz and has special circuitry to maintain a 50% duty cycle for any divide ratio. The following registers contain the P divider settings: Register 0x0434[3:0] for PLL_0, P0 divider Register 0x0534[3:0] for PLL_1, P1 divider Register 0x0634[3:0] for PLL_2, P2 divider Register 0x0734[3:0] for PLL_3, P3 divider The channel divider blocks, Q0_A and Q0_B through Q3_A and Q1_B are 10-bit integer dividers with a divide range of 1 to 1024. The channel divider block contains duty cycle correction that generates approximately 50% duty cycle for both even and odd divide ratios. The maximum input frequency to the channel dividers is 1.25 GHz. Register 0x0438 to Register 0x043A for Q0_A divider Register 0x043C to Register 0x043E for Q0_B divider Q1 dividers: same as Q0 but offset by 0x0100 registers Q2 dividers: same as Q0 but offset by 0x0200 registers Q3 dividers: same as Q0 but offset by 0x0300 registers The output drivers can be individually powered down. The output mode control (including power-down) can be found in the following registers: Register 0x0437[2:0] for OUT0A Register 0x043B[2:0] for OUT0B Register 0x0537[2:0] for OUT1A Register 0x053B[2:0] for OUT1B Register 0x0637[2:0] for OUT2A Register 0x063B[2:0] for OUT2B Register 0x0737[2:0] for OUT3A Register 0x073B[2:0] for OUT3B The operating mode controls include the following: Channel Dividers The following registers contain the channel dividers: OUTPUT AMPLITUDE AND POWER-DOWN Output drive strength Output polarity Divide ratio Phase of each output channel The HCSL drivers feature a programmable drive strength that allows the user to choose between a strong, high performance driver or a lower power setting with less electromagnetic interference (EMI) and crosstalk. The best setting is application dependent. All outputs have three current settings that provide increased output amplitude in applications that require it. However, the only modes that support dc-coupling without termination at the destination are the 14 mA HCSL and 21 mA modes. The 28 mA mode must have either 50 to ground on each leg or 100 across the differential pair. For applications where LVPECL levels are required, the user must choose the 28 mA mode, ac-couple the output signal, and provide 100 termination across the differential pair at the destination. Damage to the output drivers can result if 28 mA mode is used without external termination resistors (either to ground or across the differential pair). See the Input/Output Termination Recommendations section for recommended termination schemes. Rev. D | Page 42 of 116 Data Sheet AD9554 The digital logic triggers a sync event from one of the following sources: CLOCK DISTRIBUTION SYNCHRONIZATION Divider Synchronization The dividers in the channels can be synchronized with each other. At power-up, they are held static until a synchronization signal is initiated through the serial port, an EEPROM event, a DPLL locked synchronization. This mode of operation provides time for APLL calibration before the outputs are enabled. A user initiated sync signal can also be supplied to the dividers at any time (as a manual synchronization) using an Mx pin. A channel can be programmed to ignore the sync function. When programmed to ignore the sync function, the channel sync block issues a sync pulse immediately, and the channel ignores all other sync signals. Rev. D | Page 43 of 116 Register programming through serial port EEPROM programming A multifunction pin configured for the sync signal Other automatic conditions determined by the DPLL configuration: DPLL lock or reference clock synchronization AD9554 Data Sheet STATUS AND CONTROL In function form, this is the following: MULTIFUNCTION PINS (M0 TO M9) The AD9554 has ten digital CMOS input/output pins (M0 to M9) that are configurable for a variety of uses. The function of these pins is programmable via the register map. Each pin can control or monitor an assortment of internal functions based on Register 0x0103 to Register 0x010C. The Mx pins feature a special write detection logic that prevents these pins from behaving unpredictably when the Mx pins function changes. When the user writes to these registers, the existing Mx pin function stops. The new Mx pin function takes effect on the next IO_UPDATE (Register 0x000F = 0x01). The Mx pins operate in one of four modes: active high CMOS, active low CMOS, open-drain PMOS, and open-drain NMOS. Table 23. Mx Pins Four Modes of Operation Setting 00 Mode Active high CMOS 01 Active low CMOS 10 Opendrain PMOS 11 Opendrain NMOS Description When deasserted, the Mx pin is Logic 0. When asserted, the Mx pin is Logic 1, which is the default operating mode When deasserted, the Mx pin is Logic 1. When asserted, the Mx pin is Logic 0. When deasserted, the Mx pin is high impedance. When the Mx pin is asserted, it is active high; it requires an external pull-down resistor. When deasserted, the Mx pin is high impedance. When the Mx pin is asserted, it is active low; it requires an external pull-up resistor. To monitor an internal function with a multifunction pin, write a Logic 1 to the most significant bit of the register associated with the desired multifunction pin. The value of the seven least significant bits of the register defines the control function, as shown in Table 154. To control an internal function with a multifunction pin, write a Logic 0 to the most significant bit of the register associated with the desired multifunction pin. The monitored function depends on the value of the seven least significant bits of the register, as shown in Table 155. Note that each Mx pin has an open-drain mode that allows the user to perform logical AND and logical OR functions with the Mx pin outputs. For instance, it is possible to connect the IRQ lines of multiple AD9554s on one board together and to make the IRQ line the logical OR of each AD9554 IRQ line. It is also possible to have an input function like IRQ clearing to be the logical combination of multiple inputs. For example, IRQ clearing is desired only if M2 is high and M3 is low, and either M0 is high or M1 is low. Result = (M0 || !M1) && M2 && !M3 To accomplish this, set the M0 through M3 pins as the IRQ clearing function, and set the Mx pin modes of operation as the following: M0 = OR true signal (Register 0x100[1:0] = 10) M1 = OR inverted signal (Register 0x100[3:2] = 11) M2 = AND true signal (Register 0x100[5:4] = 00) M3 = AND inverted signal (Register 0x100[7:6] = 01) IRQ FUNCTION The AD9554 IRQ function can be assigned to any Mx pin. There are five IRQ categories: PLL0, PLL1, PLL2, PLL3, and common. This means an Mx pin can be set to respond only to IRQs that relate to one of the PLLs or to common functions. An Mx pin can also be set to respond to all IRQs. The AD9554 asserts an IRQ when any bit in the IRQ monitor register (Register 0x0D08 to Register 0x0D16) is a Logic 1. Each bit in this register is associated with an internal function that is capable of producing an interrupt. Furthermore, each bit of the IRQ monitor register is the result of a logical AND of the associated internal interrupt signal and the corresponding bit in the IRQ mask register (Register 0x010F to Register 0x011D). That is, the bits in the IRQ mask registers have a one-to-one correspondence with the bits in the IRQ monitor registers. When an internal function produces an interrupt signal and the associated IRQ mask bit is set, the corresponding bit in the IRQ monitor register is set. Be aware that clearing a bit in the IRQ mask register removes only the mask associated with the internal interrupt signal. It does not clear the corresponding bit in the IRQ monitor register. The IRQ function is edge triggered which means that if the condition that generated an IRQ (for example, loss of DPLL_0 lock) still exists after an IRQ is cleared, the IRQ does not reactivate until DPLL_0 lock is restored and lost again. However, if the IRQs are enabled when DPLL_0 is not locked, an IRQ is generated. The IRQ function of an Mx pin is the result of a logical OR of all the IRQ monitor register bits. The AD9554 asserts an IRQ as long as any of the IRQ monitor register bits is a Logic 1. Note that it is possible to have multiple bits set in the IRQ monitor registers. Therefore, when the AD9554 asserts an IRQ, it may indicate an interrupt from several different internal functions. The IRQ monitor registers provide a way to interrogate the AD9554 to determine which internal function(s) produced the interrupt. Typically, when the AD9554 asserts an IRQ, the user interrogates the IRQ monitor registers to identify the source of the interrupt request. After servicing an indicated interrupt, the user must clear the associated IRQ monitor register bit via the IRQ clearing registers (Address 0x0A05 to Address 0x0A14). The bits in the IRQ clearing registers have a one-to-one correspondence with the bits in the IRQ monitor registers. Rev. D | Page 44 of 116 Data Sheet AD9554 Note that the IRQ clearing registers are autoclearing. The Mx pin associated with an IRQ remains asserted until the user clears all of the bits in the IRQ monitor registers that indicate an interrupt. The EEPROM provides the ability to upload and download configuration settings to and from the register map. Figure 36 shows a functional diagram of the EEPROM. All IRQ monitor register bits can be cleared by setting the clear all IRQs bit in the IRQ register (Register 0x0A05). Note that the bits in Register 0x0A05 are autoclearing. Setting Bit 0 results in the deassertion of all IRQs. Alternatively, the user can program any of the multifunction pins to clear all IRQs, which allows the user to clear all IRQs by means of a hardware pin rather than by a serial input/output port operation. Register 0x0E10 to Register 0x0E6F represent a 96-byte EEPROM storage sequence area (referred to as the scratchpad in this section) that enables the user to store a sequence of instructions for transferring data to the EEPROM from the device settings portion of the register map. Note that the default values for these registers provide a sample sequence for saving/retrieving all of the AD9554 EEPROM accessible registers. Figure 36 shows the connectivity between the EEPROM and the controller that manages the data transfer between the EEPROM and the register map. There are two ways to reset the watchdog timer (thereby preventing it from causing a timeout event). The first method is to write a Logic 1 to the autoclearing clear watchdog timer bit in the clear IRQ groups register (Register 0x0A05, Bit 7). Alternatively, the user can program any of the multifunction pins to reset the watchdog timer. When used in this way, the user can reset the timer by means of a hardware pin rather than by a serial input/output port operation. EEPROM EEPROM Overview The AD9554 contains an EEPROM controller that allows the user to connect an external 2048-byte, electrically erasable, programmable read only memory (EEPROM). The AD9554 can be configured to perform a download at power-up via the multifunction pins, however, uploads and downloads can also be performed on demand via the EEPROM control registers (Address 0x0E00 to Address 0x0E03). To enable the EEPROM I2C controller, the M4 pin must be pulled high at power-up or reset. To enable the I2C EEPROM interface, pull the M4 pin high at power-up or reset. To load from the EEPROM at power-up or reset, pull the M3 pin high at power-up or reset. When configured for external EEPROM operation, the M1 (SCL) and M2 pins (SDA) are open-drain NMOS, and external pull-up resistors are needed into for the I2C EEPROM interface to function. M1 (SCL) M3 EEPROM CONTROLLER M4 DEVICE SETTINGS ADDRESS POINTER DEVICE SETTINGS EXTERNAL EEPROM M2 (SDA) SCRATCH PAD ADDRESS POINTER SCRATCH PAD (0x0E10 TO 0x0E6F) REGISTER MAP SERIAL INPUT/OUTPUT PORT 12132-024 If enabled, the timer runs continuously and generates a timeout event when the timeout period expires. The user has access to the watchdog timer status via the IRQ mechanism and the multifunction pins (M0 to M9). In the case of the multifunction pins, the timeout event of the watchdog timer is a pulse that lasts 96 system clock periods (which approximately 40 ns). The controller oversees the process of transferring EEPROM data to and from the register map. There are two modes of operation handled by the controller: saving data to the EEPROM (upload mode) or retrieving data from the EEPROM (download mode). In either case, the controller relies on a specific instruction set. DATA The watchdog timer is a general-purpose programmable timer. To set the timeout period, the user writes to the 16-bit watchdog timer register (Address 0x010D to Address 0x010E). A value of 0x0000 in this register disables the timer. A nonzero value sets the timeout period in milliseconds, giving the watchdog timer a range of 1 ms to 65.535 sec. The relative accuracy of the timer is approximately 0.1% with an uncertainty of 0.5 ms. DATA WATCHDOG TIMER Figure 36. EEPROM Functional Diagram EEPROM Instructions Table 24 lists the EEPROM controller instruction set. The controller recognizes all instruction types, whether it is in upload or download mode, except for the pause instruction, which it only recognizes in upload mode. The IO_UPDATE, calibrate, distribution sync, and end instructions are, for the most part, self-explanatory. The others, however, warrant further detail, as described in the EEPROM Data Instruction section and Table 24. EEPROM Data Instruction Data instructions are those that have a value from 0x00 to 0x7F. A data instruction tells the controller to transfer data between the EEPROM and the register map. The controller needs the following two parameters to carry out the data transfer: The number of bytes to transfer The register map starting address The controller decodes the number of bytes to transfer directly from the data instruction itself by adding 1 to the value of the instruction. Rev. D | Page 45 of 116 AD9554 Data Sheet For example, Data Instruction 0x1A has a decimal value of 26; therefore, the controller knows to transfer 27 bytes (one more than the value of the instruction). When the controller encounters a data instruction, it automatically reads the next two bytes because these contain the starting address of the AD9554 register map. The starting address is the LSB, and then the MSB. For example, storing five bytes at Starting Address 0x00FE is entered into the EEPROM buffer segment as 0x04, then 0xFE, and then 0x00. Note that the internal EEPROM controller always starts at the register map starting address and counts upward, regardless of the mode of the main serial port. As part of the transfer process during an EEPROM upload, the controller calculates a CRC-32 checksum and stores it at the end of the data transfer. As part of the transfer process during an EEPROM download, however, the controller again calculates the CRC-32 checksum and compares the newly calculated checksum with the one that was stored during the upload process. If an upload/download checksum pair does not match, the controller sets the EEPROM fault status bit. If the upload/download checksums match for all instructions encountered during a download sequence, the controller sets the EEPROM complete status bit. Table 24. EEPROM Controller Instruction Set Instruction Value (Hex) 0x00 to 0x7F Instruction Type Data Bytes Needed 3 0x80 IO_UPDATE 1 0x90 Calibrate all PLLs 1 0x91 Calibrate SYSCLK 1 0x92 Calibrate all APLLs 1 0x93/0x94/ 0x95/0x96 Calibrate APLL_0/APLL_1/ APLL_2/APLL_3 Set user free run mode (all PLLs) 1 Set DPLL_0/ DPLL_1/DPLL_2/ DPLL_3 user free run mode Distribution sync (all outputs) 1 1 0xB0 0xB1 to 0xBF Distribution sync (PLL0/PLL1/PLL2/ PLL3 outputs) Clear condition Condition 0xFE Pause 1 0xFF End of data 1 0x98 0x99/0x9A/ 0x9B/0x9C 0xA0 0xA1/0xA2/ 0xA3/0xA4 1 1 1 1 Description A data instruction tells the controller to transfer data to or from the device settings part of the register map. A data instruction requires two additional bytes that, together, indicate a starting address in the register map. Encoded in the data instruction is the number of bytes to transfer, which is one more than the instruction value. The controller issues a soft IO_UPDATE (that is analogous to the user writing Register 0x000F = 0x01). The EEPROM controller initiates a calibration sequence to the SYSCLK PLL, as well as all of the APLLs, while downloading from the EEPROM. APLL calibration does not start until the SYSCLK PLL is stable. When the controller encounters this instruction while downloading from the EEPROM, it initiates an SYSCLK calibration sequence. The controller initiates an APLL calibration sequence to all four APLLs while downloading from the EEPROM. APLL calibration is gated by the system clock being stable. When the controller encounters this instruction while downloading from the EEPROM, it initiates an APLL_0/APLL_1/APLL_2/APLL_3 calibration sequence. APLL calibration is gated by the system clock being stable. 0x93 is for APLL_0, 0x94 is for APLL_1, and so on. When the controller encounters this instruction while downloading from the EEPROM, it forces all of the DPLLs into user free run mode. The force state is cleared automatically when EEPROM loading is complete. However, the user free run bits in the register map are not changed with this command and retain their programmed values. When the controller encounters this instruction while downloading from the EEPROM, it forces DPLL_0/DPLL_1/DPLL_2/DPLL_3 into user free run mode. The force state is cleared automatically when EEPROM loading is complete. However, the user free run bits in the register map are not changed with this command, and retain their programmed values. When the controller encounters this instruction while downloading from the EEPROM, it issues a sync pulse to the PLL0, PLL1, PLL2, and PLL3 channel dividers. Note that the APLL associated with a given channel must be locked before the sync pulse reaches the output dividers of that channel. When the controller encounters this instruction while downloading from the EEPROM, it issues a sync pulse to the PLL0/PLL1/PLL2/PLL3 channel dividers. Note that, unless overridden, this sync pulse is gated by the APLL lock detect signal associated with that channel. 0xB0 is the null condition instruction. 0xB1 to 0xBF are condition instructions and correspond to Condition 1 through Condition 15, respectively. When the controller encounters this instruction in the scratchpad while uploading to the EEPROM, it resets the scratchpad address pointer and holds the EEPROM address pointer at its last value. This allows storage of more than one instruction sequence in the EEPROM. The controller does not copy this instruction to the EEPROM during upload. When the controller encounters this instruction in the scratchpad while uploading to the EEPROM, it resets both the scratchpad address pointer and the EEPROM address pointer and then enters an idle state. When the controller encounters this instruction while downloading from the EEPROM, it resets the EEPROM address pointer and then enters an idle state. Rev. D | Page 46 of 116 Data Sheet AD9554 The Condition and Pause Instructions Condition instructions are those that have a value from 0xB0 to 0xBF. The 0xB1 to 0xBF condition instructions represent Condition 1 to Condition 15, respectively. The 0xB0 condition instruction is special because it represents the null condition. A pause instruction, like an end instruction, is stored at the end of a sequence of instructions in the scratchpad. When the controller encounters a pause instruction during an upload sequence, it keeps the EEPROM address pointer at its last value. Then, the user can store a new instruction sequence in the scratchpad and upload the new sequence to the EEPROM. The new sequence is stored in the EEPROM address locations immediately following the previously saved sequence. This process is repeatable until an upload sequence contains an end instruction. The pause instruction is also useful when used in conjunction with condition processing. It allows the EEPROM to contain multiple occurrences of the same registers, with each occurrence linked to a set of conditions. EEPROM Upload o upload data to the EEPROM, take the following steps: 1. 2. 3. 4. 5. Program the AD9554 to the desired configuration. Write Register 0x0FFF = 0xF9 to enable the manual VCAL reference programming. Write Register 0x0E00 = 0x03 (for 400 kHz transfer rate) or 0x01 for 100 kHz EEPROM transfer rate. Write Register 0x0E02 = 0x01 to initiate the EEPROM data storage process. This bit is autoclearing. Write Register 0x0FFF = 0x00 to disable accidental writes to registers addresses higher than Register 0x0FFF. During the upload process, the controller reads the scratchpad data byte by byte, starting at Register 0x0E10 and incrementing the scratchpad address pointer, as it goes, until it reaches a pause or end instruction. As the controller reads the scratchpad data, it transfers the data from the scratchpad to the EEPROM (byte by byte) and increments the EEPROM address pointer accordingly, unless it encounters a data instruction. A data instruction tells the controller to transfer data from the device settings portion of the register map to the EEPROM. The number of bytes to transfer is encoded within the data instruction, and the starting address for the transfer appears in the next two bytes in the scratchpad. When the controller encounters a data instruction, it stores the instruction in the EEPROM, increments the EEPROM address pointer, decodes the number of bytes to be transferred, and increments the scratchpad address pointer. Then, it retrieves the next two bytes from the scratchpad (the target address) and increments the scratchpad address pointer by 2. Next, the controller transfers the specified number of bytes from the register map (beginning at the target address) to the EEPROM. When it completes the data transfer, the controller stores a CRC-32 checksum. Note that, when the controller transfers data associated with an active register, it actually transfers the buffered contents of the register (refer to the Buffered/Active Registers section for details on the difference between buffered and active registers). The use of the buffered registers (as opposed to the live registers) allows for the transfer of nonzero autoclearing register contents. Conditional processing does not occur during an upload sequence. Manual EEPROM Download An EEPROM download results in a data transfer from the external EEPROM to the device register map. To download data, set the autoclearing load from EEPROM bit (Register 0x0E03, Bit 0). This commands the controller to initiate the EEPROM download process. During download, the controller reads the EEPROM data byte by byte, incrementing the EEPROM address pointer as it goes, until it reaches an end instruction. As the controller reads the EEPROM data, it executes the stored instructions, which includes transferring stored data to the device settings portion of the register map whenever it encounters a data instruction. Note that conditional processing is applicable only when downloading manually. The condition value is stored in Bits[3:0] of Register 0x0E01. Automatic downloads use a condition value of 1. Automatic EEPROM Download If the M3 pin and M4 pin are high following a power-up, a hard reset using the RESET pin, or a soft reset (Register 0x0000, Bit 7 = 1), the instruction sequence stored in the external EEPROM executes automatically. If M4 is high and M3 is low, the external EEPROM I2C port is enabled on the M1 and M2 pins; however, the contents of the external EEPROM are not loaded. In that case, factory defaults are used. If M4 is low, the M3 status is ignored, and the external EEPROM I2C port is disabled. The M1 and M2 pins can be used for other status and control functions. Rev. D | Page 47 of 116 AD9554 Data Sheet Important Update to EEPROM Programming Sequence The following changes must be applied to the default EEPROM storage sequence in Register 0x0E10 to Register 0x0E6F. The AD9554 evaluation software, Version 1.0.3.0 or later, checks these registers and prompts the user to update these registers in the register programming file to this sequence: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. Register 0x0E10 = 0x01 (write 2 bytes) Register 0x0E11 = 0x00 (at Register 0x0B00) Register 0x0E12 = 0x0B Register 0x0E13 = 0x98 (Set all channels to Freerun mode) Register 0x0E14 = 0x01 (write 2 bytes) Register 0x0E15 = 0xFE (at Register 0x00FE) Register 0x0E16 = 0x00 Register 0x0E17 = 0x1F (write 32 bytes) Register 0x0E18 = 0x00 (at Register 0x0100) Register 0x0E19 = 0x01 Register 0x0E1A = 0x08 (write 9 bytes) Register 0x0E1B = 0x00 (at Register 0x0200) Register 0x0E1C = 0x02 Register 0x0E1D = 0x80 (input/output update) Register 0x0E1E = 0x91 (calibrate SYSCLK) Register 0x0E1F = 0x1E (write 32 bytes) Register 0x0E20 = 0x00 (at Register 0x0300) Register 0x0E21 = 0x03 Register 0x0E22 = 0x1E (write 31 bytes) Register 0x0E23 = 0x20 (at Register 0x0320) Register 0x0E24 = 0x03 Register 0x0E25 = 0x1E (write 31 bytes) Register 0x0E26 =0x40 (at Register 0x0340) Register 0x0E27 = 0x03 Register 0x0E28 = 0x1E (write 31 bytes) Register 0x0E29 = 0x60 (at Register 0x0360) Register 0x0E2A = 0x03 Register 0x0E2B = 0x1E (write 31 bytes) Register 0x0E2C = 0x00 (at Register 0x0400) Register 0x0E2D = 0x04 Register 0x0E2E = 0x0E (write 15 bytes) Register 0x0E2F = 0x30 (at Register 0x0430) Register 0x0E30 = 0x04 Register 0x0E31 = 0x33 (write 52 bytes) Register 0x0E32 = 0x40 (at Register 0x0440) Register 0x0E33 = 0x04 Register 0x0E34 = 0x1E (write 31 bytes) Register 0x0E35 = 0x00 (at Register 0x0500) Register 0x0E36 = 0x05 Register 0x0E37 = 0x0E (write 15 bytes) Register 0x0E38 = 0x30 (at Register 0x0530) Register 0x0E39 = 0x05 Register 0x0E3A = 0x33 (write 52 bytes) Register 0x0E3B = 0x40 (at Register 0x0540) Register 0x0E3C = 0x05 Register 0x0E3D = 0x1E (write 31 bytes) 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96. Rev. D | Page 48 of 116 Register 0x0E3E = 0x00 (at Register 0x0600) Register 0x0E3F = 0x06 Register 0x0E40 = 0x0E (write 15 bytes) Register 0x0E41 = 0x30 (at Register 0x0630) Register 0x0E42 = 0x06 Register 0x0E43 = 0x33 (write 52 bytes) Register 0x0E44 = 0x40 (at Register 0x0640) Register 0x0E45 = 0x06 Register 0x0E46 = 0x1E (write 31 bytes) Register 0x0E47 = 0x00 (at Register 0x0700) Register 0x0E48 = 0x07 Register 0x0E49 = 0x0E (write 15 bytes) Register 0x0E4A = 0x30 (at Register 0x0730) Register 0x0E4B = 0x07 Register 0x0E4C = 0x33 (write 52 bytes) Register 0x0E4D = 0x40 (at Register 0x0740) Register 0x0E4E = 0x07 Register 0x0E4F = 0x24 (write 37 bytes) Register 0x0E50 = 0x00 (at Register 0x0A00) Register 0x0E51 = 0x0A Register 0x0E52 = 0x04 (write 5 bytes) Register 0x0E53 = 0x40 (at Register 0x0A40) Register 0x0E54 = 0x0A Register 0x0E55 = 0x04 (write 5 bytes) Register 0x0E56 = 0x60 (at Register 0x0A60) Register 0x0E57 = 0x0A Register 0xE58 = 0x04 (write 5 bytes) Register 0xE59 = 0x80 (at Register 0x0A80) Register 0xE5A = 0x0A Register 0xE5B = 0x80 (input/output update) Register 0xE5C = 0x00 (write 1 byte) Register 0xE5D = 0xFF (at Register 0x0FFF) Register 0xE5E = 0x0F Register 0xE5F = 0x00 (write 1 byte) Register 0xE60 = 0x88 (at Register 0x1488) Register 0xE61 = 0x14 Register 0xE62 = 0x00 (write 1 byte) Register 0xE63 = 0x88 (at Register 0x1588) Register 0xE64 = 0x15 Register 0xE65 = 0x00 (write 1 byte) Register 0xE66 = 0x88 (at Register 0x1688) Register 0xE67 = 0x16 Register 0xE68 = 0x00 (write 1 byte) Register 0xE69 = 0x88 (at Register 0x1788) Register 0xE6A = 0x17 Register 0xE6B = 0x80 (input/output update) Register 0xE6C = 0x92 (calibrate all APLLs) Register 0xE6D = 0xA0 (sync all outputs) Register 0xE6E = 0xFF (end of data) Register 0xE6F = 0x55 (This register is past the end of the data command in R0x0E6E and is ignored.) Data Sheet AD9554 SERIAL CONTROL PORT The AD9554 serial control port is a flexible, synchronous serial communications port that provides a convenient interface to many industry-standard microcontrollers and microprocessors. The AD9554 serial control port is compatible with most synchronous transfer formats, including I2C, Motorola SPI, and Intel SSR protocols. The serial control port allows read/write access to the AD9554 register map. The AD9554 uses the Analog Devices unified SPI protocol (see Analog Devices Serial Control Interface Standard). The unified SPI protocol guarantees that all new Analog Devices products using the unified protocol have consistent serial port characteristics. The SPI port configuration is programmable via Register 0x0000. This register is a part of the SPI control logic rather than in the register map and is distinct from the I2C Register 0x0000. Unified SPI differs from the SPI port found on older products like the AD9557 and AD9558 in the following ways: Unified SPI does not have byte counts. A transfer is terminated when the CS pin goes high. The W1 and W0 bits in the traditional SPI become the A12 and A13 bits of the register address. This is similar to streaming mode in the traditional SPI. The address ascension bit (Register 0x0000) controls whether register addresses are automatically incremented or decremented regardless of the LSB/MSB first setting. In traditional SPI, LSB first dictated autoincrements and MSB first dictated autodecrements of the register address. Devices that adhere to the unified serial port have a consistent structure of the first 16 register addresses. Although the AD9554 supports both the SPI and I2C serial port protocols, only one is active following power-up (as determined by the M0, M5, M6, and M7 multifunction pins during the start-up sequence). The only way to change the serial port protocol is to reset (or power cycle) the device. SPI/IC PORT SELECTION Because the AD9554 supports both SPI and I2C protocols, the active serial port protocol depends on the logic state of M0, M5, M6, and M7 pins at reset or power-on. See Table 22 for the I2C address assignments. SPI SERIAL PORT OPERATION Pin Descriptions The SCLK (serial clock) pin serves as the serial shift clock. This pin is an input. SCLK synchronizes serial control port read and write operations. The rising edge SCLK registers write data bits, and the falling edge registers read data bits. The SCLK pin supports a maximum clock rate of 50 MHz. The SPI port supports both 3-wire (bidirectional) and 4-wire (unidirectional) hardware configurations and both MSB-first and LSB-first data formats. Both the hardware configuration and data format features are programmable. The 3-wire mode uses the SDIO (serial data input/output) pin for transferring data in both directions. The 4-wire mode uses the SDIO pin for transferring data to the AD9554, and the SDO pin for transferring data from the AD9554. The CS (chip select) pin is an active low control that gates read and write operations. Assertion (active low) of the CS pin initiates a write or read operation to the AD9554 SPI port. Any number of data bytes can be transferred in a continuous stream. The register address is automatically incremented or decremented based on the setting of the address ascension bit (Register 0x0000). CS must be deasserted at the end of the last byte transferred, thereby ending the stream mode. This pin is internally connected to a 10 k pull-up resistor. When CS is high, the SDIO and SDO pins go into a high impedance state. Implementation Specific Details A detailed description of the unified SPI protocol can be found in the AN-877 Application Note, which covers items such as timing, command format, and addressing. The following product specific items are defined in the unified SPI protocol: Analog Devices unified SPI protocol revision: 1.0 Chip type: 0x5 Product ID: 0x009 Physical layer: 3- and 4-wire supported and 1.5 V, 1.8 V, and 2.5 V operation supported Optional single-byte instruction mode: not supported Data link: not used Control: not used Communication Cycle--Instruction Plus Data The unified SPI protocol consists of a two-part communication cycle. The first part is a 16-bit instruction word that is coincident with the first 16 SCLK rising edges and a payload. The instruction word provides the AD9554 serial control port with information regarding the payload. The instruction word includes the R/W bit that indicates the direction of the payload transfer (that is, a read or write operation). The instruction word also indicates the starting register address of the first payload byte. Rev. D | Page 49 of 116 AD9554 Data Sheet Write SPI Instruction Word (16 Bits) If the instruction word indicates a write operation, the payload is written into the serial control port buffer of the AD9554. Data bits are registered on the rising edge of SCLK. Generally, it does not matter what data is written to blank registers; however, it is customary to use 0s. Note that the user must verify that all reserved registers within a specific range have a default value of 0x00; however, Analog Devices makes every effort to avoid having reserved registers with nonzero default values. The MSB of the 16-bit instruction word is R/W, which indicates whether the instruction is a read or a write. The next 15 bits are the register address (A14 to A0), which indicates the starting register address of the read/write operation (see Table 26). Note that A14 and A13 are ignored and treated as zeros in the AD9554 because there are no registers that require more than 13 address bits. Most of the serial port registers are buffered (see the Buffered/Active Registers section for details on the difference between buffered and active registers). Therefore, data written into buffered registers does not take effect immediately. An additional operation is needed to transfer buffered serial control port contents to the registers that actually control the device. This transfer is accomplished with an IO_UPDATE operation, which is performed in one of two ways. One method is to write a Logic 1 to Register 0x000F, Bit 0 (this bit is an autoclearing bit). The other method is to use an external signal via an appropriately programmed multifunction pin. The user can change as many register bits as desired before executing an IO_UPDATE. The IO_UPDATE operation transfers the buffer register contents to their active register counterparts. The AD9554 instruction word and payload can be MSB first or LSB first. The default for the AD9554 is MSB first. The LSB first mode can be set by writing a 1 to Register 0x0000, Bit 6. Immediately after the LSB first bit is set, subsequent serial control port operations are LSB first. SPI MSB-/LSB-First Transfers Address Ascension If the address ascension bit (Register 0x0000, Bit 5) is zero, the serial control port register address decrements from the specified starting address toward Address 0x0000. If the address ascension bit (Register 0x0000, Bit 5) is one, the serial control port register address increments from the starting address toward Address 0x0FFF. Reserved addresses are not skipped during multibyte input/output operations; therefore, write the default value to a reserved register and 0s to unmapped registers. Note that it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved (or unmapped) registers. Read If the instruction word indicates a read operation, the next N x 8 SCLK cycles clock out the data starting from the address specified in the instruction word. N is the number of data bytes read. The readback data is driven to the pin on the falling edge and must be latched on the rising edge of SCLK. Blank registers are not skipped over during readback. Table 25. Streaming Mode (No Addresses Skipped) Address Ascension Increment Decrement A readback operation takes data from either the serial control port buffer registers or the active registers, as determined by Register 0x0001, Bit 5. Stop Sequence 0x0000 ... 0x0FFF 0x0FFF ... 0x0000 Table 26. Serial Control Port, 16-Bit Instruction Word MSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 LSB I0 R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CS SCLK DON'T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16-BIT INSTRUCTION HEADER D7 D6 D5 D4 D3 D2 D1 REGISTER (N) DATA D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE REGISTER (N - 1) DATA 12132-029 SDIO DON'T CARE DON'T CARE Figure 37. Serial Control Port Write--MSB First, Address Decrement, Two Bytes of Data CS SCLK DON'T CARE R/W A14 A13 A12 A11 A10 DON'T CARE A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SDO DON'T CARE D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N - 1) DATA REGISTER (N - 2) DATA Figure 38. Serial Control Port Read--MSB First, Address Decrement, Four Bytes of Data Rev. D | Page 50 of 116 REGISTER (N - 3) DATA DON'T CARE 12132-030 SDIO Data Sheet AD9554 tDS tHIGH tS tDH CS DON'T CARE SDIO DON'T CARE DON'T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE 12132-031 SCLK tC tCLK tLOW Figure 39. Timing Diagram for Serial Control Port Write--MSB First CS SCLK DATA BIT N 12132-032 tDV SDIO SDO DATA BIT N - 1 Figure 40. Timing Diagram for Serial Control Port Register Read--MSB First CS SCLK DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 R/W D0 16-BIT INSTRUCTION HEADER D1 D2 D3 D4 D5 D6 REGISTER (N) DATA D7 D0 D1 D2 D3 D4 D5 D6 D7 REGISTER (N + 1) DATA Figure 41. Serial Control Port Write--LSB First, Address Increment, Two Bytes of Data CS tS tC tCLK tHIGH tLOW tDS SCLK BIT N BIT N + 1 Figure 42. Serial Control Port Timing--Write Table 27. Serial Control Port Timing Parameter tDS tDH tCLK tS tC tHIGH tLOW tDV Description Setup time between data and the rising edge of SCLK Hold time between data and the rising edge of SCLK Period of the clock Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle) Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle) Minimum period that SCLK must be in a logic high state Minimum period that SCLK must be in a logic low state SCLK to valid SDIO (see Figure 40) Rev. D | Page 51 of 116 12132-034 tDH SDIO DON'T CARE 12132-033 SDIO DON'T CARE DON'T CARE AD9554 Data Sheet Start/stop functionality is shown in Figure 44. The start condition is characterized by a high to low transition on the SDA line while SCL is high. The master always generates the start condition to initialize a data transfer. The stop condition is characterized by a low to high transition on the SDA line while SCL is high. The master always generates the stop condition to terminate a data transfer. Every byte on the SDA line must be eight bits long. Each byte must be followed by an acknowledge bit; bytes are sent MSB first. IC SERIAL PORT OPERATION The I2C interface is popular because it requires only two pins and easily supports multiple devices on the same bus. Its main disadvantage is programming speed, which is 400 kbps maximum. The AD9554 I2C port design uses the I2C fast mode; however, it supports both the 100 kHz standard mode and 400 kHz fast mode. In an effort to support 1.5 V, 1.8 V, and 2.5 V I2C operation, the AD9554 does not strictly adhere to every requirement in the original I2C specification. In particular, specifications such as slew rate limiting and glitch filtering are not implemented. Therefore, the AD9554 is I2C compatible, but may not be fully I2C compliant. The acknowledge bit (A) is the ninth bit attached to any 8-bit data byte. An acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received. It is done by pulling the SDA line low during the ninth clock pulse after each 8-bit data byte. The AD9554 I2C port consists of a serial data line (SDA) and a serial clock line (SCL). In an I2C bus system, the AD9554 is connected to the serial bus (data bus SDA and clock bus SCL) as a slave device; that is, no clock is generated by theAD9554. The AD9554 uses direct 16-bit memory addressing instead of more common 8-bit memory addressing. The nonacknowledge bit (A) is the ninth bit attached to any 8bit data byte. A nonacknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has not been received. It is done by leaving the SDA line high during the ninth clock pulse after each 8-bit data byte. After issuing a nonacknowledge bit, the AD9554 I2C state machine goes into an idle state. The AD9554 allows up to seven unique slave devices to occupy the I2C bus. These are accessed via a 7-bit slave address transmitted as part of an I2C packet. Only the device with a matching slave address responds to subsequent I2C commands. Table 22 lists the supported device slave addresses. Data Transfer Process The master initiates data transfer by asserting a start condition, which indicates that a data stream follows. All I2C slave devices connected to the serial bus respond to the start condition. I2C Bus Characteristics The master then sends an 8-bit address byte over the SDA line, consisting of a 7-bit slave address (MSB first) plus an R/W bit. This bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write and 1 = read). A summary of the various I2C abbreviations appears in Table 28. Table 28. I2C Bus Abbreviation Definitions Abbreviation S Sr P A A W R Definition Start Repeated start Stop Acknowledge Nonacknowledge Write Read The peripheral whose address corresponds to the transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is 0, the master (transmitter) writes to the slave device (receiver). If the R/W bit is 1, the master (receiver) reads from the slave device (transmitter). The transfer of data is shown in Figure 43. One clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can change only when the clock signal on the SCL line is low. The format for these commands is described in the Data Transfer Format section. SDA DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED Figure 43. Valid Bit Transfer 12132-049 SCL Data is then sent over the serial bus in the format of nine clock pulses, one data byte (eight bits) from either master (write mode) or slave (read mode) followed by an acknowledge bit from the receiving device. The number of bytes that can be transmitted per transfer is unrestricted. In write mode, the first two data bytes immediately after the slave address byte are the internal memory (control registers) address bytes, with the high address byte first. This addressing scheme gives a memory address of up to 216 - 1 = 65,535. The data bytes after these two memory address bytes are register data written to or read from the control registers. In read mode, the data bytes after the slave address byte are register data written to or read from the control registers. Rev. D | Page 52 of 116 Data Sheet AD9554 By receiving the nonacknowledge bit, the slave device knows that the data transfer is finished and enters idle mode. The master then takes the data line low during the low period before the 10th clock pulse, and high during the 10th clock pulse to assert a stop condition. When all the data bytes are read or written, stop conditions are established. In write mode, the master (transmitter) asserts a stop condition to end data transfer during the clock pulse following the acknowledge bit for the last data byte from the slave device (receiver). In read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but does not pull SDA low during the ninth clock pulse. This is known as a nonacknowledge bit. A start condition can be used in place of a stop condition. Furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded. SDA SCL S START CONDITION 12132-036 P STOP CONDITION Figure 44. Start and Stop Conditions MSB ACK FROM SLAVE RECEIVER 1 SCL 2 3 TO 7 8 ACK FROM SLAVE RECEIVER 9 1 2 3 TO 7 8 9 S 10 P 12132-037 SDA Figure 45. Acknowledge Bit MSB ACK FROM SLAVE RECEIVER 1 SCL 2 3 TO 7 8 9 ACK FROM SLAVE RECEIVER 1 2 3 TO 7 8 9 S 10 P 12132-038 SDA Figure 46. Data Transfer Process (Master Write Mode, 2-Byte Transfer) SDA ACK FROM MASTER RECEIVER 1 2 3 TO 7 8 9 1 2 3 TO 7 8 S 9 10 P Figure 47. Data Transfer Process (Master Read Mode, 2-Byte Transfer), First Acknowledge From Slave Rev. D | Page 53 of 116 12132-039 SCL NONACK FROM MASTER RECEIVER AD9554 Data Sheet Data Transfer Format The write byte format writes a register address to the RAM starting from the specified RAM address. S Slave address A W RAM address high byte A RAM address low byte A RAM Data 0 A A RAM Data 1 A RAM Data 2 P The send byte format sets up the register address for subsequent reads. S Slave address A W RAM address high byte A RAM address low byte A P A P The receive byte format reads the data byte(s) from RAM starting from the current address. S Slave address R A RAM Data 0 A RAM Data 1 A RAM Data 2 The read byte format is the combined format of the send byte and the receive byte. S Slave address W A RAM address high byte A RAM address low byte A Sr R Slave address A RAM Data 0 A RAM Data 1 A RAM Data 2 A IC Serial Port Timing SDA tLOW tF tSU; DAT tR tHD; STA tF tSP tBUF tR tHD; STA S tHD; DAT tHIGH tSU; STO tSU; STA Sr Figure 48. IC Serial Port Timing Table 29. I2C Timing Definitions Parameter fSCL tBUF tHD; STA tSU; STA tSU; STO tHD; DAT tSU; DAT tLOW tHIGH tR tF tSP Description Serial clock Bus free time between stop and start conditions Repeated hold time start condition Repeated start condition setup time Stop condition setup time Data hold time Data setup time SCL clock low period SCL clock high period Minimum/maximum receive SCL and SDA rise time Minimum/maximum receive SCL and SDA fall time Pulse width of voltage spikes that must be suppressed by the input filter Rev. D | Page 54 of 116 P S 12132-040 SCL P Data Sheet AD9554 PROGRAMMING THE INPUT/OUTPUT REGISTERS The register map (see Table 32) spans an address range from 0x0000 through 0x1788. Each address provides access to one byte (eight bits) of data. Each individual register is identified by its four digit hexadecimal address (for example, Register 0x0A23). In some cases, a group of addresses collectively defines a register. In general, when a group of registers defines a control parameter, the LSB of the value resides in the D0 position of the register with the lowest address. The bit weight increases right to left, from the lowest register address to the highest register address. BUFFERED/ACTIVE REGISTERS There are two copies of most registers: buffered and active. The value in the active registers is the one that is in use. The buffered registers are the ones that take effect the next time the user writes 0x01 to Register 0x000F (IO_UPDATE). Buffering the registers allows the user to update a group of registers (like the APLL settings) simultaneously, avoiding the potential of unpredictable behavior in the device. Registers with an L in the option column of the register map (see Table 32) are live, meaning that they take effect the moment the serial port transfers that data byte. A Wx (where x equals 1 to 8) in the option column of the register map (see Table 32) identifies a register with write detection. These registers contain additional logic to avoid glitches or unwanted operation. Table 30. Register Write Detection Description W2 W3 W5 W6 W7 W8 An A in the option column of the register map (see Table 32) identifies an autoclearing register. Typically, the active value for an autoclearing register takes effect following an IO_UPDATE. The bit is cleared by the internal device logic upon completion of the prescribed action. REGISTER ACCESS RESTRICTIONS Read and write access to the register map may be restricted, depending on the register in question, the source and direction of access, and the current state of the device. Each register can be classified into one or more access types. When more than one type applies, the most restrictive condition is the one that applies. When access is denied to a register, all attempts to read the register return a 0 byte, and all attempts to write to the register are ignored. Access to nonexistent registers is handled in the same way as for a denied register. Regular Access Registers with regular access do not fall into any other category. Both read and write access to registers of this type can be from either the serial ports or EEPROM controller. However, only one of these sources can have access to a register at any given time (access is mutually exclusive). When the EEPROM controller is active, in either upload or download mode, it has exclusive access to these registers. WRITE DETECT REGISTERS Option W1 AUTOCLEAR REGISTERS Register Operation When these registers are written to, the lock detector immediately declares it is unlocked. The lock detection restarts when the next IO_UPDATE occurs. After these registers are written to, the DPLL faults the reference input and automatically enters holdover for one PFD cycle (and then exits) when an IO_UPDATE is issued. However, this action is only performed if the written register belongs to the actively selected reference. After these registers are written to, the DPLL lock detector unlocks. The watchdog timer resets automatically when these registers are written to and then resumes counting on the next IO_UPDATE. The system clock stability timer is automatically reset when these registers are changed and then resumes counting on the next IO_UPDATE. (Note that the SYSCLK stability timer starts only after the system clock is locked. If these registers are written to while they are assigned to an existing function, the existing function stops immediately. The new function starts when the next IO_UPDATE occurs. Almost identical to W2; however, the DPLL must be in demapping mode. Read Only Access An R in the option column of the register map (see Table 32) identifies read only registers. Serial port access is available at all times, including when the EEPROM controller is active. Note that read only registers (R) are inaccessible to the EEPROM as well. Exclusion from EEPROM Access An E in the option column of the register map (see Table 32) identifies a register with contents that are inaccessible to the EEPROM. That is, the contents of this type of register cannot be transferred directly to the EEPROM or vice versa. Note that read only registers (R) are inaccessible to the EEPROM as well. Rev. D | Page 55 of 116 AD9554 Data Sheet THERMAL PERFORMANCE Table 31. Thermal Parameters for the 72-Lead LFCSP Package Symbol JA JMA JMA JB JC JT JT JT 1 2 Thermal Characteristic Using a JEDEC 51-7 Plus JEDEC 51-5 2S2P Test Board1 Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-board thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-8 (still air) Junction-to-case thermal resistance (die-to-heat sink) per MIL-Standard 883, Method 1012.1 Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air) Junction-to-top-of-package characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-top-of-package characterization parameter, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air) Value2 20.0 18.0 16.0 10.7 1.1 0.1 0.1 0.2 Unit C/W C/W C/W C/W C/W C/W C/W C/W The exposed pad on the bottom of the package must be soldered to analog ground of the PCB to achieve the specified thermal performance. Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations. The AD9554 is specified for a case temperature (TCASE). To ensure that TCASE is not exceeded, an airflow source can be used. Use the following equation to determine the junction temperature on the application PCB: TJ = TCASE + (JT x PD) Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first-order approximation of TJ by the equation TJ = TA + (JA x PD) where TA is the ambient temperature (C). where: TJ is the junction temperature (C). TCASE is the case temperature (C) measured by the customer at the top center of the package. JT is the value as indicated in Table 31. PD is the power dissipation (see Table 3). Values of JC are provided for package comparison and PCB design considerations when an external heat sink is required. Values of JB are provided for package comparison and PCB design considerations. Rev. D | Page 56 of 116 Data Sheet AD9554 POWER SUPPLY PARTITIONS The AD9554 power supplies are in two groups: VDD and VDD_SP. All power and ground pins must be connected, even if certain blocks of the chip are powered down. the bypass capacitors as possible) and populate the board with 0402, 0 resistors. By doing so, there is a place for the ferrite beads, if needed. VDD SUPPLIES The ferrite beads are required if the AD9554 is powered directly from a switching power supply. All of the VDD supplies can be connected to one common source that is either 1.5 V or 1.8 V. Place the 0.1 F bypass capacitors as close as possible to each power supply pin. Ferrite beads with low (<0.7 ) dc resistance and approximately 30 impedance at 100 MHz are suitable for this application. For example, the Murata BLM15AX300SN1D is suitable. In addition to these bypass capacitors, the AD9554 evaluation board uses eight ferrite beads between the 1.8 V (or 1.5 V) source and Pin 2, Pin 17, Pin 20, Pin 35, Pin 38, Pin 53, Pin 56, and Pin 71. VDD_SP SUPPLY Although these ferrite beads may not be needed for every application, the use of these ferrite beads is strongly recommended. At a minimum, include a place for the ferrite beads (as close to If the user needs to operate the serial port at the same voltage as the device itself, VDD_SP can be joined to VDD. Pin 30 (VDD_SP) is the serial port power supply pin and can be connected to a 2.5 V, 1.8 V, or 1.5 V power supply. Rev. D | Page 57 of 116 AD9554 Data Sheet REGISTER MAP Register addresses that are not listed in Table 32 are not used, and writing to those registers has no effect. Write the default value to sections of registers marked reserved. In the option column, R = read only; A = autoclear; E = excluded from EEPROM loading; W1, W2, W3, W5, W6, W7, and W8 = write detection (see Table 30 for more information); and L = live (IO_UPDATE not required for register to take effect or for a read only register to be updated). N/A = not applicable. Table 32. Reg Addr (Hex) Option Name D7 Serial Control Port and Part Identification 0x0000 L, E SPI Config A Soft reset 0x0001 L, E SPI Config B D6 D5 D4 D3 D2 D1 D0 Def (Hex) LSB first (SPI only) Address ascension (SPI only) Read buffer register SDO active (SPI only) SDO active (SPI only) Address ascension (SPI only) Reset sansregmap LSB first (SPI only) Soft reset 0x00 Reserved Reserved Reserved Reserved 0x00 0x0002 E 0x0003 R 0x0004 R 0x0005 R 0x0006 R 0x0007 0x0008 0x0009 0x000A 0x000B R 0x000C R 0x000D R 0x000E 0x000F L, A, E User Scratchpad 0x00FE L 0x00FF L General Configuration 0x0100 0x0101 0x0102 0x0103 W7 Reserved Chip type Product ID 0x0104 W7 M1FUNC M1 output/ input M1 function, Bits[6:0] 0x00 0x0105 W7 M2FUNC M2 output/ input M2 function, Bits[6:0] 0x00 0x0106 W7 M3FUNC M3 output/ input M3 function, Bits[6:0] 0x00 0x0107 W7 M4FUNC M4 output/ input M4 function, Bits[6:0] 0x00 0x0108 W7 M5FUNC M5 output/ input M5 function, Bits[6:0] 0x00 0x0109 W7 M6FUNC M6 output/ input M6 function, Bits[6:0] 0x00 0x010A W7 M7FUNC M7 output/ input M7 function, Bits[6:0] 0x00 Reserved Clock part serial ID, Bits[3:0] Chip type, Bits[3:0] Reserved Reserved IO_UPDATE Clock part serial ID, Bits[11:4] Part version, Bits[7:0] Reserved Reserved Reserved Reserved SPI version, Bits[7:0] Vendor ID, Bits[7:0] Vendor ID, Bits[15:8] Reserved Reserved User scratchpad User scratchpad[7:0] User scratchpad[15:8] Revision Reserved Reserved Reserved Reserved SPI version Vendor ID Mx pin drivers M0FUNC M3 driver mode, Bits[1:0] M2 driver mode, Bits[1:0] M1 driver mode, Bits[1:0] M7 driver mode, Bits[1:0] M6 driver mode, Bits[1:0] M5 driver mode, Bits[1:0] Reserved M9 driver mode, Bits[1:0] M0 function, Bits[6:0] M0 output/ input Rev. D | Page 58 of 116 IO_UPDATE 0x00 0x05 0x9F 0x00 0x05 0x00 0x00 0x00 0x00 0x00 0x56 0x04 0x00 0x00 0x00 0x00 M0 driver mode, Bits[1:0] M4 driver mode, Bits[1:0] M8 driver mode, Bits[1:0] 0x00 0x00 0x00 0x00 Data Sheet AD9554 Reg Addr (Hex) 0x010B Option W7 Name M8FUNC D7 M8 output/ input 0x010C W7 M9FUNC M9 output/ input 0x010D 0x010E 0x010F W5 W5 Watchdog timer IRQ mask common D6 D5 D4 Watchdog timer (ms), Bits[7:0] Watchdog timer (ms), Bits[15:8] SYSCLK SYSCLK Watchdog calibration calibration timer ended started REFB fault Reserved REFA validated REFD fault Reserved REFC validated Phase slew Frequency Frequency limited unlocked locked History REFD REFC updated activated activated Sync clock APLL_0 APLL_0 distribution unlocked locked SYSCLK stable SYSCLK locked 0x0110 Reserved 0x0111 Reserved REFB validated REFD validated Frequency clamped Free run REFB fault cleared REFD fault cleared Phase slew unlimited Holdover Demap controller unclamped Frequency clamped Free run Demap controller clamped Phase slew unlimited Holdover Demap controller unclamped Frequency clamped Free run Demap controller clamped Phase slew unlimited Holdover Demap controller unclamped Frequency clamped Free run Demap controller clamped Phase slew unlimited Holdover Demap controller unclamped M6 config Demap controller clamped M5 config Reserved IRQ mask DPLL_0 0x0113 0x0114 Phase step detected 0x0115 IRQ mask DPLL_1 0x0116 0x0117 Frequency unclamped Switching Phase step detected 0x0118 IRQ mask DPLL_2 0x0119 0x011A Frequency unclamped Switching Phase step detected 0x011B IRQ mask DPLL_3 0x011C 0x011D Frequency unclamped Switching Phase step detected 0x011E L 0x011F L System Clock 0x0200 0x0201 Pad control SYSCLK PLL feedback divider and configuration 0x0202 0x0203 0x0204 0x0205 Frequency unclamped Switching W6 W6 W6 W6 0x0206 W6 0x0207 W6 0x0208 W6 Reference Input A 0x0300 W1, L SYSCLK reference frequency SYSCLK stability REFA logic type M7 config D1 D0 M9 function, Bits[6:0] SYSCLK unlocked 0x0112 D3 D2 M8 function, Bits[6:0] Reserved Def (Hex) 0x00 0x00 0x00 0x00 0x00 EEPROM fault EEPROM complete REFA fault cleared REFC fault cleared Phase unlocked REFB activated APLL_0 cal complete REFA fault 0x00 REFC fault 0x00 Phase locked REFA activated APLL_0 cal started 0x00 0x00 0x00 Phase slew limited History updated Sync clock distribution Frequency unlocked REFD activated APLL_1 unlocked Frequency locked REFC activated APLL_1 locked Phase unlocked REFB activated APLL_1 cal complete Phase locked REFA activated APLL_1 cal started 0x00 Phase slew limited History updated Sync clock distribution Frequency unlocked REFD activated APLL_2 unlocked Frequency locked REFC activated APLL_2 locked Phase unlocked REFB activated APLL_2 cal complete Phase locked REFA activated APLL_2 cal started 0x00 Phase slew limited History updated Sync clock distribution Frequency unlocked REFD activated APLL_3 unlocked Frequency locked REFC activated APLL_3 locked Phase unlocked REFB activated APLL_3 cal complete Phase locked REFA activated APLL_3 cal started 0x00 M4 config M3 config M2 config SPI config M1 config M9 config M0 config M8 config 0x00 0x00 System clock K divider, Bits[7:0] SYSCLK J1 divider, Bits[1:0] SYSCLK XTAL enable SYSCLK doubler enable (J0 divider) System clock reference frequency (Hz), Bits[7:0] System clock reference frequency (Hz), Bits[15:8] System clock reference frequency (Hz), Bits[23:16] Reserved System clock reference frequency (Hz), Bits[27:24] System clock stability period (ms), Bits[7:0] System clock stability period (ms), Bits[15:8] Reserved System clock stability period (ms), Bits[19:16] Reserved Rev. D | Page 59 of 116 REFA logic type, Bits[1:0] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x32 0x00 0x00 0x00 AD9554 Reg Addr (Hex) 0x0301 0x0302 0x0303 0x0304 0x0305 0x0306 0x0307 0x0308 0x0309 0x030A 0x030B 0x030C 0x030D 0x030E 0x030F 0x0310 Option W1, L W1, L W1, L W2, L W2, L W2, L W2, L W2, L W2, L W2, L W2, L W2, L W2, L W2, L W2, L W2, L Data Sheet Name REFA R divider (20 bits) REFA period REFA frequency tolerance REFA validation timer REFA phase lock detector 0x0311 W3, L 0x0312 W3, L 0x0313 W3, L 0x0314 W3, L 0x0315 W3, L 0x0316 W3, L REFA frequency 0x0317 W3, L lock 0x0318 W3, L detector 0x0319 W3, L 0x031A W3, L 0x031B W3, L REFA phase step 0x031C W3, L threshold 0x031D W3, L 0x031E W3, L Reference Input B 0x0320 to 0x033E Reference Input C 0x0340 to 0x035E Reference Input D 0x0360 to 0x037E DPLL_0 General Settings 0x0400 0x0401 0x0402 0x0403 0x0404 0x0405 0x0406 0x0407 0x0408 0x0409 0x040A 0x040B 0x040C D7 D6 D3 R divider, Bits[7:0] R divider, Bits[15:8] D2 D1 D0 R divider, Bits[19:16] Nominal reference period (fs), Bits[7:0] Nominal reference period (fs), Bits[15:8] Nominal reference period (fs), Bits[23:16] Nominal reference period (fs), Bits[31:24] Nominal reference period (fs), Bits[39:32] Inner tolerance (1/(ppm error)), Bits[7:0] (for invalid to valid condition; maximum: 6.55%, minimum: 2 ppm) (default: 5%) Inner tolerance (1/(ppm error)), Bits[15:8] (for invalid to valid condition; maximum: 6.55%, minimum: 2 ppm) Reserved Inner tolerance (1/(ppm error)), Bits[19:16] Outer tolerance (1/(ppm error)), Bits[7:0] (for valid to invalid; maximum: 6.55%, minimum: 2 ppm) (default: 10%) Outer tolerance (1/(ppm error)), Bits[15:8] (for valid to invalid; max: 6.55%, min: 2 ppm) Reserved Outer tolerance (1/(ppm error)), Bits[19:16] Validation timer (ms), Bits[7:0] (up to 65.5 sec) Validation timer (ms), Bits[15:8] (up to 65.5 sec) Phase lock threshold (ps), Bits[7:0] Phase lock threshold (ps), Bits[15:8] Phase lock threshold (ps), Bits[23:16] Phase lock fill rate, Bits[7:0] Phase lock drain rate, Bits[7:0] Frequency lock threshold (ps), Bits[7:0] Frequency lock threshold (ps), Bits[15:8] Frequency lock threshold (ps), Bits[23:16] Frequency lock fill rate, Bits[7:0] Frequency lock drain rate, Bits[7:0] Phase step threshold (ps), Bits[7:0] Phase step threshold (ps), Bits[15:8] Phase step threshold (ps), Bits[23:16] Reserved Phase step threshold (ps), Bits[27:24] Def (Hex) 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x14 0x00 0x00 0x0A 0x00 0x00 0x0A 0x00 0xBC 0x02 0x00 0x0A 0x0A 0xBC 0x02 0x00 0x0A 0x0A 0x00 0x00 0x00 0x00 These registers mimic the Reference Input A registers (0x0300 through 0x031E) but the register addresses are offset by 0x0020. All default values are identical. These registers mimic the Reference Input A registers (0x0300 through 0x031E) but register addresses are offset by 0x0040. All default values are identical. These registers mimic the Reference Input A registers (0x0300 through 0x031E) but the register addresses are offset by 0x0060. All default values are identical. Reserved DPLL_0 holdover history D4 Reserved DPLL_0 free run frequency TW DPLL_0 DCO integer DPLL_0 frequency clamp D5 30-bit free running frequency tuning word, Bits[7:0] 30-bit free running frequency tuning word, Bits[15:8] 30-bit free running frequency tuning word, Bits[23:16] 30-bit free running frequency tuning word, Bits[29:24] Reserved DCO integer, Bits[3:0] 0x00 0x00 0x00 0x00 0x17 Lower limit of pull-in range, Bits[7:0] Lower limit of pull-in range, Bits[15:8] Reserved Lower limit of pull-in range, Bits[19:16] Upper limit of pull-in range, Bits[7:0] Upper limit of pull-in range, Bits[15:8] Reserved Upper limit of pull-in range, Bits[19:16] History accumulation timer (ms), Bits[7:0] (up to 65 sec) History accumulation timer (ms), Bits[15:8] (up to 65 sec) 0xCC 0xCC 0x00 0x33 0x33 0x0F 0x0A 0x00 Rev. D | Page 60 of 116 Data Sheet Reg Addr (Hex) 0x040D 0x040E 0x040F 0x0410 0x0411 0x0412 0x0413 0x0414 0x0415 0x0416 0x0417 0x0418 0x0419 0x041A 0x041B 0x041C 0x041D 0x041E Option AD9554 Name DPLL_0 history mode DPLL_0 closed loop phase offset (0.5 ms) D7 D6 Reserved Reserved DPLL_0 phase slew limit Demap enable D4 D3 D2 D1 D0 Incremental average, Bits[2:0] Single Persistent sample history fallback Fixed phase offset (signed; ps), Bits[7:0] Fixed phase offset (signed; ps), Bits[15:8] Fixed phase offset (signed; ps), Bits[23:16] Fixed phase offset (signed; ps), Bits[29:24] Incremental phase offset step size (ps/step), Bits[7:0] (up to 65.5 ns/step) Incremental phase offset step size (ps/step), Bits[15:8] (up to 65.5 ns/step) Phase slew rate limit (s/sec), Bits[7:0] (315 s/sec up to 65.536 ms/sec) Phase slew rate limit (s/sec), Bits[15:8] (315 s/sec up to 65.536 ms/sec) Reserved Demap sampled address Demap set point address Demap gain control Demap clamp control Output PLL_0 (APLL_0) and Channel 0 Output Drivers 0x0430 Reserved APLL_0 charge pump 0x0431 APLL_0 M0 divider 0x0432 APLL_0 loop filter 0x0433 control 0x0434 0x0435 D5 P0 divider OUT0 sync 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Sampled address, Bits[7:0] Sampled address, Bits[15:8] 0x00 0x00 Set point address, Bits[7:0] Set point address, Bits[15:8] 0x00 0x00 Gain, Bits[7:0] Gain, Bits[15:8] Gain, Bits[23:16] Clamp value, Bits[7:0] 0x00 0x00 0x00 0x00 Output PLL0 (APLL_0) charge pump current, Bits[6:0] 0x2E Output PLL0 (APLL_0) feedback (M0) divider, Bits[7:0] 0x00 APLL_0 loop filter control, Bits[7:0] Reserved Reserved Reserved 0x0436 Enable demap controller Def (Hex) 0x00 Reserved 0x7F P0 divider reset APLL_0 loop filter control, Bit 8 P0 divider divide ratio, Bits[3:0] Auto sync mode, Bits[1:0] Sync source selection APLL_0 mask Mask Mask sync OUT0B OUT0A sync sync OUT0A mode Invert polarity 0x00 0x00 0x00 0x00 0x0437 OUT0A Reserved 0x0438 0x0439 0x043A 0x043B Q0_A divider Q0_A divider, Bits[7:0] Reserved Q0_A divider, Bits[9:8] Q0_A divider phase, Bits[5:0] Reserved OUT0B mode Invert polarity Q0_B divider, Bits[7:0] Reserved Q0_B divider, Bits[9:8] Q0_B divider phase, Bits[5:0] 0x00 0x00 0x00 0x08 Reserved 0x00 Reserved OUT0B 0x043C Q0_B divider 0x043D 0x043E DPLL_0 Settings for Reference Input A 0x0440 Reference priority 0x0441 W2, L DPLL_0 loop BW 0x0442 W2, L (17 bits) 0x0443 W2, L Reserved REFA priority Digital PLL_0 loop bandwidth scaling factor, Bits[7:0] (in units of 0.1 Hz) Digital PLL_0 loop bandwidth scaling factor, Bits[15:8] (in units of 0.1 Hz) Reserved Base loop filter selection Rev. D | Page 61 of 116 Enable REFA Digital PLL_0 loop BW scaling factor, Bit 16 0x00 0x00 0x00 0x00 0x00 0x00 0x00 AD9554 Reg Addr (Hex) 0x0444 0x0445 0x0446 Option W2 W2 W2 0x0447 0x0448 0x0449 W8 W8 W8 Data Sheet Name DPLL_0 N0 divider (18 bits) DPLL_0 fractional feedback divider (24 bits) 0x044A W2 DPLL_0 fractional 0x044B W2 feedback 0x044C W2 divider modulus (24 bits) DPLL_0 Settings for Reference Input B 0x044D Reference priority 0x044E W2, L DPLL_0 loop BW 0x044F W2, L (17 bits) 0x0450 W2, L 0x0451 0x0452 0x0453 W2 W2 W2 0x0454 0x0455 0x0456 W8 W8 W8 DPLL_0 N0 divider (18 bits) DPLL_0 fractional feedback divider (24 bits) 0x0457 W2 DPLL_0 fractional 0x0458 W2 feedback 0x0459 W2 divider modulus (24 bits) DPLL_0 Settings for Reference Input C 0x045A Reference priority 0x045B W2, L DPLL_0 loop BW 0x045C W2, L (17 bits) 0x045D W2, L D7 D6 D5 D4 D3 D2 Digital PLL_0 feedback divider--Integer Part N0, Bits[7:0] Digital PLL_0 feedback divider--Integer Part N0, Bits[15:8] Reserved D1 D0 Digital PLL_0 feedback divider, Integer Part N0, Bits[17:16] Def (Hex) 0x00 0x00 0x00 Digital PLL_0 fractional feedback divider--FRAC0, Bits[7:0] Digital PLL_0 fractional feedback divider--FRAC0, Bits[15:8] Digital PLL_0 fractional feedback divider--FRAC0, Bits[23:16] 0x00 0x00 0x00 Digital PLL_0 feedback divider modulus--MOD0, Bits[7:0] Digital PLL_0 feedback divider modulus--MOD0, Bits[15:8] Digital PLL_0 feedback divider modulus--MOD0, Bits[23:16] 0x00 0x00 0x00 Reserved REFB priority Digital PLL_0 loop bandwidth scaling factor, Bits[7:0] (unit: 0.1 Hz) Digital PLL_0 loop bandwidth scaling factor, Bits[15:8] (unit: 0.1 Hz) Reserved Base loop filter selection Digital PLL_0 feedback divider--Integer Part N0, Bits[7:0] Digital PLL_0 feedback divider--Integer Part N0, Bits[15:8] Reserved Enable REFB Digital PLL_0 loop BW scaling factor, Bit 16 Digital PLL_0 feedback divider--Integer Part N0, Bits[17:16] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Digital PLL_0 fractional feedback divider--FRAC0, Bits[7:0] Digital PLL_0 fractional feedback divider--FRAC0, Bits[15:8] Digital PLL_0 fractional feedback divider--FRAC0, Bits[23:16] 0x00 0x00 0x00 Digital PLL_0 feedback divider modulus--MOD0, Bits[7:0] Digital PLL_0 feedback divider modulus--MOD0, Bits[15:8] Digital PLL_0 feedback divider modulus--MOD0, Bits[23:16] 0x00 0x00 0x00 Reserved REFC priority Digital PLL_0 loop bandwidth scaling factor, Bits[7:0] (unit: 0.1 Hz) Digital PLL_0 loop bandwidth scaling factor, Bits[15:8] (unit: 0.1 Hz) Reserved Base loop filter selection Enable REFC Digital PLL_0 loop BW scaling factor, Bit 16 0x00 0x00 0x00 0x00 0x045E 0x045F 0x0460 W2 W2 W2 DPLL_0 N0 divider (18 bits) Digital PLL_0 feedback divider--Integer Part N0, Bits[7:0] Digital PLL_0 feedback divider--Integer Part N0, Bits[15:8] Reserved 0x0461 0x0462 0x0463 W8 W8 W8 Digital PLL_0 fractional feedback divider--FRAC0, Bits[7:0] Digital PLL_0 fractional feedback divider--FRAC0, Bits[15:8] Digital PLL_0 fractional feedback divider--FRAC0, Bits[23:16] 0x00 0x00 0x00 0x0464 0x0465 0x0466 W2 W2 W2 DPLL_0 fractional feedback divider (24 bits) DPLL_0 fractional feedback divider modulus (24 bits) Digital PLL_0 feedback divider modulus--MOD0, Bits[7:0] Digital PLL_0 feedback divider modulus--MOD0, Bits[15:8] Digital PLL_0 feedback divider modulus--MOD0, Bits[23:16] 0x00 0x00 0x00 Rev. D | Page 62 of 116 Digital PLL_0 feedback divider--Integer Part N0, Bits[17:16] 0x00 0x00 0x00 Data Sheet AD9554 Reg Addr Option Name D7 (Hex) DPLL_0 Settings for Reference Input D 0x0467 Reference priority 0x0468 W2, L DPLL_0 loop BW 0x0469 W2, L (17 bits) 0x046A W2, L 0x046B 0x046C 0x046D W2 W2 W2 0x046E 0x046F 0x0470 W8 W8 W8 DPLL_0 N0 divider (18 bits) D6 D5 D4 Reserved D3 D2 D1 REFD priority Digital PLL_0 loop bandwidth scaling factor, Bits[7:0] (unit: 0.1 Hz) Digital PLL_0 loop bandwidth scaling factor, Bits[15:8] (unit: 0.1 Hz) Reserved Base loop filter selection Digital PLL_0 feedback divider--Integer Part N0, Bits[7:0] Digital PLL_0 feedback divider--Integer Part N0, Bits[15:8] Reserved D0 Enable REFD Digital PLL_0 loop BW scaling factor, Bit 16 Digital PLL_0 feedback divider--Integer Part N0, Bits[17:16] Digital PLL_0 fractional feedback divider--FRAC0, Bits[7:0] DPLL_0 fractional Digital PLL_0 fractional feedback divider--FRAC0, Bits[15:8] feedback Digital PLL_0 fractional feedback divider--FRAC0, Bits[23:16] divider (24 bits) 0x0471 W2 Digital PLL_0 feedback divider modulus--MOD0, Bits[7:0] DPLL_0 fractional 0x0472 W2 Digital PLL_0 feedback divider modulus--MOD0, Bits[15:8] feedback 0x0473 W2 Digital PLL_0 feedback divider modulus--MOD0, Bits[23:16] divider modulus (24 bits) DPLL_1 General Settings 0x0500 These registers mimic the DPLL_0 general settings registers (0x0400 through 0x041E) but the register addresses are to offset by 0x0100. All default values are identical. 0x051E Output PLL_1 (APLL_1) and Channel 1 Output Drivers 0x0530 These registers mimic the output PLL_0 (APLL_0) general settings registers (0x0430 through 0x043E) but the register to addresses are offset by 0x0100. All default values are identical. 0x053E DPLL_1 Settings for Reference Input A 0x0540 These registers mimic the DPLL_0 settings for Reference Input A registers (0x0440 through 0x044C) but the register to addresses are offset by 0x0100. All default values are identical. 0x054C DPLL_1 Settings for Reference Input B 0x054D These registers mimic the DPLL_0 settings for Reference Input B registers (0x044D through 0x0459) but the register to addresses are offset by 0x0100. All default values are identical. 0x0559 DPLL_1 Settings for Reference Input C 0x055A These registers mimic the DPLL_0 settings for Reference Input C registers (0x045A through 0x0466) but the register to addresses are offset by 0x0100. All default values are identical. 0x0566 DPLL_1 Settings for Reference Input D 0x0567 These registers mimic the DPLL_0 settings for Reference Input D registers (0x0467 through 0x0473) but the register to addresses are offset by 0x0100. All default values are identical. 0x0573 DPLL_2 General Settings 0x0600 These registers mimic the DPLL_0 general settings registers (0x0400 through 0x041E) but the register addresses are to offset by 0x0200. All default values are identical. 0x061E Output PLL_2 (APLL_2) and Channel 2 Output Drivers 0x0630 These registers mimic the output PLL_0 (APLL_0) general settings registers (0x0430 through 0x043E) but the register to addresses are offset by 0x0200. All default values are identical. 0x063E DPLL_2 Settings for Reference Input A 0x0640 These registers mimic the DPLL_0 settings for Reference Input A registers (0x0440 through 0x044C) but the register to addresses are offset by 0x0200. All default values are identical. 0x064C Rev. D | Page 63 of 116 Def (Hex) 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 AD9554 Data Sheet Reg Addr Option Name D7 D6 D5 D4 D3 D2 D1 D0 (Hex) DPLL_2 Settings for Reference Input B 0x064D These registers mimic the DPLL_0 settings for Reference Input B registers (0x044D through 0x0459) but the register to addresses are offset by 0x0200. All default values are identical. 0x0659 DPLL_2 Settings for Reference Input C 0x065A These registers mimic the DPLL_0 settings for Reference Input C registers (0x045A through 0x0466) but the register to addresses are offset by 0x0200. All default values are identical. 0x0666 DPLL_2 Settings for Reference Input D 0x0667 These registers mimic the DPLL_0 settings for Reference Input D registers (0x0467 through 0x0473) but the register to addresses are offset by 0x0200. All default values are identical. 0x0673 DPLL_3 General Settings 0x0700 These registers mimic the DPLL_0 general settings registers (0x0400 through 0x041E) but the register addresses are to offset by 0x0300. All default values are identical. 0x071E Output PLL_3 (APLL_3) and Channel 3 Output Drivers 0x0730 These registers mimic the output PLL_0 (APLL_0) general settings registers (0x0430 through 0x043E) but the register to addresses are offset by 0x0300. All default values are identical. 0x073E DPLL_3 Settings for Reference Input A 0x0740 These registers mimic the DPLL_0 settings for Reference Input A registers (0x0440 through 0x044C) but the register to addresses are offset by 0x0300. All default values are identical. 0x074C DPLL_3 Settings for Reference Input B 0x074D These registers mimic the DPLL_0 settings for Reference Input B registers (0x044D through 0x0459) but the register to addresses are offset by 0x0300. All default values are identical. 0x0759 DPLL_3 Settings for Reference Input C 0x075A These registers mimic the DPLL_0 Settings for Reference Input C registers (0x045A through 0x0466) but the register to addresses are offset by 0x0300. All default values are identical. 0x0766 DPLL_3 Settings for Reference Input D 0x0767 These registers mimic the DPLL_0 Settings for Reference Input D registers (0x0467 through 0x0473) but the register to addresses are offset by 0x0300. All default values are identical. 0x0773 Digital Loop Filter Coefficients 0x0800 L NPM Alpha-0 linear, Bits[7:0] Base loop filter 0x0801 L NPM Alpha-0 linear, Bits[15:8] coefficient 0x0802 L Reserved NPM Alpha-1 exponent, Bits[6:0] set (normal 0x0803 L NPM Beta-0 linear, Bits[7:0] phase margin of 0x0804 L NPM Beta-0 linear, Bits[15:8] 70) 0x0805 L Reserved NPM Beta-1 exponent, Bits[6:0] 0x0806 L NPM Gamma-0 linear, Bits[7:0] 0x0807 L NPM Gamma-0 linear, Bits[15:8] 0x0808 L Reserved NPM Gamma-1 exponent, Bits[6:0] 0x0809 L NPM Delta-0 linear, Bits[7:0] 0x080A L NPM Delta-0 linear, Bits[15:8] 0x080B L Reserved NPM Delta-1 exponent, Bits[6:0] 0x080C L HPM Alpha-0 linear, Bits[7:0] Base loop filter 0x080D L HPM Alpha-0 linear, Bits[15:8] coefficient 0x080E L Reserved HPM Alpha-1 exponent, Bits[6:0] set (high 0x080F L HPM Beta-0 linear, Bits[7:0] phase margin) 0x0810 L HPM Beta-0 linear, Bits[15:8] 0x0811 L Reserved HPM Beta-1 exponent, Bits[6:0] 0x0812 L HPM Gamma-0 linear, Bits[7:0] 0x0813 L HPM Gamma-0 linear, Bits[15:8] 0x0814 L Reserved HPM Gamma-1 exponent, Bits[6:0] 0x0815 L HPM Delta-0 linear, Bits[7:0] 0x0816 L HPM Delta-0 linear, Bits[15:8] 0x0817 L Reserved HPM Delta-1 exponent, Bits[6:0] Rev. D | Page 64 of 116 Def (Hex) 0x24 0x8C 0x49 0x55 0xC9 0x7B 0x9C 0xFA 0x55 0xEA 0xE2 0x57 0x8C 0xAD 0x4C 0xF5 0xCB 0x73 0x24 0xD8 0x59 0xD2 0x8D 0x5A Data Sheet AD9554 Reg Addr Option Name (Hex) Global Demapping Control 0x0900 L Demap control IO_UPDATE 0x0901 DPLL_0 0x0902 0x0903 DPLL_1 0x0904 0x0905 DPLL_2 0x0906 0x0907 DPLL_3 0x0908 0x0909 Demap control IO_UPDATE Common Operational Controls 0x0A00 Global 0x0A01 0x0A02 D7 D6 D5 D4 D3 0x0A03 0x0A04 Reserved Soft sync all Reserved REFD powerdown Reserved Clear DPLL_2 IRQs SYSCLK cal ended REFB fault REFD timeout REFD fault REFD monitor bypass Clear DPLL_1 IRQs SYSCLK cal started Reserved 0x0A06 A 0x0A07 A Clear common IRQ 0x0A08 A 0x0A09 A 0x0A0A A 0x0A0B A 0x0A0C A 0x0A0D A 0x0A0E A 0x0A0F A 0x0A10 A 0x0A11 A 0x0A12 A 0x0A13 A 0x0A14 A Clear watchdog timer SYSCLK unlocked Reserved Reserved REFD fault Reserved Clear DPLL_0 IRQ Clear DPLL_1 IRQ Clear DPLL_2 IRQ Clear DPLL_3 IRQ Frequency unclamped DPLL_0 switching Phase step detected Phase slew limited History updated Clock dist sync'd Frequency unclamped DPLL_1 switching Phase step detected Frequency unclamped DPLL_2 switching Phase step detected Frequency unclamped DPLL_3 switching Phase step detected Reserved SYSCLK stable REFB validated REFD validated Frequency clamped DPLL_0 free run Demap control unclamped Frequency clamped DPLL_1 free run Demap control unclamped Frequency clamped DPLL_2 free run Demap control unclamped Frequency clamped DPLL_3 free run Demap control unclamped Clear DPLL_3 IRQs SYSCLK locked REFB fault cleared REFD fault cleared Phase slew unlimited DPLL_0 holdover Demap control clamped Phase slew unlimited DPLL_1 holdover Demap control clamped Phase slew unlimited DPLL_2 holdover Demap control clamped Phase slew unlimited DPLL_3 holdover Demap control clamped Demap control IO_ UPDATE Def (Hex) 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Powerdown all REFA powerdown 0x00 REFA timeout REFA fault REFA monitor bypass Clear all IRQs 0x00 EEPROM complete REFA fault 0x00 REFC fault 0x00 Frequency unlocked REFD activated APLL_0 unlocked Watchdog timer REFA validated REFC validated Frequency locked REFC activated APLL_0 locked Calibrate all REFB powerdown REFB timeout REFB fault REFB monitor bypass Clear common IRQs EEPROM fault REFA fault cleared REFC fault cleared Phase unlocked REFB activated APLL_0 cal ended Phase locked REFA activated APLL_0 cal started 0x00 Phase slew limited History updated Clock dist sync'd Frequency unlocked REFD activated APLL_1 unlocked Frequency locked REFC activated APLL_1 locked Phase unlocked REFB activated APLL_1 cal ended Phase locked REFA activated APLL_1 cal started 0x00 Phase slew limited History updated Clock dist sync'd Frequency unlocked REFD activated APLL_2 unlocked Frequency locked REFC activated APLL_2 locked Phase unlocked REFB activated APLL_2 cal ended Phase locked REFA activated APLL_2 cal started 0x00 Phase slew limited History updated Clock dist sync'd Frequency unlocked REFD activated APLL_3 unlocked Frequency locked REFC activated APLL_3 locked Phase unlocked REFB activated APLL_3 cal ended Phase locked REFA activated APLL_3 cal started 0x00 Reserved Reserved Clear IRQ groups D0 Demap control IO_ UPDATE DPLL_0 sampled address, Bits[7:0] DPLL_0 sampled address, Bits[15:8] DPLL_1 sampled address, Bits[7:0] DPLL_1 sampled address, Bits[15:8] DPLL_2 sampled address, Bits[7:0] DPLL_2 sampled address, Bits[15:8] DPLL_3 sampled address, Bits[7:0] DPLL_3 sampled address, Bits[15:8] Reserved A A D1 Reserved Reference inputs 0x0A05 D2 Rev. D | Page 65 of 116 Calibrate SYSCLK REFC powerdown REFC timeout REFC fault REFC monitor bypass Clear DPLL_0 IRQs 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 AD9554 Data Sheet Reg Addr Option Name (Hex) PLL_0 Operational Controls 0x0A20 PLL_0 sync cal 0x0A21 PLL_0 output 0x0A22 PLL_0 user mode D7 D6 D5 D4 D3 Reserved Reserved Reserved OUT0B disable DPLL_0 manual reference D1 D0 APLL_0 soft sync APLL_0 calibrate (not selfclearing) OUT0B powerdown DPLL_0 user holdover Reset DPLL_0 TW history DPLL_0 decremen t phase offset PLL_0 powerdown 0x00 OUT0A powerdown DPLL_0 user free run 0x00 Reset DPLL_0 autosync DPLL_0 increment phase offset 0x00 OUT0A disable DPLL_0 switching mode 0x0A23 A PLL_0 reset Reserved Reset DPLL_0 loop filter 0x0A24 A PLL_0 phase Reserved DPLL_0 reset phase offset PLL_1 Operational Controls 0x0A40 These registers mimic the PLL_0 operational controls registers (0x0A20 through 0x0A24) but the register addresses are to offset by 0x0020. All default values are identical. 0x0A44 PLL_2 Operational Controls 0x0A60 These registers mimic the PLL_0 operational controls registers (0x0A20 through 0x0A24) but the register addresses are to offset by 0x0040. All default values are identical. 0x0A64 PLL_3 Operational Controls 0x0A80 These registers mimic the PLL_0 operational controls registers (0x0A20 through 0x0A24) but the register addresses are to offset by 0x0060. All default values are identical. 0x0A84 Voltage Regulator 0x0B00 L VREG, Bits[7:0] Voltage regulator 0x0B01 L Reserved VREG, Bits[9:8] Read Only Status Common Blocks (These registers are accessible during EEPROM transactions. To show the latest status, Register 0x0D02 to Register 0x0D05 require an IO_UPDATE before being read.) 0x0D00 R, L EEPROM Reserved EEPROM EEPROM fault EEPROM EEPROM CRC fault detected download upload in detected in progress progress 0x0D01 R, L Reserved SYSCLK and PLL_3 PLL_2 PLL_1 PLL_0 SYSCLK SYSCLK SYSCLK lock PLL status all locked all locked all locked all locked calibration stable detect busy 0x0D02 R REFA valid REFA fault REFA fast REFA slow Reference DPLL_3 DPLL_2 DPLL_1 DPLL_0 status REFA active REFA active REFA active REFA active 0x0D03 R REFB valid REFB fault REFB fast REFB slow DPLL_3 DPLL_2 DPLL_1 DPLL_0 REFB active REFB active REFB active REFB active 0x0D04 R REFC valid REFC fault REFC fast REFC slow DPLL_3 DPLL_2 DPLL_1 DPLL_0 REFC active REFC active REFC active REFC active 0x0D05 R REFD valid REFD fault REFD fast REFD slow DPLL_3 DPLL_2 DPLL_1 DPLL_0 REFD active REFD active REFD active REFD active 0x0D06 R Reserved 0x0D07 R Reserved IRQ Monitor 0x0D08 R, L IRQ, SYSCLK SYSCLK SYSCLK SYSCLK cal SYSCLK cal Watchdog EEPROM EEPROM common unlocked stable locked ended started timer fault complete 0x0D09 R, L Reserved REFB fault Reserved REFA fault REFB REFB fault REFA REFA fault validated cleared validated cleared 0x0D0A R, L Reserved REFD fault Reserved REFC fault REFD REFD fault REFC REFC fault validated cleared validated cleared 0x0D0B R, L IRQ, DPLL_0 Frequency Frequency Phase slew Phase slew Frequency Frequency Phase Phase unclamped clamped unlimited limited unlocked locked unlocked locked 0x0D0C R, L DPLL_0 DPLL_0 DPLL_0 DPLL_0 REFD REFC REFB REFA switching free run holdover history activated activated activated activated updated 0x0D0D R, L Phase step Demap Demap Clock dist APLL_0 APLL_0 APLL_0 APLL_0 direction control control sync'd unlocked locked cal ended cal started unclamped clamped Rev. D | Page 66 of 116 Def (Hex) D2 0x00 0x00 0x00 0x00 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Data Sheet Reg Addr (Hex) 0x0D0E Option R, L 0x0D0F R, L 0x0D10 R, L 0x0D11 R, L 0x0D12 R, L 0x0D13 R, L 0x0D14 R, L 0x0D15 R, L 0x0D16 R, L AD9554 Name IRQ, DPLL_1 IRQ, DPLL_2 D7 Frequency unclamped DPLL_1 switching D6 Frequency clamped DPLL_1 free run D5 Phase slew unlimited DPLL_1 holdover Phase step direction Demap control unclamped Frequency clamped DPLL_2 free run Demap control clamped Phase slew unlimited DPLL_2 holdover Demap control unclamped Frequency clamped DPLL_3 free run Demap control clamped Phase slew unlimited DPLL_3 holdover Frequency unclamped DPLL_2 switching Phase step direction IRQ, DPLL_3 Frequency unclamped DPLL_3 switching D3 Frequency unlocked REFD activated D2 Frequency locked REFC activated D1 Phase unlocked REFB activated D0 Phase locked REFA activated APLL_1 unlocked APLL_1 locked APLL_1 cal ended APLL_1 cal started N/A Phase slew limited DPLL_2 history updated Clock dist sync'd Frequency unlocked REFD activated Frequency locked REFC activated Phase unlocked REFB activated Phase locked REFA activated N/A APLL_2 unlocked APLL_2 locked APLL_2 cal ended APLL_2 cal started N/A Phase slew limited DPLL_3 history updated Clock dist sync'd Frequency unlocked REFD activated Frequency locked REFC activated Phase unlocked REFB activated Phase locked REFA activated N/A APLL_3 locked APLL_3 cal ended APLL_3 cal started N/A DPLL_0 freq lock DPLL_0 phase lock PLL_0 all locked N/A Demap Demap APLL_3 control control unlocked unclamped clamped PLL_0 Read Only Status (To show the latest status, these registers require an IO_UPDATE before being read.) 0x0D20 R, L Reserved PLL_0 lock APLL_0 cal APLL_0 freq status in progress lock 0x0D21 R 0x0D22 R 0x0D23 0x0D24 0x0D25 0x0D26 0x0D27 0x0D28 R R R R R R Phase step direction DPLL_0 loop state Reserved Reserved DPLL_0 holdover history Def (Hex) N/A D4 Phase slew limited DPLL_1 history updated Clock dist sync'd DPLL_0 active ref DPLL_0 DPLL_0 DPLL_0 free switching holdover run Demap DPLL_0 DPLL_0 DPLL_0 controller phase slew frequency history clamped limited clamped available DPLL_0 tuning word readback, Bits[7:0] DPLL_0 tuning word readback, Bits[15:8] DPLL_0 tuning word readback, Bits[23:16] DPLL_0 tuning word readback, Bits[29:24] DPLL_0 phase lock detect bucket level, Bits[7:0] DPLL_0 phase lock detect bucket level, Bits[11:8] Reserved DPLL_0 phase lock Reserved detect bucket 0x0D29 R DPLL_0 frequency lock detect bucket level, Bits[7:0] DPLL_0 frequency 0x0D2A R Reserved DPLL_0 frequency lock detect bucket level, Bits[11:8] lock detect bucket PLL_1 Read Only Status (To show the latest status, these registers require an IO_UPDATE before being read.) 0x0D40 These registers mimic the PLL_0 read only status registers (0x0D20 through 0x0D2A) but the register addresses are offset to by 0x0020. All default values are identical. 0x0D4A PLL_2 Read Only Status (To show the latest status, these registers require an IO_UPDATE before being read.) 0x0D60 These registers mimic the PLL_0 read only status registers (0x0D20 through 0x0D2A) but the register addresses are offset to by 0x0040. All default values are identical. 0x0D6A PLL_3 Read Only Status (To show the latest status, these registers require an IO_UPDATE before being read.) 0x0D80 These registers mimic the PLL_0 Read Only Status registers (0x0D20 through 0x0D2A) but the register addresses are to offset by 0x0060. All default values are identical. 0x0D8A Nonvolatile Memory (EEPROM) Control 0x0E00 E Reserved Write Enable I2C Write protect fast mode enable 0x0E01 E, L Condition Reserved Conditional value 0x0E02 L, A, E Save Reserved Save to EEPROM 0x0E03 L, A, E Load Reserved Load from EEPROM Rev. D | Page 67 of 116 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0x00 0x00 0x00 0x00 AD9554 Data Sheet Reg Addr Option Name (Hex) EEPROM Storage Sequence 0x0E10 L User free run 0x0E11 L User scratchpad 0x0E12 L 0x0E13 L 0x0E14 L Mx pins and IRQ masks 0x0E15 L 0x0E16 L 0x0E17 L System clock 0x0E18 L 0x0E19 0x0E1A 0x0E1B L L L 0x0E1C 0x0E1D 0x0E1E 0x0E1F 0x0E20 0x0E21 0x0E22 0x0E23 0x0E24 0x0E25 0x0E26 0x0E27 0x0E28 0x0E29 0x0E2A 0x0E2B 0x0E2C 0x0E2D L L L L L L L L L L L L L L L L L L 0x0E2E 0x0E2F 0x0E30 0x0E31 0x0E32 0x0E33 0x0E34 0x0E35 0x0E36 L L L L L L L L L 0x0E37 0x0E38 0x0E39 0x0E3A 0x0E3B 0x0E3C 0x0E3D 0x0E3E 0x0E3F L L L L L L L L L 0x0E40 0x0E41 0x0E42 0x0E43 0x0E44 0x0E45 L L L L L L IO_UPDATE Calibrate SYSCLK REFA D7 D6 D5 D4 D3 D2 D1 D0 Def (Hex) Command: set user free run mode 0x98 Size of transfer: two bytes Starting Address 0x00FE 0x01 0xFE 0x00 0x1F 0x00 0x01 0x08 0x00 0x02 0x80 0x91 Size of transfer: 32 bytes Starting Address 0x0100 Size of transfer: nine bytes Starting Address 0x0200 Command: IO_UPDATE Command: calibrate system clock Size of transfer: 31 bytes Starting Address 0x0300 REFB Size of transfer: 31 bytes Starting Address 0x0320 REFC Size of transfer: 31 bytes Starting Address 0x0340 REFD Size of transfer: 31 bytes Starting Address 0x0360 DPLL_0 general settings Size of transfer: 31 bytes Starting Address 0x0400 APLL_0 config and output drivers DPLL_0 dividers and BW Size of transfer: 15 bytes Starting Address 0x0430 DPLL_1 general settings Size of transfer: 31 bytes Starting Address 0x0500 APLL_1 config and output drivers DPLL_1 dividers and BW Size of transfer: 15 bytes Starting Address 0x0530 DPLL_2 general settings Size of transfer: 31 bytes Starting Address 0x0600 APLL_2 config and output drivers DPLL_2 dividers and BW Size of transfer: 15 bytes Starting Address 0x0630 DPLL_3 general settings Size of transfer: 31 bytes Starting Address 0x0700 Size of transfer: 52 bytes Starting Address 0x0440 Size of transfer: 52 bytes Starting Address 0x0540 Size of transfer: 52 bytes Starting Address 0x0640 Rev. D | Page 68 of 116 0x1E 0x00 0x03 0x1E 0x20 0x03 0x1E 0x40 0x03 0x1E 0x60 0x03 0x1E 0x00 0x04 0x0E 0x30 0x04 0x33 0x40 0x04 0x1E 0x00 0x05 0x0E 0x30 0x05 0x33 0x40 0x05 0x1E 0x00 0x06 0x0E 0x30 0x06 0x33 0x40 0x06 0x1E 0x00 0x07 Data Sheet Reg Addr (Hex) 0x0E46 0x0E47 0x0E48 Option L L L 0x0E49 0x0E4A 0x0E4B 0x0E4C 0x0E4D 0x0E4E 0x0E4F 0x0E50 0x0E51 0x0E52 0x0E53 0x0E54 0x0E55 0x0E56 0x0E57 0x0E58 0x0E59 0x0E5A 0x0E5B 0x0E5C 0x0E5D 0x0E5E 0x0E5F L L L L L L L L L L L L L L L L L L L L L L L 0x0E60 L AD9554 Name APLL_3 config and output drivers DPLL_3 dividers and BW D7 D6 D5 D4 D3 Size of transfer: 15 bytes Starting Address 0x0730 D2 D1 D0 DPLL loop filters Size of transfer: 24 bytes Starting Address 0x0800 Operational controls (common) Size of transfer: 21 bytes Starting Address 0x0A00 PLL_0 operational controls Size of transfer: five bytes Starting Address 0x0A20 PLL_1 operational controls Size of transfer: five bytes Starting Address 0x0A40 PLL_2 operational controls Size of transfer: five bytes Starting Address 0x0A60 PLL_3 operational controls Size of transfer: five bytes Starting Address 0x0A80 IO_UPDATE Calibrate APLLs Sync outputs End of data Unused Command: IO_UPDATE Command: calibrate output PLLs 0x33 0x40 0x07 0x17 0x00 0x08 0x14 0x00 0x0A 0x04 0x20 0x0A 0x04 0x40 0x0A 0x04 0x60 0x0A 0x04 0x80 0x0A 0x80 0x92 Command: distribution sync 0xA0 Command: end of data Unused (available for additional data transfers and/or commands) 0xFF 0x00 VCAL reference access 0x00 0x0E61 L L 0x0E62 to 0x0E6F VCAL Reference Control 0x0FFF VCAL reference access 0x1488 APLL_0 VCAL reference 0x1588 APLL_1 VCAL reference 0x1688 APLL_2 VCAL reference 0x1788 APLL_3 VCAL reference Size of transfer: 52 bytes Starting Address 0x0740 Def (Hex) 0x0E 0x30 0x07 Reserved Reserved Reserved Reserved Rev. D | Page 69 of 116 APLL_0 manual cal level, Bits[1:0] APLL_1 manual cal level, Bits[1:0] APLL_2 manual cal level, Bits[1:0] APLL_3 manual cal level, Bits[1:0] En APLL_0 man cal level En APLL_1 man cal level En APLL_2 man cal level En APLL_3 man cal level 0x00 0x00 0x00 0x00 AD9554 Data Sheet REGISTER MAP BIT DESCRIPTIONS SERIAL CONTROL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0001) Table 33. SPI Configuration A (Note that the contents of Register 0x0000 are not stored to the EEPROM.) Address 0x0000 Bits 7 Bit Name Soft reset (SPI only) 6 LSB first (SPI only) 5 Address ascension (SPI only) 4 SDO active (SPI only) [3:0] Description Device reset (invokes an EEPROM download or pin program ROM download if EEPROM is enabled). Bit order for SPI port. This bit has no effect in IC mode. 1 = least significant bit first. 0 (default) = most significant bit first. This bit controls whether the register address is automatically incremented during a multibyte transfer. This bit has no effect in IC mode. 1 = Register addresses are automatically incremented in multibyte transfers. 0 (default) = Register addresses are automatically decremented in multibyte transfers. Enables SPI port SDO pin. This bit has no effect in IC mode. 1 = 4-wire mode (SDO pin enabled). 0 (default) = 3-wire mode. These bits are mirrors of Bits[7:4] of this register so that when the serial port is configured, the pattern written is independent of an MSB first/LSB first setting interpretation. The AD9554 internal logic performs a logical OR on the corresponding bits. Bit 3 corresponds to Bit 4. Bit 2 corresponds to Bit 5. Bit 1 corresponds to Bit 6. Bit 0 corresponds to Bit 7. Table 34. SPI Configuration B (Note that the contents of Register 0x0001 are not stored to the EEPROM.) Address 0x0001 Bits [7:6] 5 Bit Name Reserved Read buffer register [4:3] 2 Reserved Reset sans regmap [1:0] Reserved Description Reserved. For buffered registers, this bit controls whether the value read from the serial port is from the actual (active) registers or the buffered copy. 1 = reads buffered values that take effect on the next assertion of IO_UPDATE. 0 (default) = reads values currently applied to the internal logic of the device. Reserved. This bit resets the device while maintaining the current register settings. 1 = resets the device. 0 (default) = no action. Reserved. Rev. D | Page 70 of 116 Data Sheet AD9554 CLOCK PART FAMILY ID (REGISTER 0x0003 TO REGISTER 0x0006) Table 35. Clock Part Family ID Address 0x0003 Bits [7:4] [3:0] Bit Name Reserved Chip type, Bits[3:0] 0x0004 [7:4] Clock part serial ID, Bits[3:0] 0x0005 [3:0] [7:0] Reserved Clock part serial ID, Bits[11:4] 0x0006 [7:0] Part version, Bits[7:0] Description Reserved. The Analog Devices unified SPI protocol reserves this read only register location for identifying the type of device. The default value of 0x05 identifies the AD9554 as a clock IC. The Analog Devices unified SPI protocol reserves this read only register location as the lower four bits of the clock part serial ID that (along with Register 0x0005) uniquely identifies the AD9554 within the Analog Devices clock chip family. No other Analog Devices chip that adheres to the Analog Devices unified SPI has these values for Register 0x0003, Register 0x0004, and Register 0x0005. Default: 0x9F. Default: 0xF. The Analog Devices unified SPI protocol reserves this read only register location as the upper eight bits of the clock part serial ID that (along with Register 0x0004) uniquely identifies the AD9554 within the Analog Devices clock chip family. No other Analog Devices chip that adheres to the Analog Devices unified SPI has these values for Register 0x0003, Register 0x0004, and Register 0x0005. Default: 0x00. The Analog Devices unified SPI protocol reserves this read only register location for identifying the die revision. Default: 0x05. SPI VERSION (REGISTER 0x000B) Table 36. SPI Version Address 0x000B Bits [7:0] Bit Name SPI version, Bits[7:0] Description The Analog Devices unified SPI protocol reserves this read only register location for identifying the version of the unified SPI protocol. Default: 0x00. VENDOR ID (REGISTER 0x000C TO REGISTER 0x000D) Table 37. Vendor ID Address 0x000C Bits [7:0] Bit Name Vendor ID, Bits[7:0] 0x000D [7:0] Vendor ID, Bits[15:8] Description The Analog Devices unified SPI protocol reserves this read only register location for identifying Analog Devices as the chip vendor of this device. All Analog Devices devices adhering to the unified serial port specification have the same value in this register. Default: 0x56. The Analog Devices unified SPI protocol reserves this read only register location for identifying Analog Devices as the chip vendor of this device. All Analog Devices devices adhering to the unified serial port specification have the same value in this register. Default: 0x04. IO_UPDATE (REGISTER 0x000F) Table 38. IO_UPDATE Address 0x000F Bits [7:1] 0 Bit Name Reserved IO_UPDATE Description Reserved. Default: 0000000b Writing a 1 to this bit transfers the data in the serial input/output buffer registers to the internal control registers of the device. This is an autoclearing bit. USER SCRATCHPAD (REGISTER 0x00FE TO REGISTER 0x00FF) Table 39. User Scratchpad Address 0x00FE Bits [7:0] Bit Name User scratchpad, Bits[7:0] 0x00FF [7:0] User scratchpad, Bits[15:8] Description This register has no effect on device operation. It is available for serial port debugging or register setting revision control. Default: 0x00. This register has no effect on device operation. It is available for serial port debugging or register setting revision control. Default: 0x00. Rev. D | Page 71 of 116 AD9554 Data Sheet GENERAL CONFIGURATION (REGISTER 0x0100 TO REGISTER 0x010E) Multifunction Pin Control (M0 to M9) and Watchdog Timer Table 40. Multifunction Pins (M0 to M9) Control Address 0x0100 0x0101 0x0102 0x0103 0x0104 0x0105 0x0106 0x0107 0x0108 0x0109 0x010A 0x010B 0x010C Bits [7:6] Bit Name M3 driver mode, Bits[1:0] [5:4] [3:2] [1:0] [7:6] [5:4] [3:2] [1:0] [7:4] [3:2] [1:0] 7 M2 driver mode, Bits[1:0] M1 driver mode, Bits[1:0] M0 driver mode, Bits[1:0] M7 driver mode, Bits[1:0] M6 driver mode, Bits[1:0] M5 driver mode, Bits[1:0] M4 driver mode, Bits[1:0] Reserved M9 driver mode, Bits[1:0] M8 driver mode, Bits[1:0] M0 output/input [6:0] M0 function, Bits[6:0] 7 M1 output/input [6:0] M1 function, Bits[6:0] 7 M2 output/input [6:0] M2 function, Bits[6:0] 7 M3 output/input [6:0] M3 function, Bits[6:0] 7 M4 output/input [6:0] M4 function, Bits[6:0] 7 M5 output/input [6:0] M5 function, Bits[6:0] 7 M6 output/input [6:0] M6 function, Bits[6:0] 7 M7 output/input [6:0] M7 function, Bits[6:0] 7 M8 output/input [6:0] M8 function, Bits[6:0] 7 M9 output/input [6:0] M9 function, Bits[6:0] Description 00 (default) = active high CMOS. 01 = active low CMOS. 10 = open-drain PMOS (requires an external pull-down resistor). 11 = open-drain NMOS (requires an external pull-up resistor). The settings of these bits are identical to Register 0x0100, Bits[7:6]. The settings of these bits are identical to Register 0x0100, Bits[7:6]. The settings of these bits are identical to Register 0x0100, Bits[7:6]. The settings of these bits are identical to Register 0x0100, Bits[7:6]. The settings of these bits are identical to Register 0x0100, Bits[7:6]. The settings of these bits are identical to Register 0x0100, Bits[7:6]. The settings of these bits are identical to Register 0x0100, Bits[7:6]. Reserved. The settings of these bits are identical to Register 0x0100, Bits[7:6]. The settings of these bits are identical to Register 0x0100, Bits[7:6]. Input/output control for M0 pin. 0 (default) = input (control pin). 1 = output (status pin). These bits control the function of the M0 pin. See Table 154 and Table 155 for details about the input and output functions that are available. Default: 0x00 = high impedance control pin, no function assigned. Input/output control for M1 pin (same as for the M0 pin, Register0x0103, Bit 7). These bits control the function of the M1 pin and are the same as Register 0x0103, Bits[6:0]. Default: 0x00 = high impedance control pin, no function assigned. Input/output control for M2 pin (same as for the M0 pin, Register0x0103, Bit 7). These bits control the function of the M2 pin and are the same as Register 0x0103, Bits[6:0]. Default: 0x00 = high impedance control pin, no function assigned. Input/output control for M3 pin (same as for the M0 pin, Register0x0103, Bit 7). These bits control the function of the M3 pin and are the same as Register 0x0103, Bits[6:0]. Default: 0x00 = high impedance control pin, no function assigned. Input/output control for M4 pin (same as for the M0 pin, Register0x0103, Bit 7). These bits control the function of the M4 pin and are the same as Register 0x0103, Bits[6:0]. Default: 0x00 = high impedance control pin, no function assigned. Input/output control for M5 pin (same as for the M0 pin, Register0x0103, Bit 7). These bits control the function of the M5 pin and are the same as Register 0x0103, Bits[6:0]. Default: 0x00 = high impedance control pin, no function assigned. Input/output control for M6 pin (same as for the M0 pin, Register0x0103, Bit 7). These bits control the function of the M6 pin and are the same as Register 0x0103, Bits[6:0]. Default: 0x00 = high impedance control pin, no function assigned. Input/output control for M7 pin (same as for the M0 pin, Register0x0103). These bits control the function of the M7 pin and are the same as Register 0x0103, Bits[6:0]. Default: 0x00 = high impedance control pin, no function assigned. Input/output control for M8 pin (same as for the M0 pin, Register0x0103, Bit 7). These bits control the function of the M8 pin and are the same as Register 0x0103, Bits[6:0]. Default: 0x00 = high impedance control pin, no function assigned. Input/output control for M9 pin (same as for the M0 pin, Register0x0103, Bit 7). These bits control the function of the M9 pin and are the same as Register 0x0103, Bits[6:0]. Default: 0x00 = high impedance control pin, no function assigned. Rev. D | Page 72 of 116 Data Sheet Address 0x010D Bits [7:0] 0x010E [7:0] AD9554 Bit Name Watchdog timer Description Watchdog timer, Bits[7:0]. The watchdog timer stops when this register is written and restarts on the next IO_UPDATE (Register 0x000F = 0x01). Default: 0x00 (0x0000 = disabled). The units are in milliseconds. Watchdog timer, Bits[15:8]. The watchdog timer stops when this register is written and restarts on the next IO_UPDATE (Register 0x000F = 0x01). Default: 0x00. IRQ MASK (REGISTER 0x010F TO REGISTER 0x011F) The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (0x0D08 to 0x0D16). When set to Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask bits is Logic 0, which prevents the IRQ monitor from detecting any internal interrupts. Table 41. IRQ Mask for SYSCLK, Watchdog Timer, and EEPROM Address 0x010F Bits 7 6 5 4 3 2 1 0 Bit Name SYSCLK unlocked SYSCLK stable SYSCLK locked SYSCLK calibration ended SYSCLK calibration started Watchdog timer EEPROM fault EEPROM complete Description Enables IRQ to indicate that the system clock has gone from locked to unlocked. Enables IRQ to indicate that the system clock has gone from unstable to stable. Enables IRQ to indicate that the system clock has gone from unlocked to locked. Enables IRQ to indicate that the system clock calibration sequence has ended. Enables IRQ to indicate that the system clock calibration sequence has started. Enables IRQ to indicate expiration of the watchdog timer. Enables IRQ to indicate a fault during an EEPROM upload or download operation. Enables IRQ to indicate successful completion of an EEPROM upload or download operation. Table 42. IRQ Mask for Reference Inputs Address 0x0110 0x0111 Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Bit Name Reserved REFB validated REFB fault cleared REFB fault Reserved REFA validated REFA fault cleared REFA fault Reserved REFD validated REFD fault cleared REFD fault Reserved REFC validated REFC fault cleared REFC fault Description Reserved. Enables IRQ to indicate that REFB has been validated. Enables IRQ to indicate that REFB has been cleared of a previous fault. Enables IRQ to indicate that REFB has been faulted. Reserved. Enables IRQ to indicate that REFA has been validated. Enables IRQ to indicate that REFA has been cleared of a previous fault. Enables IRQ to indicate that REFA has been faulted. Reserved. Enables IRQ to indicate that REFD has been validated. Enables IRQ to indicate that REFD has been cleared of a previous fault. Enables IRQ to indicate that REFD has been faulted. Reserved. Enables IRQ to indicate that REFC has been validated. Enables IRQ to indicate that REFC has been cleared of a previous fault. Enables IRQ to indicate that REFC has been faulted. Rev. D | Page 73 of 116 AD9554 Data Sheet Table 43. IRQ Mask for the Digital PLL0 (DPLL_0) Address 0x0112 0x0113 0x0114 Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 Bit Name Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked Switching Free run Holdover History updated REFD activated REFC activated REFB activated REFA activated Phase step detection 6 Demap control unclamped 5 Demap control clamped 4 3 2 1 0 Sync clock distribution APLL_0 unlocked APLL_0 locked APLL_0 calibration complete APLL_0 calibration started Description Enables IRQ to indicate that DPLL_0 has exited a frequency clamped state. Enables IRQ to indicate that DPLL_0 has entered a frequency clamped state. Enables IRQ to indicate that DPLL_0 has exited a phase slew limited state. Enables IRQ to indicate that DPLL_0 has entered a phase slew limited state. Enables IRQ to indicate that DPLL_0 has lost frequency lock. Enables IRQ to indicate that DPLL_0 has acquired frequency lock. Enables IRQ to indicate that DPLL_0 has lost phase lock. Enables IRQ to indicate that DPLL_0 has acquired phase lock. Enables IRQ to indicate that DPLL_0 is switching to a new reference. Enables IRQ to indicate that DPLL_0 has entered free run mode. Enables IRQ to indicate that DPLL_0 has entered holdover mode. Enables IRQ to indicate that DPLL_0 has updated its tuning word history. Enables IRQ to indicate that DPLL_0 has activated REFD. Enables IRQ to indicate that DPLL_0 has activated REFC. Enables IRQ to indicate that DPLL_0 has activated REFB. Enables IRQ to indicate that DPLL_0 has activated REFA. Enables IRQ to indicate that DPLL_0 has detected a large phase step at the reference input. Enables IRQ to indicate that the DPLL_0 demapping controller tuning word has become unclamped. Enables IRQ to indicate that the DPLL_0 demapping controller tuning word has become clamped. Enables IRQ for indicating a distribution sync event. Enables IRQ for APLL_0 unlocked. Enables IRQ for APLL_0 locked. Enables IRQ for APLL_0 calibration complete. Enables IRQ for APLL_0 calibration started. Table 44. IRQ Mask for the Digital PLL1 (DPLL_1) Address 0x0115 0x0116 0x0117 Bits [7:0] [7:0] [7:0] Bit Name See Table 43 See Table 43 See Table 43 Description IRQ mask for DPLL_1, same as IRQ mask for the digital PLL0 (DPLL_0) registers (Register 0x0112 through Register 0x0114). All default values are identical. Table 45. IRQ Mask for the Digital PLL2 (DPLL_2) Address 0x0118 0x0119 0x011A Bits [7:0] [7:0] [7:0] Bit Name See Table 43 See Table 43 See Table 43 Description IRQ mask for DPLL_2, same as IRQ mask for the digital PLL0 (DPLL_0) registers (Register 0x0112 through Register 0x0114). All default values are identical. Table 46. IRQ Mask for the Digital PLL3 (DPLL_3) Address 0x011B 0x011C 0x011D Bits [7:0] [7:0] [7:0] Bit Name See Table 43 See Table 43 See Table 43 Description IRQ mask for DPLL_3, same as IRQ mask for the digital PLL0 (DPLL_0) registers (Register 0x0112 through Register 0x0114). All default values are identical. Rev. D | Page 74 of 116 Data Sheet AD9554 Table 47. Pad Control for Mx Pins Address 0x011E 0x011F Bits 7 Bit Name M7 configuration 6 5 4 3 2 1 0 [7:3] 2 1 0 M6 configuration M5 configuration M4 configuration M3 configuration M2 configuration M1 configuration M0 configuration Reserved SPI configuration M9 configuration M8 configuration Description M7 pin output drive strength. 0 (default) = high (approximately 6 mA) drive strength. 1 = low (approximately 3 mA) drive strength. Same as Bit 7 of this register, except that it applies to the M6 pin. Same as Bit 7 of this register, except that it applies to the M5 pin. Same as Bit 7 of this register, except that it applies to the M4 pin. Same as Bit 7 of this register, except that it applies to the M3 pin. Same as Bit 7 of this register, except that it applies to the M2 pin. Same as Bit 7 of this register, except that it applies to the M1 pin. Same as Bit 7 of this register, except that it applies to the M0 pin. Default: 00000b. Same as Bit 7 of Register 0x011E, except that it applies to the M6 pin. Same as Bit 7 of Register 0x011E, except that it applies to the M9 pin. Same as Bit 7 of Register 0x011E, except that it applies to the M8 pin. SYSTEM CLOCK (REGISTER 0x0200 TO REGISTER 0x0208) Table 48. System Clock PLL Feedback Divider (K Divider) and Configuration Address 0x0200 Bits [7:0] Bit Name System clock K divider, Bits[7:0] Description System clock PLL feedback divider value = 4 K 255. Default: 0x00. Table 49. SYSCLK Configuration Address 0x0201 Bits [7:4] 3 Bit Name Reserved SYSCLK XTAL enable [2:1] SYSCLK J1 divider, Bits[1:0] 0 SYSCLK doubler enable (J0 divider) Description Reserved. Enables the crystal maintaining amplifier for the system clock input. 1 (default) = crystal mode (crystal maintaining amplifier enabled). 0 = external crystal oscillator or other system clock source. System clock input divider. 00 (default): /1. 01: /2. 10: /4. 11: /8. Enables the clock doubler on the system clock input to reduce noise. Setting this bit may prevent the SYSCLK PLL from locking if the input duty cycle is not close enough to 50%. See Table 4 for the limits on duty cycle. 0 (default) = disable. 1 = enable. Table 50. System Clock Reference Frequency Address 0x0202 0x0203 0x0204 0x0205 Bits [7:0] [7:0] [7:0] [7:4] [3:0] Bit Name System clock reference frequency (Hz), Bits[23:0] Reserved System clock reference frequency(Hz), Bits[27:24] Description System clock reference frequency, Bits[7:0]. Default: 0x00. System clock reference frequency, Bits[15:8]. Default: 0x00. System clock reference frequency, Bits[23:16]. Default: 0x00. Default: 0x0. System clock reference frequency, Bits[27:24]. Default: 0x0. Rev. D | Page 75 of 116 AD9554 Data Sheet Table 51. System Clock Stability Period Address 0x0206 Bits [7:0] 0x0207 [7:0] 0x0208 [7:4] [3:0] Bit Name System clock stability period (ms), Bits[15:0] Description System clock period, Bits[7:0]. The system clock stability period is the amount of time that the system clock PLL must be locked before it is declared stable. The system clock stability period is reset automatically if the user writes to this register. The system clock stability period restarts on the next IO_UPDATE (Register 0x000F = 0x01). Default: 0x32 (0x000032 = 50 ms). System clock period, Bits[15:8]. The system clock stability period is reset automatically if the user writes to this register. The system clock stability timer restarts on the next IO_UPDATE (Register 0x000F = 0x01). Default: 0x00. Default: 0x0. System clock period, Bits[19:16]. The system clock stability period is reset automatically if the user writes to this register. The system clock stability period restarts on the next IO_UPDATE (Register 0x000F = 0x01). Default: 0x0. The units are in milliseconds. Reserved System clock stability period, Bits[19:16] REFERENCE INPUT A (REGISTER 0x0300 TO REGISTER 0x031E) Table 52. REFA Logic Type Address 0x0300 Bits [7:2] [1:0] Bit Name Reserved REFA logic type, Bits[1:0] Description Default: 000000b. Selects logic family for REFA input receiver; only the REFA pin is used in CMOS mode. 00b (default) = 1.8 V or 1.5 V single-ended CMOS. 01b = ac-coupled differential. 10b = dc-coupled LVDS (fIN 10.24 MHz). 11b = unused. Table 53. REFA R Divider (20 Bits) DPLL Address 0x0301 Bits [7:0] Bit Name R divider, Bits[15:0] 0x0302 0x0303 [7:0] [7:4] [3:0] Reserved R divider, Bits[19:16] Description DPLL integer reference divider (minus 1), Bits[7:0]. Default: 0x00. (For example, 0x00000 equals an R divider of 1.) DPLL integer reference divider (minus 1), Bits[15:8]. Default: 0x00. Default: 0x0. DPLL integer reference divider (minus 1), Bits[19:16]. Default: 0x0. Table 54. Nominal Period of REFA Input Clock Address 0x0304 0x0305 0x0306 0x0307 0x0308 Bits [7:0] [7:0] [7:0] [7:0] [7:0] Bit Name REFA period (fs), Bits[39:0] Description Nominal reference period, Bits[7:0]. Default: 0x00. Nominal reference period, Bits[15:8]. Default: 0x00. Nominal reference period, Bits[23:16]. Default: 0x00. Nominal reference period, Bits[31:24]. Default: 0x00. Nominal reference period, Bits[39:32]. Default: 0x00. Rev. D | Page 76 of 116 Data Sheet AD9554 Table 55. REFA Frequency Tolerance Address 0x0309 Bits [7:0] 0x030A 0x030B [7:0] [7:4] [3:0] 0x030C [7:0] 0x030D 0x030E [7:0] [7:4] [3:0] Bit Name Inner tolerance (1/(ppm error)), Bits[15:0] Reserved Inner tolerance (1/(ppm error)), Bits[19:16] Outer tolerance (1/(ppm error)), Bits[15:0] Reserved Outer tolerance (1/(ppm error)), Bits[19:16] Description Input reference frequency monitor inner tolerance, Bits[7:0]. Default: 0x14. Input reference frequency monitor inner tolerance, Bits[15:8]. Default: 0x00. Default: 0x0. Input reference frequency monitor inner tolerance, Bits[19:16]. Default for Register 0x0309 to Register 0x30B: 0x000014 = 20 (5% or 50,000 ppm). The Stratum 3 clock requires an inner tolerance of 9.2 ppm and an outer tolerance of 12 ppm. An SMC clock requires an outer tolerance of 48 ppm. The allowable range for the inner tolerance is 0x00A (10%) to 0x8FF (2 ppm). Input reference frequency monitor outer tolerance, Bits[7:0]. Default: 0x0A. Input reference frequency monitor outer tolerance, Bits[15:8]. Default: 0x00. Default: 0x0. Input reference frequency monitor outer tolerance, Bits[19:16]. Default for Register 0x030C to Register 0x30E = 0x00000A = 10 (10% or 100,000 ppm). The Stratum 3 clock requires an inner tolerance of 9.2 ppm and an outer tolerance of 12 ppm. An SMC clock requires an outer tolerance of 48 ppm. The outer tolerance must be greater than the inner tolerance so that there is hysteresis. Table 56. REFA Validation Timer Address 0x030F Bits [7:0] 0x0310 [7:0] Bit Name Validation timer (ms), Bits[15:0] (up to 65.5 sec) Description Validation timer, Bits[7:0]. Default: 0x0A. This is the amount of time a reference input must be unfaulted before it is declared valid by the reference input monitor. Default: 10 ms. Validation timer, Bits[15:8]. Default: 0x00. Table 57. REFA Phase/Frequency Lock Detectors Address 0x0311 Bits [7:0] 0x0312 0x0313 0x0314 0x0315 [7:0] [7:0] [7:0] [7:0] 0x0316 [7:0] 0x0317 0x0318 0x0319 [7:0] [7:0] [7:0] 0x031A [7:0] Bit Name Phase lock threshold (ps), Bits[23:0] Phase lock fill rate, Bits[7:0] Phase lock drain rate, Bits[7:0] Frequency lock threshold (ps), Bits[23:0] Frequency lock fill rate, Bits[7:0] Frequency lock drain rate, Bits[7:0] Description Phase lock threshold, Bits[7:0]. Default: 0xBC. Default of 0x0002BC for Register 0x0311 through Register 0x313 = 700 ps. Phase lock threshold, Bits[15:8]. Default: 0x02. Phase lock threshold, Bits[23:16]. Default: 0x00. Phase lock fill rate, Bits[7:0]. Default: 0x0A = 10 code/PFD cycle. Phase lock drain rate, Bits[7:0]. Default: 0x0A = 10 code/PFD cycle. Frequency lock threshold, Bits[7:0]. Default: 0xBC. Default of 0x0002BC for Register 0x0316 through Register 0x318 = 700 ps. This is correct. Frequency lock threshold, Bits[15:8]. Default: 0x02. Frequency lock threshold, Bits[23:16]. Default: 0x00. Frequency lock fill rate, Bits[7:0]. Default: 0x0A = 10 code/PFD cycle. Frequency lock drain rate, Bits[7:0]. Default: 0x0A = 10 code/PFD cycle. Table 58. REFA Phase Step Threshold Address 0x031B Bits [7:0] 0x031C 0x031D 0x031E [7:0] [7:0] [7:4] [3:0] Bit Name Phase step threshold (ps), Bits[23:0] Reserved Phase step threshold (ps), Bits[27:24] Description Phase step threshold, Bits[7:0]. Default: 0x00. Note that a phase step threshold of 0x000000 means that this feature is disabled. Phase step threshold, Bits[15:8]. Default: 0x00. Phase step threshold, Bits[23:16]. Default: 0x00. Default: 0x0. Phase step threshold, Bits[27:24]. Rev. D | Page 77 of 116 AD9554 Data Sheet REFERENCE INPUT B (REGISTER 0x0320 TO REGISTER 0x033E) These registers mimic the Reference Input A registers (Register 0x0300 through Register 0x031E) but the register addresses are offset by 0x0020. All default values are identical. REFERENCE INPUT C (REGISTER 0x0340 TO REGISTER 0x035E) These registers mimic the Reference Input A registers (Register 0x0300 through Register 0x031E) but the register addresses are offset by 0x0040. All default values are identical. REFERENCE INPUT D (REGISTER 0x0360 TO REGISTER 0x037E) These registers mimic the Reference Input A registers (Register 0x0300 through Register 0x031E) but the register addresses are offset by 0x0060. All default values are identical. DPLL_0 CONTROLS (REGISTER 0x0400 TO REGISTER 0x041E) Table 59. DPLL_0 Free Run Frequency Tuning Word Address 0x0400 0x0401 0x0402 0x0403 Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name 30-bit free running frequency tuning word Bits[23:0] Reserved 30-bit free running frequency tuning word Bits[29:24] Description Free running frequency tuning word, Bits[7:0]. Default: 0x00. Free running frequency tuning word, Bits[15:8]. Default: 0x00. Free running frequency tuning word, Bits[23:16]. Default: 0x00. Default: 00b. Free running frequency tuning word, Bits[29:24]. Default: 0x00. Table 60. DPLL_0 DCO Integer Address 0x0404 Bits [7:4] Bit Name Reserved [3:0] DCO integer, Bits[3:0] Description This register is used internally. It is usually 0x1 but may differ depending on how the device is configured. When writing to this register, read the current value and write the same value back to this register. This register contains the integer part of the DCO frequency divider. Valid values are 0x7 to 0xD, and the AD9554 evaluation software frequency planning wizard can help determine the optimal value. Default: 0x7. Table 61. DPLL_0 Frequency Clamp Address 0x0405 Bits [7:0] 0x0406 0x0407 [7:0] [7:4] [3:0] 0x0408 0x0409 0x040A [7:0] [7:0] [7:4] [3:0] Bit Name Lower limit of pull-in range, Bits [15:0] Reserved Lower limit of pull-in range, Bits[19:16] Upper limit of pull-in range, Bits[15:0] Reserved Upper limit of pull-in range, Bits[19:16] Description Lower limit pull-in range, Bits[7:0]. The value in these registers is the 20 most significant bits of the lowest allowable tuning word used by the DPLL. Default: 0xCC. Lower limit pull-in range, Bits[15:8]. Default: 0xCC. Default: 0x0. Lower limit pull-in range, Bits[19:16]. Default: 0x0. Upper limit pull-in range, Bits[7:0]. Default: 0x33. Upper limit pull-in range, Bits[15:8]. Default: 0x33. Default: 0x0. Upper limit pull-in range, Bits[19:16]. Default: 0xF. Table 62. DPLL_0 Holdover History Address 0x040B Bits [7:0] 0x040C [7:0] Bit Name DPLL_0 history accumulation timer (ms), Bits[15:0] Description History accumulation timer, Bits[7:0]. Default: 0x0A. For Register 0x040B and Register 0x040C, 0x000A = 10 ms. Maximum: 65 sec. This register controls the amount of tuning word averaging that determines the tuning word used in holdover. Behavior is undefined for a timer value of 0. Default value: 0x000A = 10 ms. History accumulation timer, Bits[15:8]. Default: 0x00. Rev. D | Page 78 of 116 Data Sheet AD9554 Table 63. DPLL_0 History Mode Address 0x040D Bits [7:5] 4 Bit Name Reserved Single sample fallback 3 Persistent history [2:0] Incremental average, Bits[2:0] Description Reserved. Controls holdover history. If tuning word history is not available for the reference that was active just prior to holdover, then the following: 0 (default) = uses the free running frequency tuning word register value. 1 = uses the last tuning word from the DPLL. Controls holdover history initialization. When switching to a new reference: 0 (default) = clears the tuning word history. 1 = retains the previous tuning word history. History mode value from 0 to 7. Default: 0. When set to nonzero, causes the first history accumulation to update prior to the first complete averaging period. After the first full interval, updates occur only at the full period. 0 (default) = update only after the full interval has elapsed. 1 = update at 1/2 the full interval. 2 = update at 1/4 and 1/2 of the full interval. 3 = update at 1/8, 1/4, and 1/2 of the full interval. ... 7 = update at 1/256, 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, and 1/2 of the full interval. Table 64. DPLL_0 Fixed Closed Loop Phase Offset Address 0x040E 0x040F 0x0410 0x0411 Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name Fixed phase offset (signed; ps) Description Fixed phase offset, Bits[7:0]. Default: 0x00. Fixed phase offset, Bits[15:8]. Default 0x00. Fixed phase offset, Bits[23:16]. Default: 0x00. Reserved; default: 0x0. Fixed phase offset, Bits[29:24]. Default: 0x00. Reserved Fixed phase offset (signed; ps) Table 65. DPLL_0 Incremental Closed-Loop Phase Offset Step Size Address 0x0412 Bits [7:0] 0x0413 [7:0] Bit Name Incremental phase offset step size (ps), Bits[15:0] Description Incremental phase offset step size, Bits[7:0]. Default: 0x00. This register controls the static phase offset step size of the DPLL while it is locked. See Register 0x0A24 for the bits that increment, decrement, and reset the phase offset. Incremental phase offset step size, Bits[15:8]. Default: 0x00. This register controls the static phase offset step size of the DPLL while it is locked. Table 66. DPLL_0 Phase Slew Rate Limit Address 0x0414 Bits [7:0] 0x0415 [7:0] Bit Name Phase slew rate limit (s/sec), Bits[15:0] Description Phase slew rate limit, Bits[7:0]. Default: 0x00. This register controls the maximum allowable phase slewing during phase adjustment. (The phase adjustment controls are in Register 0x040E to Register 0x0411.) Default phase slew rate limit: 0, or disabled. Minimum useful value is 100 s/sec. Phase slew rate limit, Bits[15:8]. Default = 0x00. Rev. D | Page 79 of 116 AD9554 Data Sheet Table 67. DPLL_0 Demapping Control Address 0x0416 Bits [7:1] 0 Bit Name Reserved Enable demap controller 0x0417 0x0418 0x0419 0x041A 0x041B 0x041C 0x041D 0x041E [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Sampled address, Bits[15:0] Set point address, Bits[15:0] Gain, Bits[23:0] Clamp value, Bits[7:0] Description Reserved, Bits[7:1] (default: 0x00) Enables the demapping controller. 0 (default) = The demapping controller is disabled. 1 = The demapping controller is enabled. Sampled address, Bits[7:0]. Default: 0x00. Sampled address, Bits[15:8]. Default: 0x00. Set point address, Bits[7:0]. Default: 0x00. Set point address, Bits[15:8]. Default: 0x00. Gain, Bits[7:0]. Default: 0x00. Gain, Bits[15:8]. Default: 0x00. Gain, Bits[23:16]. Default: 0x00. Clamp value, Bits[7:0]. Default: 0x00. APLL_0 CONFIGURATION (REGISTER 0x0430 TO REGISTER 0x0434) Table 68. Output PLL_0 (APLL_0) Setting1 Address 0x0430 Bits 7 [6:0] 0x0431 [7:0] 0x0432 [7:6] [5:3] [2:0] Bit Name Reserved Output PLL0 (APLL_0) charge pump current, Bits[6:0] Output PLL0 (APLL_0) feedback M0 divider, Bits[7:0] APLL_0 loop filter control, Bits[7:0] Description Default: 0b. LSB: 3.5 A. 0000001b = 1 x LSB; 0000010b = 2 x LSB; 1111111b = 127 x LSB. Default: 0x2E = 451 A CP current. Division: 14 to 255. Default: 0x00. Second pole resistor (RP2). Default: 0x7F. RP2 () Bit 7 500 0 333 (default) 0 250 1 200 1 Zero resistor (RZERO). RZERO () Bit 5 1500 0 1250 0 1000 0 930 0 1250 1 1000 1 750 1 680 (default) 1 First pole capacitor (CP1). CP1 (pF) Bit 2 10 0 30 0 40 0 70 0 90 1 110 1 130 1 150 (default) 1 Rev. D | Page 80 of 116 Bit 6 0 1 0 1 Bit 4 0 0 1 1 0 0 1 1 Bit 3 0 1 0 1 0 1 0 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 Data Sheet Address 0x0433 1 AD9554 Bits [7:2] 1 Bit Name Reserved P0 divider reset 0 APLL_0 loop filter control, Bit 8 Description Default: 0x00. 0 (default) = normal operation for the P0 divider. 1 = P0 divider held in reset. Bypass internal RZERO. 0 (default) = use the internal RZERO resistor. 1 = bypass the internal RZERO resistor (makes RZERO = 0 and requires the use of an external zero resistor in addition to the capacitor to ground on the LF_0 pin). Note that the default APLL loop bandwidth is 240 kHz. OUTPUT PLL_0 (APLL_0) SYNC AND CLOCK DISTRIBUTION (REGISTER 0x0434 TO REGISTER 0x043E) Table 69. P0 Divider Settings1 Address 0x0434 1 Bits [7:4] [3:0] Bit Name Reserved P0 divider divide ratio, Bits[3:0] Description Default: 0x0. 0000b (default)/0001b: undefined. 0010b: /2. This setting is permitted only if the APLL VCO frequency is 2500 MHz. 0011b: /3. 0101b: /5. 0110b: /6. 0111b: /7. 1000b: /8. 1001b: /9. 1010 b: /10. 1011b: /11. If the user changes this register after APLL calibration, the user must either issue another APLL calibration (see Figure 28), or issue a P divider reset for that PLL. For example, if the user reconfigures the P0 divider after APLL_0 calibration, the user must reset the P0 divider using Bit 1 in Register 0x0433. Table 70. Distribution Output Synchronization Settings (OUT0) Address 0x0435 0x0436 Bits [7:3] 2 Bit Name Reserved Sync source selection [1:0] Automatic sync mode, Bits[1:0] [7:3] 2 Reserved APLL_0 mask sync 1 Mask OUT0B sync Description Default: 0x00. Selects the sync source for the clock distribution output channels. 0 (default) = direct. The sync pulse is gated only by APLL calibration and lock. 1 = active reference. This mode is similar to direct mode except that the sync pulse occurs on the next edge of the actively selected reference. Auto sync mode. 00 = (default) disabled. 01 = sync on DPLL frequency lock. 10 = sync on DPLL phase lock. 11 = reserved. Reserved. 0 (default) = the clock distribution SYNC function is delayed until the APLL has been calibrated and is locked. After APLL calibration and lock, the output clock distribution sync is armed, and the SYNC function for the clock outputs is under the control of Register 0x0435. 1 = overrides the lock detector state of the APLL; allows Register 0x0435 to control the output SYNC function, regardless of the APLL lock status. Masks the synchronous reset to the OUT0B divider. 0 (default) = unmasked. 1 = masked. Setting this bit asynchronously releases the OUT0B divider from static sync state, thus allowing the OUT0B divider to toggle. OUT0B ignores all sync events while this bit is set. Setting this bit does not enable the output drivers connected to this channel. Rev. D | Page 81 of 116 AD9554 Address Bits 0 Data Sheet Bit Name Mask OUT0A sync Description Masks the synchronous reset to the OUT0A divider. 0 (default) = unmasked. 1 = masked. Setting this bit asynchronously releases the OUT0A divider from static sync state, thus allowing the OUT0A divider to toggle. OUT0A ignores all sync events while this bit is set. Setting this bit does not enable the output drivers connected to this channel. Table 71. Distribution OUT0A Settings Address 0x0437 Bits [7:3] [2:1] Bit Name Reserved OUT0A mode 0 Invert polarity Description Default: 00. Selects the operating mode of OUT0A. 00 (default) = 14 mA (used for ac-coupled LVDS and dc-coupled HCSL). 01 = 21 mA (intended as an intermediate amplitude setting). 10 = 28 mA (used for ac-coupled LVPECL-compatible amplitudes with 100 termination). Damage to the output drivers can result if the 28 mA mode is used without external termination resistors (either to ground or across the differential pair). 11 = power down and tristate outputs. Controls the OUT0A polarity. 0 (default) = normal polarity. 1 = inverted polarity. Table 72. Q0_A Divider Settings Address 0x0438 Bits [7:0] 0x0439 [7:2] [1:0] 0x043A [7:6] [5:0] Bit Name Q0_A divider , Bits[7:0] Description 10-bit channel divider, Bits[7:0] (LSB). Division equals channel divider, Bits[9:0] + 1. Default: 0x00. [9:0] = 0 is divide-by-1. [9:0] = 1 is divide-by-2. ... [9:0] = 1023 is divide-by-1024. Reserved. Default: 0x00. 10-bit channel divider, Bits[9:8] (MSB). Default: 0x0. Reserved Q0_A divider, Bits[9:8] Reserved Q0_A divider phase, Bits[5:0] Reserved. Default: 0x0. Divider initial phase after sync relative to the divider input clock (from the P0 divider output). LSB is 1/2 of a period of the divider input clock. Phase = 0 is no phase offset. Phase = 1 is 1/2 a period offset. Default: 0x0. Table 73. Distribution OUT0B Settings Address 0x043B Bits [7:3] [2:1] Bit Name Reserved OUT0B mode 0 Invert polarity Description Reserved. Default: 0x00 Selects the operating mode of OUT0B. 00 (default) = 14 mA (used for ac-coupled LVDS and dc-coupled HCSL). 01 = 21 mA (intended as an intermediate amplitude setting). 10 = 28 mA (used for ac-coupled LVPECL-compatible amplitudes with 100 termination).Damage to the output drivers can result if the 28 mA mode is used without external termination resistors (either to ground or across the differential pair). 11 = power down and tristate outputs. Controls the OUT0B polarity. 0 (default) = normal polarity. 1= inverted polarity. Rev. D | Page 82 of 116 Data Sheet AD9554 Table 74. Q0_B Divider Setting Address 0x043C Bits [7:0] Bit Name Q0_B divider, Bits[7:0] 0x043D [7:2] [1:0] [7:6] [5:0] Reserved Q0_B divider, Bits[9:8] Reserved Q0_B divider phase, Bits[5:0] 0x043E Description 10-bit channel divider, Bits[7:0] (LSB). Default: 0x00. Division equals channel divider, Bits[9:0] + 1. [9:0] = 0 is divide-by-1. [9:0] = 1 is divide-by-2. ... [9:0] = 1023 is divide-by-1024. Default: 0x00. 10-bit channel divider, Bits[9:8] (MSB). Default: 0x0. Divider initial phase after sync relative to the divider input clock (from the P0 divider output). LSB is 1/2 of a period of the divider input clock. Default: 0x0. Phase = 0 is no phase offset. Phase = 1 is 1/2 a period offset. DPLL_0 SETTINGS FOR REFERENCE INPUT A (REFA) (REGISTER 0x0440 TO REGISTER 0x044C) Table 75. DPLL_0 REFA Priority Setting Address 0x0440 Bits [7:3] [2:1] Bit Name Reserved REFA priority 0 Enable REFA Description Default: 00000b. These bits set the priority level (0 to 3) of REFA relative to the other input references. 00 (default) = 0 (highest). 01 = 1. 10 = 2. 11 = 3. This bit enables DPLL_0 to lock to REFA. 0 (default) = REFA is not enabled for use by DPLL_0. 1 = REFA is enabled for use by DPLL_0. Table 76. DPLL_0 REFA Loop Bandwidth Scaling Factor Address 0x0441 0x0442 Bits [7:0] [7:0] Bit Name Digital PLL_0 loop bandwidth scaling factor, Bits[15:0] (unit of 0.1 Hz) 0x0443 [7:2] 1 Reserved Base loop filter selection 0 Digital PLL_0 loop BW scaling factor, Bit 16 (unit of 0.1 Hz) Description Digital PLL loop bandwidth scaling factor, Bits[7:0]. Default: 0x0. Digital PLL loop bandwidth scaling factor, Bits[15:8]. Default: 0x00. The default for Register 0x0441 to Register 0x0443 = 0x000000. The loop bandwidth must always be less than the DPLL phase detector frequency divided by 50. The DPLL may not lock reliably if the DPLL loop bandwidth is <50 Hz and a crystal is used for the system clock. See the Choosing the SYSCLK Source section for details. Default: 0x00. 0 = base loop filter with normal (70) phase margin (default). 1 = base loop filter with high phase margin. (For loop bandwidth 2 kHz, there is 0.1 dB peaking in the closed-loop transfer function. Setting this bit is also recommended for loop bandwidths >2 kHz.) Digital PLL loop bandwidth scaling factor, Bit 16. Default: 0x0. Rev. D | Page 83 of 116 AD9554 Data Sheet Table 77. DPLL_0 REFA Integer Part of Feedback (N0) Divider Address 0x0444 Bits [7:0] Bit Name Digital PLL_0 feedback divider--Integer Part N0 0x0445 0x0446 [7:0] [7:2] [1:0] Reserved Digital PLL_0 feedback divider--Integer Part N0 Description DPLL integer feedback divider (minus 1), Bits[7:0]. Default: 0x00. (For example, an N0 divider value of one is achieved by writing 0x000000 to Register 0x0444 to Register 0x0446.) DPLL integer feedback divider, Bits[15:8]. Default: 0x00. Default: 0x00. DPLL integer feedback divider, Bits[17:16]. Default: 0b. Default for Register 0x0444 to Register 0x0446: 0x000000. Table 78. DPLL_0 REFA Fractional Part of Fractional Feedback Divider--FRAC0 Address 0x0447 0x0448 0x0449 Bits [7:0] [7:0] [7:0] Bit Name Digital PLL_0 fractional feedback divider--FRAC0, Bits[23:0] Description The numerator of the fractional-N feedback divider, Bits[7:0]. Default: 0x00. The numerator of the fractional-N feedback divider, Bits[15:8]. Default: 0x00. The numerator of the fractional-N feedback divider, Bits[23:16]. Default: 0x00. Table 79. DPLL_0 REFA Modulus of Fractional Feedback Divider--MOD0 Address 0x044A Bits [7:0] 0x044B 0x044C [7:0] [7:0] Bit Name Digital PLL_0 feedback divider modulus--MOD0, Bits[23:0] Description The denominator of the fractional-N feedback divider, Bits[7:0]. Default: 0x00. Setting MOD0 to 0x000000 disables and bypasses the fractional divider. The denominator of the fractional-N feedback divider, Bits[15:8]. Default: 0x00. The denominator of the fractional-N feedback divider, Bits[23:16]. Default: 0x00. DPLL_0 SETTINGS FOR REFERENCE INPUT B (REFB) (REGISTER 0x044D TO REGISTER 0x0459) Table 80. DPLL_0 REFB Priority Setting Address 0x044D Bits [7:3] [2:1] Bit Name Reserved REFB priority 0 Enable REFB Description Default: 0x00. These bits set the priority level (0 to 3) of REFB relative to the other input references. 00 (default) = 0 (highest). 01 = 1. 10 = 2. 11 = 3. This bit enables DPLL_0 to lock to REFB. 0 (default) = REFB is not enabled for use by DPLL_0. 1 = REFB is enabled for use by DPLL_0. Table 81. DPLL_0 REFB Loop Bandwidth Scaling Factor Address 0x044E Bits [7:0] 0x044F [7:0] Bit Name Digital PLL_0 loop bandwidth scaling factor (unit of 0.1 Hz) 0x0450 [7:2] 1 Reserved Base loop filter selection 0 Digital PLL_0 loop BW scaling factor (unit of 0.1 Hz) Description Digital PLL_0 loop bandwidth scaling factor, Bits[7:0]. Default: 0x00. Operation with the digital PLL_0 loop bandwidth scaling factor set to zero is undefined. Digital PLL_0 loop bandwidth scaling factor, Bits[15:8]. Default: 0x00. The default for Register 0x044E to Register 0x0450 = 0x000000. The loop bandwidth must always be less than the DPLL phase detector frequency divided by 20. The DPLL may not lock reliably if the DPLL loop bandwidth is <50 Hz and a crystal is used for the system clock. See the Choosing the SYSCLK Source section for details. Default: 0x00. 0 = base loop filter with normal (70) phase margin (default). 1 = base loop filter with high phase margin. (For loop bandwidths 2 kHz, there is 0.1 dB peaking in the closed-loop transfer function. Setting this bit is also recommended for loop bandwidths >2 kHz.) Digital PLL loop bandwidth scaling factor, Bit 16. Default: 0b. Rev. D | Page 84 of 116 Data Sheet AD9554 Table 82. DPLL_0 REFB Integer Part of Feedback (N0) Divider Address 0x0451 0x0452 0x0453 Bits [7:0] [7:0] [7:2] [1:0] Bit Name Digital PLL_0 feedback divider--Integer Part N0 Reserved Digital PLL_0 feedback divider--Integer Part N0 Description Digital PLL_0 integer feedback divider (minus 1), Bits[7:0]. Default: 0x00. Digital PLL_0 integer feedback divider, Bits[15:8]. Default: 0x00. Default: 0x00. Digital PLL_0 integer feedback divider, Bits[17:16]. Default: 00. Table 83. DPLL_0 REFB Fractional Part of Fractional Feedback Divider--FRAC0 Address 0x0454 0x0455 0x0456 Bits [7:0] [7:0] [7:0] Bit Name Digital PLL_0 fractional feedback divider--FRAC0 Description The numerator of the fractional-N feedback divider, Bits[7:0]. Default: 0x00. The numerator of the fractional-N feedback divider, Bits[15:8]. Default: 0x00. The numerator of the fractional-N feedback divider, Bits[23:16]. Default: 0x00. Table 84. DPLL_0 REFB Modulus of Fractional Feedback Divider--MOD0 Address 0x0457 0x0458 0x0459 Bits [7:0] [7:0] [7:0] Bit Name Digital PLL_0 feedback divider modulus--MOD0 Description The denominator of the fractional-N feedback divider, Bits[7:0]. Default: 0x00. The denominator of the fractional-N feedback divider, Bits[15:8]. Default: 0x00. The denominator of the fractional-N feedback divider, Bits[23:16]. Default: 0x00. DPLL_0 SETTINGS FOR REFERENCE INPUT C (REFC) (REGISTER 0x045A TO REGISTER 0x0466) Table 85. DPLL_0 REFC Priority Setting Address 0x045A Bits [7:3] [2:1] Bit Name Reserved REFC priority 0 Enable REFC Description Default: 00000b. These bits set the priority level (0 to 3) of REFC relative to the other input references. 00 (default) = 0 (highest). 01 = 1. 10 = 2. 11 = 3. This bit enables DPLL_0 to lock to REFC. 0 (default) = REFC is not enabled for use by DPLL_0. 1 = REFC is enabled for use by DPLL_0. Table 86. DPLL_0 REFC Loop Bandwidth Scaling Factor Address 0x045B 0x045C Bits [7:0] [7:0] Bit Name Digital PLL_0 loop bandwidth scaling factor (unit of 0.1 Hz) 0x045D [7:2] 1 Reserved Base loop filter selection 0 Digital PLL_0 loop BW scaling factor (unit of 0.1 Hz) Description Digital PLL_0 loop bandwidth scaling factor, Bits[7:0]. Default: 0x00. Digital PLL_0 loop bandwidth scaling factor, Bits[15:8]. Default: 0x00. The default for Register 0x045B to Register 0x045D = 0x000000. The loop bandwidth must always be less than the DPLL phase detector frequency divided by 20. The DPLL may not lock reliably if the DPLL loop bandwidth is <50 Hz and a crystal is used for the system clock. See the Choosing the SYSCLK Source section for details. Default: 0x00. 0 = base loop filter with normal (70) phase margin (default). 1 = base loop filter with high phase margin. For loop bandwidth 2 kHz, there is 0.1 dB peaking in the closed-loop transfer function. Setting this bit is also recommended for loop bandwidths >2 kHz.) Digital PLL_0 loop bandwidth scaling factor, Bit 16 (default: 0b). Rev. D | Page 85 of 116 AD9554 Data Sheet Table 87. DPLL_0 REFC Integer Part of Feedback (N0) Divider Address 0x045E 0x045F 0x0460 Bits [7:0] [7:0] [7:2] [1:0] Bit Name Digital PLL_0 feedback divider--Integer Part N0 Reserved Digital PLL_0 feedback divider--Integer Part N0 Description Digital PLL_0 integer feedback divider (minus 1), Bits[7:0]. Default: 0x00. Digital PLL_0 integer feedback divider, Bits[15:8]. Default: 0x00. Default: 0x00. Digital PLL_0 integer feedback divider, Bits[17:16]. Default: 00b. The default for Register 0x045E to Register 0x460: 0x000000. Table 88. DPLL_0 REFC Fractional Part of Fractional Feedback Divider--FRAC0 Address 0x0461 0x0462 0x0463 Bits [7:0] [7:0] [7:0] Bit Name Digital PLL_0 fractional feedback divider--FRAC0 Description The numerator of the fractional-N feedback divider, Bits[7:0]. Default: 0x00. The numerator of the fractional-N feedback divider, Bits[15:8]. Default: 0x00. The numerator of the fractional-N feedback divider, Bits[23:16]. Default: 0x00. Table 89. DPLL_0 REFC Modulus of Fractional Feedback Divider--MOD0 Address 0x0464 0x0465 0x0466 Bits [7:0] [7:0] [7:0] Bit Name Digital PLL_0 feedback divider modulus--MOD0 Description The denominator of the fractional-N feedback divider, Bits[7:0]. Default: 0x00. The denominator of the fractional-N feedback divider, Bits[15:8]. Default: 0x00. The denominator of the fractional-N feedback divider, Bits[23:16]. Default: 0x00. DPLL_0 SETTINGS FOR REFERENCE INPUT D (REFD) (REGISTER 0x0467 TO REGISTER 0x0473) Table 90. DPLL_0 REFD Priority Setting Address 0x0467 Bits [7:3] [2:1] Bit Name Reserved REFD priority 0 Enable REFD Description Default: 00000b. These bits set the priority level (0 to 3) of REFD relative to the other input references. 00 (default) = 0 (highest). 01 = 1. 10 = 2. 11 = 3. This bit enables DPLL_0 to lock to REFD. 0 (default) = REFD is not enabled for use by DPLL_0. 1 = REFD is enabled for use by DPLL_0. Table 91. DPLL_0 REFD Loop Bandwidth Scaling Factor Address 0x0468 0x0469 Bits [7:0] [7:0] Bit Name Digital PLL_0 loop bandwidth scaling factor (unit of 0.1 Hz) 0x046A [7:2] 1 Reserved Base loop filter selection 0 Digital PLL_0 loop BW scaling factor (unit of 0.1 Hz) Description Digital PLL_0 loop bandwidth scaling factor, Bits[7:0]. Default: 0x00. Digital PLL_0 loop bandwidth scaling factor, Bits[15:8]. Default: 0x00. The loop bandwidth must always be less than the DPLL phase detector frequency divided by 20. The DPLL may not lock reliably if the DPLL loop bandwidth is <50 Hz and a crystal is used for the system clock. See the Choosing the SYSCLK Source section for details. Default: 0x00. 0 = base loop filter with normal (70) phase margin (default). 1 = base loop filter with high phase margin. For loop bandwidths 2 kHz, there is 0.1 dB peaking in the closed-loop transfer function. Setting this bit is also recommended for loop bandwidths >2 kHz. Digital PLL loop bandwidth scaling factor, Bit 16. Default: 0b. Rev. D | Page 86 of 116 Data Sheet AD9554 Table 92. DPLL_0 REFD Integer Part of Feedback (N0) Divider Address 0x046B 0x046C 0x046D Bits [7:0] [7:0] [7:2] [1:0] Bit Name Digital PLL_0 feedback divider--Integer Part N0 Reserved Digital PLL_0 feedback divider--Integer Part N0 Description Digital PLL_0 integer feedback divider (minus 1), Bits[7:0]. Default: 0x00. Digital PLL_0 integer feedback divider, Bits[15:8]. Default: 0x00. Default: 0x00. Digital PLL_0 integer feedback divider, Bits[17:16]. Default: 00b. Table 93. DPLL_0 REFD Fractional Part of Fractional Feedback Divider--FRAC0 Address 0x046E 0x046F 0x0470 Bits [7:0] [7:0] [7:0] Bit Name Digital PLL_0 fractional feedback divider--FRAC0 Description The numerator of the fractional-N feedback divider, Bits[7:0]. Default: 0x00. The numerator of the fractional-N feedback divider, Bits[15:8]. Default: 0x00. The numerator of the fractional-N feedback divider, Bits[23:16]. Default: 0x00. Table 94. DPLL_0 REFD Modulus of Fractional Feedback Divider--MOD0 Address 0x0471 0x0472 0x0473 Bits [7:0] [7:0] [7:0] Bit Name Digital PLL_0 feedback divider modulus--MOD0 Description The denominator of the fractional-N feedback divider, Bits[7:0]. Default: 0x00. The denominator of the fractional-N feedback divider, Bits[15:8]. Default: 0x00. The denominator of the fractional-N feedback divider, Bits[23:16]. Default: 0x00. DPLL_1 CONTROLS (REGISTER 0x0500 TO REGISTER 0x051E) These registers mimic the DPLL_0 general settings registers (Register 0x0400 through Register 0x041E) but the register addresses are offset by 0x0100. All default values are identical. APLL_1 CONFIGURATION (REGISTER 0x0530 TO REGISTER 0x0533) These registers mimic the APLL_0 configuration registers (Register 0x0430 through Register 0x0433) but the register addresses are offset by 0x0100. All default values are identical. PLL_1 OUTPUT SYNC AND CLOCK DISTRIBUTION (REGISTER 0x0534 TO REGISTER 0x053E) These registers mimic the PLL_0 output SYNC and clock distribution registers (Register 0x0434 through Register 0x043E) but the register addresses are offset by 0x0100. All default values are identical. DPLL_1 SETTINGS FOR REFERENCE INPUT A (REFA) (REGISTER 0x0540 TO REGISTER 0x054C) These registers mimic the DPLL_0 settings for the Reference Input A (REFA) registers (Register 0x0440 through Register 0x044C) but the register addresses are offset by 0x0100. All default values are identical. DPLL_1 SETTINGS FOR REFERENCE INPUT B (REFB) (REGISTER 0x054D TO REGISTER 0x0559) These registers mimic the DPLL_0 settings for the Reference Input B (REFB) registers (Register 0x044D through Register 0x0459) but the register addresses are offset by 0x0100. All default values are identical. DPLL_1 SETTINGS FOR REFERENCE INPUT C (REFC) (REGISTER 0x055A TO REGISTER 0x0566) These registers mimic the DPLL_0 settings for the Reference Input C (REFC) registers (Register 0x045A through Register 0x0466) but the register addresses are offset by 0x0100. All default values are identical. DPLL_1 SETTINGS FOR REFERENCE INPUT D (REFD) (REGISTER 0x0567 TO REGISTER 0x0573) These registers mimic the DPLL_0 settings for the Reference Input D (REFD) registers (Register 0x0467 through Register 0x0473) but the register addresses are offset by 0x0100. All default values are identical. DPLL_2 CONTROLS (REGISTER 0x0600 TO REGISTER 0x061E) These registers mimic the DPLL_0 controls registers (Register 0x0400 through Register 0x041E) but the register addresses are offset by 0x0200. All default values are identical. APLL_2 CONFIGURATION (REGISTER 0x0630 TO REGISTER 0x0633) These registers mimic the APLL_0 configuration registers (Register 0x0430 through Register 0x0433) but the register addresses are offset by 0x0200. All default values are identical. Rev. D | Page 87 of 116 AD9554 Data Sheet PLL_2 OUTPUT SYNC AND CLOCK DISTRIBUTION (REGISTER 0x0634 TO REGISTER 0x063E) These registers mimic the PLL_0 output SYNC and clock distribution registers (Register 0x0434 through Register 0x043E) but the register addresses are offset by 0x0200. All default values are identical. DPLL_2 SETTINGS FOR REFERENCE INPUT A (REFA) (REGISTER 0x0640 TO REGISTER 0x064C) These registers mimic the DPLL_0 settings for the Reference Input A (REFA) registers (Register 0x0440 through Register 0x044C) but the register addresses are offset by 0x0200. All default values are identical. DPLL_2 SETTINGS FOR REFERENCE INPUT B (REFB) (REGISTER 0x064D TO REGISTER 0x0659) These registers mimic the DPLL_0 settings for the Reference Input B (REFB) registers (Register 0x044D through Register 0x0459) but the register addresses are offset by 0x0200. All default values are identical. DPLL_2 SETTINGS FOR REFERENCE INPUT C (REFC) (REGISTER 0x065A TO REGISTER 0x0666) These registers mimic the DPLL_0 settings for the Reference Input C (REFC) registers (Register 0x045A through Register 0x0466) but the register addresses are offset by 0x0200. All default values are identical. DPLL_2 SETTINGS FOR REFERENCE INPUT D (REFD) (REGISTER 0x0667 TO REGISTER 0x0673) These registers mimic the DPLL_0 settings for the Reference Input D (REFD) registers (Register 0x0467 through Register 0x0473) but the register addresses are offset by 0x0200. All default values are identical. DPLL_3 CONTROLS (REGISTER 0x0700 TO REGISTER 0x071E) These registers mimic the DPLL_0 controls registers (Register 0x0400 through Register 0x041E) but the register addresses are offset by 0x0300. All default values are identical. APLL_3 CONFIGURATION (REGISTER 0x0730 TO REGISTER 0x0733) These registers mimic the APLL_0 configuration registers (Register 0x0430 through Register 0x0433) but the register addresses are offset by 0x0300. All default values are identical. PLL_3 OUTPUT SYNC AND CLOCK DISTRIBUTION (REGISTER 0x0734 TO REGISTER 0x073E) These registers mimic the PLL_0 output SYNC and clock distribution registers (Register 0x0434 through Register 0x043E) but the register addresses are offset by 0x0300. All default values are identical. DPLL_3 SETTINGS FOR REFERENCE INPUT A (REFA) (REGISTER 0x0740 TO REGISTER 0x074C) These registers mimic the DPLL_0 settings for the Reference Input A (REFA) registers (Register 0x0440 through Register 0x044C) but the register addresses are offset by 0x0300. All default values are identical. DPLL_3 SETTINGS FOR REFERENCE INPUT B (REFB) (REGISTER 0x074D TO REGISTER 0x0759) These registers mimic the DPLL_0 settings for the Reference Input B (REFB) registers (Register 0x044D through Register 0x0459) but the register addresses are offset by 0x0300. All default values are identical. DPLL_3 SETTINGS FOR REFERENCE INPUT C (REFC) (REGISTER 0x075A TO REGISTER 0x0766) These registers mimic the DPLL_0 settings for the Reference Input C (REFC) registers (Register 0x045A through Register 0x0466) but the register addresses are offset by 0x0300. All default values are identical. DPLL_3 SETTINGS FOR REFERENCE INPUT D (REFD) (REGISTER 0x0767 TO REGISTER 0x0773) These registers mimic the DPLL_0 settings for the Reference Input D (REFD) registers (Register 0x0467 through Register 0x0473) but the register addresses are offset by 0x0300. All default values are identical. Rev. D | Page 88 of 116 Data Sheet AD9554 DIGITAL LOOP FILTER COEFFICIENTS (REGISTER 0x0800 TO REGISTER 0x0817) Note that the digital loop filter base coefficients (, , , and ) have the general form: x(2y), where x is the linear component, and y is the exponential component of the coefficient. The value of the linear component (x) constitutes a fraction, where 0 x 1. The exponential component (y) is a signed integer. These are live registers; therefore, an IO_UPDATE is not needed. However, the updated coefficients do not take effect while the loop is active. Table 95. Base Digital Loop Filter with Normal Phase Margin (PM = 70) Address 0x0800 0x0801 0x0802 0x0803 0x0804 0x0805 0x0806 0x0807 0x0808 0x0809 0x080A 0x080B Bits [7:0] [7:0] 7 [6:0] [7:0] [7:0] 7 [6:0] [7:0] [7:0] 7 [6:0] [7:0] [7:0] 7 [6:0] Bit Name NPM Alpha-0 linear Reserved NPM Alpha-1 exponent NPM Beta-0 linear Reserved NPM Beta-1 exponent NPM Gamma-0 linear Reserved NPM Gamma -1 exponent NPM Delta-0 linear Reserved NPM Delta-1 exponent Description Alpha-0 coefficient linear, Bits[7:0]. Default: 0x24. Alpha-0 coefficient linear, Bits[15:8]. Default: 0x8C. Default: 0b. Alpha-1 coefficient exponent, Bits[6:0]. Default: 0x49. Beta-0 coefficient linear, Bits[7:0]. Default: 0x55. Beta-0 coefficient linear, Bits[15:8]. Default: 0xC9. Default: 0b. Beta-1 coefficient exponent, Bits[6:0]. Default: 0x7B. Gamma-0 coefficient linear, Bits[7:0]. Default: 0x9C. Gamma-0 coefficient linear, Bits[15:8]. Default: 0xFA. Default: 0b. Gamma-1 coefficient exponent, Bits[6:0]. Default: 0x55. Delta-0 coefficient linear, Bits[7:0]. Default: 0xEA. Delta-0 coefficient linear, Bits[15:8]. Default: 0xE2. Default: 0b. Delta-1 coefficient exponent, Bits[6:0]. Default: 0x57. Note that the base digital loop filter coefficients (, , , and ) have the general form: x(2y), where x is the linear component, and y is the exponential component of the coefficient. The value of the linear component (x) constitutes a fraction, where 0 x 1. The exponential component (y) is a signed integer. These are live registers; therefore, an IO_UPDATE is not needed. However, the updated coefficients do not take effect while the loop is active. Table 96. Base Digital Loop Filter with High Phase Margin (PM = 88.5) Address 0x080C 0x080D 0x080E 0x080F 0x0810 0x0811 0x0812 0x0813 0x0814 0x0815 0x0816 0x0817 Bits [7:0] [7:0] 7 [6:0] [7:0] [7:0] 7 [6:0] [7:0] [7:0] 7 [6:0] [7:0] [7:0] 7 [6:0] Bit Name HPM Alpha-0 linear Reserved HPM Alpha-1 exponent HPM Beta-0 linear Reserved HPM Beta-1 exponent HPM Gamma-0 linear Reserved HPM Gamma-1 exponent HPM Delta-0 linear Reserved HPM Delta-1 exponent Description Alpha-0 coefficient linear, Bits[7:0]. Default = 0x8C. Alpha-0 coefficient linear, Bits[15:8]. Default: 0xAD. Default: 0b. Alpha-1 coefficient exponent, Bits[6:0]. Default: 0x4C. Beta-0 coefficient linear, Bits[7:0]. Default: 0xF5. Beta-0 coefficient linear, Bits[15:8]. Default: 0xCB. Default: 0b. Beta-1 coefficient exponent, Bits[6:0]. Default: 0x73. Gamma-0 coefficient linear, Bits[7:0]. Default: 0x24. Gamma-0 coefficient linear, Bits[15:8]. Default: 0xD8. Default: 0b. Gamma-1 coefficient exponent, Bits[6:0]. Default: 0x59. Delta-0 coefficient linear, Bits[7:0]. Default: 0xD2. Delta-0 coefficient linear, Bits[15:8]. Default: 0x8D. Default: 0b. Delta-1 coefficient exponent, Bits[6:0]. Default: 0x5A. Rev. D | Page 89 of 116 AD9554 Data Sheet Table 97. Global Demapping Control Address 0x0900 Bits [7:1] 0 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:1] 0 0x0901 0x0902 0x0903 0x0904 0x0905 0x0906 0x0907 0x0908 0x0909 Bit Name Reserved Demap control IO_UPDATE DPLL_0 sampled address, Bits[15:0] DPLL_1 sampled address, Bits[15:0] DPLL_2 sampled address, Bits[15:0] DPLL_3 sampled address, Bits[15:0] Reserved Demap control IO_UPDATE Description Reserved, Bits[7:1]. Default = 0x00. Demap control IO_UPDATE, Bit 0. Default = 0b. DPLL_0 sampled address, Bits[7:0]. Default = 0x00. DPLL_0 sampled address, Bits[15:8]. Default: 0x00. DPLL_1 sampled address, Bits[7:0]. Default = 0x00. DPLL_1 sampled address, Bits[15:8]. Default: 0x00. DPLL_2 sampled address, Bits[7:0]. Default = 0x00. DPLL_2 sampled address, Bits[15:8]. Default: 0x00 DPLL_3 sampled address, Bits[7:0]. Default = 0x00. DPLL_3 sampled address, Bits[15:8]. Default: 0x00. Reserved, Bits[7:1]. Default = 0x00. Demap control IO_UPDATE, Bit 0. Default = 0b. COMMON OPERATIONAL CONTROLS (REGISTER 0x0A00 TO REGISTER 0x0A0E) Table 98. Global Operational Controls Address 0x0A00 Bits [7:4] 3 Bit Name Reserved Soft sync all 2 Calibrate SYSCLK 1 Calibrate all 0 Power-down all Description Default: 0x0. Setting this bit initiates synchronization of all clock distribution outputs (default = 0b). Nonmasked outputs stall when value is 1; restart is initialized on a 1-to-0 transition. Note that like all buffered registers, an IO_UPDATE (0x000F = 0x01) is needed every time there is a change for this bit to take effect. A 0-to-1 transition of this bit (followed by an IO_UPDATE) calibrates the SYSCLK PLL. Default: 0b. A 0-to-1 transition of this bit (followed by an IO_UPDATE) calibrates the system clock PLL, as well as all four output PLLs (APLL_0, APLL_1, APLL_2, APLL_3). Default: 0b. Note that like all buffered registers, an IO_UPDATE (0x000F = 0x01) is needed every time there is a change for this bit to take effect. This bit is not self clearing; however, it is strongly recommended to clear this bit after using it. If this bit is set, calibration of the individual APLLs (APLL_0, APLL_1, APLL_2, and APLL_3) in Register 0xA20, Register 0xA40, Register 0xA60, and Register 0xA80 is masked and APLL calibration does not occur. Places the entire device in deep sleep mode. Default: device is not powered down. Table 99. Power Down of Reference Inputs Address 0x0A01 Bits [7:4] 3 Bit Name Reserved REFD power-down 2 REFC power-down 1 REFB power-down 0 REFA power-down Description Default: 0x0 Powers down REFD input receiver 0 (default) = not powered down 1 = powered down Powers down REFC input receiver 0 (default) = not powered down 1 = powered down Powers down REFB input receiver 0 (default) = not powered down 1 = powered down Powers down REFA input receiver 0 (default) = not powered down 1 = powered down Rev. D | Page 90 of 116 Data Sheet AD9554 Table 100. Reference Input Validation Timeout Address 0x0A02 Bits [7:4] 3 Bit Name Reserved REFD timeout 2 REFC timeout 1 REFB timeout 0 REFA timeout Description Default: 0x0. If REFD is unfaulted, setting this autoclearing bit forces the reference validation timer for REFD to zero, thus making it valid immediately. Default = 0b. If REFC is unfaulted, setting this autoclearing bit forces the reference validation timer for REFC to zero, thus making it valid immediately. Default = 0b. If REFB is unfaulted, setting this autoclearing bit forces the reference validation timer for REFB to zero, thus making it valid immediately. Default = 0b. If REFA is unfaulted, setting this autoclearing bit forces the reference validation timer for REFA to zero, thus making it valid immediately. Default = 0b. Table 101. Force Reference Input Fault Address 0x0A03 Bits [7:4] 3 Bit Name Reserved REFD fault 2 REFC fault 1 REFB fault 0 REFA fault Description Default: 0x0 Faults REFD input receiver 0 (default) = not faulted 1 = faulted (REFD is not used) Faults REFC input receiver 0 (default) = not faulted 1 = faulted (REFC is not used) Faults REFB input receiver 0 (default) = not faulted 1 = faulted (REFB is not used) Faults REFA input receiver 0 (default) = not faulted 1 = faulted (REFA is not used) Table 102. Reference Input Monitor Bypass Address 0x0A04 Bits [7:4] 3 Bit Name Reserved REFD monitor bypass 2 REFC monitor bypass 1 REFB monitor bypass 0 REFA monitor bypass Description Default: 0x0 Bypasses REFD input receiver frequency monitor; setting this bit to 1 forces REFD to be unfaulted as long as the REFD fault bit in Register 0x0A03 is not set. 0 (default) = REFD frequency monitor not bypassed. 1 = REFD frequency monitor bypassed. Bypasses REFC input receiver frequency monitor; setting this bit to 1 forces REFC to be unfaulted as long as the REFC fault bit in Register 0x0A03 is not set. 0 (default) = REFC frequency monitor not bypassed. 1 = REFC frequency monitor bypassed. Bypasses REFB input receiver frequency monitor; setting this bit to 1 forces REFB to be unfaulted as long as the REFB fault bit in Register 0x0A03 is not set. 0 (default) = REFB frequency monitor not bypassed. 1 = REFBB frequency monitor bypassed. Bypasses REFA input receiver frequency monitor; setting this bit to 1 forces REFA to be unfaulted as long as the REFA fault bit in Register 0x0A03 is not set. 0 (default) = REFA frequency monitor not bypassed. 1 = REFA frequency monitor bypassed. Rev. D | Page 91 of 116 AD9554 Data Sheet IRQ CLEARING (REGISTER 0x0A05 TO REGISTER 0x0A14) The IRQ clearing registers are identical in format to the IRQ monitor registers (Register 0x0D08 to Register 0x0A14). When set to Logic 1, an IRQ clearing bit resets the corresponding IRQ monitor bit, thereby cancelling the interrupt request for the indicated event. The IRQ clearing registers are autoclearing. Table 103. Clear IRQ Groups Address 0x0A05 Bits 7 6 5 4 3 2 1 0 Bit Name Clear watchdog timer Reserved Clear DPLL_3 IRQs Clear DPLL_2 IRQs Clear DPLL_1 IRQs Clear DPLL_0 IRQs Clear common IRQs Clear all IRQs Description Clears watchdog timer alert Reserved Clears all IRQs associated with DPLL_3 Clears all IRQs associated with DPLL_2 Clears all IRQs associated with DPLL_1 Clears all IRQs associated with DPLL_0 Clears all IRQs associated with common IRQ group Clears all IRQs Table 104. IRQ Clearing for SYSCLK and EEPROM Address 0x0A06 Bits 7 6 Bit Name SYSCLK unlocked SYSCLK stable 5 4 3 2 1 0 SYSCLK locked SYSCLK cal ended SYSCLK cal started Watchdog timer EEPROM fault EEPROM complete Description Clears IRQ indicating a SYSCLK PLL state transition from locked to unlocked Clears IRQ indicating that SYSCLK stability time has expired and that the SYSCLK PLL is considered to be stable Clears IRQ indicating a SYSCLK PLL state transition from unlocked to locked Clears IRQ indicating a SYSCLK PLL calibration has ended Clears IRQ indicating a SYSCLK PLL calibration has started Clears IRQ indicating expiration of the watchdog timer Clears IRQ indicating a fault during an EEPROM upload or download operation Clears IRQ indicating successful completion of an EEPROM upload or download operation Table 105. IRQ Clearing for Reference Inputs Address 0x0A07 0x0A08 Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Bit Name Reserved REFB validated REFB fault cleared REFB fault Reserved REFA validated REFA fault cleared REFA fault Reserved REFD validated REFD fault cleared REFD fault Reserved REFC validated REFC fault cleared REFC fault Description Reserved Clears IRQ indicating that REFB has been validated Clears IRQ indicating that REFB has been cleared of a previous fault Clears IRQ indicating that REFB has been faulted Reserved Clears IRQ indicating that REFA has been validated Clears IRQ indicating that REFA has been cleared of a previous fault Clears IRQ indicating that REFA has been faulted Reserved Clears IRQ indicating that REFD has been validated Clears IRQ indicating that REFD has been cleared of a previous fault Clears IRQ indicating that REFD has been faulted Reserved Clears IRQ indicating that REFC has been validated Clears IRQ indicating that REFC has been cleared of a previous fault Clears IRQ indicating that REFC has been faulted Rev. D | Page 92 of 116 Data Sheet AD9554 Table 106. IRQ Clearing for Digital PLL0 (DPLL_0) Address 0x0A09 0x0A0A 0x0A0B Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Bit Name Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked DPLL_0 switching DPLL_0 free run DPLL_0 holdover History updated REFD activated REFC activated REFB activated REFA activated Phase step detected Demap control unclamped Demap control clamped Clock dist sync'd APLL_0 unlocked APLL_0 locked APLL_0 cal ended APLL_0 cal started Description Clears IRQ indicating that DPLL_0 has exited a frequency unclamped state Clears IRQ indicating that DPLL_0 has entered a frequency clamped state Clears IRQ indicating that DPLL_0 has exited a phase slew limited state Clears IRQ indicating that DPLL_0 has entered a phase slew limited state Clears IRQ indicating that DPLL_0 has lost frequency lock Clears IRQ indicating that DPLL_0 has acquired frequency lock Clears IRQ indicating that DPLL_0 has lost phase lock Clears IRQ indicating that DPLL_0 has acquired phase lock Clears IRQ indicating that DPLL_0 is switching to a new reference Clears IRQ indicating that DPLL_0 has entered free run mode Clears IRQ indicating that DPLL_0 has entered holdover mode Clears IRQ indicating that DPLL_0 has updated its tuning word history Clears IRQ indicating that DPLL_0 has activated REFD Clears IRQ indicating that DPLL_0 has activated REFC Clears IRQ indicating that DPLL_0 has activated REFB Clears IRQ indicating that DPLL_0 has activated REFA Clears IRQ indicating that DPLL_0 has detected a large phase step at its input Clears IRQ indicating that the DPLL_0 demapping controller has an unclamped state Clears IRQ indicating that the DPLL_0 demapping controller has a clamped state Clears IRQ indicating a distribution sync event Clears IRQ indicating that APLL_0 has been unlocked Clears IRQ indicating that APLL_0 has been locked Clears IRQ indicating that APLL_0 calibration complete Clears IRQ indicating that APLL_0 calibration started Table 107. IRQ Clearing for Digital PLL1 (DPLL_1) Address 0x0A0C 0x0A0D Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Bit Name Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked DPLL_1 switching DPLL_1 free run DPLL_1 holdover History updated REFD activated REFC activated REFB activated REFA activated Description Clears IRQ indicating that DPLL_1 has exited a frequency unclamped state Clears IRQ indicating that DPLL_1 has entered a frequency clamped state Clears IRQ indicating that DPLL_1 has exited a phase slew limited state Clears IRQ indicating that DPLL_1 has entered a phase slew limited state Clears IRQ indicating that DPLL_1 has lost frequency lock Clears IRQ indicating that DPLL_1 has acquired frequency lock Clears IRQ indicating that DPLL_1 has lost phase lock Clears IRQ indicating that DPLL_1 has acquired phase lock Clears IRQ indicating that DPLL_1 is switching to a new reference Clears IRQ indicating that DPLL_1 has entered free run mode Clears IRQ indicating that DPLL_1 has entered holdover mode Clears IRQ indicating that DPLL_1 has updated its tuning word history Clears IRQ indicating that DPLL_1 has activated REFD Clears IRQ indicating that DPLL_1 has activated REFC Clears IRQ indicating that DPLL_1 has activated REFB Clears IRQ indicating that DPLL_1 has activated REFA Rev. D | Page 93 of 116 AD9554 Address 0x0A0E Data Sheet Bits 7 6 5 4 3 2 1 0 Bit Name Phase step detected Demap control unclamped Demap control clamped Clock dist sync'd APLL_1 unlocked APLL_1 locked APLL_1 cal ended APLL_1 cal started Description Clears IRQ indicating that DPLL_1 has detected a large phase step at its input Clears IRQ indicating that the DPLL_1 demapping controller has an unclamped state Clears IRQ indicating that the DPLL_1 demapping controller has a clamped state Clears IRQ indicating a distribution sync event Clears IRQ indicating that APLL_1 has been unlocked Clears IRQ indicating that APLL_1 has been locked Clears IRQ indicating that APLL_1 calibration complete Clears IRQ indicating that APLL_1 calibration started Table 108. IRQ Clearing for Digital PLL2 (DPLL_2) Address 0x0A0F 0x0A10 0x0A11 Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Bit Name Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked DPLL_2 switching DPLL_2 free run DPLL_2 holdover History updated REFD activated REFC activated REFB activated REFA activated Phase step detected Demap control unclamped Demap control clamped Clock dist sync'd APLL_2 unlocked APLL_2 locked APLL_2 cal ended APLL_2 cal started Description Clears IRQ indicating that DPLL_2 has exited a frequency unclamped state Clears IRQ indicating that DPLL_2 has entered a frequency clamped state Clears IRQ indicating that DPLL_2 has exited a phase slew limited state Clears IRQ indicating that DPLL_2 has entered a phase slew limited state Clears IRQ indicating that DPLL_2 has lost frequency lock Clears IRQ indicating that DPLL_2 has acquired frequency lock Clears IRQ indicating that DPLL_2 has lost phase lock Clears IRQ indicating that DPLL_2 has acquired phase lock Clears IRQ indicating that DPLL_2 is switching to a new reference Clears IRQ indicating that DPLL_2 has entered free run mode Clears IRQ indicating that DPLL_2 has entered holdover mode Clears IRQ indicating that DPLL_2 has updated its tuning word history Clears IRQ indicating that DPLL_2 has activated REFD Clears IRQ indicating that DPLL_2 has activated REFC Clears IRQ indicating that DPLL_2 has activated REFB Clears IRQ indicating that DPLL_2 has activated REFA Clears IRQ indicating that DPLL_2 has detected a large phase step at its input Clears IRQ indicating that the DPLL_2 demapping controller is unclamped Clears IRQ indicating that the DPLL_2 demapping controller is clamped Clears IRQ indicating a distribution sync event Clears IRQ indicating that APLL_2 has been unlocked Clears IRQ indicating that APLL_2 has been locked Clears IRQ indicating that APLL_2 calibration complete Clears IRQ indicating that APLL_2 calibration started Rev. D | Page 94 of 116 Data Sheet AD9554 Table 109. IRQ Clearing for Digital PLL3 (DPLL_3) Address 0x0A12 0x0A13 0x0A14 Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Bit Name Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked DPLL_3 switching DPLL_3 free run DPLL_3 holdover History updated REFD activated REFC activated REFB activated REFA activated Phase step detected Demap control unclamped Demap control clamped Clock dist sync'd APLL_3 unlocked APLL_3 locked APLL_3 cal ended APLL_3 cal started Description Clears IRQ indicating that DPLL_3 has exited a frequency unclamped state Clears IRQ indicating that DPLL_3 has entered a frequency clamped state Clears IRQ indicating that DPLL_3 has exited a phase slew limited state Clears IRQ indicating that DPLL_3 has entered a phase slew limited state Clears IRQ indicating that DPLL_3 has lost frequency lock Clears IRQ indicating that DPLL_3 has acquired frequency lock Clears IRQ indicating that DPLL_3 has lost phase lock Clears IRQ indicating that DPLL_3 has acquired phase lock Clears IRQ indicating that DPLL_3 is switching to a new reference Clears IRQ indicating that DPLL_3 has entered free run mode Clears IRQ indicating that DPLL_3 has entered holdover mode Clears IRQ indicating that DPLL_3 has updated its tuning word history Clears IRQ indicating that DPLL_3 has activated REFD Clears IRQ indicating that DPLL_3 has activated REFC Clears IRQ indicating that DPLL_3 has activated REFB Clears IRQ indicating that DPLL_3 has activated REFA Clears IRQ indicating that DPLL_3 has detected a large phase step at its input Clears IRQ indicating that the DPLL_3 demapping controller is unclamped Clears IRQ indicating that the DPLL_3 demapping controller is clamped Clears IRQ indicating a distribution sync event Clears IRQ indicating that APLL_3 has been unlocked Clears IRQ indicating that APLL_3 has been locked Clears IRQ indicating that APLL_3 calibration complete Clears IRQ indicating that APLL_3 calibration started PLL_0 OPERATIONAL CONTROLS (REGISTER 0x0A20 TO REGISTER 0x0A24) Table 110. PLL_0 Sync and Calibration Address 0x0A20 Bits [7:3] 2 Bit Name Reserved APLL_0 soft sync 1 APLL_0 calibrate (not selfclearing) 0 PLL_0 power-down Description Default: 0x0. Setting this bit initiates synchronization of the clock distribution output. 0 (default) = normal operation. 1 = nonmasked PLL_0 outputs stall; restart initialized on a 1-to-0 transition. 1 = initiates VCO calibration (calibration occurs on the IO_UPDATE following a 0-to-1 transition of this bit.) This bit is not autoclearing. 0 (default) = does nothing. Places DPLL_0, APLL_0, and PLL_0 clock in deep sleep mode. 0 (default) = normal operation. 1 = powered down. Table 111. PLL_0 Output Address 0x0A21 Bits [7:4] 3 Bit Name Reserved OUT0B disable 2 OUT0A disable 1 OUT0B power-down 0 OUT0A power-down Description Default 0x0 Setting this bit puts the OUT0B driver into power-down. Default: 0b. Channel synchronization is maintained, but runt pulses may be generated. Setting this bit puts the OUT0A driver into power-down. Default: 0b. Channel synchronization is maintained, but runt pulses may be generated. Setting this bit puts the OUT0B divider and driver into power-down. Default: 0b. This mode saves the most power, but runt pulses may be generated during exit. Setting this bit puts the OUT0A divider and driver into power-down. Default: 0b. This mode saves the most power, but runt pulses may be generated during exit. Rev. D | Page 95 of 116 AD9554 Data Sheet Table 112. PLL_0 User Mode Address 0x0A22 Bits 7 [6:5] Bit Name Reserved DPLL_0 manual reference [4:2] DPLL_0 switching mode 1 DPLL_0 user holdover 0 DPLL_0 user free run Description Default: 0b. Input reference when user selection mode = 00, 01, 10, or 11. 00 (default) = Input Reference A. 01 = Input Reference B. 10 = Input Reference C. 11 = Input Reference D. Selects the operating mode of the reference switching state machine. Reference Switchover Mode, Bits[2:0] Reference Selection Mode 000b Automatic revertive mode 001b Automatic nonrevertive mode 010b Manual reference select mode (with automatic fallback) 011b Manual reference select mode (with holdover fallback) 100b Manual reference select mode (without holdover fallback) 101b Not used 110b Not used 111b Not used Forces DPLL_0 into holdover mode. Note that the AD9554 enters free run mode if this bit is set when there is no holdover history available. 0 (default) = normal operation. 1 = DPLL_0 is forced into holdover mode until this bit is cleared. Note that holdover mode is used if the holdover history is available. User free run mode is used if the holdover history is not available. See Register 0x0D22, Bit 0 for the DPLL_0 history available indication. Forces DPLL_0 into free run mode. 0 (default) = normal operation. 1 = DPLL_0 is forced into free run mode until this bit is cleared. Table 113. PLL_0 Reset Address 0x0A23 Bits [7:3] 2 Bit Name Reserved Reset DPLL_0 loop filter 1 Reset DPLL_0 TW history 0 Reset DPLL_0 autosync Description Default: 00000b. Resets the digital loop filter. 0 (default) = normal operation. 1 = DPLL_0 digital loop filter is reset. This is an autoclearing bit. Resets the tuning word history (part of holdover functionality). 0 (default) = normal operation. 1 = DPLL_0 tuning word history is reset. This is an autoclearing bit. Resets the automatic synchronization logic (see Register 0x0435). 0 (default) = normal operation. 1 = DPLL_0 automatic synchronization logic is reset. This is an autoclearing bit. Table 114. PLL_0 Phase Address 0x0A24 Bits [7:3] 2 1 Bit Name Reserved DPLL_0 reset phase offset DPLL_0 decrement phase offset 0 DPLL_0 increment phase offset Description Default: 00000b. Resets the incremental phase offset to zero. This is an autoclearing bit. Decrements the incremental phase offset by the amount specified in the incremental phase lock offset step size registers (Register 0x0412 and Register 0x0413). This is an autoclearing bit. Increments the incremental phase offset by the amount specified in the incremental phase lock offset step size registers (Register 0x0412 and Register 0x0413). This is an autoclearing bit. Rev. D | Page 96 of 116 Data Sheet AD9554 PLL_1 OPERATIONAL CONTROLS (REGISTER 0x0A40 TO REGISTER 0x0A44) These registers mimic the PLL_0 controls registers (Register 0x0A20 through Register 0x0A24) but the register addresses are offset by 0x0020. All default values are identical. PLL_2 OPERATIONAL CONTROLS (REGISTER 0x0A60 TO REGISTER 0x0A64) These registers mimic the PLL_0 controls registers (Register 0x0A20 through Register 0x0A24) but the register addresses are offset by 0x0040. All default values are identical. PLL_3 OPERATIONAL CONTROLS (REGISTER 0x0A80 TO REGISTER 0x0A84) These registers mimic the PLL_0 controls registers (Register 0x0A20 through Register 0x0A24) but the register addresses are offset by 0x0060. All default values are identical. VOLTAGE REGULATOR (REGISTER 0x0B00 TO REGISTER 0x0B01) The bits in these registers adjust the internal voltage regulator for 1.5 V input voltage operation. Table 115. Voltage Regulator Address 0x0B00 Bits [7:0] Bit Name VREG, Bits[7:0] 0x0B01 [7:2] [1:0] Reserved VREG, Bits[9:8] Description Adjusts internal voltage regulators for 1.5 V operation. There are only two valid settings for this register, and all bits in VREG[9:0] must be all 1s or all 0s, depending on whether the device is powered at 1.5 V or 1.8 V. 0x00 (default) = 1.8 V operation. 0xFF = 1.5 V operation. Default: 000000b. Adjusts internal voltage regulators for 1.5 V operation. There are only two valid settings for this register. 00b (default): 1.8 V operation. 11b: 1.5 V operation. STATUS READBACK (REGISTER 0x0D00 TO REGISTER 0x0D05) All bits in Register 0x0D00 to Register 0x0D05 are read only. To report the latest status, these bits require an IO_UPDATE (Register 0x000F = 0x01) immediately before being read. Table 116. EEPROM Status Address 0x0D00 Bits [7:4] 3 2 1 0 Bit Name Reserved EEPROM CRC fault detected EEPROM fault detected EEPROM download in progress EEPROM upload in progress Description Default: 00000b. An CRC error occurred during an EEPROM operation. An error occurred during an EEPROM operation. The control logic sets this bit while data is being downloaded from the EEPROM. The control logic sets this bit while data is being uploaded to the EEPROM. Table 117. SYSCLK and PLL Status Address 0x0D01 Bits 7 Bit Name PLL_3 all locked 6 PLL_2 all locked 5 PLL_1 all locked 4 PLL_0 all locked 3 Reserved Description Indicates the status of the system clock, APLL_3, and DPLL_3. 0 = system clock or APLL_3 or DPLL_3 is unlocked. 1 = all three PLLs (system clock, APLL_3, and DPLL_3) are locked. Indicates the status of the system clock, APLL_2, and DPLL_2. 0 = system clock or APLL_2 or DPLL_2 is unlocked. 1 = all three PLLs (system clock, APLL_2, and DPLL_2) are locked. Indicates the status of the system clock, APLL_1, and DPLL_1. 0 = system clock or APLL_1 or DPLL_1 is unlocked. 1 = all three PLLs (system clock, APLL_1, and DPLL_1) are locked. Indicates the status of the system clock, APLL_0, and DPLL_0. 0 = system clock or APLL_0 or DPLL_0 is unlocked. 1 = all three PLLs (system clock, APLL_0, and DPLL_0) are locked. Default: 0b. Rev. D | Page 97 of 116 AD9554 Address Data Sheet Bits 2 Bit Name SYSCLK calibration busy 1 SYSCLK stable 0 SYSCLK lock detect Description Indicates the status of the system clock calibration. 0 (default) = normal operation. 1 = system clock calibration in progress. The control logic sets this bit when the device considers the system clock to be stable (see the System Clock Stability Timer section). Indicates the status of the system clock PLL. 0 = unlocked. 1 = locked. Table 118. Status of Reference Inputs Address 0x0D02 0x0D03 0x0D04 0x0D05 Bits 7 6 5 4 3 Bit Name DPLL_3 REFA active DPLL_2 REFA active DPLL_1 REFA active DPLL_0 REFA active REFA valid 2 1 REFA fault REFA fast 0 7 6 5 4 3 REFA slow DPLL_3 REFB active DPLL_2 REFB active DPLL_1 REFB active DPLL_0 REFB active REFB valid 2 1 REFB fault REFB fast 0 7 6 5 4 3 REFB slow DPLL_3 REFC active DPLL_2 REFC active DPLL_1 REFC active DPLL_0 REFC active REFC valid 2 1 REFC fault REFC fast 0 7 6 5 4 3 REFC slow DPLL_3 REFD active DPLL_2 REFD active DPLL_1 REFD active DPLL_0 REFD active REFD valid 2 1 REFD fault REFD fast 0 REFD slow Description This bit is 1 if DPLL_3 is either locked to or attempting to lock to REFA. This bit is 1 if DPLL_2 is either locked to or attempting to lock to REFA. This bit is 1 if DPLL_1 is either locked to or attempting to lock to REFA. This bit is 1 if DPLL_0 is either locked to or attempting to lock to REFA. This bit is 1 if the REFA frequency is within the programmed limits and the validation timer has expired. This bit is 1 if the REFA frequency is outside of the programmed limits. This bit is 1 if the REFA frequency is higher than allowed by its profile settings. (Note that if no REFA input is detected, the REFA fast and slow bits may both be high.) This bit is 1 if the REFA frequency is lower than allowed by its profile settings. This bit is 1 if DPLL_3 is either locked to or attempting to lock to REFB. This bit is 1 if DPLL_2 is either locked to or attempting to lock to REFB. This bit is 1 if DPLL_1 is either locked to or attempting to lock to REFB. This bit is 1 if DPLL_0 is either locked to or attempting to lock to REFB. This bit is 1 if the REFB frequency is within the programmed limits and the validation timer has expired. This bit is 1 if the REFB frequency is outside of the programmed limits. This bit is 1 if the REFB frequency is higher than allowed by its profile settings. (Note that if no REFB input is detected, the REFB fast and slow bits may both be high.) This bit is 1 if the REFB frequency is lower than allowed by its profile settings. This bit is 1 if DPLL_3 is either locked to or attempting to lock to REFC. This bit is 1 if DPLL_2 is either locked to or attempting to lock to REFC. This bit is 1 if DPLL_1 is either locked to or attempting to lock to REFC. This bit is 1 if DPLL_0 is either locked to or attempting to lock to REFC. This bit is 1 if the REFC frequency is within the programmed limits and the validation timer has expired. This bit is 1 if the REFC frequency is outside of the programmed limits. This bit is 1 if the REFC frequency is higher than allowed by its profile settings. (Note that if no REFC input is detected, the REFC fast and slow bits may both be high.) This bit is 1 if the REFC frequency is lower than allowed by its profile settings. This bit is 1 if DPLL_3 is either locked to or attempting to lock to REFD. This bit is 1 if DPLL_2 is either locked to or attempting to lock to REFD. This bit is 1 if DPLL_1 is either locked to or attempting to lock to REFD. This bit is 1 if DPLL_0 is either locked to or attempting to lock to REFD. This bit is 1 if the REFD frequency is within the programmed limits and the validation timer has expired. This bit is 1 if the REFD frequency is outside of the programmed limits. This bit is 1 if the REFD frequency is higher than allowed by its profile settings. (Note that if no REFD input is detected, the REFD fast and slow bits may both be high.) This bit is 1 if the REFD frequency is lower than allowed by its profile settings. Rev. D | Page 98 of 116 Data Sheet AD9554 IRQ MONITOR (REGISTER 0x0D08 TO REGISTER 0x0D16) If not masked via the IRQ mask registers (Register 0x010F to Register 0x011D), the appropriate IRQ monitor bit is set to Logic 1 when the indicated event occurs. These bits can be cleared by writing a 1 to the corresponding bit in the IRQ clearing registers (Register 0x0A05 to Register 0x0A0E) by setting the clear all IRQs bit in Register 0x0A05 or by a device reset. Table 119. IRQ Common Functions Address 0x0D08 0x0D09 0x0D0A Bits 7 6 Bit Name SYSCLK unlocked SYSCLK stable 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 SYSCLK locked SYSCLK cal ended SYSCLK cal started Watchdog timer EEPROM fault EEPROM complete Reserved REFB validated REFB fault cleared REFB fault Reserved REFA validated REFA fault cleared REFA fault Reserved REFD validated REFD fault cleared REFD fault Reserved REFC validated REFC fault cleared REFC fault Description IRQ indicating a SYSCLK PLL state transition from locked to unlocked IRQ indicating that SYSCLK stability time has expired and that the SYSCLK PLL is considered to be stable IRQ indicating a SYSCLK PLL state transition from unlocked to locked IRQ indicating a SYSCLK PLL has ended its calibration IRQ indicating a SYSCLK PLL has started its calibration IRQ indicating expiration of the watchdog timer IRQ indicating a fault during an EEPROM operation IRQ indicating successful completion of an EEPROM operation Reserved IRQ indicating that REFB has been validated IRQ indicating that REFB has been cleared of a previous fault IRQ indicating that REFB has been faulted Reserved IRQ indicating that REFA has been validated IRQ indicating that REFA has been cleared of a previous fault IRQ indicating that REFA has been faulted Reserved IRQ indicating that REFD has been validated IRQ indicating that REFD has been cleared of a previous fault IRQ indicating that REFD has been faulted Reserved IRQ indicating that REFC has been validated IRQ indicating that REFC has been cleared of a previous fault IRQ indicating that REFC has been faulted Table 120. IRQ Monitor for Digital PLL0 (DPLL_0) Address 0x0D0B 0x0D0C Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Bit Name Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked DPLL_0 switching DPLL_0 free run DPLL_0 holdover DPLL_0 history updated REFD activated REFC activated REFB activated REFA activated Description IRQ indicating that DPLL_0 has exited a frequency clamped state IRQ indicating that DPLL_0 has entered a frequency clamped state IRQ indicating that DPLL_0 has exited a phase slew limited state IRQ indicating that DPLL_0 has entered a phase slew limited state IRQ indicating that DPLL_0 has lost frequency lock IRQ indicating that DPLL_0 has acquired frequency lock IRQ indicating that DPLL_0 has lost phase lock IRQ indicating that DPLL_0 has acquired phase lock IRQ indicating that DPLL_0 is switching to a new reference IRQ indicating that DPLL_0 has entered free run mode IRQ indicating that DPLL_0 has entered holdover mode IRQ indicating that DPLL_0 has updated its tuning word history IRQ indicating that DPLL_0 has activated REFD IRQ indicating that DPLL_0 has activated REFC IRQ indicating that DPLL_0 has activated REFB IRQ indicating that DPLL_0 has activated REFA Rev. D | Page 99 of 116 AD9554 Address 0x0D0D Data Sheet Bits 7 6 5 4 3 2 1 0 Bit Name Phase step direction Demap control unclamped Demap control clamped Clock dist sync'd APLL_0 unlocked APLL_0 locked APLL_0 cal ended APLL_0 cal started Description IRQ indicating that the DPLL_0 demapping controller phase step direction IRQ indicating that the DPLL_0 demapping controller is unclamped IRQ indicating that the DPLL_0 demapping controller is clamped IRQ indicating a distribution sync event IRQ indicating that APLL_0 has been unlocked IRQ indicating that APLL_0 has been locked IRQ indicating that APLL_0 calibration complete IRQ indicating that APLL_0 calibration started Table 121. IRQ Monitor for Digital PLL1 (DPLL_1) Address 0x0D0E 0x0D0F 0x0D10 Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Bit Name Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked DPLL_1 switching DPLL_1 free run DPLL_1 holdover DPLL_1 history updated REFD activated REFC activated REFB activated REFA activated Phase step direction Demap control unclamped Demap control clamped Clock dist sync'd APLL_1 unlocked APLL_1 locked APLL_1 cal ended APLL_1 cal started Description IRQ indicating that DPLL_1 has exited a frequency clamped state IRQ indicating that DPLL_1 has entered a frequency clamped state IRQ indicating that DPLL_1 has exited a phase slew limited state IRQ indicating that DPLL_1 has entered a phase slew limited state IRQ indicating that DPLL_1 has lost frequency lock IRQ indicating that DPLL_1 has acquired frequency lock IRQ indicating that DPLL_1 has lost phase lock IRQ indicating that DPLL_1 has acquired phase lock IRQ indicating that DPLL_1 is switching to a new reference IRQ indicating that DPLL_1 has entered free run mode IRQ indicating that DPLL_1 has entered holdover mode IRQ indicating that DPLL_1 has updated its tuning word history IRQ indicating that DPLL_1 has activated REFD IRQ indicating that DPLL_1 has activated REFC IRQ indicating that DPLL_1 has activated REFB IRQ indicating that DPLL_1 has activated REFA IRQ indicating that the DPLL_1 demapping controller phase step direction IRQ indicating that the DPLL_1 demapping controller is unclamped IRQ indicating that the DPLL_1 demapping controller is clamped IRQ indicating a distribution sync event IRQ indicating that APLL_1 has been unlocked IRQ indicating that APLL_1 has been locked IRQ indicating that APLL_1 calibration complete IRQ indicating that APLL_1 calibration started Rev. D | Page 100 of 116 Data Sheet AD9554 Table 122. IRQ Monitor for Digital PLL2 (DPLL_2) Address 0x0D11 0x0D12 0x0D13 Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Bit Name Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked DPLL_2 switching DPLL_2 free run DPLL_2 holdover DPLL_2 history updated REFD activated REFC activated REFB activated REFA activated Phase step direction Demap control unclamped Demap control clamped Clock dist sync'd APLL_2 unlocked APLL_2 locked APLL_2 cal ended APLL_2 cal started Description IRQ indicating that DPLL_2 has exited a frequency clamped state IRQ indicating that DPLL_2 has entered a frequency clamped state IRQ indicating that DPLL_2 has exited a phase slew limited state IRQ indicating that DPLL_2 has entered a phase slew limited state IRQ indicating that DPLL_2 has lost frequency lock IRQ indicating that DPLL_2 has acquired frequency lock IRQ indicating that DPLL_2 has lost phase lock IRQ indicating that DPLL_2 has acquired phase lock IRQ indicating that DPLL_2 is switching to a new reference IRQ indicating that DPLL_2 has entered free run mode IRQ indicating that DPLL_2 has entered holdover mode IRQ indicating that DPLL_2 has updated its tuning word history IRQ indicating that DPLL_2 has activated REFD IRQ indicating that DPLL_2 has activated REFC IRQ indicating that DPLL_2 has activated REFB IRQ indicating that DPLL_2 has activated REFA IRQ indicating that the DPLL_2 demapping controller phase step direction IRQ indicating that the DPLL_2 demapping controller is unclamped IRQ indicating that the DPLL_2 demapping controller is clamped IRQ indicating a distribution sync event IRQ indicating that APLL_2 has been unlocked IRQ indicating that APLL_2 has been locked IRQ indicating that APLL_2 calibration complete IRQ indicating that APLL_2 calibration started Rev. D | Page 101 of 116 AD9554 Data Sheet Table 123. IRQ Monitor for Digital PLL3 (DPLL_3) Address 0x0D14 Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0x0D15 0x0D16 Bit Name Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked DPLL_3 switching DPLL_3 free run DPLL_3 holdover DPLL_3 history updated REFD activated REFC activated REFB activated REFA activated Phase step direction Demap control unclamped Demap control clamped Clock dist sync'd APLL_3 unlocked APLL_3 locked APLL_3 cal ended APLL_3 cal started Description IRQ indicating that DPLL_3 has exited a frequency clamped state IRQ indicating that DPLL_3 has entered a frequency clamped state IRQ indicating that DPLL_3 has exited a phase slew limited state IRQ indicating that DPLL_3 has entered a phase slew limited state IRQ indicating that DPLL_3 has lost frequency lock IRQ indicating that DPLL_3 has acquired frequency lock IRQ indicating that DPLL_3 has lost phase lock IRQ indicating that DPLL_3 has acquired phase lock IRQ indicating that DPLL_3 is switching to a new reference IRQ indicating that DPLL_3 has entered free run mode IRQ indicating that DPLL_3 has entered holdover mode IRQ indicating that DPLL_3 has updated its tuning word history IRQ indicating that DPLL_3 has activated REFD IRQ indicating that DPLL_3 has activated REFC IRQ indicating that DPLL_3 has activated REFB IRQ indicating that DPLL_3 has activated REFA IRQ indicating that the DPLL_3 demapping controller phase step direction IRQ indicating that the DPLL_3 demapping controller is unclamped IRQ indicating that the DPLL_3 demapping controller is clamped IRQ indicating a distribution sync event IRQ indicating that APLL_3 has been unlocked IRQ indicating that APLL_3 has been locked IRQ indicating that APLL_3 calibration complete IRQ indicating that APLL_3 calibration started PLL_0 READ ONLY STATUS (REGISTER 0x0D20 TO REGISTER 0x0D2A) All bits in Register 0x0D20 to Register 0x0D2A are read only. To report the latest status, these bits require an IO_UPDATE (Register 0x000F = 0x01) immediately before being read. Table 124. PLL_0 Lock Status Address 0x0D20 Bits [7:5] 4 3 Bit Name Reserved APLL_0 cal in progress APLL_0 frequency lock 2 DPLL_0 frequency lock 1 DPLL_0 phase lock 0 PLL_0 all locked Description Default: 000b. The control logic holds this bit set while the calibration of the APLL_0 VCO is in progress. Indicates the status of APLL_0. 0 = unlocked. 1 = locked. Indicates the frequency lock status of DPLL_0. 0 = unlocked. 1 = locked. Indicates the phase lock status of DPLL_0. 0 = unlocked. 1 = locked. Indicates the status of the system clock, APLL_0, and DPLL_0. 0 = system clock PLL, APLL_0, or DPLL_0 is unlocked. 1 = all three PLLs (system clock PLL, APLL_0, and DPLL_0) are locked. Rev. D | Page 102 of 116 Data Sheet AD9554 Table 125. DPLL_0 Loop State Address 0x0D21 0x0D22 Bits [7:5] [4:3] Bit Name Reserved DPLL_0 active ref 2 DPLL_0 switching 1 DPLL_0 holdover 0 DPLL_0 free run [7:4] 3 2 1 0 Reserved Demap controller clamped DPLL_0 phase slew limited DPLL_0 frequency clamped DPLL_0 history available Description Default: 000b. Indicates the reference input that DPLL_0 is using. 00 = DPLL_0 has selected REFA. 01 = DPLL_0 has selected REFB. 10 = DPLL_0 has selected REFC. 11 = DPLL_0 has selected REFD. Indicates that DPLL_0 is switching input references. 0 = DPLL is not switching. 1 = DPLL is switching input references. Indicates that DPLL_0 is in holdover mode. 0 = not in holdover. 1 = in holdover mode. Indicates that DPLL_0 is in free run mode. 0 = not in free run mode. 1 = in free run mode. Default: 00000b. The control logic sets this bit when DPLL_0 demapping controller is clamped. The control logic sets this bit when DPLL_0 is phase slew limited. The control logic sets this bit when DPLL_0 is frequency clamped. The control logic sets this bit when the tuning word history of DPLL_0 is available. (See Register 0x0D23 to Register 0x0D26 for the tuning word.) Table 126. DPLL_0 Holdover History Address 0x0D23 Bits [7:0] 0x0D24 0x0D25 0x0D26 [7:0] [7:0] [7:6] [5:0] Bit Name DPLL_0 tuning word readback, Bits[23:0] Reserved DPLL_0 tuning word readback, Bits[29:24] Description DPLL_0 tuning word readback bits, Bits[7:0]. This group of registers contains the averaged digital PLL tuning word used when the DPLL enters holdover. Setting the history accumulation timer to its minimal value allows the user to use these registers for a read back of the most recent DPLL tuning word with only 1 ms of averaging. Instantaneous tuning word readback is not available. DPLL_0 tuning word readback, Bits[15:8]. DPLL_0 tuning word readback, Bits[23:16]. Reserved. DPLL_0 tuning word readback, Bits[29:24]. Table 127. DPLL_0 Phase Lock and Frequency Lock Bucket Levels Address 0x0D27 Bits [7:0] 0x0D28 [7:4] [3:0] 0x0D29 [7:0] 0x0D2A [7:4] [3:0] Bit Name DPLL_0 phase lock detect bucket level Reserved DPLL_0 phase lock detect bucket level DPLL_0 frequency lock detect bucket level Reserved DPLL_0 frequency lock detect bucket level Description Read only digital PLL lock detect bucket level, Bits[7:0]; see the DPLL Frequency Lock Detector section for details. Reserved. Read only digital PLL lock detect bucket level, Bits[11:8]; see the DPLL Frequency Lock Detector section for details. Read only digital PLL lock detect bucket level, Bits[7:0]; see the DPLL Phase Lock Detector section for details. Reserved. Read only digital PLL lock detect bucket level, Bits[11:8]; see the DPLL Phase Lock Detector section for details. Rev. D | Page 103 of 116 AD9554 Data Sheet PLL_1 READ ONLY STATUS (REGISTER 0x0D40 TO REGISTER 0x0D4A) These registers mimic the PLL_0 control registers (Register 0x0D20 through Register 0x0D2A) but the register addresses are offset by 0x0020. All default values are identical. All bits in Register 0x0D40 to Register 0x0D4A are read only. To report the latest status, these bits require an IO_UPDATE (Register 0x000F = 0x01) immediately before being read. PLL_2 READ ONLY STATUS (REGISTER 0x0D60 TO REGISTER 0x0D6A) These registers mimic the PLL_0 control registers (Register 0x0D20 through Register 0x0D2A) but the register addresses are offset by 0x0040. All bits in Register 0x0D60 to Register 0x0D6A are read only. To report the latest status, these bits require an IO_UPDATE (Register 0x000F = 0x01) immediately before being read. PLL_3 READ ONLY STATUS (REGISTER 0x0D80 TO REGISTER 0x0D8A) These registers mimic the PLL_0 control registers (Register 0x0D20 through Register 0x0D2A) but the register addresses are offset by 0x0060. All bits in Register 0x0D40 to Register 0x0D4A are read only. To report the latest status, these bits require an IO_UPDATE (Register 0x000F = 0x01) immediately before being read. EEPROM CONTROL (REGISTER 0x0E00 TO REGISTER 0x0E03) Table 128. Nonvolatile Memory (EEPROM) Control Address 0x0E00 Bits [7:2] 1 Bit Name Reserved Enable I2C fast mode 0 Write enable 0x0E01 [7:4] [3:0] Reserved Conditional value 0x0E02 [7:1] 0 Reserved Save to EEPROM 0x0E03 [7:1] 0 Reserved Load from EPROM Description Reserved Sets the speed of the external I2C EEPROM interface. 0 (default) = 100 kHz. 1 = 400 kHz. EEPROM write enable. 0 (default) = EEPROM write disabled. 1 = EEPROM write enabled. Note that the external EEPROM may have its own write protect mechanism that is not controlled by this bit. Reserved. When set to a nonzero value, it establishes the condition for EEPROM downloads. The default value is 0. A value of 0 indicates that the power-up/reset condition is used. Any nonzero value overrides this condition. Reserved. Uploads data to the EEPROM (see the EEPROM Storage Sequence (Register 0x0E10 to Register 0x0E61) section for more information). This bit is autoclearing. Reserved. Downloads data from the EEPROM. This bit is autoclearing. Rev. D | Page 104 of 116 Data Sheet AD9554 EEPROM STORAGE SEQUENCE (REGISTER 0x0E10 TO REGISTER 0x0E61) The default settings of Register 0x0E10 to Register 0x0E61 contain the default EEPROM instruction sequence. Table 129 to Table 152 provide descriptions of the register defaults. The default values assume that the user wishes to carry out an EEPROM storage sequence in which all of the registers are stored and loaded by the EEPROM. Table 129. EEPROM Storage Sequence for Mx Pin Settings and IRQ Masks Address 0x0E10 Bits [7:0] Bit Name User free run 0x0E11 [7:0] User scratchpad 0x0E12 0x0E13 [7:0] 0x0E14 [7:0] 0x0E15 [7:0] Mx pins and IRQ masks 0x0E16 Description The default value of this register is 0x98, which is a user free run command for all PLLs. The controller stores 0x98 in the EEPROM and increments the EEPROM address pointer. The default value of this register is 0x01, which is a data instruction. Its decimal value is 1, which tells the controller to transfer two bytes of data (1 + 1), beginning at the address specified by the next two bytes. The default value of these two registers is 0x00FE. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x00FE in the EEPROM and increments the EEPROM pointer by 2. It then transfers two bytes from the register map (beginning at Address 0x00FE) to the external EEPROM. The two bytes transferred are the EEPROM ID (user scratchpad) in the register map. The default value of this register is 0x1F, which is a data instruction. Its decimal value is 31, which tells the controller to transfer 32 bytes of data (31 + 1), beginning at the address specified by the next two bytes. The default value of these two registers is 0x0100. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0100 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 32 bytes from the register map (beginning at Address 0x0200) to the external EEPROM. The 32 bytes transferred are the Mx pin and IRQ settings in the register map. Table 130. EEPROM Storage Sequence for System Clock Settings Address 0x0E17 Bits [7:0] Bit Name System clock 0x0E18 0x0E19 [7:0] [7:0] 0x0E1A [7:0] IO_UPDATE 0x0E1B [7:0] Calibrate SYSCLK Description The default value of this register is 0x08, which is a data instruction. Its decimal value is 8, which tells the controller to transfer nine bytes of data (8 + 1), beginning at the address specified by the next two bytes. The controller stores 0x08 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0200. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0200 in the EEPROM and increments the EEPROM pointer by 2. It then transfers nine bytes from the register map (beginning at Address 0x0200) to the external EEPROM and increments the EEPROM address pointer by 9. The nine bytes transferred are the system clock settings in the register map. The default value of this register is 0x80, which is an IO_UPDATE instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer. The default value of this register is 0x91, which is a SYSCLK Calibrate instruction. The controller stores 0x91 in the EEPROM and increments the EEPROM address pointer. Table 131. EEPROM Storage Sequence for Reference Input Settings Address 0x0E1C Bits [7:0] 0x0E1D 0x0E1E [7:0] [7:0] Bit Name REFA Description The default value of this register is 0x1E, which is a data instruction. Its decimal value is 30, which tells the controller to transfer 31 bytes of data (30 + 1), beginning at the address specified by the next two bytes. The controller stores 0x1E in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0300. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0300 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 31 bytes from the register map (beginning at Address 0x0300) to the external EEPROM and increments the EEPROM address pointer by 31. The 31 bytes transferred are the REFA parameters in the register map. Rev. D | Page 105 of 116 AD9554 Address 0x0E1F Bits [7:0] 0x0E20 [7:0] 0x0E21 [7:0] 0x0E22 [7:0] 0x0E23 0x0E24 [7:0] [7:0] 0x0E25 [7:0] 0x0E26 0x0E27 [7:0] [7:0] Data Sheet Bit Name REFB REFC REFD Description The default value of this register is 0x1E, which is a data instruction. Its decimal value is 30, which tells the controller to transfer 31 bytes of data (30 + 1), beginning at the address specified by the next two bytes. The controller stores 0x1E in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0320. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0320 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 31 bytes from the register map (beginning at Address 0x0320) to the external EEPROM and increments the EEPROM address pointer by 31. The 31 bytes transferred are the REFB parameters in the register map. The default value of this register is 0x1E, which is a data instruction. Its decimal value is 30, which tells the controller to transfer 31 bytes of data (30 + 1), beginning at the address specified by the next two bytes. The controller stores 0x1A in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0340. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0340 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 31 bytes from the register map (beginning at Address 0x0340) to the external EEPROM and increments the EEPROM address pointer by 31. The 31 bytes transferred are the REFC parameters in the register map. The default value of this register is 0x1E, which is a data instruction. Its decimal value is 30, which tells the controller to transfer 31 bytes of data (30 + 1), beginning at the address specified by the next two bytes. The controller stores 0x1A in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0360. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0360 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 31 bytes from the register map (beginning at Address 0x0360) to the external EEPROM and increments the EEPROM address pointer by 31. The 31 bytes transferred are the REFD parameters in the register map. Table 132. EEPROM Storage Sequence for DPLL_0 General Settings Address 0x0E28 Bits [7:0] 0x0E29 [7:0] 0x0E2A [7:0] Bit Name DPLL_0 general settings Description The default value of this register is 0x1E, which the controller interprets as a data instruction. Its decimal value is 30, which tells the controller to transfer 31 bytes of data (30 + 1), beginning at the address specified by the next two bytes. The controller stores 0x1E in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0400. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0400 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 31 bytes from the register map (beginning at Address 0x0400) to the external EEPROM and increments the EEPROM address pointer by 32 (31 data bytes and one checksum byte). The 31 bytes transferred correspond to the DPLL_0 general settings (for example, free running tuning word) in the register map. Table 133. EEPROM Storage Sequence for APLL_0 Configuration and Output Drivers Address 0x0E2B Bits [7:0] 0x0E2C 0x0E2D [7:0] [7:0] Bit Name APLL_0 config and output drivers Description The default value of this register is 0x0E, which is a data instruction. Its decimal value is 14, which tells the controller to transfer 15 bytes of data (14 + 1) beginning at the address specified by the next two bytes. The controller stores 0x0E in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0430. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0430 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 31 bytes from the register map (beginning at Address 0x0430) to the external EEPROM and increments the EEPROM address pointer by 15. The 15 bytes transferred correspond to the APLL_0 settings as well as the PLL_0 output driver settings in the register map. Rev. D | Page 106 of 116 Data Sheet AD9554 Table 134. EEPROM Storage Sequence for PLL_0 Dividers and Bandwidth Settings Address 0x0E2E Bits [7:0] 0x0E2F 0x0E30 [7:0] [7:0] Bit Name DPLL_0 dividers and BW Description The default value of this register is 0x33, which is a data instruction. Its decimal value is 51, which tells the controller to transfer 52 bytes of data (51 + 1), beginning at the address specified by the next two bytes. The controller stores 0x33 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0440. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0440 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 52 bytes from the register map (beginning at Address 0x0440) to the external EEPROM and increments the EEPROM address pointer by 52. The 52 bytes transferred correspond to the DPLL_0 feedback dividers and loop bandwidth settings in the register map. Table 135. EEPROM Storage Sequence for DPLL_1 General Settings Address 0x0E31 Bits [7:0] 0x0E32 0x0E33 [7:0] [7:0] Bit Name DPLL_1 general settings Description The default value of this register is 0x1E, which is a data instruction. Its decimal value is 30, which tells the controller to transfer 31 bytes of data (30 + 1), beginning at the address specified by the next two bytes. The controller stores 0x1E in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0500. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0500 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 31 bytes from the register map (beginning at Address 0x0500) to the external EEPROM and increments the EEPROM address pointer by 31. The 31 bytes transferred correspond to the DPLL_1 general settings (for example, free running tuning word) in the register map. Table 136. EEPROM Storage Sequence for APLL_1 Configuration and Output Drivers Address 0x0E34 Bits [7:0] 0x0E35 [7:0] 0x0E36 [7:0] Bit Name APLL_1 config and output drivers Description The default value of this register is 0x0E, which is a data instruction. Its decimal value is 14, which tells the controller to transfer 15 bytes of data (14 + 1) beginning at the address specified by the next two bytes. The controller stores 0x0E in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0530. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0530 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 31 bytes from the register map (beginning at Address 0x0530) to the external EEPROM and increments the EEPROM address pointer by 31. The 31 bytes transferred correspond to the APLL_1 settings as well as the PLL_1 output driver settings in the register map. Table 137. EEPROM Storage Sequence for PLL_1 Dividers and Bandwidth Settings Address 0x0E37 Bits [7:0] 0x0E38 0x0E39 [7:0] [7:0] Bit Name DPLL_1 dividers and BW Description The default value of this register is 0x33, which is a data instruction. Its decimal value is 52, which tells the controller to transfer 53 bytes of data (52 + 1), beginning at the address specified by the next two bytes. The controller stores 0x33 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0540. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0540 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 52 bytes from the register map (beginning at Address 0x0540) to the external EEPROM and increments the EEPROM address pointer by 52. The 52 bytes transferred correspond to the DPLL_1 feedback dividers and loop bandwidth settings in the register map. Rev. D | Page 107 of 116 AD9554 Data Sheet Table 138. EEPROM Storage Sequence for DPLL_2 General Settings Address 0x0E3A Bits [7:0] 0x0E3B [7:0] 0x0E3C [7:0] Bit Name DPLL_2 general settings Description The default value of this register is 0x1E, which is a data instruction. Its decimal value is 30, which tells the controller to transfer 31 bytes of data (30 + 1), beginning at the address specified by the next two bytes. The controller stores 0x1E in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0600. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0600 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 31 bytes from the register map (beginning at Address 0x0600) to the external EEPROM and increments the EEPROM address pointer by 31. The 31 bytes transferred correspond to the DPLL_2 general settings (for example, free running tuning word) in the register map. Table 139. EEPROM Storage Sequence for APLL_2 Configuration and Output Drivers Address 0x0E3D Bits [7:0] 0x0E3E 0x0E3F [7:0] [7:0] Bit Name APLL_2 config and output drivers Description The default value of this register is 0x0E, which is a data instruction. Its decimal value is 14, which tells the controller to transfer 15 bytes of data (14 + 1) beginning at the address specified by the next two bytes. The controller stores 0x0E in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0630. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0630 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 31 bytes from the register map (beginning at Address 0x0630) to the external EEPROM and increments the EEPROM address pointer by 31. The 31 bytes transferred correspond to the APLL_2 settings as well as the PLL_2 output driver settings in the register map. Table 140. EEPROM Storage Sequence for PLL_2 Dividers and Bandwidth Settings Address 0x0E40 Bits [7:0] 0x0E41 0x0E42 [7:0] [7:0] Bit Name DPLL_2 dividers and BW Description The default value of this register is 0x33, which is a data instruction. Its decimal value is 51, which tells the controller to transfer 52 bytes of data (51 + 1), beginning at the address specified by the next two bytes. The controller stores 0x33 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0640. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0640 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 52 bytes from the register map (beginning at Address 0x0640) to the external EEPROM and increments the EEPROM address pointer by 52. The 52 bytes transferred correspond to the DPLL_2 feedback dividers and loop bandwidth settings in the register map. Table 141. EEPROM Storage Sequence for DPLL_3 General Settings Address 0x0E43 Bits [7:0] 0x0E44 0x0E45 [7:0] [7:0] Bit Name DPLL_3 general settings Description The default value of this register is 0x1E, which is a data instruction. Its decimal value is 30, which tells the controller to transfer 31 bytes of data (30 + 1), beginning at the address specified by the next two bytes. The controller stores 0x1E in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0700. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0700 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 31 bytes from the register map (beginning at Address 0x0700) to the external EEPROM and increments the EEPROM address pointer by 31. The 31 bytes transferred correspond to the DPLL_3 general settings (for example, free running tuning word) in the register map. Rev. D | Page 108 of 116 Data Sheet AD9554 Table 142. EEPROM Storage Sequence for APLL_3 Configuration and Output Drivers Address 0x0E46 Bits [7:0] 0x0E47 [7:0] 0x0E48 [7:0] Bit Name APLL_3 config and output drivers Description The default value of this register is 0x0E, which is a data instruction. Its decimal value is 14, which tells the controller to transfer 15 bytes of data (14 + 1) beginning at the address specified by the next two bytes. The controller stores 0x0E in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0730. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0730 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 31 bytes from the register map (beginning at Address 0x0730) to the external EEPROM and increments the EEPROM address pointer by 31. The 31 bytes transferred correspond to the APLL_3 settings as well as the PLL_3 output driver settings in the register map. Table 143. EEPROM Storage Sequence for PLL_3 Dividers and Bandwidth Settings Address 0x0E49 Bits [7:0] 0x0E4A [7:0] 0x0E4B [7:0] Bit Name DPLL_3 dividers and BW Description The default value of this register is 0x33, which is a data instruction. Its decimal value is 52, which tells the controller to transfer 53 bytes of data (52 + 1), beginning at the address specified by the next two bytes. The controller stores 0x33 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0740. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0740 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 52 bytes from the register map (beginning at Address 0x0740) to the external EEPROM and increments the EEPROM address pointer by 52. The 52 bytes transferred correspond to the DPLL_3 feedback dividers and loop bandwidth settings in the register map. Table 144. EEPROM Storage Sequence for Loop Filter Settings Address 0x0E4C Bits [7:0] 0x0E4D 0x0E4E [7:0] [7:0] Bit Name DPLL loop filters Description The default value of this register is 0x17, which is a data instruction. Its decimal value is 23, which tells the controller to transfer 24 bytes of data (23 + 1), beginning at the address specified by the next two bytes. The controller stores 0x17 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0800. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0800 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 24 bytes from the register map (beginning at Address 0x0800) to the external EEPROM and increments the EEPROM address pointer by 24. The 24 bytes transferred are the digital loop filter settings in the register map. Table 145. EEPROM Storage Sequence for Operational Control Common Settings Address 0x0E4F Bits [7:0] 0x0E50 [7:0] 0x0E51 [7:0] Bit Name Operational controls (common) Description The default value of this register is 0x14, which is a data instruction. Its decimal value is 20, which tells the controller to transfer 21 bytes of data (20 + 1), beginning at the address specified by the next two bytes. The controller stores 0x0E in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0A00. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0A00 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 21 bytes from the register map (beginning at Address 0x0A00) to the external EEPROM and increments the EEPROM address pointer by 21. The 21 bytes transferred correspond to the common operational controls in the register map. Rev. D | Page 109 of 116 AD9554 Data Sheet Table 146. EEPROM Storage Sequence for PLL_0 Operational Control Settings Address 0x0E52 Bits [7:0] 0x0E53 0x0E54 [7:0] [7:0] Bit Name PLL_0 operational controls Description The default value of this register is 0x04, which is a data instruction. Its decimal value is 4, which tells the controller to transfer five bytes of data (4 + 1), beginning at the address specified by the next two bytes. The controller stores 0x04 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0A20. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0A20 in the EEPROM and increments the EEPROM pointer by 2. It then transfers five bytes from the register map (beginning at Address 0x0A20) to the external EEPROM and increments the EEPROM address pointer by five. The five bytes transferred correspond to the PLL_0 operational controls in the register map. Table 147. EEPROM Storage Sequence for PLL_1 Operational Control Settings Address 0x0E55 Bits [7:0] 0x0E56 0x0E57 [7:0] [7:0] Bit Name PLL_1 operational controls Description The default value of this register is 0x04, which is a data instruction. Its decimal value is 4, which tells the controller to transfer five bytes of data (4 + 1), beginning at the address specified by the next two bytes. The controller stores 0x04 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0A40. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0A40 in the EEPROM and increments the EEPROM pointer by 2. It then transfers five bytes from the register map (beginning at Address 0x0A40) to the external EEPROM and increments the EEPROM address pointer by five. The five bytes transferred correspond to the PLL_1 operational controls in the register map. Table 148. EEPROM Storage Sequence for PLL_2 Operational Control Settings Address 0x0E58 Bits [7:0] 0x0E59 0x0E5A [7:0] [7:0] Bit Name PLL_2 operational controls Description The default value of this register is 0x04, which is a data instruction. Its decimal value is 4, which tells the controller to transfer five bytes of data (4 + 1), beginning at the address specified by the next two bytes. The controller stores 0x04 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0A60. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0A60 in the EEPROM and increments the EEPROM pointer by 2. It then transfers five bytes from the register map (beginning at Address 0x0A60) to the external EEPROM and increments the EEPROM address pointer by five. The five bytes transferred correspond to the PLL_2 operational controls in the register map. Table 149. EEPROM Storage Sequence for PLL_3 Operational Control Settings Address 0x0E5B Bits [7:0] 0x0E5C 0x0E5D [7:0] [7:0] Bit Name PLL_3 operational controls Description The default value of this register is 0x04, which is a data instruction. Its decimal value is 4, which tells the controller to transfer five bytes of data (4 + 1), beginning at the address specified by the next two bytes. The controller stores 0x04 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0A80. This is the starting address of an EEPROM data transfer because the previous register contains a data instruction that specifies the number of bytes (minus one) to transfer. The controller stores 0x0A80 in the EEPROM and increments the EEPROM pointer by 2. It then transfers five bytes from the register map (beginning at Address 0x0A80) to the external EEPROM and increments the EEPROM address pointer by five. The five bytes transferred correspond to the PLL_3 operational controls in the register map. Rev. D | Page 110 of 116 Data Sheet AD9554 Table 150. EEPROM Storage Sequence for APLL Calibration Address 0x0E5E Bits [7:0] Bit Name IO_UPDATE 0x0E5F [7:0] Calibrate APLLs 0x0E60 [7:0] Sync outputs Description The default value of this register is 0x80, which is an IO_UPDATE instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer. The default value of this register is 0x92, which is a calibrate instruction for all of the APLLs. The controller stores 0x92 in the EEPROM and increments the EEPROM address pointer. The default value of this register is 0xA0, which is a distribution sync instruction for all of the output dividers. The controller stores 0xA0 in the EEPROM and increments the EEPROM address pointer. Table 151. EEPROM Storage Sequence for End of Data Address 0x0E61 Bits [7:0] Bit Name End of data Description The default value of this register is 0xFF, which is an end of data instruction. The controller stores this instruction, as well as four CRC-32 bytes in the EEPROM, resets the EEPROM address pointer, and enters an idle state. Note that if the user replaces this command with a pause rather than an end instruction, the controller actions are the same except that the controller increments the EEPROM address pointer rather than resetting it. This allows the user to store multiple EEPROM profiles in the EEPROM. Bit Name Unused Description This area is unused in the default configuration and is available for additional EEPROM storage sequence commands. Note that the EEPROM storage sequence must always end with either an end of data or pause command. Table 152. Unused Address 0x0E62 to 0x0E6F Bits [7:0] Table 153. VCAL Reference Settings Address 0x0FFF Bits [7:0] Bit Name VCAL reference access 0x1488 [7:3] [2:1] Reserved APLL_0 manual cal level 0 En APLL_0 man cal level [7:3] [2:1] Reserved APLL_1 manual cal level 0 En APLL_1 man cal level 0x1588 Description Writing 0xF9 to this register allows access to VCAL reference registers at Register 0x1488, Register 0x1588, Register 0x1688, and Register 0x1788. Set this register back to 0x00 after writing to Register 0x1488, Register 0x1588, Register 0x1688, and Register 0x1788 to avoid accidental writes above Register 0x0FFF. 0x00 (and all other values except 0xF9) = access disabled. Default: 0x00. 0xF9 = access enabled. Default: 00000b. APLL_0 reference voltage used during APLL_0 calibration. Set these bits (and issue an IO_UPDATE by writing Register 0x000F = 0x01) before calibrating the APLLs to ensure optimal performance over temperature and voltage extremes. These bits must be set only once per power cycle. Before writing to this register, Register 0x0FFF must be 0xF9. 00b = Reference Voltage 0 (default). 01b = Reference Voltage 1 (recommended). 10b = Reference Voltage 2. 11b = Reference Voltage 3. Enables manual control of the VCAL reference setting for APLL_0. 0 = manual control disabled (default). 1 = manual control enabled (recommended). Default: 00000b. APLL_1 reference voltage used during APLL_0 calibration. Set these bits (and issue an IO_UPDATE by writing Register 0x000F = 0x01) before calibrating the APLLs to ensure optimal performance over temperature and voltage extremes. These bits must be set only once per power cycle. Before writing to this register, Register 0x0FFF must be 0xF9. 00b = Reference Voltage 0 (default). 01b = Reference Voltage 1 (recommended). 10b = Reference Voltage 2. 11b = Reference Voltage 3. Enables manual control of the VCAL reference setting for APLL_1. 0 = manual control disabled (default). 1 = manual control enabled (recommended). Rev. D | Page 111 of 116 AD9554 Address 0x1688 0x1788 Data Sheet Bits [7:3] [2:1] Bit Name Reserved APLL_2 manual cal level 0 En APLL_2 man cal level [7:3] [2:1] Reserved APLL_3 manual cal level 0 En APLL_3 man cal level Description Default: 00000b. APLL_2 reference voltage used during APLL_0 calibration. Set these bits (and issue an IO_UPDATE by writing Register 0x000F = 0x01) before calibrating the APLLs to ensure optimal performance over temperature and voltage extremes. These bits must be set only once per power cycle. Before writing to this register, Register 0x0FFF must be 0xF9. 00b = Reference Voltage 0 (default). 01b = Reference Voltage 1 (recommended). 10b = Reference Voltage 2. 11b = Reference Voltage 3. Enables manual control of the VCAL reference setting for APLL_2. 0 = manual control disabled (default). 1 = manual control enabled (recommended). Default: 00000b. APLL_3 reference voltage used during APLL_0 calibration. Set these bits (and issue an IO_UPDATE by writing Register 0x000F = 0x01) before calibrating the APLLs to ensure optimal performance over temperature and voltage extremes. These bits must be set only once per power cycle. Before writing to this register, Register 0x0FFF must be 0xF9. 00b = Reference Voltage 0 (default). 01b = Reference Voltage 1 (recommended). 10b = Reference Voltage 2. 11b = Reference Voltage 3. Enables manual control of the VCAL reference setting for APLL_3. 0 = manual control disabled (default). 1 = manual control enabled (recommended). Table 154. Multifunction Pin Output Functions (D7 = 1) Bits[D7:D0] Value 0x80 0x81 0x82 0x83 0x91 0x92/0x93/0x94/0x95 0xA0/0xA1/0xA2/0xA3 Output Function Static Logic 0 Static Logic 1 System clock divided by 32 Watchdog timer output; this is a strobe whose duration equals (32/(one system clock period)) when timer expires SYSCLK PLL calibration busy SYSCLK PLL lock detected SYSCLK PLL stable All PLLs locked (logical AND of 0x88, 0x89, 0x8A, 0x8B) (DPLL_0 phase lock) AND (APLL_0 lock) AND (SYSCLK PLL lock) (DPLL_1 phase lock) AND (APLL_1 lock) AND (SYSCLK PLL lock) (DPLL_2 phase lock) AND (APLL_2 lock) AND (SYSCLK PLL lock) (DPLL_3 phase lock) AND (APLL_3 lock) AND (SYSCLK PLL lock) EEPROM upload (write to EEPROM) in progress EEPROM download (read from EEPROM) in progress EEPROM fault detected All IRQs: (IRQ_common) OR (IRQ_PLL_0) OR (IRQ_PLL_1) OR (IRQ_PLL_2) OR (IRQ_PLL_3) IRQ_common IRQ_PLL_0/IRQ_PLL_1/IRQ_PLL_2/IRQ_PLL_3 REFA/REFB/REFC/REFD fault 0xA8/0xA9/0xAA/0xAB REFA/REFB/REFC/REFD valid 0xB0 0xB1 0xB2 REFA active (any PLL) REFB active (any PLL) REFC active (any PLL) 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x90 Rev. D | Page 112 of 116 Source Proxy None None None None Register 0x0D01, Bit 2 Register 0x0D01, Bit 0 Register 0x0D01, Bit 1 Register 0x0D01, Bits[7:4] Register 0x0D01, Bit 4 Register 0x0D01, Bit 5 Register 0x0D01, Bit 6 Register 0x0D01, Bit 7 Register 0x0D00, Bit 0 Register 0x0D00, Bit 1 Register 0x0D00, Bit 2 None None None Register 0x0D02/Register 0x0D03/ Register 0x0D04/Register 0x0D05, Bit 2 Register 0x0D02/Register 0x0D03/ Register 0x0D04/Register 0x0D05, Bit 3 Register 0x0D02, Bit 4||Bit 5||Bit 6||Bit 7 Register 0x0D03, Bit 4||Bit 5||Bit 6||Bit 7 Register 0x0D04, Bit 4||Bit 5||Bit 6||Bit 7 Data Sheet AD9554 Bits[D7:D0] Value 0xB3 0xC0 0xC1 0xC2 0xC3 0xC4 Output Function REFD active (any PLL) DPLL_0 phase locked DPLL_0 frequency locked APLL_0 frequency lock APLL_0 cal in process DPLL_0 active 0xC5 0xC6 0xC7 0xC8 0xC9 DPLL_0 in free run mode DPLL_0 in holdover DPLL_0 switching DPLL_0 history available DPLL_0 history updated 0xCA 0xCB 0xCC 0xCD 0xD0 0xD1 0xD2 0xD3 0xD4 DPLL_0 clamp DPLL_0 phase slew limited PLL_0 clock distribution sync pulse DPLL_1 demapping controller clamped DPLL_1 phase locked DPLL_1 frequency locked APLL_1 frequency lock APLL_1 cal in process DPLL_1 active 0xD5 0xD6 0xD7 0xD8 0xD9 DPLL_1 in free run mode DPLL_1 in holdover DPLL_1 in switchover DPLL_1 history available DPLL_1 history updated 0xDA 0xDB 0xDC 0xDD 0xE0 0xE1 0xE2 0xE3 0xE4 DPLL_1 clamp DPLL_1 phase slew limited PLL_1 clock distribution sync pulse DPLL_1 demapping controller clamped DPLL_2 phase locked DPLL_2 frequency locked APLL_2 frequency lock APLL_2 cal in process DPLL_2 active 0xE5 0xE6 0xE7 0xE8 0xE9 DPLL_2 in free run mode DPLL_2 in holdover DPLL_2 in switchover DPLL_2 history available DPLL_2 history updated 0xEA 0xEB 0xEC 0xED 0xF0 0xF1 0xF2 0xF3 DPLL_2 clamp DPLL_2 phase slew limited PLL_2 clock distribution sync pulse DPLL_2 demapping controller clamped DPLL_3 phase locked DPLL_3 frequency locked APLL_3 frequency lock APLL_3 cal in process Rev. D | Page 113 of 116 Source Proxy Register 0x0D05, Bit 4||Bit 5||Bit 6||Bit 7 Register 0x0D20, Bit 1 Register 0x0D20, Bit 2 Register 0x0D20, Bit 3 Register 0x0D20, Bit 4 Logical OR of Bit 4 in Register 0x0D02 through Register 0x0D05 Register 0x0D21, Bit 0 Register 0x0D21, Bit 1 Register 0x0D21, Bit 2 Register 0x0D22, Bit 0 Register 0x0D0C, Bit 4 (IRQ does not need to be set for this setting to work) Register 0x0D22, Bit 1 Register 0x0D22, Bit 2 None Register 0x0D22, Bit 3 Register 0x0D40, Bit 1 Register 0x0D40, Bit 2 Register 0x0D40, Bit 3 Register 0x0D40, Bit 4 Logical OR of Bit 5 in Register 0x0D02 through Register 0x0D05 Register 0x0D41, Bit 0 Register 0x0D41, Bit 1 Register 0x0D41, Bit 2 Register 0x0D42, Bit 0 Register 0x0D0F, Bit 4 (IRQ does not need to be set for this setting to work) Register 0x0D42, Bit 1 Register 0x0D42, Bit 2 None Register 0x0D42, Bit 3 Register 0x0D60, Bit 1 Register 0x0D60, Bit 2 Register 0x0D60, Bit 3 Register 0x0D60, Bit 4 Logical OR of Bit 6 in Register 0x0D02 through Register 0x0D05 Register 0x0D61, Bit 0 Register 0x0D61, Bit 1 Register 0x0D61, Bit 2 Register 0x0D62, Bit 0 Register 0x0D0C, Bit 4 (IRQ does not need to be set for this setting to work) Register 0x0D62, Bit 1 Register 0x0D62, Bit 2 None Register 0x0D62, Bit 4 Register 0x0D80, Bit 1 Register 0x0D80, Bit 2 Register 0x0D80, Bit 3 Register 0x0D80, Bit 4 AD9554 Data Sheet Bits[D7:D0] Value 0xF4 Output Function DPLL_3 active 0xF5 0xF6 0xF7 0xF8 0xF9 DPLL_3 in free run mode DPLL_3 in holdover DPLL_3 in switchover DPLL_3 history available DPLL_3 history updated 0xFA 0xFB 0xFC 0xFD 0xFE to 0xFF DPLL_3 clamp DPLL_3 phase slew limited PLL_3 clock distribution sync pulse DPLL_3 demapping controller clamped Reserved Source Proxy Logical OR of Bit 7 in Register 0x0D02 through Register 0x0D05 Register 0x0D81, Bit 0 Register 0x0D81, Bit 1 Register 0x0D81, Bit 2 Register 0x0D82, Bit 0 Register 0x0D0F, Bit 4 (IRQ does not need to be set for this setting to work) Register 0x0D82, Bit 1 Register 0x0D82, Bit 2 None Register 0x0D82, Bit 3 None Table 155. Multifunction Pin Input Functions (D7 = 0) Bits[D7:D0] Value 0x00 0x01 0x02 0x03 0x04 0x10 0x11 0x12 0x13 0x14 0x15 0x20/0x21/0x22/0x23 0x28/0x29/0x2A/0x2B 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x58 0x59 0x5A 0x5B Input Function No function IO_UPDATE Full power-down Clear watchdog timer Soft sync all Clear all IRQs Clear common IRQs Clear DPLL_0 IRQs Clear DPLL_1 IRQs Clear DPLL_2 IRQs Clear DPLL_3 IRQs Force fault REFA/REFB/REFC/REFD Force validation timeout REFA/REFB/REFC/REFD PLL_0 power-down DPLL_0 user free run DPLL_0 user holdover DPLL_0 tuning word history reset DPLL_0 increment phase offset DPLL_0 decrement phase offset DPLL_0 reset phase offset APLL_0 soft sync PLL_0 disable all output drivers PLL_0 disable OUT0A PLL_0 disable OUT0B PLL_0 manual reference input selection, Bit 0 PLL_0 manual reference input selection, Bit 1 PLL_1 power-down DPLL_1 user free run DPLL_1 user holdover DPLL_1 tuning word history reset DPLL_1 increment phase offset DPLL_1 decrement phase offset DPLL_1 reset phase offset APLL_1 soft sync PLL_1 disable all output drivers PLL_1 disable OUT1A PLL_1 disable OUT1B Rev. D | Page 114 of 116 Destination Proxy None Register 0x000F, Bit 0 Register 0x0A00, Bit 0 Register 0x0A05, Bit 7 Register 0x0A00, Bit 3 Register 0x0A05, Bit 0 Register 0x0A05, Bit 1 Register 0x0A05, Bit 2 Register 0x0A05, Bit 3 Register 0x0A05, Bit 4 Register 0x0A05, Bit 5 Register 0x0A03, Bits[3:0] Register 0x0A02, Bits[3:0] Register 0x0A20, Bit 0 Register 0x0A22, Bit 0 Register 0x0A22, Bit 1 Register 0x0A23, Bit 1 Register 0x0A24, Bit 0 Register 0x0A24, Bit 1 Register 0x0A24, Bit 2 Register 0x0A20, Bit 2 Register 0x0A21, Bits[3:2] Register 0x0A21, Bit 2 Register 0x0A21, Bit 3 Register 0x0A22, Bit 5 Register 0x0A22, Bit 6 Register 0x0A40, Bit 0 Register 0x0A42, Bit 0 Register 0x0A42, Bit 1 Register 0x0A43, Bit 1 Register 0x0A44, Bit 0 Register 0x0A44, Bit 1 Register 0x0A44, Bit 2 Register 0x0A40, Bit 2 Register 0x0A41, Bits[3:2] Register 0x0A41, Bit 2 Register 0x0A41, Bit 3 Data Sheet Bits[D7:D0] Value 0x5C 0x5D 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E to 0x7F AD9554 Input Function PLL_1 manual reference input selection, Bit 0 PLL_1 manual reference input selection, Bit 1 PLL_2 power-down DPLL_2 user free run DPLL_2 user holdover DPLL_2 tuning word history reset DPLL_2 increment phase offset DPLL_2 decrement phase offset DPLL_2 reset phase offset APLL_2 soft sync PLL_2 disable all output drivers PLL_2 disable OUT2A PLL_2 disable OUT2B PLL_2 manual reference input selection, Bit 0 PLL_2 manual reference input selection, Bit 1 PLL_2 power-down DPLL_3 user free run DPLL_3 user holdover DPLL_3 tuning word history reset DPLL_3 increment phase offset DPLL_3 decrement phase offset DPLL_3 reset phase offset APLL_3 soft sync PLL_3 disable all output drivers PLL_3 disable OUT3A PLL_3 disable OUT3B PLL_3 manual reference input selection, Bit 0 PLL_3 manual reference input selection, Bit 1 Reserved Rev. D | Page 115 of 116 Destination Proxy Register 0x0A42, Bit 5 Register 0x0A42, Bit 6 Register 0x0A60, Bit 0 Register 0x0A62, Bit 0 Register 0x0A62, Bit 1 Register 0x0A63, Bit 1 Register 0x0A64, Bit 0 Register 0x0A64, Bit 1 Register 0x0A64, Bit 2 Register 0x0A60, Bit 2 Register 0x0A61, Bits[3:2]) Register 0x0A61, Bit 2 Register 0x0A61, Bit 3 Register 0x0A62, Bit 5 Register 0x0A62, Bit 6 Register 0x0A60, Bit 0 Register 0x0A82, Bit 0 Register 0x0A82, Bit 1 Register 0x0A83, Bit 1 Register 0x0A84, Bit 0 Register 0x0A84, Bit 1 Register 0x0A84, Bit 2 Register 0x0A80, Bit 2 Register 0x0A81, Bits[3:2] Register 0x0A81, Bit 2 Register 0x0A81, Bit 3 Register 0x0A82, Bit 5 Register 0x0A82, Bit 6 None AD9554 Data Sheet OUTLINE DIMENSIONS 10.10 10.00 SQ 9.90 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 55 72 54 9.85 9.75 SQ 9.65 0.50 BSC 12 MAX 18 37 19 36 TOP VIEW 1.00 0.85 0.80 7.25 7.10 SQ 6.95 EXPOSED PAD 0.50 0.40 0.30 BOTTOM VIEW 0.80 MAX 0.65 TYP 0.25 MIN 8.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 06-25-2012-A PIN 1 INDICATOR 1 Figure 49. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm x 10 mm Body, Very Thin Quad (CP-72-4) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9554BCPZ AD9554BCPZ-REEL AD9554BCPZ-REEL7 AD9554/PCBZ 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2014-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12132-0-3/17(D) Rev. D | Page 116 of 116 Package Option CP-72-4 CP-72-4 CP-72-4 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: AD9554R/PCBZ