AM27C4096-200PC - AMD - Datasheet.Live

Publication# 11408 Rev. EAmendment/0

Issue Date: May 1995

2-126

Advanced

Micro

Devices

Am27C4096

4 Megabit (262,144 x 16-Bit) CMOS EPROM

FINAL

DISTINCTIVE CHARACTERISTICS

■Fast access time

— 90 ns

■Low power consumption

— 100 µA maximum CMOS standby current

■JEDEC-approved pinout

— Plug in upgrade of 1 Mbit and 2 Mbit EPROMs

— 40-pin DIP/PDIP

— 44-pin PLCC

■Single + 5 V power supply

■± 10% power supply tolerance standard on

most speeds

■100% Flashrite programming

— Typical programming time of 32 seconds

■Latch-up protected to 100 mA from –1 V

to VCC + 1 V

■High noise immunity

GENERAL DESCRIPTION

The Am27C4096 is a 4 Mbit ultraviolet erasable pro-

grammable read-only memory. It is organized as 256K

words by 16 bits per word, operates from a single +5 V

supply, has a static standby mode, and features fast sin-

gle address location programming. The Am27C4096 is

ideal for use in 16-bit microprocessor systems. Products

are available in windowed ceramic DIP packages as

well as plastic one time programmable (OTP) PDIP and

PLCC packages.

Typically, any byte can be accessed in less than 90 ns,

allowing operation with high-performance microproces-

sors without any WAIT states. The Am27C4096 offers

separate Output Enable (OE) and Chip Enable (CE)

controls, thus eliminating bus contention in a multiple

bus microprocessor system.

AMDs CMOS process technology provides high speed,

low power, and high noise immunity. Typical power con-

sumption is only 125 mW in active mode, and 125 µW in

standby mode.

All signals are TTL levels, including programming

signals. Bit locations may be programmed singly, in

blocks, or at random. The Am27C4096 supports AMD’s

Flashrite programming algorithm (100 µs pulses) result-

ing in typical programming times of 32 seconds.

BLOCK DIAGRAM

11408E-1

VCC

VPP

CE/PGM

Output Enable

Chip Enable

and

Prog Logic

Decoder

Output Buffers

Gating

4.194,304-Bit

Cell Matrix

A0–A17

Address

Inputs

Data Outputs

DQ0–DQ15

VSS

AMD

2-127Am27C4096

PRODUCT SELECTOR GUIDE

Family Part No.

Ordering Part No:

VCC + 5% -95 -105 -255

VCC +10% -100 -120 -150 -200

Max Access Time (ns) 90 100 120 150 200 250

CE (E) Access Time (ns) 90 100 120 150 200 250

OE (G) Access Time (ns) 50 50 50 65 75 75

Am27C4096

CONNECTION DIAGRAMS

Top View

VPP

CE (E)/PGM (P)

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

VSS

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

OE (G)

VCC

A15

A14

A13

A12

A11

A10

VSS

11408E-2

DIP PLCC

Note:

1. JEDEC nomenclature is in parentheses.

A17

A16

144 43 42

5432

641

17 23 24 25 26

19 20 21 22

18 27 28

DQ12

DQ11

DQ10

DQ9

DQ8

VSS

DQ7

DQ6

DQ5

DQ4

A13

A12

A11

A10

VSS

DQ13

DQ14

DQ15

CE (E)/PGM (P)

VPP

VCC

A17

A16

A15

A14

DQ3

DQ2

DQ1

DQ0

OE (G)

11408E-3

11408E-4

PIN DESIGNATIONS

A0–A17 = Address Inputs

CE (E)/PGM (P) = Chip Enable Input

DQ0–DQ15 = Data Input/Outputs

DU = No External Connection

NC = No Internal Connection

OE (G) = Output Enable Input

VCC =V

CC Supply Voltage

VPP = Program Voltage Input

VSS = Ground

LOGIC SYMBOL

A0–A17

CE (E)/PGM

OE (G)

DQ0–DQ15

AMD

2-128 Am27C4096

ORDERING INFORMATION

UV EPROM Products

AM27C4096-95

AM27C4096-100

AM27C4096-105

AM27C4096-120

AM27C4096-150

AM27C4096-200

AM27C4096-255

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of:

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended Commercial (–55°C to +125°C)

PACKAGE TYPE

D = 40-Pin Ceramic DIP (CDV040)

SPEED OPTION

See Product Selector Guide and

Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am27C4096

4 Megabit (262,144x16 Bit) CMOS UV EPROM

AM27C4096 -95 D C

Valid Combinations

Valid Combinations list configurations planned to be

supported in volume for this device. Consult the lo-

cal AMD sales office to confirm availability of specific

valid combinations and to check on newly released

combinations.

Valid Combinations

OPTIONAL PROCESSING

Blank = Standard processing

B = Burn-in

DC, DCB, DE,

DEB, DI, DIB

DC, DCB,

DI, DIB

DC, DCB

DC, DCB, DI, DIB

AMD

2-129Am27C4096

ORDERING INFORMATION

OTP Products

AM27C4096-105

AM27C4096-120

AM27C4096-150

AM27C4096-200

AM27C4096-255

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of:

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

PACKAGE TYPE

P = 40-Pin Plastic DIP (PD 040)

J = 44-Pin Rectangular Plastic Leaded

Chip Carrier (PL 044)

SPEED OPTION

See Product Selector Guide and

Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am27C4096

4 Megabit (262,144 x16 Bit) CMOS OTP EPROM

AM27C4096 -105 P C

Valid Combinations

Valid Combinations list configurations planned to be

supported in volume for this device. Consult the lo-

cal AMD sales office to confirm availability of specific

valid combinations and to check on newly released

combinations.

Valid Combinations

OPTIONAL PROCESSING

Blank = Standard processing

PC, JC, PI, JI

PC, JC

AMD

2-130 Am27C4096

FUNCTIONAL DESCRIPTION

Erasing The Am27C4096

In order to clear all locations of their programmed con-

tents, it is necessary to expose the Am27C4096 to an ul-

traviolet light source. A dosage of 15 W seconds/cm2 is

required to completely erase an Am27C4096. This dos-

age can be obtained by exposure to an ultraviolet lamp

— wavelength of 2537 A

° — with intensity of 12,000 µW/

cm2 for 15 to 20 minutes. The Am27C4096 should be di-

rectly under and about one inch from the source and all

filters should be removed from the UV light source prior

to erasure.

It is important to note that the Am27C4096 and similar

devices will erase with light sources having wavelengths

shorter than 4000 A

°. Although erasure times will be

much longer than with UV sources at 2537 A

°, exposure

to fluorescent light and sunlight will eventually erase the

Am27C4096 and exposure to them should be prevented

to realize maximum system reliability. If used in such an

environment, the package window should be covered

by an opaque label or substance.

Programming the Am27C4096

Upon delivery or after each erasure the Am27C4096

has all 4,194,304 bits in the “ONE” or HIGH state.

“ZEROs” are loaded into the Am27C4096 through the

procedure of programming.

The programming mode is entered when 12.75 V

± 0.25 V is applied to the VPP pin, CE/PGM is at VIL and

OE is at VIH.

For programming, the data to be programmed is applied

16 bits in parallel to the data output pins.

The Flashrite algorithm reduces programming time by

using 100 µs programming pulses and by giving each

address only as many pulses as are necessary in order

to reliably program the data. After each pulse is applied

to a given address, the data in that address is verified. If

the data does not verify, additional pulses are given until

it verifies or the maximum is reached. This process is

repeated while sequencing through each address of the

Am27C4096. This part of the algorithm is done at VCC =

6.25 V to assure that each EPROM bit is programmed to

a sufficiently high threshold voltage after the final

address is completed, the entire EPROM memory is

verified at VCC = VPP = 5.25 V.

Please refer to Section 6 for programming flow chart

and characteristics.

Program Inhibit

Programming of multiple Am27C4096 in parallel with

different data is also easily accomplished. Except for

CE/PGM, all like inputs of the parallel Am27C4096 may

be common. A TTL low-level program pulse applied to

an Am27C4096 CE/PGM input with VPP = 12.75 V ±

0.25V and OE HIGH will program that Am27C4096. A

high-level CE/PGM input inhibits the other Am27C4096

devices from being programmed.

Program Verify

A verify should be performed on the programmed bits to

determine that they were correctly programmed. The

verify should be performed with OE at VIL, CE/PGM at

VIH, and VPP between 12.5 V and 13.0 V.

Auto Select Mode

The auto select mode allows the reading out of a binary

code from an EPROM that will identify its manufacturer

and type. This mode is intended for use by programming

equipment for the purpose of automatically matching

the device to be programmed with its corresponding

programming algorithm. This mode is functional in the

25°C ± 5°C ambient temperature range that is required

when programming the Am27C4096.

To activate this mode, the programming equipment

must force 12.0 V ± 0.5 V on address line A9 of the

Am27C4096. Two identifier bytes may then be

sequenced from the device outputs by toggling address

line A0 from VIL to VIH. All other address lines must be

held at VIL during auto select mode.

Byte 0 (A0 = VIL) represents the manufacturer code, and

byte 1(A0 = VIH), the device identifier code. For the

Am27C4096, these two identifier bytes are given in the

Mode Select Table. All identifiers for manufacturer and

device codes will possess odd parity, with the MSB

(DQ7) defined as the parity bit.

Read Mode

The Am27C4096 has two control functions, both of

which must be logically satisfied in order to obtain data

at the outputs. Chip Enable (CE/PGM) is the power con-

trol and should be used for device selection. Output En-

able (OE) is the output control and should be used to

gate data to the output pins, independent of device se-

lection. Assuming that addresses are stable, address

access time (tACC) is equal to the delay from CE/PGM to

output (tCE). Data is available at the outputs tOE after the

falling edge of OE, assuming that CE/PGM has been

LOW and addresses have been stable for at least

tACC

– tOE.

Standby Mode

The Am27C4096 has a CMOS standby mode which

reduces the maximum VCC current to 100 µA. It is placed

in CMOS-standby when CE/PGM is at VCC ± 0.3 V. The

Am27C4096 also has a TTL-standby mode which

reduces the maximum VCC current to 1.0 mA. It is placed

in TTL-standby when CE/PGM is at VIH. When in

standby mode, the outputs are in a high-impedance

state, independent of the OE input.

AMD

2-131Am27C4096

Output OR-Tieing

To accommodate multiple memory connections, a two-

line control function is provided to allow for:

Low memory power dissipation

Assurance that output bus contention will not

occur

It is recommended that CE/PGM be decoded and used

as the primary device-selecting function, while OE be

made a common connection to all devices in the array

and connected to the READ line from the system control

bus. This assures that all deselected memory devices

are in low-power standby mode and that the output pins

are only active when data is desired from a particular

memory device.

System Applications

During the switch between active and standby condi-

tions, transient current peaks are produced on the rising

and falling edges of Chip Enable. The magnitude of

these transient current peaks is dependent on the

output capacitance loading of the device. At a minimum,

a 0.1-µF ceramic capacitor (high frequency, low inher-

ent inductance) should be used on each device between

VCC and VSS to minimize transient effects. In addition, to

overcome the voltage drop caused by the inductive

effects of the printed circuit board traces on EPROM

arrays, a 4.7-µF bulk electrolytic capacitor should be

used between VCC and VSS for each eight devices. The

location of the capacitor should be close to where the

power supply is connected to the array.

MODE SELECT TABLE

Mode CE/PGM OE A0 A9 VPP Outputs

Read VIL VIL XXXDOUT

Output Disable VIL VIH X X X High Z

Standby (TTL) VIH XXXXHigh Z

Standby (CMOS) VCC ± 0.3 V XXXXHigh Z

Program VIL VIH XXVPP DIN

Program Verify VIH VIL XXVPP DOUT

Program Inhibit VIH XXXVPP High Z

Manufacturer Code VIL VIL VIL VHX O1H

Device Code VIL VIL VIH VHX 19H

Notes:

1. V

= 12.0 V

0.5 V.

2. X = Either V

or V

3. A1–A8 = A10–A17 = V

4. See DC Programming Characteristics for V

voltage during programming.

Pins

Auto Select

(Note 3)

AMD

2-132 Am27C4096

ABSOLUTE MAXIMUM RATINGS

Storage Temperature:

OTP Products –65°C to +125°C. . . . . . . . . . . . . . . . .

All Other Products –65°C to +150°C. . . . . . . . . . . . . .

Ambient Temperature

with Power Applied –55°C to +125°C. . . . . . . . . . . . .

Voltage with Respect to VSS:

All pins except A9, VPP,

and VCC (Note 1) –0.6 V to VCC + 0.6 V. . . . . . . . . .

A9 and VPP (Note 2) –0.6 V to 13.5 V. . . . . . . . . . . . .

VCC –0.6 V to 7.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . .

Notes:

1. During transitions, the inputs may overshoot VSS to –2.0 V

for periods of up to 20 ns. Maximum DC voltage on input

and I/O may overshoot to VCC + 2.0 V for periods of up to

20 ns.

2. During transitions, A9 and VPP may overshoot VSS to

–2.0 V for periods of up to 20 ns. A9 and VPP must not ex-

ceed 13.5 V for any period of time.

Stresses above those listed under Absolute Maximum Rat-

ings may cause permanent device failure. Functionality at or

above these limits is not implied. Exposure to absolute maxi-

mum ratings for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA)0°C to +70°C. . . . . . . . . .

Industrial (I) Devices

Ambient Temperature (TA) –40°C to +85°C. . . . . . . .

Extended Commercial (E) Devices

Ambient Temperature (TA) –55°C to +125°C. . . . . . .

Supply Read Voltages:

VCC for Am27C4096-XX5 +4.75 V to +5.25 V. . . . . . .

VCC for Am27C4096-XX0 +4.50 V to +5.50 V. . . . . . .

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

AMD

2-133Am27C4096

DC CHARACTERISTICS over operating range unless otherwise specified

(Notes 1, 2 and 4)

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

VOH Output HIGH Voltage IOH = –400 µA 2.4 V

VOL Output LOW Voltage IOL = 2.1 mA 0.45 V

VIH Input HIGH Voltage 2.0 VCC +0.5 V

VIL Input LOW Voltage –0.5 +0.8 V

ILI Input Load Current VIN = 0 V to VCC 1.0 µA

ILO Output Leakage Current VOUT = 0 V to VCC 5.0 µA

ICC1 VCC Active Current CE = VIL, f = 5 MHz C/I Devices 50

(Note 3) IOUT = 0 mA E Devices 60

ICC2 VCC TTL Standby CE = VIH 1.0 mA

ICC3 VCC CMOS Standby CE = Vcc ± 0.3 V 100 µA

IPP1 VPP Current During Read CE = OE = VIL, VPP = VCC 100 µA

Notes:

1. V

must be simultaneously or before V

, and removed simultaneously or after V

2. Caution: The Am27C4096 must not be removed from (or inserted into) a socket when V

or V

is applied.

3. I

CC1

is tested with

= V

to simulate open outputs.

4. Minimum DC Input Voltage is –0.5 V during transitions, the inputs may overshoot –2.0 V for periods less than 20 ns. Maximum

DC Voltage on output pins is V

+0.5 V, which may overshoot to V

+2.0 V for periods less than 20 ns.

–75 –50 –25 0 25 50 75 100 125 150

Frequency in MHz

11408E-5

12345678910

Supply Current

in mA

Supply Current

in mA

Temperature in °C

Figure 1. Typical Supply Current

vs. Frequency

VCC = 5.5 V, T = 25°C

Figure 2. Typical Supply Current

vs. Temperature

VCC = 5.5 V, f = 5 MHz

11408E-6

AMD

2-134 Am27C4096

CAPACITANCE

Parameter Parameter

Symbol Description Test Conditions Typ Max Typ Max Typ Max Unit

CIN Input Capacitance VIN = 0 V 10 13 6 8 10 13 pF

COUT Output Capacitance VOUT = 0 V 10 13 8 10 12 14 pF

Notes:

1. This parameter is only sampled and not 100% tested.

2. T

= +25

C, f = 1 MHz.

CDV040 PD040 PL044

SWITCHING CHARACTERISTICS over operating range unless otherwise specified

(Notes 1, 3 and 4)

JEDEC Standard Parameter Description Test Conditions -95 -105 -120 -150 -200 -255 Unit

AVQV tACC Address to CE = OE = VIL Min————— —

Output Delay Max 90 100 120 150 200 250

tELQV tCE Chip Enable to OE = VIL Min————— —

Output Delay Max 90 100 120 150 200 250

tGLQV tOE Output Enable to CE = VIL Min————— —

Output Delay Max 50 50 50 65 75 75

tEHQZ ,tDF Min————— —

tGHQZ (Note 2) Max 30 30 40 40 40 60

tAXQX tOH Min00000 0

Max————— —

Parameter

Symbols Am27C4096

Chip Enable HIGH or

Output Enable HIGH,

whichever comes first,

to Output Float

Notes:

1. V

must be applied simultaneously or before V

PP,

and removed simultaneously or after V

2. This parameter is only sampled and not 100% tested.

3. Caution: The Am27C4096 must not be removed from (or inserted into) a socket or board when V

or V

is applied.

4. Output Load: 1 TTL gate and C

= 100 pF

Input Rise and Fall Times: 20 ns

Input Pulse Levels: 0.45 V to 2.4 V

Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs.

Output Hold from

Addresses, CE, or

OE, whichever

occurred first

AMD

2-135Am27C4096

SWITCHING TEST CIRCUIT

11408E-7

Device

Under

Test 5.0 V

Diodes = IN3064

or Equivalent

CL6.2 kΩ

2.7 kΩ

CL = 100 pF including jig capacitance

SWITCHING TEST WAVEFORM

11408E-8

AC Testing: Inputs are driven at 2.4 V for a Logic “1” and 0.45 V for a Logic “0”. Input pulse rise and fall times are ≤ 20 ns.

2.4 V

0.45 V

2.0 V

0.8 V

Test Points

2.0 V

0.8 V

Input Output

AMD

2-136 Am27C4096

KEY TO SWITCHING WAVEFORMS

KS000010

Must be

Steady

May

Change

from H to L

May

Change

from L to H

Does Not

Apply

Don’t Care,

Any Change

Permitted

Will be

Steady

Will be

Changing

from H to L

Will be

Changing

from L to H

Changing,

State

Unknown

Center

Line is High-

Impedance

“Off” State

WAVEFORM INPUTS OUTPUTS

SWITCHING WAVEFORM

Addresses

CE/PGM

Output

Addresses Valid

High Z High Z

tCE

Valid Output

2.4

0.45

2.0

0.8 2.0

0.8

tACC

(Note 1)

tOE tDF

(Note 2)

tOH

Notes:

may be delayed up to t

ACC

– t

after the falling edge of the addresses without impact on t

ACC.

2. t

is specified from

, whichever occurs first.

11408E-9