TS5070FN/MT013TR - STMicroelectronics

TS5070

TS5071

PROGRAMMABLE CODEC/FILTER

COMBO 2ND GENERATION

COMPLETE CODEC AND FILTER SYSTEM

INCLUDING :

– TRANSMI T AND RECEIVE P CM CHANNEL

FILTERS

–µ-LAW OR A-LAW COMPANDING CODER

AND DE CODER

– RECEIVE POWER AMPLIFIER DRIVES

300

Ω

– 4.096 MHz SERIAL P CM DATA (max)

PROGRAMMA BLE FUN C TION S :

– TRANSMI T GAIN : 25. 4 dB RANGE, 0.1 dB

STEPS

– RECEIVE GAIN : 25.4 dB RANGE, 0.1 dB

STEPS

– HYBRID BALANCE CANCELLATION FIL-

TER

– TIME-SLOT ASSIGNMENT: UP TO 64

SLOTS/FRAME

– 2 PORT ASSIGNM ENT (TS5070)

– 6 INTERFACE LATCHE S (TS 5070)

–A OR µ

-LAW

– ANALOG LOOPBACK

– DIGITAL LOOPB ACK

DIRECT INTERFACE TO SOLID-STATE

SLICs

SIMPLIFIES TRANSFORMER SLIC, SINGLE

WINDING SECONDA RY

STANDARD SERIAL CONTROL INTERFACE

80 mW O PE R A T ING PO W ER (typ )

1.5mW STANDB Y P OW ER (typ)

MEETS OR EXCEEDS ALL CCITT AND

LSSGR SPECIFICATIONS

TTL AND CMOS COMPATIBLE DIGITAL IN-

TERFACES

DESCRIPTION

The TS5070 series are the second generation com-

bi ne d PC M CODE C and F ilte r d evices opt i mized

for digital switching applications on subscriber and

trunk line cards.

Using advanced switched capacitor techniques the

TS507 0 and TS5071 co mbine t ransmit bandpass

and receive lowpass channel filters with a com-

pand ing PCM encoder and decoder. The devices

are A-law and µ-law selectable and employ a con-

ventional serial PCM interface capable of being

clocked up to 4.096 MHz. A number of programma-

ble functions may be controlled via a serial control

port.

Channe l gains are pro grammable over a 25.4 dB

range in each direction, and a programmable filter

is included to enable Hybrid Balancing to be ad-

justed to suit a wide range of loop impedance con-

ditions.

Both transformer and active SLIC int erface circuits

with re al or compl ex t er mination impedances can

be ba lanced by this filter, with cancell ation in ex-

cess of 30 dB being readily achievable when meas-

ured across the passband against standard test ter-

mination networks.

To enable COMBO IIG to interface to the SLIC con-

trol leads, a num ber of programmable latches are

included ; each may be configured as either an in-

put or an out put. The TS5070 provi des 6 latche s

and the TS5071 5 latches.

September 2003

DIP20 (Plastic)

ORDERING NUMBER:TS5071N

PLCC28

ORDERING NUMBERS: TS5070FN

TS5070FNTR

1/32

TS5070 PIN FUNCTIONALITY (PLCC28)

No. Name Function

1 GND Ground Input (+0V)

2VF

0 Analog Output

SS Supply Input (-5V)

4 NC Not Connected

5 NC Not Connected

6 IL3 Digital Input or Output defined by LDR register content

7 IL2 Digital Input or Output defined by LDR register content

8FS

RDigital input

1 Digital input sampled by BCLK falling edge

10 DR0 Digital input sampled by BCLK falling edge

11 CO Digital output (shifted out on CCLK rising edge)

12 CI Digital input (sampled on CCLK falling edge)

13 CCLK Digital input (clock)

14 CS Digital input (chip select for CI/CO)

15 MR Digital Input

16 BCLK Digital input (clock)

17 MCLK Digital input

18 DX0 Digital output clocked by BCLK rising edge

19 DX1 Digital output clocked by BCLK rising edge

20 TSX0 Open drain output (pulled low by active DX0 time slot)

21 TSX1 Open drain output (pulled low by active DX1 time slot)

22 FSXDigital input

23 IL5 Digital input or output defined by LDR register content

24 IL4 Digital input or output defined by LDR register content

25 IL1 Digital input or output defined by LDR register content

26 IL0 Digital input or output defined by LDR register content

27 VCC Supply input (+5V)

28 VFXI Analog input

HYBRID

BALANCE

FILTER

ENCODER

TX GAIN

TX TIME SLOT

Vref

HYBAL 1

HYBAL 2

HYBAL 3

TIME-SLOT

ASSIGNMENT

CTL REG.

RX TIME SLOT

RX GAIN

DECODER

TS5070/71

INTERFACE

LATCHES LATCH DIR

LATCH CONT. CONTROL

INTERFACE

DX0

DX1

TSX0

TSX1

FSX

BCLK

FSR

DR0

DR1

MCLK

CCLK

VSS=-5VVCC=+5V

VFXI

VFRO

GND

IL5

IL4

IL3

IL2

IL1

IL0

D94TL135

TS5070 FUNCT IONAL DIAGRAM

TS5070 - TS5071

2/32

BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC VCC to GND 7 V

VSS VSS to GND – 7 V

Voltage at VFXI VCC + 0.5 to VSS – 0.5 V

VIN Voltage at Any Digital Input VCC + 0.5 to GND – 0.5 V

Current at VFRO ± 100 mA

IOCurrent at Any Digital Output ± 50 mA

Tstg Storage Temperature Range – 65, + 150 °C

Tlead Lead Temperature Range (soldering, 10 seconds) 300 °C

TS5070 - TS5071

3/32

PIN C ONNECTIONS

POWER SUP P LY, CLOCK

Name Pin

Type TS5070

FN TS5071

NFunction Description

VCC

VSS

GND

Positive Power

Supply

Negative

Power Supply

Ground

+ 5 V ± 5 %

– 5 V ± 5 %

All analog and digital signals are referenced to this pin.

BCLK I 16 12 Bit Clock Bit clock input used to shift PCM data into and out of the

DR and DX pins. BCLK may vary from 64 kHz to 4.096

MHz in 8 kHz increments, and must be synchronous with

MCLK (TS5071 only).

MCLK I 17 12 Master Clock Master clock input used by the switched capacitor filters

and the encoder and decoder sequencing logic. Must be

512 kHz, 1. 536/1. 544 MHz,

2.048 MHz or 4.096 MHz and synchronous with BCLK.

BCLK and MCLK are wired together in the TS5071.

PLCC28

TS5070FN DIP20

TS5071N

TS5070 - TS5071

4/32

TRA N SM IT SE CT ION

Name Pin

Type TS5070

FN TS5071

NFunction Description

FSXI 22 15 Transmit

Frame Sync. Normally a pulse or squarewave waveform with an 8 kHz

repetition rate is applied to this input to define the start of

the transmit time-slot assigned to this device (non-delayed

data mode) or the start of the transmit frame (delayed

data mode using the internal time-slot assignment

counter).

VFXI I 28 20 Transmit

Analog This is a high–impedance input. Voice frequency signals

present on this input are encoded as an A–law or µ–law

PCM bit stream and shifted out on the selected DX pin.

DX0

DX10

018

19 13

–Transmit Data DX1 is available on the TS5070 only, DX0 is available on

all devices. These transmit data TRI–STATE outputs

remain in the high impedance state except during the

assigned transmit time–slot on the assigned port, during

which the transmit PCM data byte is shifted out on the

rising edges of BCLK.

TSX0

TSX10

020

21 14

–Transmit

Time–slot TSX1 is available on the TS5070 only.

TSX0 is available on all devices. Normally these opendrain

outputs are floating in a high impedance state except

when a time–slot is active on one of the DX outputs, when

the apppropriate TSX output pulls low to

enable a backplane line–driver. Should be strapped to

ground (GND) when not used.

REC EIV E SECTI ON

Name Pin

Type TS5070

FN TS5071

NFunction Description

FSRI 8 6 Receive Frame

Sync. Normally a pulse or squarewave waveform with an 8 kHz

repetition rate is applied to this input to define the start of

the receive time–slot assigned to this device (non-delayed

frame mode) or the start of the receive frame (delayed

frame mode using the internal time-slot assignment

counter.

VFR0 0 2 2 Receive Analog The receive analog power amplifier output, capable of

driving load impedances as low as 300 Ω (depending on

the peak overload level required). PCM data received on

the assigned DR pin is decoded and appears at this output

as voice frequency signals.

DR0

DR1I

I10

–Receive Data DR1 is available on the TS5070 only, DR0 is available on

all devices. These receive data input(s) are inactive

except during the assigned receive time–slot of the

assigned port when the receive PCM data is shifted in on

the falling edges of BCLK.

TS5070 - TS5071

5/32

FUNCTIONAL DESCRIPTION

POWER-ON INITIALIZATION

When power is first applied, power-on reset cir-

cuitry initializes COMBO IIG and puts it into the

power-down state. The gain control registers for

the transmit and receive gain sections are pro-

grammed for no output , t he hybrid balance circuit

is turned off, the power amp is disabled and the

device is in the non-delayed timing mode. The

Latch Direction Register (LDR) is pre-set with all

IL pins programmed as inputs, placing the SLIC

interface pins in a high impedance state. The

CI/O pin is set as an input r eady for the first con-

trol byte of t he initialization sequence. Ot her initial

states in the Con trol Register are indicated in Ta-

ble 2.

A reset to these same initial conditions may also be

forced by driving the MR pin momentarily high. This

may be done either when powered-up or down. For

normal operation this pin must be pulled low. If not

used, MR should be hard-wired to ground.

The desired m odes for all programmable functions

may be initialized via the control port prior to a

Power-up command.

INTERFACE, CONTRO L, RESET

Name Pin

Type TS5070

FN TS5071

NFunction Description

IL5

IL4

IL3

IL2

IL1

IL0

I/O

–

Interface

Latches IL5 through IL0 are available on the TS5070,

IL4 through IL0 are available on the TS5071.

Each interface Latch I/O pin may be individually

programmed as an input or an output determined by the

state of the corresponding bit in the Latch Direction

state sensed on each input is latched into the interface

Latch Register (ILR) whenever control data is written to

COMBO IIG, while CS is low, and the information is

shifted out on the CO (or CI/O) pin. When configured as

outputs, control data written into the ILR appears at the

corresponding IL pins.

CCLK I 13 9 Control Clock This clock shifts serial control information into or out of CI

or CO (or CI/O) when the CS input is low depending on

the current instruction. CCLK may be asynchronous with

the other system clocks.

CI/O I/O – 8 Control Data

Input/output This is Control Data I/O pin wich is provided on the

TS5071. Serial control information is shifted into or out of

COMBO IIG on this pin when CS is low. The direction of

the data is determined by the current instruction as defined

in Table 1.

–

Control Data

Input

Control Data

Output

These are separate controls, availables only on the

TS5070. They can be wired together if required.

CS I 14 10 Chip Select When this pins is low, control information can be written to

or read from the COMBO IIG via the CI and CO pins (or

CI/O).

MR I 15 11 Master Reset This logic input must be pulled low for normal operation of

COMBO IIG. When pulled momentarily high, all

programmable registers in the device are reset to the

states specified under "Power–on Initialization".

TS5070 - TS5071

6/32

POWER-DOWN STATE

Following a period of activity in the powered-up

state the power-down state may be re-entered by

writing any of the control instructions into the serial

control port with the "P" bit set to "1" It is recom-

mended that the chip be powered down before writ-

ing any additional instructions. In the power-down

state, all non-essential circuitry is de-activated and

the DX0 and DX1 outputs are in the high impedance

TRI-STATE condition.

The coefficients stored in the Hybrid Balance circuit

and the Gain Control registers, the data in the LDR

and ILR, and all control bits remain unchanged in

t he po wer- down state u nle ss changed by writ ing

new data via the serial control port, which remains

oper ation al. The out puts of t he Interf ace Latches

also remain active, maintaining the ability to moni-

tor and control a SLIC.

TRANSMIT FILTER AND ENCO DE R

The Transmit s ection input, VFXI, is a high imped-

ance summing input which is used as the differenc-

ing point for the internal hybrid balance cancellation

signal. No external components are needed to set

th e gain. Followi ng this circuit is a programmable

gain/attenuation amplifier which is controlled by the

co ntent s of the Tra nsmit Gain R egi ster (see Pro-

gr ammable Fu nctions sectio n). An active prefilter

then precedes the 3rd order high-pass and 5th or-

der low-pass switched capacitor filters. The A/D

converter has a compressing characteristic accord-

ing to the standard CCI TT A or µ255 coding laws,

which must be selected by a control instruction dur-

ing initialization (see table 1 and 2). A precision on-

chip voltage reference ensures accurate and highly

stable transmission levels. Any offset voltage aris-

ing in the gain-set amplifier, the filters or the com-

parator is cancelled by an internal auto-zero circuit.

Each encode cycle begins immediately following

the assigned Transmit time-slot. The total signal

delay referenced to t he s tart of the time- slot is ap-

proximately 165 µs (due to the Transmit Filter)

plus 125 µs (due to encoding delay), which totals

290 µs. Data is shifted out on DX0 or DX1 during

the selected time slot on eight rising edges of

BCLK.

DECODER AN D RECEIVE FILTER

PCM data is shifted into the Decoder’s Receive

PCM Register via the DR0 or DR1 pin during the se-

lected time-slot on the 8 falling edges of BCLK. The

Decoder consists of an ex panding DA C w ith either

A or µ255 law decoding characteristic, which is se-

lected by the same control instruction used to select

th e En co de law during initialization. F ollowing the

Decoder is a 5th order low-pass switched capacitor

fi lter with int egral Sin x/x corr ection for th e 8 kHz

sample and hold. A programmable gain amplifier,

whic h must be set by writing to the Receive Gain

Amplifier capable of driving a 300 Ω load to ± 3.5

V, a 600 Ω load to ± 3.8 V or 15 kΩ load to ± 4.0 V

at peak overload.

A decode cycle begins immediately after each re-

ceive time-slot, and 10 µs later the Decoder DAC

output is updated. The total signal delay is 10 µs

plus 120 µs (filter delay) plus 62.5 µs (1/ 2 frame)

which gives approximately 190 µs.

PCM INTERFACE

The FSX and F S R frame s ync input s determine the

beginning of the 8-bit transmit and receive time-

slots respectively. They may have any duration

from a si ngle cycle of BCL K to one MCLK period

LOW. Two different relationships may be estab-

lished between the frame sync inputs and the actual

time-slots on the PCM busses by setting bit 3 in the

Cont rol Register ( see table 2). Non d elayed dat a

mode is similar to long-frame timing on the

ETC5050/60 series of devices : time-slots being

nominally coincident with the rising edge of the ap-

propriate FS input. The alternative is to use De-

layed Data mode which is similar to short-frame

sync timing, in which each FS input must be high

at least a half -cy cle of BCLK earlier than the time-

slot.

The Time-Slot Assignment circuit on the device can

only be used with Delayed Data timing. When using

Time-Slot Assignment, the beginning of the first

time-slot in a frame is identified by the appropriate

FS input. The actual transmit and receive time-slots

are then determ ined by the inte rnal Time-Slot As-

sign ment coun ters. Transmit and Receive frames

and time-slots may be skewed from each other by

any number of BCLK cycle s.

During each assigned transmit time-slot, the se-

lected DX0/1 output shifts data out from the PCM

TSX1 as appropriate) also pulls low for the first 7

1/2 bit times of the time-slot to control the TRI-

STATE Enable of a backplane line driver. Serial

PCM data is shifted into t he selected DR0/1 input

during each assigned Receive time slot on the

falling edges of BCLK. DX0 or DX1 and DR0 or

DR1 are selectable on the TS5070 only.

SERI AL CONTROL PORT

Control information and data are written into or

readback from COMBO IIG via the serial control

port consisting of the control clock CCLK ; the serial

dat a in put/ou tp ut CI/O (or separate input CI , and

output CO on the TS5070 only) ; and the Chip Se-

lect input CS. All control instructions require 2

bytes, as listed in table 1, with the exception of a sin-

gle byte power-up/down command. The byte 1 bits

are used as follows: bit 7 specifies power-up or

power-down; bits 6, 5, 4 and 3 specify the r egister

address; bit 2 s pecifies whether the instruc tions is

read or write; bit 1 specifies a one or two byte in-

TS5070 - TS5071

7/32

struction; and bit 0 is not used. To shift control data

into COMBO IIG, CCLK must be pulsed high 8

times while CS is low. Data on the CI or CI/O input

is shifted into the serial input register on the falling

edge of each CCLK pulse. After all data is shifted

in, the contents of the input shift register are de-

coded, and may indicate that a 2nd byte of control

data will follow. This second byte may either be de-

fined by a second byte-wide CS pulse or may follow

the first continuously, i.e. it is not mandatory for CS

to return high in between the first and second con-

trol bytes. On the falling edge of the 8th CCLK clock

pulse in the 2nd control byte the data is loaded into

the appropriate programmable register. CS may re-

main low continuously when programming succes -

sive registers, if desired. However CS should be set

high when no data transfers are in progress.

To readback interface Latch data or status informa-

tion from COMBO IIG, the first byte of the appropri-

ate instruction is strobed in during the first CS pulse,

as defined in table 1. CS must then be taken low for

a further 8 CCLK cycles, during which the data is

shifted onto the CO or C I/O pin on the rising edges

of CCLK. When CS is high the CO or CI /O pin is in

the high-impedance TRI-STATE, enabling the CI/O

pin s of man y devices to be multip lexed to gether.

Thus, to summarize, 2-by te READ and WRI TE in-

structions may use either two 8-bit wide CS pulses

or a single 16-bit wide CS pulse.

Function Byte 1 Byte 2

76543210

Single Byte Power–up/down P X X X X X 0 X None

Write Control Register

Read–back Control Register P

XSee Table 2

See Table 2

Write Latch Direction Register (LDR)

Read Latch Direction Register P

XSee Table 4

See Table 4

Write Latch Content Register (ILR)

Read Latch Content Register P

XSee Table 5

See Table 5

Write Transmit Time–slot/port

Read–back Transmit Time–slot/port P

XSee Table 6

See Table 6

Write Receive Time–slot/port

Read–back Receive Time–slot/port P

XSee Table 6

See Table 6

Write Transmit Gain Register

Read Transmit Gain Register P

XSee Table 7

See Table 7

Write Receive Gain Register

Read Receive Gain Register P

XSee Table 8

See Table 8

Write Hybrid Balance Register ≠ 1

Read Hybrid Balance Register ≠ 1 P

XSee Table 9

See Table 9

Write Hybrid Balance Register ≠ 2

Read Hybrid Balance Register ≠ 2 P

XSee Table 10

See Table 10

Write Hybrid Balance Register ≠ 3

Read Hybrid Balance Register ≠ 3 P

Ta ble 1 : Programmable Register Instructions

PROGRA MMABL E FUNCTIONS

POWER-UP/DOWN CONTROL

Following power-on initialization, power-up and

power-down control may be accomplished by

writing any of the control instructions listed in ta-

ble 1 into COMBO IIG with the "P" bit set to "0"

for power -up or " 1" for power-down. Normall y it is

recommended t hat all programmable functions be

initially programmed while the device is powered

down. Power state control can then be included

with the l ast programming instruction or the sepa-

rate single-byte instruction. Any of the program-

mable registers may also be modified while the

device is powered-up or down be setting the "P"

bit as indicated. When the power up or down c on-

trol is entered as a single byte instruction, bit one

(1) must be set to a 0.

When a power-up command is given, all de-acti-

vated circuits are activated, but the TRI-STATE

PCM output(s), DX0 (and DX1), will remain in the

high impedance state until the second FSX pulse

after power-up.

Notes: 1. Bit 7 of bytes 1 and 2 is always the first bit clocked into or out of the CI, CO or CI/CO pin.

2. "P" is the power-up/down control bit, see "Power-up" section ("0" = Power Up "1" = Power Down).

TS5070 - TS5071

8/32

CONTROL REGISTER INSTRUCTION

The first byte of a READ or WRITE instruction to

the Control Register is as shown in table 1. The

second byte functions are detailed in table 2.

MASTER CLOCK FREQU ENC Y SELEC TION

A Master clock must be provided to COMBO IIG

for operation of the filter and coding/decoding

functions. The MCLK frequency must be either

512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or

4.096 MHz and must be synchronous with BCLK.

Bits F1 and F0 (see table 2) must be set during

initialization to select the corr ect internal divider.

CODING LAW SELECTI ON

Bits "MA" and "IA" in table 2 permit the selection

of µ255 coding or A-law coding with or without

even-bit inversion.

ANALOG LOOPBACK

Analog Loopback mode is entered by setting the

"AL" and " DL" bits in the Cont r ol Regis ter as s hown

in table 2. In t he analog loopback m ode, t he Trans-

mit input VFXI is isolat ed from the input pin and in -

ternally connected to the VFRO output, forming a

loop from the Receive PCM Register back to the

Tr ansmi t PCM Regist er. T he VFRO pin r ema ins ac-

tive, and the programmed settings of the Transmit

and Receive gains remain unchanged, thus care

must be taken to ensure that overload levels are

not exceeded anywhere in the loop.

Hybrid balancing must be disabled for meaning

ful analog loopback Function.

DIGI TAL L OOPB ACK

Digital Loopback mode is entered by setting the

"DL" bit in the Control Register as shown in table 2.

Bit Number Function

76543210

F1 F0 MA IA DN DL AL PP

MCLK = 512 kHz

MCLK = 1. 536 or 1. 544 MHz

MCLK = 2. 048 MHz *

MCLK = 4. 096 MHz

Select µ. 255 Law *

A–law, Including Even Bit Inversion

A–Law, No Even Bit Inversion

1Delayed Data Timing

Non–delayed Data Timing *

Normal Operation *

Digital Loopback

Analog Loopback

1Power Amp Enabled in PDN

Power Amp Disabled in PDN *

Ta ble 2 : Control Register Byte 2 Functions

Ta ble 3 : Coding Law Conventions.

m255 Law

MSB LSB

True A-law with

even bit inversion

MSB LSB

A-law without

even bit inversion

MSB LSB

VIN = +Full Scale100000001010101011111111

IN = 0V 1

VIN = -Full Scale000000000010101001111111

Note: The MSB is always the first PCM bit shifted in or out of COMBO IIG.

(*) State at power-on initialization (bit 4 = 0)

TS5070 - TS5071

9/32

This mode provides another stage of path verifica-

tion by enabling data written into the Receive PCM

Transmit time-slot at DX0 or DX1.

For A nalog Loopbac k a s well as for Digital Loop-

back PCM decoding continues and analog output

appe ars at VFRO. The ou tput can be disabled by

pro gramming "No Output" in the Receive Gain

INTERFACE LATCH DIRECT ION S

Immediately following power-on, all Interface

Latches assume they are inputs, and therefore all

IL pins are in a high impedance state . E ach IL pin

may be individually pr ogrammed as a logic input or

output by writing the appropriate instruction to the

LDR, see table 1 and 4. Bits L5-L0 must be set by

writing the specific instruction to the LDR with the

L bits in the second byte set as specified in table 4.

Unused interface latches should be programmed

as outputs. For the TS5071, L5 should al ways be

programmed as an out put.

(*) State at powe r-on initilization .

Note: L5 should be programmed as an output for the TS5071.

INT ERFACE L ATCH STATES

Interface Latches configured as outputs assume

the state determined by the appropriate data bit in

the 2-byte instruction wr itten to t he Latch Content

Latches configured as inputs will sense the state

applied by an external source, such as the Off-

Hook detect output of a SLIC. All bits of the ILR,

i.e. sensed inputs and the programmed state of

outputs, can be read back in the 2nd byte of a

READ from the ILR. It is recommended that, dur-

ing initialization, the state of IL pins to be config-

ured as outputs should first be programmed, fol-

lowed immediately by the Latch Direction

TIME-SLOT ASSIGNMENT

COMBO I IG can operate in either fixed time-slot or

time-slot assignment mode for selecting the Trans-

mit and Receiv e PCM time-slots. Following power-

on, the device is automatically in Non-Delayed Tim-

ing mode, in which the time-slot always begins with

the leading (r ising) edge of fr ame sync inputs FSX

and FS R. Time-Slot Ass ignment may only be used

with De layed Data t iming : see fig ure 6. FSX and

FSR may have any phase relationship with each

other in BCLK period increments.

Bit Number

76543210

L0 L1 L2 L3 L4 L5 X X

Table 4: Byte 2 Function of Latch Direction Register

LN Bit IL Direction

1Input *

Output

Bit Number Function

(note 1)

(note 2)

T4 3

T3 2

T2 1

T1 0

0X X XXXXX

Disable DX Outputs (transmit instruction) *

Disable DR Inputs (receive instruction) *

10Assign One Binary Coded Time-slot from 0–63

Assign One Binary Coded Time-slot from 0–63

Enable DX0 Output, Disable DX1 Output

(Transmit instruction)

Enable DR0 Input, Disable DR1 Input

(Receive Instruction)

11Assign One Binary Coded Time-slot from 0–63

Assign One Binary Coded Time-slot from 0–63

Enable DX1 Output, Disable DX0 Output

(Transmit instruction)

Enable DR1 Input, Disable DR0 Input

(Receive Instruction)

Ta ble 6 : By te 2 of Time-slot and Port Assignment Instructions

Bit Number

76543210

D0 D1 D2 D3 D4 D5 X X

Table 5: Interface Latch Data Bit Order

Notes:

1. The "PS" bit MUST always be set to 0 for the TS5071.

2. T5 is the MSB of the time-slot ass i gnm ent.

(*) State at power-on initialization

TS5070 - TS5071

10/32

Alternatively, the internal time-slot assignment

counters and comparators can be used t o access

any time-slot in a frame, using the frame sync inputs

as marker pulses for the beginning of transmit and

receive time-slot 0. In this mode, a frame may con-

sist of up to 64 time-slots of 8 bits each. A time-slot

is assigned by a 2-byte instruction as shown in table

1 and 6. The last 6 bits of the second byte indicate

th e se lected ti me -slot f rom 0-63 using straight bi-

nar y notati on. A new assignment becomes active

on the second frame f ollowing the end of the Chip

Select for the second control byte. The "EN" bit al-

lows the PCM inputs DR0/1 or outputs DX0/1 as ap-

propriate, to be enabled or disabled.

Time-Slot Assignment mode requires that the FSX

and FSR pulses must conform to the delayed timing

format shown in figure 6.

PORT SELECTION

On the TS5070 only, an additional capability is

av ailable : 2 Transm it seria l PCM po rts, DX0 and

DX1, and 2 receive serial PCM ports, DR0 and DR1,

are provided to enable two-way space switching to

be implemented. Port selections for transmit and

re ceive are made within t he appropriate time-slot

assignment instruction using the "PS" bit in the sec-

ond byte.

On the TS5071, only ports DX0 and DR0 are avail-

able, therefore the "PS" bit MUS T alway s be set t o

0 for these devices.

Table 6 shows the format for the second byte of

both transmit and receive time-slot and port assign-

ment instructions.

TRANSM IT GAIN INSTRUCT ION BYTE 2

The transmit gain can be programmed in 0.1 dB

steps by writing to the Transmit Gain Register as

defined in tables 1 and 7. This corresponds to a

range of 0 dBm0 levels at VFXI between 1.619

Vrms and 0. 087 V rms (eq uivalent to + 6. 4 dB m to

– 19.0 dBm in 600 Ω).

To calculate the binary code for byte 2 of this in-

struction for any desired input 0 dBm0 level in

Vrms, take the nearest integer to the decimal

number given by :

and convert to the binary equivalent. Some exam-

ples are given in table 7.

Bit Number 0dBm0 Test Leve at VFXI

7 6 5 4 3 2 1 0 In dBm (Into 600Ω) In Vrms (approx.)

00000000 No Output

0– 19

– 18.9 0.087

0.088

10111111 0 0.775

1+6.3

+6.4 1.60

1.62

Ta ble 7 : By te 2 of Transmit Gain Instruction s.

(*) State at power initialization

RECEIVE GAIN INSTRUCTION BYTE 2

The receive gain can be programmed in 0.1 dB

steps by writing to the Receive Gain Register as de-

fined in table 1 and 8. Note the following restriction

on output drive capability :

a) 0 dBm0 levels ≤ 8.1dBm at VFRO may be

driven into a load of ≥ 15 kΩ to GND,

b) 0 dBm0 levels ≤ 7.6dBm at VFRO may be

driven into a load of ≥ 600 Ω to GND,

c) 0 dBm levels ≤ 6.9dBm at VFRO may be driven

into a load of ≥ 300 Ω to GND .

To cal culate th e binary code for byte 2 of th is in-

struction for any desired output 0 dBm0 level in

Vrms, take the nearest integer to the decimal num-

ber given by :

d convert to the binary equivalent. Some exam-

ples are given in table 8.

200 X log10 (V/√6 ) + 191

200 X log10 (V/√6 ) + 174

TS5070 - TS5071

11/32

HYBRID BALANCE F ILTER

The Hybrid Balance Filter on COMBO IIG is a

programmable filter consisting of a second-order

Bi-Quad section, Hybal1, followed by a first-order

section, Hybal2, and a programmable attenuator.

Either of the filter sections can be bypassed if

only one is req uired to achieve good cancellation.

A selectable 180 degree inverting stage is in-

cluded to compensate for interface circuits which

also invert the transmit input relative to the re-

ceive output signal. The Bi-Quad is intended

mainly t o balance low frequency signals across a

transformer SLIC, and the first order section to

balance midrange to higher audio frequency sig-

nals. The attenuator can be programmed to com-

pensate for VFRO to VFXI echos in the range

of -2.5 to – 8.5 dB.

As a Bi-Quad, Hybal1 has a pair of low frequency

zeroes and a pair of complex conjugate poles.

When configuring the Bi-Quad, matching the

phase of the hybrid at low to midband frequencies

is most critical. Once the echo path is correctly

balanced in phase, the magnitude of the cancella-

tion signal c an be corrected by the progr ammable

attenuator.

The Bi- Qua d mode of Hyba l1 is most suitable for

balancing interfaces with transformers having high

inductance of 1.5 Henries or more. An alternative

confi guration f or smaller transformers is available

by converting Hybal1 to a s imple first-order section

with a single real low frequency pole and 0 Hz zero.

In this mode, the pole/zero frequency may be pro-

grammed.

Many line interfaces can be adequately balanced

by use of the Hybal1 section only, in which case

the Hybal2 filter should be de-selected to bypass

it.

Hybal2, the higher frequency f irst-order section, is

provided for balancing an electronic SLIC, and is

also helpful with a transformer SLIC in providing

additional phase correction for m id and high-band

frequencies, typically 1 kHz to 3.4 kHz. Such a

correction is particularly useful if the test balance

impedance includes a capacitor of 100 nF or less,

such as the loaded and non-loaded loop test net-

works in the United States. Independent place-

ment of the pole and zero location is provided.

Bit State Function

7 0 Disable Hybrid Balance Circuit Completely.

No internal cancellation is provided. *

1 Enable Hybrid Balance Cancellation Path

6 0 Phase of the internal cancellation signal assumes inverted phase of the echo

path from VFRO to VFXI.

1 Phase of the internal cancellation signal assumes no phase inversion in the line

interface.

5 0 Bypass Hybal 2 Filter Section

1 Enable Hybal 2 Filter Section

G4–G0 Attenuation Adjustment for the Magnitude of the Cancellation Signal. Range is

– 2.5 dB (00000) to – 8.5 dB (11000)

Ta ble 9 : Hybrid Balance Register 1 Byte 2 Instruction.

Notes:

1. Maximum level into 300Ω ; 2. Maximum level into 600Ω; 3. RL ≥15KΩ (*) State at power on initialization

(*) State at power on initialization

Setti ng = Please refer to software TS5077 2

Bit Number 0dBm0 Test Leve at VFR0

7 6 5 4 3 2 1 0 In dBm (Into 600Ω) In Vrms (approx.)

00000000 No Output

0– 17.3

– 17.2 0.106

0.107

10101110 0 0.775

1 1 1 1 0 0 1 1 + 6.9 (note 1) 1.71

1 1 1 1 1 0 1 0 + 7.6 (note 2) 1.86

1 1 1 1 1 1 1 1 + 8.1 (note 3) 1.07

Ta ble 8 : By te 2 of Receive Gain Instructions.

TS5070 - TS5071

12/32

Figure 1 shows a simplified diagram of the local

echo path for a typical application with a trans-

former interface. The magnitude and phase of t he

local echo signal, measured at VFXI , are a function

of the termination impedance ZT, the line trans-

former and the impedance of the 2 W loop, ZL. If the

impedance reflected back into the transformer pri-

mary is expressed as ZL’ then the echo path t rans-

fer function from VFRO to VFXI is :

H(W) = ZL’ /(ZT + ZL’) (1)

Figure 1: Simplified Diagram of Hybrid Balance Circuit

PROGR AMM ING THE FI L TER

On initial power-up the Hybrid Balance filter is dis-

abled. Before the hybrid balance filter can be pro-

grammed it is necessary to design the transformer

and termination impedance in order to meet system

2 W input return loss specifications, which are nor-

mally measured against a fixed test impedance

(600 or 900 Ω in most countries). Only then can the

echo path be modeled and the hybrid balance f ilter

pr ogra mmed. Hyb rid balan cing is also measured

against a fixed test imp edance, specified by each

national Telecom administration to provide ade-

quat e cont rol of talker an d listener echo o ve r th e

majority of their network connections. This test im-

pedance is ZL in figure 1. The echo signal and the

degree of transhybrid loss obtained by the pro-

grammable filter must be measured from the PCM

digital input DR0, to the PCM digital output DX0,

either by digital test signal analysis or by conversion

back to analog by a PCM CODEC /Filter.

Three registers must be programmed in COMBO

IIG to fully configure the Hybrid Balance Filter as

follows :

invert/non-invert cancellation signal;

select/de-select Hybal2 filter section;

attenuator setting.

set Hybal1 to Bi-Quad or 1st order;

program pole and zero frequency.

prog ram zero frequen cy in Hy bal2 filt er;

settings = Please refer to software

TS5077-2.

Standar d filter design techniques may be used to

model the echo path (see equation (1)) and design

a matching hybrid balance filter configuration. Alter-

natively, the f requency response of the echo path

can be measured and the hybrid balance filter pro-

grammed to replicate it.

An Hybrid Balance filter design guide and soft-

ware optimization program are available under li-

cense from SGS-THOMSON Micr oelectr onics (or-

der TS5077-2).

Bit Number Function

76543210

0 0 0 0 0 0 0 0 By Pass Hybal 1

Filter

X X X X X X X X Pole/zero Setting

Table 10: Hybrid Balance Register 2 Byte 2 in-

structions

TS5070 - TS5071

13/32

APPLICAT ION IN FOR MATION

Figure 2 shows a typic al applic ation of the T S5070

togeth er with a transformer SLIC.

The design of the trans former is greatly simplified

due to the on-chip hybrid balance cancellation filter.

Only one single secondary winding is required (see

appl icatio n note AN.091 - Designing a subscriber

line ca rd modul e using the TS5070/COMBO IIG).

Figures 3 and 4 show an arrangement with SGS-

Thomson monolithic SLICS.

POW E R SUPPLIES

While the pins of the TS5070 and TS5071/COMBO

IIG devices are well protected against electrical

misuse, it is recommended that the standard

CMOS practice of applying GND t o the device be-

fore any other connections are made should always

be followed. In applications where the printed circuit

card may be plugged into a hot socket with power

and clocks already present, an extra long ground

pin on the connector should be used and a Schottky

diode connected between VSS and GND. To m ini-

mize noise sources all ground connections to each

device should meet at a common point as close as

possible to the GND pin in order t o prevent the in-

teraction of ground return currents flowing through

a common bu s impeda nce. Power supply decou-

pling capacitors of 0.1 µF should be connected from

this common device ground point t o VCC and VSS

as close to the device pins as possible. VCC and VSS

should also be decoupled with low effective series

resis-tance capacitors of at least 10 µF located near

the card edge connector.

TS5070 - TS5071

14/32

Figure 2: Transformer SLIC + COMBO IIG.

TS5070 - TS5071

15/32

Figure 4: Interface with L3092 + L3000 Silicon SLIC.

L3092

L3000

TS5070 - TS5071

16/32

ELECTRICAL OPERATING CHARACTERISTICS

Unless otherwise not ed, lim its in BOLD characters

are guarant eed for VCC = + 5 V ± 5 % ; VSS = – 5

V ± 5 %. TA = -40 °C to 85 °C by correlation with

100% electrical testing at TA = 25 °C. All other limits

are assured by correlation with other production

test s a nd/or pro duct desig n and characterisation.

All signals referenced to GND. Typicals specified at

VCC = + 5 V, VSS = − 5 V, TA = 25 °C.

DIGITAL INTERFACE

Symbol Parameter Min. Typ. Max. Unit

VIL Input Low Voltage All Digital Inputs (DC measurement) 0.7 V

VIH Input High Voltage All Digital Inputs (DC measurement) 2.0 V

VOL Output Low Voltage

DX0 and DX1, TSX0, TSX1 and CO, IL = 3.2mA

All Other Digital Outputs, IL = 1mA 0.4 V

VOH Output High Voltage DX0 and DX1 and CO, IL = -3.2mA

All other digital outputs except TSX, IL = -1mA

All Digital Outputs, IL = -100µA2.4

VCC-0.5 V

IIL Input Low Current all Digital Inputs (GND < VIN < VIL)-10 10 µA

IIH Input High Current all Digital Inputs Except MR (VIH < VIN < VCC)-10 10 µA

IIH Input High Current on MR -10 100 µA

IOZ Output Current in High Impedance State (TRI-STATE)

DX0 and DX1, CO and CI/O (as an input) IL5-IL0 as inputs

(GND < VO < VCC)

-10 10 µA

ANALOG IN TERFACE

Symbol Parameter Min. Typ. Max. Unit

IVFXI Input Current VFXI (-3.3V < VFXI < 3.3V) -10 10 µA

RVFXI Input Resistance VFXI (-3.3V < VFXI < 3.3V) 390 620 kΩ

VOSXInput offset voltage at VFXI

0dBm0 = -19dBm

0dBm0 = +6.4dBm 10

200 mV

RLVFRO Load Resistance at VFRO

0dBm0 = 8.1dBm

0dBm0 = 7.6dBm

0dBm0 = 6.9dBm

600

300

kΩ

Ω

CLVFRO Load Capacitance CLVFRO from VFRO to GND 200 pF

ROVFRO Output Resistance VFRO (steady zero PCM code applied to DR0 or

DR1) 13Ω

OSR Output Offset Voltage at VFRO (alternating ±zero PCM code applied

to DR0 or DR1, 0dBm0 = 8.1dBm) -200 200 mV

TS5070 - TS5071

17/32

TIMING SPEC IFIC ATIONS

Unless otherwise noted, limits in BOLD characters are

guaranteed for VCC = + 5 V ± 5 %; VSS = -5V ± 5 %.

TA = -40 °C to 85 °C by correlation with 100 % elec-

trical testing at TA = 25 °C. All other limits are as-

sured by correlation with other production tests

and/ or product desi gn and cha racteri zatio n. All sig -

nals referenced to GND. Typicals specified at

VCC = + 5 V, VSS = -5 V, TA = 25 °C. All timing pa-

rameters are measured at VOH = 2.0 V and VOL = 0.7 V.

See Definitions and Timing Conventions section

for test methods inform ation.

ELECTRICA L OPERATI NG CHARACT ER ISTICS (continued)

POW E R DIS SI PATION

Symbol Parameter Min. Typ. Max. Unit

ICC0 Power Down Current (CCLK, CI/O, CI = 0.4V, CS = 2.4V)

Interface Latches set as Outputs with no load

All over Inputs active, Power Amp Disabled

0.3 1.5 mA

-ISS0 Power Down Current (as above) 0.1 0.3 mA

ICC1 Power Up Current (CCLK, CI/O, CI = 0.4V, CS = 2.4V)

No Load on Power Amp

Interface Latches set as Outputs with no Load 7 11 mA

-ISS1 Power Up Current (as above) 7 11 mA

ICC2 Power Down Current with Power Amp Enabled 2 4mA

-ISS2 Power Down Current with Power Amp Enabled 2 4mA

MASTER CLOCK TIMING

Symbol Parameter Min. Typ. Max. Unit

fMCLK Frequency of MCLK

(selection of frequency is programmable, see table 2) 512

1.536

1.544

2.048

4.096

kHz

MHz

tWMH Period of MCLK High (measured from VIH to VIH, see note 1) 80 ns

tWML Period of MCLK Low (measured from VIL to VIL, see note 1 ) 80 ns

tRM Rise Time of MCLK (measured from VIL or VIH)30ns

FM Fall Time of MCLK (measured from VIH to VIL)30

HBM Hold Time, BCLK Low to MCLK High (TS5070 only) 50 ns

tWFL Period of FSX or FSR Low (Measured from VIL to VIL) 1 (*)

(*) MCLK period

TS5070 - TS5071

18/32

TIMING SPEC IFIC AT ION S (continued)

PCM IN TERFACE TIM ING

Symbol Parameter Min. Typ. Max. Unit

fBCLK Frequency of BCLK (may vary from 64KHz to 4.096MHz in 8KHz

increments, TS5070 only) 64 4096 kHz

tWBH Period of BCLK High (measured from VIH to VIH)80 ns

tWBL Period of BCLK Low (measured from VIL to VIL)80 ns

tRB Rise Time of BCLK (measured from VIL to VIH)30ns

FB Fall Time of BCLK (measured from VIH to VIL)30ns

HBF Hold Time, BCLK Low to FSX/R High or Low 30 ns

tSFB Setup Time FSX/R High to BCLK Low 30 ns

tDBD Delay Time, BCLK High to Data Valid (load = 100pF plus 2 LSTTL

loads) 80 ns

tDBZ Delay Time from BCLK8 Low to Dx Disabled (if FSx already low);

FSx Low to Dx Disabled (if BCLK8 low);

BCLK9 High to Dx Disabled (if FSx still high) 15 80 ns

tDBT Delay Time from BCLK and FSx Both High to TSx Low (Load = 100pF

plus 2 LSTTL loads) 60 ns

tZBT Delay Time from BCLK8 low to TSx Disabled (if FSx already low);

FSx Low to TSx Disabled (if BCLK8 low);

BCLK9 High to TSx Disabled (if FSx still high);

15 60 ns

tDFD Delay Time, FSx High to Data Valid (load = 100pF plus 2 LSTTL

loads, applies if FSx rises later than BCLK rising edge in non-

delayed data mode only)

80 ns

tSDB Setup Time, DR 0/1 Valid to BCLK Low 30 ns

tHBD Hold Time, BCLK Low to DR0/1 Invalid 20 ns

Figure 5: Non Delayed Data Timing (s hor t frame mode)

TS5070 - TS5071

19/32

Figure 6: Delayed Data Timing (short frame mode)

SERIAL CONTRO L PORT TIMING

Symbol Parameter Min. Typ. Max. Unit

fCCLK Frequency of CCLK 2.048 MHz

tWCH Period of CCLK High (measured from VIH to VIH)160 ns

tWCL Period of CCLK Low (measured from VIL to VIL)160 ns

tRC Rise Time of CCLK (measured from VIL to VIH)50ns

FC Fall Time of CCLK (measured from VIH to VIL)50ns

HCS Hold Time, CCLK Low to CS Low (CCLK1) 10 ns

tHSC Hold Time, CCLK Low to CS High (CCLK8) 100 ns

tSSC Setup Time, CS Transition to CCLK Low 70 ns

tSSCO Setup Time, CS Transition to CCLK High (to insure CO is not

enabled for single byte) 50 ns

tSDC Setup Time, CI (CI/O) Data in to CCLK low 50 ns

tHCD Hold Time, CCLK Low to CI (CI/O) Invalid 50 ns

tDCD Delay Time, CCLK High to CO (CI/O) Data Out Valid

(load = 100 pF plus 2 LSTTL loads) 80 ns

tDSD Delay Time, CS Low to CO (CI/O) Valid

(applies only if separate CS used for byte 2) 80 ns

tDDZ Delay Time, CS or CCLK9 High to CO (CI/O) High Impedance

(applies to earlier of CS high or CCLK9 high) 15 80 ns

INTERFACE LATCH TIMING

Symbol Parameter Min. Typ. Max. Unit

tSLC Setup Time, IL Valid to CCLK 8 of Byte 1 Low. IL as Input 100 ns

tHCL Hold Time, IL Valid from CCLK 8 of Byte 1 Low. IL as Input 50 ns

tDCL Delay Time, CCLK 8 of Byte 2 Low to IL. CL = 50 pF. IL as Output 200 ns

MAST ER RESET PI N

Symbol Parameter Min. Typ. Max. Unit

tWMR Duration of Master Reset High 1 µs

TS5070 - TS5071

20/32

Figure 7: Control Por t Timing

TS5070 - TS5071

21/32

TRANSMISS ION CHARAC TERISTI CS

Unless otherwise noted, limits printed in BOLD

characters are guaranteed for VCC = + 5 V ± 5 % ;

VSS = – 5 V ± 5 %, TA =-40 °C to 85 °C by correlation

with 100 % electrical testing at T A = 25 °C (-40 °C

to 8 5 °C for TS5070-X and TS5071-X).

f = 1 031.2 5 Hz, VFXI = 0 dBm0, DR0 or DR1 = 0

dBm0 PCM code, Hybrid Balance filter disabled. All

other limits are assur ed by correlation with other

production tests and/or product design and char-

acter ization. All signals referenced t o GND. dBm

levels are into 600 ohms. Typicals specified at

VCC = + 5 V, VSS = -5 V, TA = 25 °C.

AMPLITUDE R ESPO NSE

Symbol Parameter Min. Typ. Max. Unit

Absolute levels

The nominal 0 dBm 0 levels are :

VFXI 0 dB Tx Gain

25.4 dB Tx Gain

VFRO 0 dB Rx Attenuation (RL ≥ 15 kΩ)

0.5 dB Rx Attenuation (RL ≥ 600 Ω)

1.2 dB Rx Attenuation (RL ≥ 300 Ω)

25.4 dB Rx Attenuation

1.618

86.9

1.968

1.858

1.714

105.7

Vrms

mVrms

Vrms

mVrms

Maximum Overload

The nominal overload levels are :

A-law

VFXI 0 dB Tx Gain

25.4 dB Tx Gain

VFRO 0 dB Rx Attenuation (RL ≥ 15 kΩ)

0.5 dB Rx Attenuation (RL ≥ 300 Ω)

1.2 dB Rx Attenuation (RL ≥ 300 Ω)

25.4 dB Rx Attenuation

µ-law

VFXI 0 dB Tx Gain

25.4 dB Tx Gain

VFRO 0 dB Rx Attenuation (RL ≥ 15 kΩ)

0.5 dB Rx Attenuation (RL ≥ 600 Ω)

1.2 dB Rx Attenuation (RL ≥ 300 Ω)

25.4 dB Rx Attenuation

2.323

124.8

2.825

2.667

2.461

151.7

2.332

125.2

2.836

2.677

2.470

152.3

Vrms

mVrms

Vrms

mVrms

Vrms

mVrms

Vrms

mVrms

GXA

Transmit Gain Absolute Accurary

Transmit Gain Programmed for 0 dBm0 = 6.4 dBm, A-law

Measure Deviation of Digital Code from Ideal 0 dBm0 PCM Code

at DX0/1, f = 1031.25 Hz

TA = 25 °C, VCC = 5 V, VSS = – 5 V – 0.15 0.15 dB

GXAG

Transmit gain Variation with Programmed Gain

Programmed level from

-12.6dBm ≤ 0dBm ≤ 6.4dBm

Programmed level from

-19dBm ≤ 0dBm ≤ 12.7dBm

Note: ±0.1dB min/max is available as a selected part

Calculate the Deviation from the Programmed Gain Relative to

GXA

i.e., GXAG = Gactual – Gprog – GXA

TA = 25 °C, VCC = 5 V, VSS = – 5 V

– 0.1

– 0.3

0.1

0.3

TS5070 - TS5071

22/32

AMPLITUDE R ESPO NSE (continued)

Symbol Parameter Min. Typ. Max. Unit

GXAF Transmit Gain Variation with Frequency

Relative to 1031.25 Hz (note 2)

-19 dBm < o dBm0 < 6.4 dBm

DR0 (or DR1) = 0 dBm0 Code

f = 60Hz

f = 200 Hz

f = 300 Hz to 3000 Hz

f = 3400 Hz

f = 4000 Hz

f > 4600 Hz Measure Response at Alias Frequency from 0 kHz to 4 kHz

0 dBm0 = 6.4 dBm

VFXI = -4 dBm0 (note2)

f = 62.5 Hz

f = 203.125 Hz

f = 2093.750 Hz

f = 2984.375 Hz

f = 3296.875 Hz

f = 3406.250 Hz

f = 3984.375 Hz

f = 5250 Hz, Measure 2750 Hz

f = 11750Hz, Measure 3750 Hz

f = 49750 Hz, Measure 1750 Hz

-1.8

-0.15

-0.7

-1.7

-0.15

-0.74

-26

-0.1

0.15

-14

-32

GXAT Transmit Gain Variation with Temperature

Measured Relative to GXA, VCC = 5V, VSS = -5V -19dBm < 0dBm < 6.4dBm -0.1 0.1 dB

GXAV Transmit Gain Variation with Supply

VCC = 5V ± 5%, VSS = -5V ± 5%

Measured Relative to GXA

TA = 25 °C, o dBm0 = 6.4dBm -0.05 0.05 dB

GXAL Transmit Gain Variation with Signal Level

Sinusoidal Test Method, Reference Level = 0 dBm0

VFXI = -40 dBm0 to + 3 dBm0

VFXI = -50 dBm0 to -40 dBm0

VFXI = -55 dBm0 to -50 dBm0

-0.2

-0.4

-1.2

0.2

0.4

1.2

GRA Receive Gain Absolute Accuracy

0 dBm0 = 8.1 dBm, A-law

Apply 0 dBm0 PCM Code to DR0 or DR1 Measure VFRO, f =1015.625Hz

TA = 25 °C, VCC = 5V, VSS = -5V -0.15 0.15 dB

GRAG Receive Gain Variation with Programmed Gain

Programmed level from

-10.9dBm ≤ 0dBm ≤ 8.1dBm

Programmed level from

-17.3dBm ≤ 0dBm ≤ -11dBm

Note: ±0.1dB min/max is available as a selected part

Calculate the Deviation from the Programmed Gain Relative to GRA

I.e. GRAG = Gactual - Gprog - GRA TA = 25°C, VCC = 5V, VSS = -5V

-0.1

-0.3

0.1

0.3

-24.9

-0.1

0.15

-13.5

-32

TS5070 - TS5071

23/32

AMPLITUDE RESPONSE (continued)

Symbol Parameter Min. Typ. Max. Unit

GRAT Receive Gain Variation with Temperature

Measure Relative to GRA

VCC = 5V, VSS = -5V -17dBm < 0dBm0 < 8.1dBm -0.1 0.1 dB

GRAV Receive Gain Variation with Supply

Measured Relative to GRA

VCC = 5V ± 5%, VSS = -5V ± 5%

TA = 25°C, 0dBm 0 = 8.1 dBm -0.05 0.05 dB

GRAF Receive Gain Variation with Frequency

Relative to 1015.625 Hz, (note 2)

DR0 or DR1 = 0 dBm0 Code

-17.3dBm < 0 dBm0 < 8.1dBm

f = 200Hz

f = 300Hz to 3000Hz

f = 3400Hz

f = 4000Hz

GR = 0dBm0 = 8.1dBm

DR0 = -4dBm0

Relative to 1015.625 (note 2)

f = 296.875 Hz

f = 1906.250Hz

f = 2812.500Hz

f = 2984.375Hz

f = 3406.250Hz

f = 3984.375Hz

-0.25

-0.15

-0.7

-0.15

-0.74

0.15

-14

0.15

-13.5

GRAL Receive Gain Variation with Signal Level

Sinusoidal Test Method Reference Level = 0dBm0

DR0 = -40dBm0 to +3dBm0

DR0 = -50dBm0 to -40dBm0

DR0 = -55dBm0 to -50dBm0

DR0 = 3.1dBm0

RL = 600Ω, 0dBm0 = 7.6dBm

RL = 300Ω, 0dBm0 = 6.9dBm

-0.2

-0.4

-1.2

-0.2

0.2

0.4

1.2

0.2

TS5070 - TS5071

24/32

ENVELOPE DELAY DISTORTION WITH FREQUENCY

Symbol Parameter Min. Typ. Max. Unit

DXA Tx Delay Absolute

f = 1600 Hz 315 µs

DXR Tx Delay, Relative to DXA

f = 500 – 600 Hz

f = 600 – 800 Hz

f = 800 – 1000 Hz

f = 1000 – 1600 Hz

f = 1600 – 2600 Hz

f = 2600 – 2800 Hz

f = 2800 – 3000 Hz

220

145

105

155

µs

DRA Rx Delay, Absolute

f = 1600 Hz 200 µs

DRR Rx Delay, Relative to DRA

f = 500 – 1000 Hz

f = 1000 – 1600 Hz

f = 1600 – 2600 Hz

f = 2600 – 2800 Hz

f = 2800 – 3000 Hz

– 40

– 30 90

125

175

µs

TS5070 - TS5071

25/32

NOISE

Symbol Parameter Min. Typ. Max. Unit

NXC Transmit Noise, C Message Weighted

µ-law Selected (note 3)

0 dBm0 = 6.4dBm

12 15 dBrnC0

NXP Transmit Noise, Psophometric Weighted

A-law Selected (note 3)

0 dBm0 = 6.4dBm

-74 -67 dBm0p

NRC Receive Noise, C Message Weighted

µ-law Selected

PCM code is alternating positive and negative zero

8 11 dBrnC0

NRP Receive Noise, Psophometric Weighted

A-law Selected

PCM Code Equals Positive Zero

-82 -79 dBm0p

NRS Noise, Single Frequency

f = 0Hz to 100kHz, Loop Around Measurement VFXI = 0Vrms -53 dBm0

PPSRX Positive Power Supply Rejection Transmit

VCC = 5VDC + 100mVrms

f = 0Hz to 4000Hz (note 4)

f = 4kHz to 50kHz 30

30 dBp

dBp

NPSRX Negative Power Supply Rejection Transmit

VSS = -5VDC + 100mVrms

f = 0Hz to 4000Hz (note 4)

f = 4kHz to 50kHz 30

30 dBp

dBp

PPSRR Positive Power Supply Rejection Receive

PCM Code Equals Positive Zero

VCC = 5VDC + 100mVrms

Measure VFR0

f = 0Hz to 4000Hz

f = 4kHz to 25kHz

f = 25kHz to 50kHz

dBp

NPSRR Negative Power Supply Rejection Receive

PCM Code Equals Positive Zero

VSS = -5VDC + 100mVrms

Measure VFR0

f = 0Hz to 4000Hz

f = 4kHz to 25kHz

f = 25kHz to 50kHz

dBp

SOS Spurious Out-of Band Signals at the Channel Output

0dBm0 300Hz to 3400Hz input PCM code applied at DR0 (DR1)

Relative to f = 1062.5Hz

4600Hz to 7600Hz

7600Hz to 8400Hz

8400Hz to 50000Hz

-30

-40

-30

TS5070 - TS5071

26/32

DISTORTION

Symbol Parameter Min. Typ. Max. Unit

STDX Signal to Total Distortion Transmit

Sinusoidal Test Method

Half Channel

Level = 3dBm0

Level = -30dBm0 to 0dBm0

Level = -40dBm0

Level = -45dBm0

dBp

STDR Signal to Total Distortion Receive

Sinusoidal Test Method

Half Channel

Level = 3dBm0

Level = -30dBm0 to 0dBm0

Level = -40dBm0

Level = -45dBm0

dBp

SFDX Single Frequency Distortion Transmit -46 dB

SFDR Single Frequency Distortion Receive -46 dB

IMD Intermodulation Distortion Transmit or Receive

Two Frequencies in the Range 300Hz to 3400Hz -41 dB

CROSSTALK

Symbol Parameter Min. Typ. Max. Unit

CTX-R Transmit to Receive Crosstalk,

0dBm0 Transmit Level

f = 300 to 3400Hz

DR = Idle PCM Code

-90 -75 dB

CTR-X Receive to Transmit Crosstalk,

0dBm0 Receive Level

f = 300 to 3400Hz (note 4)

-90 -70 dB

Notes:

1. Applies onl y to MCLK frequencies ≥ 1.536 MHz. At 512 kHz A 50:50 ± 2 % duty cycle m ust be used.

2. A multi-tone test technique is used (peak/rms ≤ 9.5 dB).

3. Measured by grounded input at VFXI.

4. PPSRX, NPSRX and CTR-X are measured with a – 50 dBm0 activation signal applied to VFXI.

A signal is Valid if it is above VIH or below VIL and invalid if it is between VIL and V IH. For the purpose of the specification the following conditions

appl y :

a) All input signals are defined as VIL = 0.4 V, VIH = 2.7 V, tR < 10 ns, tF 10 ns

b) tR is measured from VIL to VIH, tF is measured from VIH to VIL

c) Del ay Times are measur ed from the input signal Valid to the clock input invalid

d) Setup Times are measured from the data input Valid to the clock input invalid

e) Hold Times are measured from the clock signal Valid to the data input invalid

f) Puls e widths are m easur ed from VIL to VIL or from VIH to VIH

TS5070 - TS5071

27/32

DEFINITIONS AND TIMING CONVENTIONS

DEFINITIONS

VIH VIH is the D.C. input level above w hich an input level is guaranteed to appear as a logical one.

This parameter is to be measured by performing a functional test at reduced c lock speeds and

nominal timing (i.e. not minimum setup and hold times or output strobes), with the high level of

all driving signals set to VIH and maximum supply voltages applied to the device.

VIL VIL is the D.C. input level below which an input level is guaranteed to appear as a logical zero

the device. This parameter is measured in the same manner as VIH but with all driving signal

low levels set to VIL and minimum supply voltage applied to the device.

VOH VOH is the minimmum D.C. output level to which an output placed in a logical one state will

converge when loaded at the maximum specified load current.

VOL VOL is the maximum D.C. output level to which an output placed in a logical zero state will

converge when loaded at the maximum specified load current.

Threshold Region

Valid Signal The threshold region is the range of input voltages between VIL and VIH.

A signal is Valid if it is in one of the valid logic states. (i.e. above VIH or below VIL). In timing

specifications, a signal is deemed valid at the instant it enters a valid state.

Invalid signal A signal is invalid if it is not in a valid logic state, i.e., when it is in the threshold region between

VIL and VIH. In timing specifications, a signal is deemed Invalid at the instant it enters the

threshold region.

TIMING CONVENTIONS

For the purpose of this timing specifications the following conventions apply :

Input Signals All input signals may be characterized as : VL = 0.4 V, VH = 2.4 V, tR < 10 ns, tF < 10 ns.

Period The period of the clock signal is designated as tPxx where xx represents the m nem onic of the

clock signal being specified.

Rise Time Rise times are designated as tRyy, where yy represents a mnemonic of the signal whose rise

time is being specified, tRyy is measured from VIL to VIH.

Fall Time Fall times are designated as tFyy, where yy represents a mnemonic of the signal whose fall

time is being specified, tFyy is measured from VIH to VIL.

Pulse Width High The high pulse width is designated as tWzzH, where zz represents the mnemonic of the input

or output signal whose pulse width is being specified. High pulse width are measured from V IH

to VIH.

Pulse Width Low The low pulse is designated as tWzzL’ where zz represents the mnemonic of the input or output

signal whose pulse width is being specified. Low pulse width are measured from VIL to VIL.

Setup Time Setup times are designated as tSww xx where ww represents the mnemonic of the input signal

whose setup time is being specified relative to a clock or strobe input represented by mnemonic

xx. Setup times are measured from the ww Valid to xx Invalid.

Hold Time Hold times are designated as THww xx where ww represents the mnemonic of the input signal

whose hold time is being specified relative to a clock or strobe input represented by the

mnemonic xx. Hold times are measured from xx Valid to ww Invalid

Delay Time Delay times are designated as TDxxyy [H/L], where xx represents the mnemonic of the input

reference signal and yy represents the mnemonic of the output signal whose timing is being

specified relative to xx. The mnemonic may optionally be terminated by an H or L to specify the

high going or low going transition of the output signal. Maximum delay times are measured from

xx Valid to yy Valid. Minimum delay times are measured from xx Valid to yy Invalid. This

parameter is tested under the load conditions specified in the Conditions column of the Timing

Specifications section of this datasheet.

TS5070 - TS5071

28/32

COMBO II SALES TYPE LIST

Ordering

Number Electrical

description Package Marking Packing

TS5070FN Stdandard

Selection

Datasheet

December

1997

PLCC28 TS5070FN Tubes

TS5070FNTR PLCC28 TS5070FN Tape

and reel

TS5071N PDIP20 TS5071N Tubes

TSW5070FN Relaxed

selection

(Gxa, Gra,

Grag, Gxag)

PLCC28 TS5070FN Tubes Param Page Conditions Min Max Unit

TSW5070FNTR PLCC28 TS5070FN Tape

and reel Gxa 22 -- -0.2 0.2 dB

TSW5071N PDIP20 TS5071N Tubes Gxag 22 -6.3dBm<0dbm0<6.4dBm -0.1 0.1 dB

-12.7dBm<0dBm0<-6.4dBm -0.2 0.2 dB

-19dBm<0dBm0<-12.8dBm -0.5 0.5 dB

Gra 23 -- -0.2 0.2 dB

Grag 23 -4.6dBm<0dBm0<8.1dBm -0.1 0.1 dB

-11dBm<0dBm0<-4.7dBm -0.2 0.2 dB

-17.3dBm<0dBm0<-11.1dBm -0.5 0.5 dB

TSP5070FN Special

selection

for

Grag/Gxag

PLCC28 TS5070FN Tubes Param Page Conditions Min Max Unit

TSP5070FNTR PLCC28 TS5070FN Tape

and reel Gxag 22 all programmed gains -0.1 0.1 dB

TSP5071N PDIP20 TS5071N Tubes Grag 23 all programmed gains -0.1 0.1 dB

TS5070 - TS5071

29/32

PLCC28

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 12.32 12.57 0.485 0.495

B 11.43 11.58 0.450 0.456

D 4.2 4.57 0.165 0.180

D1 2.29 3.04 0.090 0.120

D2 0.51 0.020

E 9.91 10.92 0.390 0.430

e 1.27 0.050

e3 7.62 0.300

F 0.46 0.018

F1 0.71 0.028

G 0.101 0.004

M 1.24 0.049

M1 1.143 0.045

OUTLINE AND

MECHANICAL DATA

TS5070 - TS5071

30/32

DIP20

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.254 0.010

B 1.39 1.65 0.055 0.065

b 0.45 0.018

b1 0.25 0.010

D 25.4 1.000

E 8.5 0.335

e 2.54 0.100

e3 22.86 0.900

F 7.1 0.280

I 3.93 0.155

L 3.3 0.130

Z 1.34 0.053

OUTLINE AND

MECHANICAL DATA

TS5070 - TS5071

31/32

Infor mation furni shed is bel ieved to be ac curate and reliabl e. Howev er, STMicroel ectr onics assum es no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is

grante d by i mplication or oth erwise under a ny patent or patent right s of STMicro electronics . Spec ifications ment ioned in this publi cation are

subj ect to change without notic e. This public ation supers edes and rep laces all informat ion p rev iously suppl ied. STMic roelectron ics pro ducts

are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a regist ered trademark of STMicroelect roni cs.

All other names are the property of their respective owners

STMicroelectronics GROUP OF COMPANIES

Aust ral i a – Belgium - Braz i l - Canada - China – Czec h Republ i c - Finland - Fr ance - Germ any - Hong Kong - India - Israe l - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States

www.st.com

TS5070 - TS5071

32/32