ANALOG DEVICES CMOS Dual 8-Bit Buffered Multiplying DAC AD7528 FEATURES On-Chip Latches for Both DACs +5V to + 15V Operation DACs Matched to 1% Four Quadrant Multiplication TIL/CMOS Compatible Latch Free (Protection Schottkys not Required) APPLICATIONS Digital Control of: Gain/Attenuation Filter Parameters Stereo Audio Circuits X-Y Graphics GENERAL DESCRIPTION The AD7528 is a monolithic dual 8-bit digital/analog converter featuring excellent DAC-to-DAC matching. It is available in skinny 0.3 wide 20-pin DIPs and in 20-terminal surface mount packages. Separate on-chip latches are provided for each DAC to allow easy microprocessor interface. Data is transferred into either of the two DAC data latches via a common 8-bit TTL/CMOS compatible input port. Control input DAC A/DAC B determines which DAC is to be loaded. The AD7528s load cycle is similar to the write cycle of a random access memory and the device is bus compatible with most 8-bit microprocessors, including 6800, 8080, 8085, Z80. The device operates from a +5V to +15V power supply, dis- sipating only 20mW of power. Both DACs offer excellent four quadrant multiplication charac- teristics with a separate reference input and feedback resistor for each DAC. This is an abridged data sheet. To obtain the most recent version or complete data sheet, call our fax retrieval system at 1-800-446-6212. REV. A FUNCTIONAL BLOCK DIAGRAM Yoo @ Bo DATA e INPUT INPUTS BUFFER very aa) pac BoE tj cs J Loic wr 16 OGND: 6 PRODUCT HIGHLIGHTS 1. DAC to DAC matching: since both of the AD7528 DACs are fabricated at the same time on the same chip, precise matching and tracking between DAC A and DAC B is inherent. The AD7528s matched CMOS DACs make a whole new range of applications circuits possible, particularly in the audio, graphics and process contro! areas. 2. Small package size: combining the inputs to the on-chip DAC latches into a common data bus and adding a DAC A/ -DAC B select line has allowed the AD7528 to be packaged in either a small 20-pin DIP, SOIC, PLCC or LCCC. DIGITAL-TO-ANALOG CONVERTERS 3-163AD7528 SPECIFICATIONS (Vaer A = Veep B = +10; OUT A = OUT B = OV unless otherwise specified) Yoo = +5 Voo = +1SV Paremeter Version! Ta= +28C Toes Tom Ta= +28 Testes Toe Units Test Canditions/Commanta STATICPERPORMANCE | Resolution Alt 8 8 a Bia Relative Accuracy JAS 1 tl x) 21 LSB max This inan Endpoint Linearity Specification K,B,T th 2% 2" % LSB max . L,c,U th 2% t" 2% LSB max Differential Nonlinearity All +1 +1 +1 +1 LSB max All Grades Guaranteed Mamotonic Over Full Operating Temperature Range Gain Error JAS 24 26 4 3 LSB max Measured Using Internal RFB A and RFBB. K,B,T 2 x4 22 23 LSB max Both DAC Latches Loaded with 12111111. L,,U +1 +3 +1 tl LSB max Gain Error is Adjusteble Using Circuits of Figures 4and 5. Gain Temperature Coefficient* ASGain/A Temperature All + 0.007 0.007 = 0.0035 20.0035 C max Output Leakage Current OUT A (Pin 2) All = 2400 50 +200 nAmax DAC Latches Loaded with 00000000. OUT B(Pin 20) AL +50 2400 250 2200 nA max Input Resistance (Vper A, Var B) All 8 8 8 & kN min Input Resistance TC = 30ppav"C, Typical Is 1s 1S 18 kN max Input Resistance is 11k Veer A/Vane B Input Resistance Match All a1 #1 +) +1 max DIGITAL INPUTS? Input High Voltage Vin All 24 24 13,5 13.5 Vmin Input Low Voltage Vin All Os 08 1S 1S Vmax Input Current lew All +1 +10 +1 +10 wA max Vin = Vor Vpp Input Capecitance DBO-DB7 All 10 10 10 i pF max WR,CS, DACA/DACB All 15 15 5 15 pF max SWITCHING CHARACTERISTICS* See Timing Diagram Chip Select to Write Set Up Time les All 200 230 ao 60 nsmin Chip Select to Write Hold Time low All 20 30 10 15 nsmin DAC Select to Write Set Up Time tas All 200 230 o ) asmin DAC Select to Write Hold Time tan All 20 Ei 15 asmin Data Valid to Write Set Up Time tos All 110 130 30 40 nsmin Dats Valid to Write Hold Time tbH All 0 9 Q 0 asmin Write Pulse Width twr All 180 200 6 80. nsmin POWER SUPPLY See Figure 3 Ipp All 2 2 2 2 mA max AIL Digital Inputs V1.0 Vin All 100 500 100 $00 vA max AU Digital Inputs OV of Vop AC PERFORMANCE CHARACTERISTICS: Pc ccd ie ances as output Amplites) Vpo = +5 Von = +15V Parameter Version Ta = +25 Tos Tes Ta= +25 Taiy Tues Unis Test Conditioes/Commeats DC SUPPLY REJECTION (AGAIN/AV pp) All 0.02 0.04 oot 0.02 Soper%max AV = 5% CURRENT SETTLING TIME? All 350 400 180 200 os max To 1/21.SB. Out A/Out B load = 1009. WR = CS = 0V. DBO_DB? = 0V 10 Vapor Vp 100V PROPAGATION DELAY (From Digital Vac A = VrerB= +10V Input to. 90% of Final Analog Output Current) All 220 270 30 100 ns max OUT A, OUT B Load = 1008tCexr = 13pF WR, CS = 0V DBO-DB? = DV 10 Vppor Vpn to OV DIGITAL TO ANALOGGLITCHIMPLLSE All 160 - 440 - aV sec typ For Code Transition 00000000 to 11111111 QUTPUT CAPACITANCE Cour A All 50 50 50 50 pF max DAC Latches Loaded with 00000000 Cour B 50 50 50 50 pF max Cour A 120 120 120 120 pF max DAC Latches Loaded with 11111111 Coury B 120 120 120 120 pF max AC FEEDTHROUGH Varr AtoOUTA Au -70 -65 -70 -65 4Bmax VaerA, Vacr B = 20V p-pSine Wave VarrBtoOUT B -70 -65 -70 ~65 4B max @ 100kHz CHANNEL TOCHANNEL ISOLATION Both DAC Latches Loaded with 11111111. Var AtoOUTB All -7 - -77 - dBtyp Vuzr A = 20Vp-p Sine Wave @ 100kHz Ver B = OV see Figure 6. Varr BtoOUTA -77 - -77 - dBryp Vaer A = 20V p-p Sine Wave @ 100kH2z Vazr A = OV see Figure6, DIGITAL CROSSTALK Alt 0 - pr) ~ aV sec typ Measured for Code Transition 00000000 to 11111111 HARMONIC DISTORTION All 85 - 85 ~ aBryp Vin = 6V rms @ LkHz NOTES "Temperacure Ranges are J,K,L Versions: 40C to + 85C A,B,C Versions: - 40C 10 + 85C S,T,U Versions: - 55C ta + 125C 2Specification applies to both DACsin AD7528. Logic inputs are MOS Gates. Typical input current ( + 25C) isless than InA. $Cuaranoed by design bur noe production texted, oR lid on Uh D)w DGND. Specifications subject 10 change without notice. 3-164 DIGITAL-TO-ANALOG CONVERTERS REV. AABSOLUTE MAXIMUM RATINGS (Ty = +25C unless otherwise noted) VpptoAGND ....... 200-0. ee eee OV, +17V VpptoDGND .........-5..--006- OV, +17V AGND toDGND............--.-. Vpp +0.3V DGND toAGND......-..--2--52-05-- Vpp +0.3V Digital Input Voltage to DGND -... 0.3V, Vpp +0.3V Veme; Vemo to AGND......... -0.3V, Vpp +0.3V Veer A, Vrrer BtoAGND .. 2... 2 ee eee +25V Varg A; Vrrp BtoAGND ..........-000- +25V Power Dissipation (Any Package) to +75C ..... 450mW Derates above + 75C by .. 0-2... 22 ee ee 6m W/C Operating Temperature Range Commercial (J, K, L) Grades... 2... 40C to +85C 40C to +85C - 55C to +: 125C 65C to + 150C + 300C Industrial (A, B, C) Grades Extended (S, T, U) Grades Storage Temperature Lead Temperature (Soldering, 10 secs.). . 2... 5. CAUTION: 1. ESD sensitive device. The digital control inputs are diode pro- tected; however, permanent damage may occur on unconnected devices subjected to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. 2. Do not insert this device into powered sockets. Remove power before insertion or removal. TERMINOLOGY Relative Accuracy: Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the end- points of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of full scale reading. ORDERING GUIDE Temperature Relative | Gain Package Model? Range Accuracy | Error Option? AD7528IN 40C to + 85C +1LSB +4LSB | N-20 AD7528KN 40C to + 85C +V/2LSB ] +2LSB | N-20 AD7528LN 40C to + 85C +V2LSB | +1LSB | N-20 AD7528JP 40C to + 85C + 1LSB +4LSB | P-20A AD7528KP 40C to + 85C +1/2LSB | +2LSB_ | P-20A AD7528LP ~ 40C to + 85C +1/2LSB | +1LSB_ | P-20A AD7528JR 40C to +. 85C +1LSB +4LSB [| R-20 AD7528KR 40C to + 85C +1/2LSB | +2LSB |; R-20 AD7528LR 40C to + 85C +1/2LSB | +ILSB | R-20 AD7528AQ 40C to + 85C +I1LSB +4LSB | Q-20 AD7528BQ 40C to + 85C +U2LSB | +2LSB Q20 AD7528CQ 40C to + 85C +1/2LSB | +1LSB | Q-20 AD75285Q 55Cto +125C | +1LSB +4LSB | Q-20 AD7528TQ 55Cto +125C | +1/2LSB | +2LSB | Q-20 AD7528UQ ~55Cto +125C | +1/2LSB | +1LSB | Q-20 AD7528SE ~55Cto +125C | +1LSB +4LSB | E-20A AD7528TE 55C to + 125C + V/2LSB | +2LSB E-20A AD7528UE 55C to + 125C +V2LSB ) +1LSB E-20A NOTES Analog Devices reserves the right to ship side-brazed ceramic in lieu of cerdip. Parts will be marked with cerdip designator Q. ?Processing to MIL-STD-893C, Class B is available. To order, add suffix /883B to part number. For further information, see Analog Devices 1990 Military Products Databook. 3E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. For outline information see Package Information section. REV. A AD7528 Differential Nonlinearity: Differential nonlinearity is the difference between the measured change and the ideal J LSB change between any two adjacent codes. A specified differential nonlinearity of + 1LSB max over the operating temperature range ensures monotonicity. Gain Error: Gain error or full-scale error is a measure of the output error be- tween an ideal DAC and the actual device output. For the AD7528, ideal maximum output is Vezr 1LSB. Gain error of both DACs is adjustable to zero with external resistance. Output Capacitance: Capacitance from OUT A or OUT B to AGND. Digital to Analog Glitch Impulse: The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal. Glitch impulse is measured with Veer A, Vrer B = AGND. Propagation Delay: This is a measure of the internal delays of the circuit and is defined as the time from a digital input change to the analog output current reaching 90% of its final value. Channel-to-Channel Isolation: The proportion of input signal from one DACs reference input which appears at the output of the other DAC, expressed as a ratio in dB. Digital Crosstalk: The glitch energy transferred to the output of one converter due to a change in digital input code to the other converter. Specified in nV secs. PIN CONFIGURATIONS AD?7528 LCCC wrt <n 2ee 32a 3203 09 Var A 4 i 18 Vines & DGND 5 VW Voo BAEHwac e 8h]) tor view 16 wa (mse) DB? 7 (Not to Scale! 6 oes 8 14 080 (LSB) DIP, SOIC 9 19 12 13 R22 2 5 acno [i] ouT outa [2] An 8 Rig A [3] Vner B Ver & [4 | Yoo cana [5] an7528 wr oac apace [e | (Me ta Seu) oS sei oe7 [7] Dao (LSB) ope [0 | ber oss [3 ] on? pes [ro] ops DIGITAL-TO-ANALOG CONVERTERS 3-165AD7528 INTERFACE LOGIC INFORMATION DAC Selection: Both DAC latches share a common 8-bit input port. The control input DAC A /DAC B selects which DAC can accept data from the input port. Mode Selection: Inputs GS and WR control the operating mode of the selected DAC. See Mode Selection Table below. Write Mode: When CS and WR are both low the selected DAC is in the write mode. The input data latches of the selected DAC are transparent and its analog output responds to activity on DBO- DB7. Hold Mode: The selected DAC latch retains the data which was present on DBO-DB7 just prior to CS or WR assuming a high state. Both analog outputs remain at the values corresponding to the data in their respective latches. DAC A/ DACB cs WR DACA DACB L L L WRITE HOLD H L L HOLD WRITE x H xX HOLD HOLD xX xX H HOLD HOLD 1. = Low State H = High State X = Dont Care Mode Selection Table WRITE CYCLE TIMING DIAGRAM I J Vop + _ 9 Vo CHIP SELECT DAC ADAC B he Voo Yoo Vow DATA IN STABLE mk DATA IN (DBO-DB7) on NOTES 1 ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF Voo Voo = +5V,t, = ty = 20ns, Vou = + 15V.t, = t= 40ns 2 TIMING MEASUREMENT REFERENCE LeveL 1s Yeo Yu CIRCUIT INFORMATION-D/A SECTION The AD7528 contains two identical 8-bit multiplying D/A con- verters, DAC A and DAC B. Each DAC consists of a highly stable thin film R-2R ladder and eight N-channel current steering switches. A simplified D/A circuit for DAC A is shown in Figure 1. An inverted R-2R ladder structure is used, that is, binary weighted currents are switched between the DAC output and AGND thus maintaining fixed currents in each ladder leg inde- pendent of switch state. R A R Vaer ar aR aR 2R 2A s1 S2 s3 s8 R ? ? { ? ! ? t cee A i 1 ! T s+! T OUT A To 0 AGND DAC A DATA LATCHES AND DRIVERS Figure 1. Simplified Functional Circuit for DACA 3-166 DIGITAL-TO-ANALOG CONVERTERS EQUIVALENT CIRCUIT ANALYSIS Figure 2 shows an approximate equivalent circuit for one of the AD7528s D/A converters, in this case DAC A. A similar equivalent circuit can be drawn for DAC B. Note that AGND (Pin 1) is common for both DAC A and DAC B. The current source I_Eaxace is composed of surface and junction leakages and, as with most semiconductor devices, approximately doubles every 10C. The resistor Ro as shown in Figure 2 is the equivalent output resistance of the device which varies with input code (excluding ail 0s code) from 0.8R to 2R. R is typically 11k. Cour is the capacitance due to the N-channel switches and varies from about SOpF to 120pF depending upon the digital input. g(Vrer A, N) is the Thevenin equivalent voltage generator due to the reference input voltage Vper A and the transfer function of the R-2R ladder. gtVner A, Nb Figure 2. Equivalent Analog Output Circuit of DAC A For further information on CMOS multiplying D/A converters refer to Appplication Guide to CMOS Muluplying D/A Con- verters available from Analog Devices, Publication Number G479-15-8/78. CIRCUIT INFORMATION-DIGITAL SECTION The input buffers are simple CMOS inverters designed such that when the AD7528 is operated with Vpp = 5V, the buffer converts TTL input levels (2.4V and 0.8V) into CMOS logic levels. When Vyy is in the region of 2.0 volts to 3.5 volts the input buffers operate in their linear region and pass a quiescent current, see Figure 3. To minimize power supply currents it is recommended that the digita) input voltages be as close to the supply rails (Vpp and DGND) as is practically possible. The AD7528 may be operated with any supply voltage in the range 5=Vpp=15 volts. With Vpp = +15V the input logic levels are CMOS compatible only, i.e., 1.5V and 13.5V. = +15V Ae + ALL DIGITAL INPUTS. TIED TOGETHER 700 Is 8 2 3 & 600 8S "S00 8 & 2 a00 a? 2 300 33 3 $s 200 2 So at 1 2 3 4 5 6 7 a 8 1 11 Vin ~ Volts 12 =13~14 Figure 3. Typical Plots of Supply Current, Ipp vs. Logic Input Voltage Vin, for Vpp = +5V and +15V REV.A