DS14C89A
Quad CMOS Receiver
General Description
The DS14C89A, pin-for-pin compatible to the DS1489A/
MC1489A, ia a quad receiver designed to interface data
terminal equipment (DTE) with data circuit-terminating
equipment (DCE). These devices translate levels conform-
ing to EIA-232E and CCITT V.28 standards to TTL/CMOS
logic levels.
The device is fabricated in low threshold CMOS metal gate
technology. The device provides very low power consump-
tion compared to their bipolar equivalents: 900 µA
(DS14C89A) versus 26 mA (DS1489A).
The DS14C89A provides on chip noise filtering which elimi-
nates the need for external response control filter capacitors.
When replacing the DS1489A with the DS14C89A, the re-
sponse control filter pins can be tied high, low, or not con-
nected.
Features
nMeets EIA/TIA-232-E and CCITT V.28 Standards
nFailsafe - Output High for Open Input
nLOW Power consumption
nOn chip noise filter
nAvailable in SOIC Package
Connection Diagram
01110601
Order Number DS14C89AN, DS14C89AM,
See NS Package Number M14A, N14A
May 1998
DS14C89A Quad CMOS Receiver
© 2004 National Semiconductor Corporation DS011106 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
CC
+6V
Input Voltage −30V to +30V
Receiver Output Voltage (V
CC
) +0.3V to
GND−0.3V
Junction Temperature +150˚C
Continuous Power Dissipation @+25˚C (Note 2)
N Package 1513 mW
M Package 1063 mW
Lead Temp.
(Soldering 4 seconds) +260˚C
Storage Temp. Range −65˚C to +150˚C
ESD Rating 1.8 kV, Typically 2kV
(HMB, 1.5 k, 100 pF)
Recommended Operating
Conditions
Min Max Units
V
CC
(GND = 0V) +4.5 +5.5 V
Operating Free Air Temp. (T
A
)
DS14C89A 0 +75 ˚C
Electrical Characteristics
Over recommended operating conditions, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
V
TH
Input High Threshold 1.3 2.7 V
V
TL
Input Low Threshold 0.5 1.9 V
V
HY
Typical Input Hysteresis 1.0 V
I
IN
Input Current V
IN
= +25V V
CC
= +4.5V to +5.5V 3.6 8.3 mA
V
IN
= −25V −3.6 −8.3 mA
V
IN
= +3V 0.43 1.0 mA
V
IN
= −3V −0.43 −1.0 mA
V
IN
= +15V V
CC
= 0V (Power-Off) 2.14 5.0 mA
V
IN
= −15V (Note 4) −2.14 −5.0 mA
V
IN
= +3V 0.43 1.0 mA
V
IN
= −3V −0.43 −1.0 mA
V
OH
Output High Voltage V
IN
=V
TL
(min) I
OUT
= −3.2 mA 2.8 4.0 V
I
OUT
= −20µA 3.5 4.7 V
V
OL
Output Low Voltage V
IN
=V
TH
(max) 0.15 0.4 V
I
OUT
= +3.2 mA
I
CC
Supply Current No Load, V
IN
= 2.7V or 0.5V 0.5 900 µA
AC Electrical Characteristics (Note 3)
Over recommended operating conditions, unless otherwise specified, C
I
=50pF
Symbol Parameter ConditIons Min Typ Max Units
t
PLH
Propagation Delay Low to High Input Pulse Width 10 µs 3.5 6.5 µs
t
PHL
Propagation Delay High to Low Input Pulse Width 10 µs 3.2 6.5 µs
t
SK
Typical Propagation Delay Skew 400 ns
t
r
Output Rise TIme 40 300 ns
t
f
Output Fall Time 40 300 ns
t
nw
Pulse Width assumed to be Noise 1.0 µs
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Derate N Package 12.1 mW/˚C, and M Package 8.5 mW/˚C above +25˚C.
Note 3: AC input waveforms for test purposes: tr=t
f= 200 ns, VIH = +3V, VL=−3V,f=20KHz.
Note 4: Under the power-off supply conditions it is assumed that the power supply potential drops to zero (0V) and is replaced by a low impedance or short circuit
to ground.
DS14C89A
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Parameter Measurement Information
Typical Application Information
01110602
FIGURE 1. Receiver Load Circuit
01110603
FIGURE 2. Receiver Switching Waveform (Note 3)
01110604
FIGURE 3. Receiver Block Diagram
01110605
FIGURE 4. EIA-232D Data Transmission
DS14C89A
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Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS14C89AM
NS Package Number M14A
Order Number DS14C89AN
NS Package Number N14A
DS14C89A
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Notes
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
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DS14C89A Quad CMOS Receiver
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