To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 2tENESAS Renesas Technology Corp.MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL DESCRIPTION M51995A is the primary switching regulator controller which is especially designed to get the regulated DC voltage from AC power supply. This IC can directly drive the MOS-FET with fast rise and fast fall output pulse. Type M51995A has the functions of not only high frequency OSC and fast output drive but also current limit with fast response and high sensibility so the true "fast switching regulator" can be realized. It has another big feature of current protection to short and over current,owing to the integrated timer-type protection circuit,if few parts are added to the primary side. The M51995A is equivalent to the M51977 with externally re- settable OVP(over voltage protection)circuit. FEATURES @ 500kHz operation to MOS FET Output current... erecus ceetgveescutest *Output rise time 60ns,fall time 40ns Modified totempole output method with small through current t2A Compact and light-weight power supply Small start-up current... .. SONA typ. *Big difference between "start-up no and en voltage" makes the smoothing capacitor of the power input section small. Start-up threshold 16V,stop voltage 10V Packages with high power dissipation are used to with-stand the heat generated by the gate-drive current of MOS FET. 16-pin DIP,20-pin SOP 1.5W(at 25C) @ Simplified peripheral circuit with protection circuit and built-in large-capacity totempole output *High-speed current limiting circuit using pulse-by-pulse method(Two system of CLM+pin,CLM-pin) Protection by intermittent operation of output over current...... ssacureusnareaatesteeds .... Fimer protection circuit Over-voltage protection circuit with an externally re-settable latech(OVP) Protection circuit for output miss action at low supply voltage(UVLO) High-performance and highly functional power supply Triangular wave oscillator for easy dead time setting APPLICATION Feed forward regulator,fly-back regulator RECOMMENDED OPERATING CONDITIONS Supply voltage range.... 12 to 36V Operating frequency... ..less than 500kKHz Oscillator frequency setting resistance 10k to 75k 2k to 30kQ *T-ON pin resistance RON.............ccccceeee *T-OFF pin resistance ROFF.............0cccee PIN CONFIGURATION (TOP VIEW) COLLECTOR VouT EMITTER VF ON/OFF DET F/B COLLECTOR VOUT EMITTER VF HEAT SINK PIN ON/OFF OVP DET F/B Ly [16] fz GB] = 4} o (fs) GB] & fa [s} 9 fa] [7 [s | EI Outline 16P4 dAjVS661SIN _ =] f=] y= = a co] |e) [on ~d SSIOIGISIGIOISICNSIE Outline 20P2N- > Vec CLM+ CLM- GND CT T-OFF CF T-ON Vcc CLM+ CLM- GND HEAT SINK PIN CT T-OFF CF T-ON Connect the heat sink pin to GND. 2tENESAS (1 / 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL BLOCK DIAGRAM Veco F/B DET GND UNDER LOCKOUT | | 1 OVP(shut down) ( {LATCH 2.5V COLLECTOR | 1 | PWM PWM VOUT | COMPARATO! LATCH \ EMITTER OSCILLATOR CAPACITANCE | | 1 1 OSCILLATOR RESISTANCE T-ON OSCILLATOR 4 CURRENT CURRENT [-* NNT: INTERMITTENT (ON duty) (TRIANGLE) LIMIT LATCH LIMITLATCH | ros CONTROL ACTION OSCILLATOR RESISTANCE T-OFF| (OFF duty) | 1 VF ( t | CLM+ CLM- CT +CGURRENT LIMIT = -CURRENT LIMIT INTERMITTENT OPERATION DETERMINE CAPACITANCE ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Ratings Unit Vec Supply voltage 36 Vv Vc Collector voltage 36 Vv Peak +2 lo Output current Continuous 0.15 A Vive VF terminal voltage Vec Vv Vonworr | ON/OFF terminal voltage Vec V VcLM- CLM-terminal voltage -4.0 to +4.0 V VCLM+ CLM+terminal voltage -0.3 to +4.0 Vv love OVP terminal current 8 mA VDET DET terminal voltage 6 V IDET DET terminal input current 5 mA VFB F/B terminal voltage 0~10 Vv ITON T-ON terminal input current -1 mA ITOFF T-OFF terminal input current -2 mA Pa Power dissipation Ta=25'C 1.5 Ww Ke Thermal derating factor Ta>25'C 12 mWwi'C Topr Operating temperature -30 to +85 C Tstg Storage temperature -40 to +125 C Tj Junction temperature 150 Cc Note 1."+" sign shows the direction of current flow into the IC and "-" sign shows the current flow from the IC. 2.This terminal has the constant voltage characteristic of 6 to 8V,when current is supplied from outside. The maximum allowable voltage is 6V when the constant voltage is applied to this terminal.And maximum allowable current into this terminal is 5mA. 3.The low impedance voltage supply should not be applied to the OVP terminal. (2 / 27 ) 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL ELECTRICAL CHARACTERISTICS (vVcc=18V, Ta=25C, unless otherwise noted) si Limits Block} Symbol Parameter Test conditions Min. | Typ. | Max Unit Vec Operating supply voltage range Vee(STOP) 35 V | VccistarT)| Operation start up voltage 15.2 16.2 17.2 Vv E Vccistop) | Operation stop voltage 9.0 9.9 10.9 V = AVcc cpewioacatdcos AVcec=Vcc(sTART) -Vcc(SToP) 5.0 6.3 7.6 V 2 Vec=14.5V,Ta=25C 50 | 90 | 140 A 6 lect Shand by Guireit Voo=14.5V,-30<Ta<85C 40 | 90 | 190 a | Icco Operating circuit current Vec=30V 10 15 21 mA = $ Icc OFF Circuit current in OFF state ear = ie 2s i a oo. Vec=25V 0.95 | 1.35 2.0 mA 2 lec cT Circuit current in timer OFF state Vaniay 160 340 uA a Vec=25V 13 | 20 | 3.0 | ma lec ove Circuit current in OVP state VWaRLDEV 105 300 310 uA i VTHH ON/OFR ON/OFF terminal high threshold voltage 2.1 2.6 3.1 Vv S VTHL ON/OFF ON/OFF terminal low threshold voltage 1.9 2.4 29 Vv |AVTHON/OFF] ON/OFF terminal hysteresis voltage 0.1 0.2 3.0 Vv |FBMIND Current at 0% duty F/B terminal input current -2.1 -1.54 | -1.0 mA Pe lFaMaxD | Current at maximum duty F/B terminal input current -0.90 | -0.55 | -0.40 | mA i AlFB Current difference between max and 0% duty AIFB=IFBMIND-IFBMAXD -1.35 | -0.99 | -0.70 mA VFB Terminal voltage F/B terminal input current=0.95mA 4.9 5.9 7.1 V RFB Terminal resistance 420 600 780 Q S| Vober | Detection voltage 24 | 25 2.6 Vv 3 lINDET Input current of detection amp VoeT=2.5V 1.0 3.0 pA a GavpeT | Voltage gain of detection amp 30 40 dB VTHOVPH | OVP terminal H threshold voltage 540 750 960 mV AVtHove | OVP terminal hysteresis voltage AVTHOVP=VTHOVPH-VTHOVPL 30 mV ItHove =| OVP terminal threshold current 80 150 250 pA a |_linove | OVP terminal input current Vovp=400mV 80 150 250 HA 5 Vccovec | OVP reset supply voltage OVP terminal is open. 75 9.0 10.0 V Vec(stop) Difference supply voltage between | (high impedance) 0.55 | 1.20 Vv -Vecovec | operation stop and OVP reset ITHOVeS Cree from OVP terminal for Vec=30V 480 | -320 | -213 WA VP reset Vec=18V -210 | -140 -93 fTiMeR | Timer frequency CT=4.7uF 0.27 | 0.40 | 0.60 Hz 5 VeT=3.3V,Ta=-5C -193 | -138 | -102 | itimecH | Timer charge current Ta=25C -178 | -127 -94 LA rs Ta=85C -147 | -105 | -78 TIMEOFF/ON OFF time/ON time ratio 7.0 8.7 11.0 < VTHcLm- | CLM- terminal threshold voltage -5sTas85C -299 | -200 | -180 mv _ liNcLM- | CLM- terminal current Veim-=-0.1V -170 | -125 -90 pA o Trocim- | Delay time from CLM- to Vout 100 ns + | VTHCLM+ | CLM+ terminal threshold voltage -5<Tas<85C 180 200 220 mV = lincLM+ | CLM+ terminal current Vcim+=0V -270 | -205 | -140 pA | Tevcume Delay time from CLM+ to VouT 100 ns (3 / 27 ) 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL ELECTRICAL CHARACTERISTICS (Vcc=18V,Ta=25'C, unless otherwise noted)(CONTINUE) Limits Block] Symbol Parameter Test conditions Min. Tia Max. Unit tLati Ron=20kQ, ROFF=17kQ Oscillating f 170 188 207 fosc scillating frequency Cr=220pF,-5<Ta<85C kHz s TDUTY Maximum ON duty 47.0 | 50.0 | 53.0 % = VOSCH Upper limit voltage of oscillation waveform fosc=188kHz 3.97 | 4.37 | 4.77 Vv 8 | Vosc Lower limit voltage of oscillation waveform fosc=188kHz 1.76 1.96 2.16 Vv o , Sasi AVosc __ | Voltage difference between upper limit and | fogc-188kHz 241 241 | 271 lower limit of OSC waveform foscve | OSC frequency in CLM vESoy RON=20kQ,ROFF=17kQ 170 | 188 | 207 | yy, operating state VF=2V Cr=220pF 108 124 143 SS | Tveouty | Duty in CLM operating state VF=0.2V Min off duty/Max on duty 11.0 | 13.7 | 22.0 VTHTIME | VF voltage at timer operating start 27 3.0 3.3 Vv IvF VF terminal input current Source current 2 6 pA Vout Vec=18V,lo=10mA 0.05 0.4 Vv VoL2 OuiDuL low vores Vec=18V,lo=100mA 0.7 1.4 V w | VOL3 p 9 Vec=5V,lo=1mA 0.69 1.0 Vv a| vod Vec=5V,lo=100mA 13 | 2.0 ij - = | Von1 Vee=18V,lo=-10mA 16.0 | 16.5 Vv Output high voltage VoH2 pene ee Voc=18V,lo=-100mA 155 | 16.0 V TRISE Output voltage rise time No load 50 ns TFALL __| Output voltage fall time No load 35 ns ( 4 / 27 ) 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL TYPICAL CHARACTERISTICS 2tENESAS THERMAL DERATING CIRCUIT CURRENT VS.SUPPLY VOLTAGE 4800 (MAXIMUM RATING) (NORMAL OPERATION) 22m RON=18k22 18m ROFF=20kQ ' 4500 jOSC=5O0KHz = = E = 16m 1200 = z 2 14m e b = 200 ~ 42m a N x = 3 10m O 600 E Tr = FS = y 9 100 2 100) | | 2 300 \ 5 7 Ta=-30C 50u, Ta=85C \ 0 25 50 7585 100 125 150 0 10 20 30 40 SUPPLY VOLTAGE Vec(V) AMBIENT TEMPERATURE Ta(C) CIRCUIT CURRENT VS.SUPPLY VOLTAGE CIRCUIT CURRENT VS.SUPPLY VOLTAGE (OVP OPERATION) (OFF STATE) 8.0 OVP RESET POINT __ 3.0 7 9| 8:87(-30C) l 8.94(25C) _ 9.23V(85C) < = o = 8 8 50 E 20 Ta=25C KE Wu i 4.0 \Ta=-30C & Ta=85C a _Ta=25C SH | 2 Ta=-30C BD 3.0 -Ta=85C\ E [yo | 5 k o 1.0 a 2.0 4 tc oO o 4.0 0 0 0 10.0 20.0 30.0 40.0 0 10 20 30 40 SUPPLY VOLTAGE Vcc(V) SUPPLY VOLTAGE Vec(V) CIRCUIT CURRENT VS.SUPPLY VOLTAGE > OVP TERMINAL THRESHOLD VOLTAGE (TIMER OFF STATE) a4 VS.AMBIENT TEMPERATURE 2 . 3.0 = we 1.0 O z = z 0.9 8 8 Ta=25C a o8 Hesiod voles 2 Ta=85C Oo Ww . 7 7 : ! fr w 07 c Ta=-30C : | sesee | o = 06 | L threshold voltage-, 5 1.0 2 (VTHOVPL)_| 3 Z 05 x = 5 fi We 0.4 = 0 6 (03 0 10 20 30 40 40 -20 0 20 40 60 80 100 SUPPLY VOLTAGE Vcc(V) AMBIENT TEMPERATURE Ta(C) Ce 4 eryMITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL CHARGE CURRENT OF TIMER ITIMEON(HA) THRESHOLD VOLTAGE OF ON/OFF TERMINAL VTHON/OFF() INPUT CURRENT OF VF TERMINAL Ivr(yA) 3.4 3.2 3.0 2.8 2.6 24 2.2 2.0 -10 9 -200 THRESHOLD VOLTAGE OF ON/OFF TERMINAL VS.AMBIENT TEMPERATURE ON-OFF OFF*ON 40 = -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(C) INPUT CURRENT OF VF TERMINAL VS.INPUT VOLTAGE Ta=-30C Ta=25C Ta=85C 1 2@ 3 4 5 6 7 8 9 10 VF TERMINAL VOLTAGE VveF(V) CHARGE CURRENT OF TIMER VS.AMBIENT TEMPERATURE -180 -160 -140 -120 -100 -80 40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(C) 2tENESAS THRESHOLD VOLTAGE OF ON/OFF TERMINAL ITHONIOFF( 1A) DISCHARGE CURRENT OF TIMER ITIMEOFF(pA) ON DURATION OF TIMER Ton(ms) THRESHOLD VOLTAGE OF ON/OFF TERMINAL VS.AMBIENT TEMPERATURE 25.0 ON OFF 20.0 sh OFFRON 0 60 -40 -20 0 20 40 =660 80 = 100 AMBIENT TEMPERATURE Ta(C) DISCHARGE CURRENT OF TIMER 48 VS.AMBIENT TEMPERATURE 17 16 W 10 60 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(C) ON AND OFF DURATION OF TIMER VS.AMBIENT TEMPERATURE (INTERMITTENT OPERATION) 175 1.4 TIMER ON*CIRCUIT OPERATION ON TIMER OFF*CIRCUIT OPERATION OFF g a E 150 13 6 oc Ww TIMER ON = - 125 1200 O = oO E << 100 'TIMER OFF. wa = = a Ww L O 75 1.0 60 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(C) (6 / 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL VF THRESHOLD VOLTAGE FOR TIMER VS. AMBIENT TEMPERATURE THRESHOLD VOLTAGE OF CLM+ TERMINAL VS. AMBIENT TEMPERATURE 2tENESAS _ _/ _ => = F Ze lu 2 z = FE Wo oc 35 Fez 205 Oo +> Ez = = wi Oo Go 0 ee ue << = o a 3.0 | | | | | t wi 200 2 gq Q A 0 oO am 25 a (19 u - c= F i E 60 -40 -20 0 20 40 60 80 100 - 0 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(C) AMBIENT TEMPERATURE Ta(C) THRESHOLD VOLTAGE OF CLN- TERMINAL CLM+ TERMINAL CURRENT VS. AMBIENT TEMPERATURE VS. CLM+ TERMINAL VOLTAGE pe -400 = ze < = = i : Ww _ wk z> 205 2-300 | = a o z Ta=-30C y ra a Ta=25C o na , o 200 3 -200 | Ta=85C =< 4 call z o < > = D195 f .100 oO e .s + w = z 3 e 0 -0 -40 -20 0 20 40 60 80 100 0 0.1 0.2 0.3 0.4 0.5 06 0.7 08 0.9 1.0 AMBIENT TEMPERATURE Ta(C) CLM+ TERMINAL VOLTAGE Vc.m+(V) CLM- TERMINAL CURRENT OUTPUT HIGH VOLTAGE VS. VS. CLM- TERMINAL VOLTAGE OUTPUT SOURCE CURRENT -500 2.6 Vec=18V > > 2.4/;-Ta=25C = z -400 $ 22 8 oO = i 2.0 Ww -300 | | | g 1.8 na Ta=-30C E 5 |_| a 16 Oo o Ta=25C > q -200 + | xm 14 z Ta=85C g Ww F -100 e 1.0 = o 08 o 0.6 05 -0.2 -0.4 -0.6 -0.8 -1.0 im 10m 100m 1 10 CLM- TERMINAL VOLTAGE Vc.w-(V) OUTPUT SOURCE CURRENT IoH(A) (7/27)MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL INPUT CURRENT OF DETECTION AMP IINDET(HA) OUTPUT LOW VOLTAGE VoL(V) ON duty (%) OUTPUT LOW VOLTAGE VS. OUTPUT SINK CURRENT 5.0/-TTTT Ta=25C 4.0 3.0 Vec=18V } 2.0 Ty cc= WY Uy Z 1.0 <p = | 0 Le im 10m 100m 1 10 OUTPUT SINK CURRENT IoL(A) INPUT CURRENT OF DETECTION AMP VS. AMBIENT TEMPERATURE 1.6 1.5 1.4 13 1.2 11 1.0 0.9 0.8 60 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(C) ON duty VS. F/B TERMINAL INPUT CURRENT (fosc=100kHz) RON=18kQ 40 | ROFF=20kQ _ Ta=-30C Ta=25C 20 f Ta=85C 10 9 05 7.0 1 20 25 F/B TERMINAL INPUT CURRENT Iris (mA) 2tENESAS DETECTION AMP VOLTAGE GAIN GpeT(dB) DETECTION VOLTAGE VpeT(V) ON duty (%) DETECTION VOLTAGE VS. AMBIENT TEMPERATURE 2.555 2.50 2.455 2.40 0 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(*C) DETECTION AMP VOLTAGE GAIN VS. FREQUENCY 50.0 40.0 =a q N 30.0 \ \ 20.0 \ N 10.0 \ N 0 100 1k 10k 100k 1M 10M FREQUENCY f(Hz) ON duty 5 VS. F/B TERMINAL INPUT CURRENT 5 (fosc=200kKHz) Ron=18kQ 40 RorrF=20kQ 30 + Ta=-30C Ta=25C 20 : Ta=85C 10 0 0 0.5 1.0 1.5 2.0 2.5 F/B TERMINAL INPUT CURRENT Iris (mA) (8 / 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL OSCILLATING FREQUENCY fosc(kHz) ON duty (%) OSCILLATING FREQUENCY fosc(kHz) ON duty VS. UPPER & LOWER LIMIT VOLTAGE OF OSC F/B TERMINAL INPUT CURRENT VS. AMBIENT TEMPERATURE 50 ee (fosc=500kHz) a= Ron=18k2 Ron=18kQ e 9 5.21 _RoFF=20kQ fosc=500kHz a5 | ROFF=20kQ Os fosc=200kHz on 48 fosc=100kHz =o 2a 7 4.4 30 = Ta=-30C = Ta=25C = a0 dcoudlacgead =I me osc=100kHz 20 - Ta=85C c 99} ___ 4 fosc=200kHz = //, Aose=S00kH2 ml a 2.0 10 Sa c wi 1.8 a a 0 = 0 0.5 1.0 1.5 20 25 -60 -40 -20 O 20 40 60 80 100 o F/B TERMINAL INPUT CURRENT IF/a(mA) DeRIENT TEMPERS BE Tere) OSCILLATING FREQUENCY VS. CF TERMINAL CAPACITY 06 ON duty VS. Rorr 10000 90 80 1000 %5 Ron=75kQ =~ I | Il im I - otk =~ " i: a z 40 18kQ = 5kQ 10 Pe 10kQ 10 1 0 + i 3 10 100 1000 10000 1 10 100 CF TERMINAL CAPACITY (pF) Rorr(ko2) OSCILLATING FREQUENCY VS. OSCILLATING FREQUENCY VS. AMBIENT TEMPERATURE AMBIENT TEMPERATURE 120 700 Ron=24kQ N Ron=24kQ RoFF=20kQ =~ 600 RoFF=20kQ ss Cr=47pF 110 Cr=330pF g p > Too 2 500 2 | | | | | | ui >To 100 S c 9 400 90 < 3 300 oO a oO 80 200 60 -40 -20 0 20 40 60 80 100 0 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(?C) AMBIENT TEMPERATURE Ta(C) (9/27) 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL ON duty (%) ON duty (%) INPUT VOLTAGE OF TERMINAL VvF(V) ON duty VS. AMBIENT TEMPERATURE 10 (fosc=100kKHz) 80 = RON=36k, ROFF=6.2k 70 i & 60 RON=22k,ROFF=12k > a 50 RON=24k,ROFF=20k & RON=22k, ROFF=22k 5 40 RON=18k, ROFF=24k 30 QQuQuQuaaant em _RON=15k, ROFF=27k 20 10 0 -60 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(C) ON duty VS. AMBIENT TEMPERATURE 100 (fosc=500kKHz) 90 | | = Ww 80 RON=36k,ROFF=6.2k = = 70 z = 60 _-RON=22k, ROFF=12k i Ke 50 RON=24k,ROFF=20k LL RON=22k, ROFF=22k 0 40 | | |__RON=18k, ROFF=24k o % ee es ee er ane RON= 15k, ROFF=27k Fe = 20 - a 10 Zz 0 -60 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(*C) INPUT VOLTAGE OF TERMINAL VS. EXPANSION RATE OF PERIOD 5.0 | {fosc=500kHz) a r 5 7) RON=15k,ROFF=27k 5 (D\-RON=18k, ROFF=24k | - 3) RON=22k, ROFF=22k ia 1 3.0 4) RON=24k, ROFF=20k ] 3 5) RON=22k,ROFF=12k E 6 RON=36k,AOFF=6.2k | = 2.0 < | = = = 1.0 a | a > i o 0 2 4 6 8 10 12 14 16 18 20 EXPANSION RATE OF PERIOD(TIMES) 2tENESAS ON duty VS. AMBIENT TEMPERATURE 100 (fosc=200kHz) 90 | | | 80 RON=36k, ROFF=6.2k 70 60 RON=22k, ROFF=12k 50 eee RONR24k, ROFF=20k RON 22k, ROFF= 22K 40 1 | | +-RON=18k, ROFF=24k 30 ARON 15k, ROFF=27K 20 10 0 -0 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(C) INPUT VOLTAGE OF TERMINAL VS. 50 EXPANSION RATE OF PERIOD , (fosc=100kHz) = 1 RON=15k,ROFF=27k 2\ RON=18k,ROFF=24k 4) RON=22k,ROFF=22k 3.0 d) RON=24k, ROFF=20k 5) RON=22k, ROFF=12k 6) RON=36k, ROFF=6.2k 2.0 1.0 5 NTs Vs 0 2 4 6 8 10 12 14 16 18 20 EXPANSION RATE OF PERIOD(TIMES) OVP TERMINAL INPUT VOLTAGE VS. INPUT CURRENT im | Ta=85C || | Ta=26C ; Ta=-30C> 00u FE 10 1p 0.2 0.4 0.6 0.8 1.0 OVP TERMINAL INPUT VOLTAGE Vove(V) (10 / 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL CURRENT FROM OVP TERMINAL FOR OVP e> bel s RESET VS. SUPPLY VOLTAGE Wo 800 3 SE 700 c 600 _) 3 500 = Ta=-30C ___ +, cr Ta=25C WW {ee on rT a ao Ta=B85C | 5 300 5 c 200 - A 100 c c 3 ) o o 5 10 15 20 25 30 35 40 SUPPLY VOLTAGE Vec(V) (11/ 27 ) 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL FUNCTION DESCRIPTION Type M51995AP and M51995AFP are especially designed for parts can be reduced and also parts can be replaced by off-line primary PWM control IC of switching mode power supply reasonable one. (SMPS) to get DC voltage from AC power supply. In the following circuit diagram,MOS-FIT is used for output Using this IC,smart SMPS can be realized with reasonable transistor,however bipolar transistor can be used with no cost and compact size as the number of external electric problem. gt | CrIN Ri L L - a rs) ; a Vourt L LL + = M51995AP == = 3 R2 fh Cvec Ls} ANN rm | + CT J I x a = ANW-a-\iy + | p ANN = li CT at Tw] bl a Ron *ROFF 1 A nn Pin No.is related with M51995AP Fig.1 Example application circuit diagram of feed forward regulator t : atts CFIN Ri s J 3 rc - ANN, 4 + : an VouT 2 M51995AP * O [| : THIET] Ron *Rorr Pin No.is related with M51995AP Fig.2 Example application circuit diagram of fly-back regulator (12 / 27 ) 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL Start-up circuit section The start-up current is such low current level as typical 90y A,as shown in Fig.3,when the Vcc voltage is increased from low level to start-up voltage Vcc(START). In this voltage range,only a few parts in this IC,which has the function to make the output voltage low level,is alive and Icc current is used to keep output low level.The large voltage difference between Vcc(STaRT) and Vcc(stor) makes start-up easy, because it takes rather long duration from Vcc(sTART) to Vec(stop). = Icco Slama [Peeters - = WwW aa o 5 = Ilece Po OQ c Vcc Vcc o (STOP) (START) =9.9V =16.2V SUPPLY VOLTAGE Vec(V) Fig.3 Circuit current vs.supply voltage Oscillator section The oscillation waveform is the triangle one. The ON-duration of output pulse depends on the rising duration of the triangle waveform and dead-time is decided by the falling duration. The rising duration is determined by the product of external resistor Ron and capacitor Cr and the falling duration is mainly determined by the product of resistor RorF and capacitor Cr. (1)Oscillator operation when intermittent action and OSC control circuit does not operate Fig.4 shows the equivalent charging and discharging circuit diagram of oscillator when the current limiting circuit does not operate. It means that intermittent action and OSC control circuit does not operate. The current flows through Ron from the constant voltage source of 5.8V.Cr is charged up by the same amplitude as Ron current,when internal switch SW1 is switched to "charging side" The rise rate of Cr terminal is given as VT - ON where VT- ON 4.5V The maximum on duration is approximately given as ~ _(VOSCH-VoscL) X Ron X Cr $ = een (S) ooo eeeeeeeeesveeee(2) where VoscH = 4.4V Vosc. = 2.0V WAVEFORM OF VouT TERMINAL IN MAX. Cr is discharged by the summed-up of Rorr current and one sixteenth (1/16) of Ron current by the function of 2,03 and Q4 when SW1,SWe2 are switched to "discharge side". 5.8V 4 CHARGING +. SW1 SWITCHED BY CHARGING AND DISCHARGING SIGNAL DISCHARGING M51995 ae Fig.4 Schematic diagram of charging and discharging control circuit for OSC.capacitor Cr VOSCH =44V VOSCL | _ =2.0V WAVEFORM OF CF TERMINAL VOH F -- ON DUTY CONDITION VOL Fig.5 OSC.waveform at normal condition (no- operation of intermittent action and OSC.control circuit) So fall rate of CF terminal is given as ~~ _VT- OFF VT -ON Rorr X Ce + 16 X RON X Cr (VIS) oo ccccseeseeseeeeeee(S) The minimum off duration approximately is given as ~ _(VOSCH-VoscL) X CF 'VT-OFF 4 _VT-ON (8) sraninnwmnrmnnan(4) ROFF 16 X Ron where VT - OFF ~ 3.5V The cycle time of oscillation is given by the summation of Equations 2 and 4. The frequency including the dead-time is not influenced by the temperature because of the built-in temperature compensating circuit. 2tENESAS (13 / 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL (2)Oscillator operation when intermittent action and OSC control circuit operates. When over current signal is applied to CLM+ or CLM- terminal,and the current limiting circuit,intermittent action and OSC control circuit starts to operate.|In this case T-OFF terminal voltage depends on VF terminal voltage,so the oscillation frequency decreases and dead-time spreads. The rise rate of oscillation waveform is given as ~ _VT-ON oe en) The fall rate of oscillation waveform is given as ~ Vve- VvFo VT - ON Rorr X Cr + 16 X RON X CE (VIS) ..ccccccseeeee(B) where VT-oN ~ 4.5V VveFiVF terminal voltage Vveo 0.4V Vve-Vro=0 if VvF-Vvro<0 VvF-VVFO=VT-OFF if VVF-VVFO>VT-OFF 3.5V So when VvF>3.5V,the operation is just same as that in the no current limiting operation state. The maximum on-duration is just same as that in the no- operation state of intermittent and oscillation control circuit and is given as follows; ~ (VoscH - VoscL) X Rorr X Cr VT - ON (S) ecceeneee(7) The minimum off-duration is approximately given as; (VOSCH - VOSCL) X CF Vve - VvFO Rorr X Cr VT - ON 16 X RON X Cp S)es8) The oscillation period is given by the summation of Equation(7) and (8). As shown in Fig.7,the internal circuit kills the first output pulse in the output waveform.The output waveform will appear from the second pulse cycle because the duration of first cycle takes Cr charging time longer comparing with that at the stable operating state. Usually the applied voltage to VF terminal must be proportional the output voltage of the regulator. So when the over current occurs and the output voltage of the regulator becomes low,the off-duration becomes wide. There are two methods to get the contro! voltage,which depends on the output voltage,on primary side.For the fly back type regulator application,the induced voltage on the third or bias winding is dependent on output voltage.On the other hand,for the feed forward type regulator application, it can be used that the output voltage depends on the product of induced voltage and "on-duty",as the current of choke coil will continue at over load condition,it means the "continuous current" condition. Fig.8 shows one of the examples for VF terminal application for the feed forward type regulator. = VOSCH Py =44V ad az == w VoscL|_ OF z20v BS Ss S. <a 5 4 be Zee zws VOH Ww Fo orz 2 852 vo 23s , Fig.6 OSC.waveform with operation of intermittent and OSC.control circuit operation START FROM OV ac fo >B voscu}--------7--y == == : w c i gF EF VOSCL } ----774------ pom 3 | =O Ol 1 &, 3% FIRST o3 : PULSE SS> Vou;--1---------- veo z6 'NO GENERATE wed PULSE! g5s EE x VoL r : 93 oO 4 OPERATION START Fig.7 Relation between OSC. and output waveform circuit operation at start up M51995 a Vout ; RVFFB CvFFB Fig.8 Feedback loop with low pass filter from output to VF terminal choke coil will continue at over load condition,it means the continuous current" condition. Fig.8 shows one of the examples for VF terminal application for the feed forward type regulator. 2tENESAS (14/ 27 )F/B MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL PWM comparator and PWM latch section Fig.9 shows the PWM comparator and latch section. The on- duration of output waveform coincides with the rising duration of CF terminal waveform,when the infinitive resistor is connected between F/B terminal and GND. When the F/B terminal has finite impedance and current flows out from F/B terminal,"A" point potential shown in Fig.9 depends on this current.So the "A" point potential is close to GND level when the flow-out current becomes large. "A" point potential is compared with the CF terminal oscillator waveform and PWM comparator,and the latch circuit is set when the potential of oscillator waveform is higher than "A" point potential. On the other hand, this latch circuit is reset by high level signal during the dead-time of oscillation(falling duration of oscillation waveform).So the "B" point potential or output waveform of latch circuit is the one shown in Fig.10. The final output waveform or "C" point potential is got by combining the "B" point signal and dead-time signal logically.(please refer to Fig.10) = 7.1 OSC M51995A Fig.9 PWM comparator and latch circuit OSC WAVEFORM / POINT A F \ WAVEFORM OF 0.8.0. & POINT A POINT B POINT C Fig.10 Waveforms of PWM comparator input point A, latch circuit points B and C Current limiting section When the current-limit signal is applied before the crossing instant of "A" pint potential and CF terminal voltage shown in Fig.9,this signal makes the output "off" and the off state will continue until next cycle.Fig.11 shows the timing relation among them. The current limiting circuit has two input terminals,one has the detector-sensitivity of +200mV to the GND terminal and the other has -200mV.The circuit will be latched if the input signal is over the limit of either terminal. If the current limiting circuit is set,no waveform is generated at output terminal however this state is reset during the succeeding dead-time. So this current limiting circuit is able to have the function in every cycle,and is named "pulse-by-pulse current limit. OSC WAVEFORM OF CF TERMINAL VIHCLM= 200mV fl fe CURRENT LIMIT | | SIGNAL TO SET LATCH (a) +current limit WAVEFORM OF CLM+ TERMINAL WAVEFORM OF VOUT TERMINAL OSC WAVEFORM OF CF TERMINAL WAVEFORM OF CLM- TERMINAL VIHCLM= -200mV CURRENT LIMIT | | SIGNAL TO SET LATCH (b) -current limit WAVEFORM OF VOUT TERMINAL Fig.11 Operating waveforms of current limiting circuit 2tENESAS (15/ 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL Itis rather recommended to use not "CLM+" but "CLM-" terminal,as the influence from the gate drive current of MOS-FIT can be eliminated and wide voltage rating of + 4V to -4V is guaranteed for absolute maximum rating. There happen some noise voltage on Rc_m during the switching of power transistor due to the snubber circuit and stray capacitor of the transformer windings. To eliminate the abnormal operation by the noise voltage,the low pass filter,which consists of RF and Cnr is used as shown in Fig.12. It is recommended to use 10 to 100 for Rnr because such range of Rn is not influenced by the flow-out current of some 200yA from CLM terminal and CneF is designed to have the enough value to absorb the noise voltage. + + M51995A q M51995A ae VOUT O \ VOUT O I I ANF CLM+ O44 GND or. CNE = RcLM ! wo] | | ANF RCLM | (a)ln case of CLM+ (b)In case of CLM- Fig.12 How to connect current limit circuit Intermittent action and oscillation control section When the internal current limiting circuit states to operate and also the VF level decreases to lower than the certain level of some 3V,the dead-time spreads and intermittent action and OSC control circuit(which is one of the timer-type-protection circuit}starts to operate. The intermittent action and OSC control circuit is the one to generate the control signal for oscillator and intermittent action circuit. Fig.13 shows the timing-chart of this circuit.When the output of intermittent action and oscillation control is at "high" level,the waveform of oscillator depends on the VF terminal voltage and the intermittent action circuit begins to operate. OSC WAVEFORM OF CF TERMINAL CURRENT LIMIT | | SIGNAL OUTPUT OF [| , | LATCH CURRENT LIMIT OUTPUT OF INTERMITTENT | | ACTION and OSC, CONTROL CIRCUIT (a) With current limit signal OSC WAVEFORM OF CF TERMINAL CURRENT LIMIT SIGNAL GND OUTPUT OF CURRENT LIMIT LATCH GND OUTPUT OF INTERMITTENT ACTION and OSC. GND CONTROL CIRCUIT (b) Without current limit signal Fig.13 Timing chart of intermittent and OSC.control circuit Intermittent action circuit section Intermittent action circuit will start to operate when the output signal from the intermittent action and oscillation control circuit are "high" and also VF terminal voltage is lower than VTHTIME of about 3V. Fig.14 shows the block diagram of intermittent action circuit. Transistor Q is on state when VF terminal voltage is higher than VTHTIME of about 3V,so the CT terminal voltage is near to GND potential. When VF terminal voltage is lower than VTHTIME,Q becomes off" and the CT has the possibility to be charged up. Under this condition, if the intermittent action and oscillation control signal become "high" the switch SWA will close only in this "high" duration and Crt is charged up by the current of 120A through SWa (SWs is open) and CT terminal potential will rise. The output pulse can be generated only this duration. When the CT terminal voltage reaches to 8V,the control logic circuit makes the SWa "off" and SW6e "on",in order to flow in the ITIMEOFF of 15UA to CT terminal. The IC operation will be ceased in the falling duration. On the other hand,when CT terminal voltage decreases to lower than 2V,the IC operation will be reset to original state,as the control logic circuit makes the SWa "on" and SWe "off". Therefore the parts in power circuit including secondary rectifier diodes are protected from the overheat by the over current. ITIMEON } (=120uA) VTHTIME (~ 3) A 7 swa| CONTROL LOGIC VE i ITIMEOFF (=15pA) Fig.14 Block diagram of intermittent action circuit 2tENESAS ( 16/ 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL NO OPERATING DURATION <== BV Fig.15 Waveform of CT terminal Fig.16 shows the Icc versus Vcc in this timer-off duration. In this duration the power is not supplied to IC from the third winding of transformer but through from the resistor R1 connected toVcc line. If the R1 shown in Fig.1 and 2 is selected adequate value,Vcc terminal voltage will be kept at not so high or low but adequate value,as the Icc versus Vcc characteristics has such the one shown in Fig. 16. 2.0 = e 15 v 8 - = Ww = 1.0 = oO E = & 5 05 0 0 5 10 15 #20 25 30 SUPPLY VOLTAGE Vec(V) Fig.16 Ice vs.Vcc in timer-off duration of intermittent action circuit To ground the CT terminal is recommended,when the intermittent mode is not used. In this case the oscillated frequency will become low but the IC will neither stop the oscillation nor change to the intermittent action mode,when the current limit function becomes to operate and the VF terminal voltage becomes low. Voltage detector circuit(DET) section The DET terminal can be used to control the output voltage which is determined by the winding ratio of fly back transformer in fly-back system or in case of common ground circuit of primary and secondary in feed forward system. The circuit diagram is quite similar to that of shunt regulator type 431 as shown in Fig.17.As well known from Fig.17 and Fig.18,the output of OP AMP has the current-sink ability,when the DET terminal voltage is higher than 2.5V but it becomes high impedance state when lower than 2.5V DET terminal and F/B terminal have inverting phase characteristics each other,so it is recommended to connect the resistor and capacitor in series between them for phase compensation. It is very important,one can not connect by resistor directly as there is the voltage difference between them and the capacitor has the DC stopper function. 3k Fig.17 Equivalent circuit diagram of voltage detector =7.1V 3k 50022 DET Fig.18 Equivalent circuit diagram of voltage detector ON-OFF circuit section Fig.19 shows the circuit diagram of ON-OFF circuit.The current flown into the ON-OFF terminal makes the Q4 "on" and the switching operation stop.On the other hand.the switching operation will recover as no current flown into ON/OFF terminal makes @4 "off" As the constant current source connected to Q4 base terminal has such the hysteresis characteristics of 20UA at operation and 3yA at stopping.So the unstable operation is not appeared even if the ON/OFF terminal voltage signal varies slowly. 2tENESAS (17 / 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL Fig.20 shows how to connect the ON/OFF terminal. The switching operation will stop by swich-off and operate by switch- on. Transistor or photo transistor can be replaced by this switch,of course.No resistor of 30 to 100kQ is connected and ON/OFF terminal is directly connected to GND,when it is not necessary to use the ON/OFF operation. Fig.21 shows the Icc versus Vcc characteristics in OFF state and Vcc will be kept at not so high or low but at the adequate voltage,when R1 shown in Fig.1 and 2 is selected properly. ON/OFF Q2 Q3 Q4 OPERATE STOP AT Q4 ON |:3nA AT STOPPING 1} |:20uA AT OPERATING Fig.19 ON/OFF circuit Vec 30k~100kKQ M51995A ON/OFF I Fig.20 Connecting of ON/OFF terminal 1.6 < 1.2 Do 2 z cc c 0.8 = oO E 5 id G (A 0 0 5 10 15 20 25 30 SUPPLY VOLTAGE Vec(V) Fig.21 Icc vs.Vcc in OFF state OVP circuit(over voltage protection circuit)section OVP circuit is basically positive feedback circuit constructed by Q2,Q3 as shown in Fig.22. Q2,Q3 turn on and the circuit operation of IC stops,when the input signal is applied to OVP terminal.(threshold voltage ~ 750mvV) The current value of 12 is about 150HA when the OVP does not operates but it decreases to about 2uA when OVP operates. It is necessary to input the sufficient larger current(BOOLA to 8mA)than |2 for triggering the OVP operation. The reason to decrease I2 is that it is necessary that Icc at the OVP rest supply voltage is small. It is necessary that OVP state holds by circuit current from R11 in the application example,so this IC has the characteristic of small Icc at the OVP reset supply voltage(~stand-by current + 20yA) On the other hand,the circuit current is large in the higher supply voltage,so the supply voltage of this IC doesn't become so high by the voltage drop across R1. This characteristic is shown in Fig.23. The OVP terminal input current in the voltage lower than the OVP threshold voltage is based on I2 and the input current in the voltage higher than the OVP threshold voltage is the sum of the current flowing to the base of Q3 and the current flowing from the collector of Q2 to the base. For holding in the latch state,it is necessary that the OVP terminal voltage is kept in the voltage higher than VBE of Q3. So if the capacitor is connected between the OVP terminal and GND,even though Q2 tums on in a moment by the surge voltage,etc,this latch action does not hold if the OVP terminal voltage does not become higher than Vee of Q3 by charging this capacitor. For resetting OVP state,it is necessary to make the OVP terminal voltage lower than the OVP L threshold voltage or make Vcc lower than the OVP reset supply voltage. As the OVP reset voltage is settled on the rather high voltage of 9.0V,SMPS can be reset in rather short time from the switch-off of the AC power source if the smoothing capacitor is not so large value. 2tENESAS (18 / 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL CIRCUIT CURRENT Iec(mA) Vcc O ? 7.8V 1 100A 8k lt 12k a1 -# > a2) 400 ove Q3 2.5k 1 GND = l1=0 when OVP operates Fig.22 Detail diagram of OVP circuit OVP RESET POINT 8.82V(-30C) 8.97V(25C) 9.07V(85C) Ta=-30C ___1_ | Ta=25C Ta=85C 0 5 10 15 20 2 30 3 40 SUPPLY VOLTAGE Vec(V) Fig.23 CIRCUIT CURRENT VS. SUPPLY VOLTAGE (OVP OPERATION) Output section It is required that the output circuit have the high sink and source abilities for MOS-FET drive. it is well known that the "totempole circuit has high sink and source ability. However, it has the demerit of high through current. For example,the through current may reach such the high current level of 1A, if type M51995A has the "conventional" totempole circuit.For the high frequency application such as higher than 100kHz,this through current is very important factor and will cause not only the large Icc current and the inevitable heat-up of IC but also the noise voltage. This IC uses the improved totempole circuit,so without deteriorating the characteristic of operating speed,its through current is approximately 100mA. APPLICATION NOTE OF TYPE M51995AP/FP Design of start-up circuit and the power supply of IC (1)The start-up circuit when it is not necessary to set the start and stop input voltage Fig.24 shows one of the example circuit diagram of the start-up circuit which is used when it is not necessary to set the start and stop voltage. It is recommended that the current more than 300U/A flows through R11 in order to overcome the operation start-up current Icc(START) and Cvcc is in the range of 10 to 47uF.The product of R1 by Cvcc causes the time delay of operation,so the response time will be long if the product is too much large. RECTIFIED DC VOLTAGE FROM MAIN TRANSFORMER SMOOTHING CAPACITOR Ri VE ( Veo M51995A + Vee THIRD WINDING OR BIAS WINDING GND Fig.24 Start-up circuit diagram when it is not necessary to set the start and stop input voltage Just after the start-up,the Icc current is supplied from Cvcc,however,under the steady state condition ,IC will be supplied from the third winding or bias winding of transformer,the winding ratio of the third winding must be designed so that the induced voltage may be higher than the operation-stop voltage Vcc(SToP). The Vcc voltage is recommended to be 12V to 17V as the normal and optimum gate voltage is 10 to 15V and the output voltage(VoHu) of type M51995AP/FP is about(Vcc-2V). 2tENESAS (19/ 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL It is not necessary that the induced voltage is settled higher than the operation start-up voltage Vcc(sTART),and the high gate drive voltage causes high gate dissipation,on the other hand,too low gate drive voltage does not make the MOS-FET fully on- state or the saturation state. RECTIFIED DC VIN * PRIMARY WINDING VOLTAGE FROM NP OF TRANSFORMER SMOOTHING CAPACITOR 4 a VF Voc Ne THIRD WINDING OF TRANSFORMER + MS1995A Re = az CVec GND Fig.25 Start-up circuit diagram when it is not necessary to set the start and stop input voltage (2)The start-up circuit when it is not necessary to set the start and stop input voltage It is recommend to use the third winding of "forward winding" or "positive polarity" as shown in Fig.25,when the DC source voltages at both the IC operation start and stop must be settled at the specified values. The input voltage(VIN(START)),at which the IC operation starts,is decided by R1 and R2 utilizing the low start-up current characteristics of type M51995AP/FP. The input voltage(Vin(stop)),at which the IC operation stops,is decided by the ratio of third winding of transformer. The VIN(START) and Vin(sTOP) are given by following equations. VIN(START)= R1 * loc + ce + 1) * VOC(START)......0.....(9) N VIN(STOP)= (Vec(STOP)-VF) C + + V'IN RIP(P-P),.........(10) where IccL is the operation start-up current of IC Vec(START) is the operation start-up voltage of IC Vec(sTop) is the operation stop voltage of IC VF is the forward voltage of rectifier diode V'n(P-P) is the peak to peak ripple voltage of 3 Ne Vec terminal = Np V'INRIP(P-P) It is required that the Vin(starRT) must be higher than Vin(sToP). When the third winding is the "fly back winding or "reverse polarity",the Vin(sTarRT) can be fixed, however, VIN(STOP) can not be settled by this system,so the auxiliary circuit is required. (3)Notice to the Vec,Vcc line and GND line To avoid the abnormal IC operation, it is recommended to design the Vcc is not vary abruptly and has few spike voltage,which is induced from the stray capacity between the winding of main transformer. To reduce the spike voltage,the Cvcc,which is connected between Vcc and ground,must have the good high frequency characteristics. To design the conductor-pattern on PC board,following cautions must be considered as shown in Fig.26. (a)To separate the emitter line of type M51995A from the GND line of the IC (b)The locate the Cvcc as near as possible to type M51995A and connect directly (c)To separate the collector line of type M51995A from the Vcc line of the IC (d)To connect the ground terminals of peripheral parts of ICs to GND of type M51995A as short as possible MAIN COLLECTOR vec ( ; Y~ TRANSFORMER THIRD WINDING M51995A OF OUTPUT RcLm owen ann { / + CVcc Be Fig.26 How to design the conductor-pattern of type M51995A on PC board(schematic example) (4)Power supply circuit for easy start-up When IC start to operate,the voltage of the Cvcc begins to decrease till the Cvcc becomes to be charged from the third winding of main-transformer as the Icc of the IC increases abruptly.In case shown in Fig.24 and 25,some "unstable start- up" or fall to start-up" may happen, as the charging interval of Cvcc is very short duration;that is the charging does occur only the duration while the induced winding voltage is higher than the Cvcc voltage, if the induced winding voltage is nearly equal to the "operation-stop voltage" of type M51995. It is recommended to use the 10 to 47uF for Cvcc1,and about 5 times capacity bigger than Cvcc1 for Cvcca in Fig.27. 2tENESAS (20 / 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL +d MAIN Mec TRANSFORMER THIRD WINDING M51995A + is CVec1| CVec2 GND Fig.27 DC source circuit for stable start-up OVP circuit (1)To avoid the miss operation of OVP It is recommended to connect the capacitor between OVP terminal and GND for avoiding the miss operation by the spike noise. The OVP terminal is connected with the sink current source (~150pA) in IC when OVP does not operate,for absorbing the leak current of the photo coupler in the application. So the resistance between the OVP terminal and GND for leak- cut is not necessary. If the resistance is connected,the supply current at the OVP reset supply voltage becomes large. As the result,the OVP reset supply voltage may become higher than the operation stop voltage. In that case,the OVP action is reset when the OVP is triggered at the supply voltage a little high than the operation stop voltage. So it should be avoided absolutely to connect the resistance between the OVP terminal and GND. oe 10k le a. M51995A (+ ove PHOTO COUPLER + a GND Fig.28 Peripheral circuit of OVP terminal TO MAIN TRANSFORMER > =A 9 a + + | Voc alll | aE HE ] CrIN/R2 | Cvec | M51995A |@nb THE TIME CONSTANT OF THIS PART SHOULD BE SHORT Fig.29 Example circuit diagram to make the OVP-reset-time fast MAIN TRANSFORMER THIRD WINDING 4700 MS51995A a= CVec GND FIG.30 OVP setting method using the induced third winding voltage on fly back system (2)Application circuit to make the OVP-reset time fast The reset time may becomes problem when the discharge time constant of Crin * (R1+R2) is long. Under such the circuit condition, it is recommended to discharge the Cvcc forcedly and to make the Vcc low value.This makes the OVP-reset time fast. (3)OVP setting method using the induced third winding voltage on fly back system For the over voltage protection (OVP),the induced fly back type third winding voltage can be utilized,as the induced third winding voltage depends on the output voltage.Fig.30 shows one of the example circuit diagram. 2tENESAS (21/ 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL Current limiting circuit (1)Peripheral circuit of CLM+,CLM- terminal Fig.31 and 32 show the example circuit diagrams around the CLM+ and CLM- terminal.It is required to connect the low pass filter,as the main current or drain current contains the spike current especially during the turn-on duration of MOS-FIT. 1,000pF to 22,000pF is recommended for Cnr and the RNF1 and Rnr2 have the functions both to adjust the "current- detecting-sensitivity and to consist the low pass filter. r, t CFIN 4 INPUT jal b, SMOOTHING Vee COLLECTOR CAPACITOR + = Cyee VOUT HO M51995A RNF1 RNF2 RCLM Pano EMITTER + + Fig.31 Peripheral circuit diagram of CLM+ terminal =n + CFIN 4 INPUT aon des oe VOUT 2 Cvee {-O$ Wi LO GND RNF1 Fig.32 Peripheral circuit diagram of CLM- terminal To design the Rne1 and Rnrz,it is required to consider the influence of CLM terminal source current(liINCLM+ or INFCLIV-), which value is in the range of 90 to 270pA. In order to be not influenced from these resistor paralleled value of RNFi and Rnr2,(RANF1/RNF2)is recommended to be less than 10022. The Reto should be the non-inductive resistor. (2)Over current limiting curve (a)In case of feed forward system Fig.33 shows the primary and secondary current wave-forms under the current limiting operation. At the typical application of pulse by pulse primary current detecting circuit,the secondary current depends on the primary current.As the peak value of secondary current is limited to specified value,the characteristics curve of output voltage versus output current become to the one as shown in Fig.34. Lo <1 CLM+ WW ale JCNF CLM+ TENE RNF2 RCLM (b) Primary and secondary current Fig.33 Primary and secondary current waveforms under the current limiting operation condition on feed forward system OUTPUT VOLTAGE ______+ OUTPUT CURRENT Fig.34 Over current limiting curve on feed forward system The demerit of the pulse by pulse current limiting system is that the output pulse width can not reduce fo less than some value because of the delay time of low pass filter connected to the CLM terminal and propagation delay time TeocLm from CLM terminal to output terminal of type M51995A.The typical TeocLm is 100ns. As the frequency becomes higher,the delay time must be shorter.And as the secondary output voltage becomes higher,the dynamic range of on-duty must be wider;it means that it is required to make the on-duration much more narrower. So this system has the demerit at the higher oscillating frequency and higher output voltage applications. To improve these points,the oscillating frequency is set low using the characteristics of VF terminal.When the current limiting circuit operates under the over current condition,the oscillating frequency decreases in accordance with the decrease of VF terminal voltage,if the VF is lower than 3.5V.And also the dead time becomes longer. 2tENESAS (22 / 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL Under the condition of current limiting operation,the output current |2 continues as shown in Fig.33.So the output voltage depends on the product of the input primary voltage Vin and the on-duty. If the third winding polarity is positive ,the Vcc depends on Vin,so it is concluded that the smoothed voltage of Vout terminal depends on the output DC voltage of the SMPS. So the sharp current limiting characteristics will be got,if the Vout voltage if feed back to VF terminal through low pass filter as shown in Fig.35. M51995A I CVFFB Fig.35 Feed back loop through low pass filter from Vout to VF terminal It is recommended to use 15kQ for Rvere,and 10,000pF for Cvere in Fig.35. Fig.36 shows how to control the knee point where the frequency becomes decrease. FROM TO VF FROM TO VF FROM TO VF TO MAKE THE KNEE TO MAKE THE KNEE POINT HIGH POINT LOW Fig.36 How to control the knee point (b)In case of fly back system The DC output voltage of SMPS depends on the Vcc voltage of type M51995A when the polarity of the third winding is negative and the system is fly back.So the operation of type M51995A will stop when the Vcc becomes lower than "Operation-stop voltage" of M51995A when the DC output voltage of SMPS decreases under specified value at over load condition. Lu o A 5 POINT THAT Voc VOLTAGE a ~ ORTHIRD WINDING 5 wert VOLTAGE DECREASES = att UNDER "OPERATION-STOP a et VOLTAGE" oO ao DC OUTPUT CURRENT Fig.37 Over current limiting curve on fly back system However,the M51995A will non-operate and operate intermittently,as the Vcc voltage rises in accordance with the decrease of Icc current. The fly back system has the constant output power characteristics as shown in Fig.37 when the peak primary current and the operating frequency are constant. To control the increase of DC output current,the operating frequency is decreased using the characteristics of VF terminal when the over current limiting function begins to operate. The voltage which mode by dividing the Vcc is applied to VF terminal as shown in Fig.38,as the induced third winding voltage depends on the DC output voltage of SMPS. 15kQ or less is recommended for Re in Fig.38,it is noticed that the current flows through Ri and Re will superpose on the Icc(START) current. If the Ri is connected to Cvcc2 in Fig.27,the current flows through Ri and Ra is independent of the Icc(sTAAT). ( ) COLLECTOR M51995A Fig.38 Circuit diagram to make knee point low on fly back system (c)Application circuit to keep the non-operating condition when over load current condition will continue for specified duration The CT terminal voltage will begin to rise and the capacitor connected to CT terminal will be charged-up,if the current limiting function starts,and VF terminal voltage decreases below VTHTIME(~3V). If the charged-up CT terminal voltage is applied to OVP terminal through the level-shifter consisted of buffer transistor and resistor,it makes type M51995A keep non-operating condition. 2tENESAS (23 / 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL cT CT oe st | M51995A Fig.39 Application circuit diagram to keep the non-operating condition when over load current condition will continue for specified duration GATE-SOURCE VOLTAGE Ves(V) Output circuit (1)The output terminal characteristics at the Vcc voltage lower than the "Operation-stop" voltage TO MAIN TRANSFORMER Vout M51995A 100ko2 RLM Fig.40 Circuit diagram to prevent the MOS-FIT gate potential rising The output terminal has the current sink ability even though the Vcc voltage lower than the "Operation-stop" voltage or Vcc(stor) (It means that the terminal is "Output low state" and please refer characteristics of output low voltage versus sink current.) This characteristics has the merit not to damage the MOS-FIT at the stop of operation when the Vcc voltage decreases lower than the voltage of Vcce(stor),as the gate charge of MOS- FIT,which shows the capacitive load characteristics to the output terminal,is drawn out rapidly. The output terminal has the draw-out ability above the Vcc voltage of 2V,however,lower than the 2V,it loses the ability and the output terminal potential may rise due to the leakage current. In this case, it is recommended to connect the resistor of 100kQ between gate and source of MOS-FIT as shown in Fig.40. (2)MOS-FIT gate drive power dissipation Fig.41 shows the relation between the applied gate voltage and the stored gate charge. In the region (1) ,the charge is mainly stored at Cas as the depletion is spread and Ceo is small owing to the off-state of MOS-FIT and the high drain voltage. In the region (2) ,the Cop is multiplied by the "mirror effect" as the characteristics of MOS-FIT transfers from off-state to on- state. In the region 3) ,both the Cap and Ces affect to the characteristics as the MOS-FIT is on-state and the drain voltage is low. ho o on o a DRAIN -vps=80V. vps=200V | rD _vos=s20v, || bon 3 1 cps f | | | ante = vb 4 cas Vas a SOURCE 1 lo=4.A 4 8 12 16 20 TOTAL STORED GATE CHARGE(nC) Fig.41 The relation between applied gate-source voltage and stored gate charge The charging and discharging current caused by this gate charge makes the gate power dissipation. The relation between gate drive current Ip and total gate charge Qasu is shown by following equation; ID=CIGSH fOSC ---1cceesssersetcccessersereeteeee( 1) Where fosc is switching frequency As the gate drive current may reach up to several tenths milliamperes at 500kHz operation,depending on the size of MOS-FIT,the power dissipation caused by the gate current can not be neglected. In this case,following action will be considered to avoid heat up of type M51995A. (1) To attach the heat sink to type M51995A (2) To use the printed circuit board with the good thermal conductivity (3) To use the buffer circuit shown next section (3)Output buffer circuit Itis recommended to use the output buffer circuit as shown in Fig.42,when type M51995A drives the large capacitive load or bipolar transistor. 2tENESAS ( 24/ 27 )MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL Vout M51995A Fig.42 Output buffer circuit diagram DET Fig.43 shows how to use the DET circuit for the voltage detector and error amplifier. For the phase shift compensation, it is recommended to connected the CR network between det terminal and F/B terminal. ct DETECTING c VOLTAGE i Ny Ri . M51995A DET ce RS wt C45 J Fig.43 How to use the DET circuit for the voltage detector Fig.44 shows the gain-frequency characteristics between point B and point C shown in Fig.43. The G1,e1 and2 are given by following equations; Gi= B8 PARQ cesssssssssssssssssssessesseesessessesseeeees(11) 4 iti PORE socetennenensesareenceenant ot oye C1+C2 C1iC2eR3 cesses eeseeseesareeeseersseseeeeee TQ) At the start of the operation,there happen to be no output pulse due to F/B terminal current through C1 and C2,as the potential of F/B terminal rises sharply just after the start of the operation. * GAVDET (DC VOLTAGE GAIN) Not to lack the output pulse,is recommended to connect the capacitor C4 as shown by broken line. Please take notice that the current flows through the R1 and R2 are superposed to Icc(STaART).Not to superpose,R1 is connected to Cvec2 as shown in Fig.27. How to get the narrow pulse width during the start of operation Fig.45 shows how to get the narrow pulse width during the start of the operation. |f the pulse train of forcedly narrowed pulse- width continues too long,the misstart of operation may happen,so it is recommended to make the output pulse width narrow only for a few pulse at the start of operation.0.1pF is recommended for the C. FIB M51995A 1002 TO PHOTO c COUPLER | Fig.45 How to get the narrow pulse width during the start of operation How to synchronize with external circuit Type M51995A has no function to synchronize with external circuit, however,there is some application circuit for synchronization as shown in Fig.46.If this circuit is used,the synchronization may be out of order at the overload condition when the current limiting function starts to operate and VF terminal voltage becomes lower than 3V. M51995A T-ON CF T-OFF CT fe 120nA SYNCHRONOU $ PULSE RON ao 3 o Bf GIpssteresesne, g 7 a 56 Log & | wa 5 w aa Fig.44 Gain-frequency characteristics between oF point B and C shown in Fig.43 a ov Nl a2 fe gw > | = a a ne ov MINIMUMPULSE 7 WIDTH OF MAXIMUM PULSE WIDTH OF PULSE OS = SYNCHRONOUS PULSE Fig.46 How to synchronize with external circuit (25/ 27) 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL s s \\\ we 3 Vee ie VOUT M51995A -Vss GND EMITTER Fig.47 Driver circuit diagram (1) for bipolar transistor 9 Qeuoen | Driver circuit for bipolar transistor When the bipolar transistor is used instead of MOS-FIT,the vee Vour base current of bipolar transistor must be sinked by the BIPOLAR negative base voltage source for the switching-off duration, in M51995A TRANSISTOR order to make the switching speed of bipolar transistor fast one. In this case,over current can not be detected by detecting GND EMITTER resistor in series to bipolar transistor,so it is recommended to use the CT(current transformer). For the low current rating transistor,type M51995A can drive it directly as shown in Fig.48. ~ ~ ~ Fig.48 Driver circuit diagram (2) for bipolar transistor Attention for heat generation The maximum ambient temperature of type M51995A is +85C,however,the ambient temperature in vicinity of the IC is not uniform and varies place by place,as the amount of power dissipation is fearfully large and the power dissipation is generated locally in the switching regulator. So it is one of the good idea to check the IC package temperature. The temperature difference between IC junction and the surface of IC package is 15C or less,when the IC junction temperature is measured by temperature dependency of forward voltage of pin junction,and IC package temperature is measured by "thermo- viewer" and also the IC is mounted on the "phenol-base" PC board in normal atmosphere. So it is concluded that the maximum case temperature(surface temperature of IC) rating is 120C with adequate margin. As type M51995 has the modified totempole driver circuit, the transient through current is very small and the total power H-Axis : 20ns/div dissipation is decreased to the reasonable power level.Fig.49 V-Axis : 50mA/div shows the transient rush (through)current waveforms at the rising AT RISING EDGE OF OUTPUT PULSE and falling edges of output pulse,respectively. H-Axis : 20ns/div V-Axis : 10mAvdiv AT RISING EDGE OF OUTPUT PULSE Fig.49 Through current waveform of totempole driver circuit at no-load and Vcc of 18V condition (26 / 27 ) 2tENESASAC MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL APPLICATION EXAMPLE Feed forward types SMPS with multi-output. M5 + COLLECTOR w L 9 1995AP z Ron ty ON/OFF 2tENESAS (27/ 27 )