STM8S103K3 STM8S103F3 STM8S103F2 Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data EEPROM,10-bit ADC, 3 timers, UART, SPI, IC Interrupt management Nested interrupt controller with 32 interrupts LQFP32 7x7 UFQFPN32 5x5 * * Up to 27 external interrupts on 6 vectors SDIP32 400 mils Timers Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization * TSSOP20 SO20W 300 mils UFQFPN20 3x3 Features Core 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline * * Extended instruction set Memories Program memory: 8 Kbytes Flash; data retention 20 years at 55 C after 10 kcycles * memory: 640 bytes true data EEPROM; * Data endurance 300 kcycles * RAM: 1 Kbytes Clock, reset and supply management 2.95 to 5.5 V operating voltage * clock control, 4 master clock sources: * Flexible - Low power crystal resonator oscillator - External clock input - Internal, user-trimmable 16 MHz RC - Internal low power 128 kHz RC * Clock security system with clock monitor management: * Power Low - power modes (wait, active-halt, halt) - Switch-off peripheral clocks individually active, low consumption power-on * Permanently and power-down reset June 2012 general purpose timer, with 3 CAPCOM * 16-bit channels (IC, OC or PWM) * 8-bit basic timer with 8-bit prescaler * Auto wake-up timer watchdog and independent watchdog * Window timers Communications interfaces UART with clock output for synchronous operation, Smartcard, IrDA, LIN master mode * * SPI interface up to 8 Mbit/s * I C interface up to 400 Kbit/s 2 Analog to digital converter (ADC) 10-bit, 1 LSB ADC with up to 5 multiplexed channels, scan mode and analog watchdog * I/Os Up to 28 I/Os on a 32-pin package including 21 high sink outputs * robust I/O design, immune against current * Highly injection Development support Embedded single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging * Unique ID 96-bit unique key for each device * DocID15441 Rev 9 1/117 www.st.com Contents STM8S103K3 STM8S103F3 STM8S103F2 Contents 1 2 3 4 Introduction ..............................................................................................................8 Description ...............................................................................................................9 Block diagram ........................................................................................................10 Product overview ...................................................................................................11 4.1 Central processing unit STM8 .....................................................................................11 4.2 Single wire interface module (SWIM) and debug module (DM) ..................................11 4.3 Interrupt controller .......................................................................................................12 4.4 Flash program and data EEPROM memory ................................................................12 4.5 Clock controller ............................................................................................................13 4.6 Power management ....................................................................................................14 4.7 Watchdog timers ..........................................................................................................14 4.8 Auto wakeup counter ...................................................................................................15 4.9 Beeper ........................................................................................................................15 4.10 TIM1 - 16-bit advanced control timer .........................................................................15 4.11 TIM2 - 16-bit general purpose timer ..........................................................................16 4.12 TIM4 - 8-bit basic timer ..............................................................................................16 4.13 Analog-to-digital converter (ADC1) ............................................................................16 4.14 Communication interfaces .........................................................................................17 4.14.1 UART1 ...............................................................................................17 4.14.2 SPI .....................................................................................................18 4.14.3 IC ......................................................................................................18 5 Pinout and pin description ...................................................................................19 5.1 STM8S103Kx UFQFPN32/LQFP32/SDIP32 pinout and pin description .....................20 5.2 STM8S103Fx TSSOP20/SO20/UFQFPN20 pinout and pin description .....................24 5.2.1 STM8S103Fx TSSOP20/SO20 pinout .................................................24 5.2.2 STM8S103Fx UFQFPN20 pinout ........................................................25 5.2.3 STM8S103Fx TSSOP20/SO20/UFQFPN20 pin description ................25 5.3 Alternate function remapping .......................................................................................27 6 Memory and register map .....................................................................................28 6.1 Memory map 6.2 Register map 6.2.1 6.2.2 6.2.3 ................................................................................................................28 ...............................................................................................................29 I/O port hardware register map ............................................................29 General hardware register map ..........................................................30 CPU/SWIM/debug module/interrupt controller registers .....................40 7 Interrupt vector mapping ......................................................................................42 8 Option bytes ...........................................................................................................44 8.1 Alternate function remapping bits ................................................................................46 2/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Contents 9 Unique ID ................................................................................................................49 10 Electrical characteristics ....................................................................................50 10.1 Parameter conditions .................................................................................................50 10.1.1 Minimum and maximum values .........................................................50 10.1.2 Typical values .....................................................................................50 10.1.3 Typical curves ....................................................................................50 10.1.4 Loading capacitor ...............................................................................50 10.1.5 Pin input voltage .................................................................................51 10.2 Absolute maximum ratings ........................................................................................51 10.3 Operating conditions ..................................................................................................53 10.3.1 VCAP external capacitor ....................................................................54 10.3.2 Supply current characteristics ............................................................55 10.3.3 External clock sources and timing characteristics .............................65 10.3.4 Internal clock sources and timing characteristics ...............................67 10.3.5 Memory characteristics ......................................................................70 10.3.6 I/O port pin characteristics .................................................................71 10.3.7 Reset pin characteristics ....................................................................79 10.3.8 SPI serial peripheral interface ............................................................82 2 10.3.9 I C interface characteristics ...............................................................85 10.3.10 10-bit ADC characteristics ................................................................86 10.3.11 EMC characteristics .........................................................................90 11 Package information ............................................................................................94 11.1 32-pin LQFP package mechanical data .....................................................................94 11.2 32-lead UFQFPN package mechanical data .............................................................96 11.3 20-lead UFQFPN package mechanical data .............................................................97 11.4 SDIP32 package mechanical data .............................................................................98 11.5 20-pin TSSOP package mechanical data ................................................................100 11.6 20-pin SO package mechanical data .......................................................................101 11.7 UFQFPN recommended footprint ............................................................................102 12 Thermal characteristics ....................................................................................104 12.1 Reference document ...............................................................................................105 12.2 Selecting the product temperature range ................................................................105 13 Ordering information .........................................................................................106 13.1 STM8S103 FASTROM microcontroller option list ...................................................106 14 STM8 development tools ..................................................................................111 14.1 Emulation and in-circuit debugging tools .................................................................111 14.2 Software tools ..........................................................................................................111 14.2.1 STM8 toolset ....................................................................................112 14.2.2 C and assembly toolchains ..............................................................112 14.3 Programming tools ..................................................................................................112 15 Revision history .................................................................................................113 DocID15441 Rev 9 3/117 List of tables STM8S103K3 STM8S103F3 STM8S103F2 List of tables Table 1. STM8S103xx access line features .............................................................................................9 Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14 Table 3. TIM timer features ....................................................................................................................16 Table 4. Legend/abbreviations for pinout tables ...................................................................................19 Table 5. UFQFPN32/LQFP32/SDIP32 pin description ...........................................................................21 Table 6. STM8S103Fx pin description ...................................................................................................25 Table 7. I/O port hardware register map ................................................................................................29 Table 8. General hardware register map ...............................................................................................30 Table 9. CPU/SWIM/debug module/interrupt controller registers .........................................................40 Table 10. Interrupt mapping ...................................................................................................................42 Table 11. Option bytes .........................................................................................................................113 Table 12. Option byte description ...........................................................................................................44 Table 13. STM8S103K alternate function remapping bits for 32-pin devices ........................................46 Table 14. STM8S103F alternate function remapping bits for 20-pin devices ........................................47 Table 15. Unique ID registers (96 bits) .................................................................................................113 Table 16. Voltage characteristics ...........................................................................................................51 Table 17. Current characteristics ...........................................................................................................52 Table 18. Thermal characteristics ..........................................................................................................52 Table 19. General operating conditions .................................................................................................53 Table 20. Operating conditions at power-up/power-down ......................................................................54 Table 21. Total current consumption with code execution in run mode at VDD = 5 V .............................55 Table 22. Total current consumption with code execution in run mode at VDD = 3.3 V ..........................56 Table 23. Total current consumption in wait mode at VDD = 5 V ............................................................57 Table 24. Total current consumption in wait mode at VDD = 3.3 V .........................................................57 Table 25. Total current consumption in active halt mode at VDD = 5 V ..................................................58 Table 26. Total current consumption in active halt mode at VDD = 3.3 V ...............................................59 Table 27. Total current consumption in halt mode at VDD = 5 V .............................................................60 Table 28. Total current consumption in halt mode at VDD = 3.3 V ..........................................................60 Table 29. Wakeup times .........................................................................................................................60 Table 30. Total current consumption and timing in forced reset state ....................................................61 Table 31. Peripheral current consumption .............................................................................................62 Table 32. HSE user external clock characteristics .................................................................................65 Table 33. HSE oscillator characteristics .................................................................................................66 Table 34. HSI oscillator characteristics ..................................................................................................67 Table 35. LSI oscillator characteristics ...................................................................................................69 Table 36. RAM and hardware registers ..................................................................................................70 Table 37. Flash program memory/data EEPROM memory ....................................................................70 Table 38. I/O static characteristics .........................................................................................................71 Table 39. Output driving current (standard ports) ..................................................................................73 Table 40. Output driving current (true open drain ports) ........................................................................74 Table 41. Output driving current (high sink ports) ..................................................................................74 Table 42. NRST pin characteristics ........................................................................................................79 Table 43. SPI characteristics ..................................................................................................................82 2 Table 44. I C characteristics ..................................................................................................................85 Table 45. ADC characteristics ................................................................................................................87 Table 46. ADC accuracy with RAIN < 10 k , VDD= 5 V .........................................................................87 Table 47. ADC accuracy with RAIN < 10 k RAIN, VDD = 3.3 V ..............................................................88 4/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 List of tables Table 48. EMS data ................................................................................................................................91 Table 49. EMI data .................................................................................................................................91 Table 50. ESD absolute maximum ratings .............................................................................................92 Table 51. Electrical sensitivities .............................................................................................................93 Table 52. 32-pin low profile quad flat package mechanical data ............................................................94 Table 53. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data .............................96 Table 54. 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package mechanical data ....98 Table 55. 32-lead shrink plastic DIP (400 ml) package mechanical data ..............................................98 Table 56. 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data .......................................................101 Table 57. 20-lead, plastic small outline (300 mils) mechanical data ....................................................101 Table 58. Thermal characteristics ........................................................................................................104 Table 59. Document revision history ....................................................................................................113 DocID15441 Rev 9 5/117 List of figures STM8S103K3 STM8S103F3 STM8S103F2 List of figures Figure 1. Block diagram .........................................................................................................................10 Figure 2. Flash memory organization ....................................................................................................13 Figure 3. STM8S103Kx UFQFPN32/LQFP32 pinout .............................................................................20 Figure 4. STM8S103Kx SDIP32 pinout .................................................................................................21 Figure 5. STM8S103Fx TSSOP20/SO20 pinout ....................................................................................24 Figure 6. STM8S103Fx UFQFPN20-pin pinout .....................................................................................25 Figure 7. Memory map ...........................................................................................................................28 Figure 8. Pin loading conditions .............................................................................................................50 Figure 9. Pin input voltage .....................................................................................................................51 Figure 10. fCPUmax versus VDD ..............................................................................................................54 Figure 11. External capacitor CEXT .......................................................................................................55 Figure 12. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz .............................................63 Figure 13. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V ....................................................63 Figure 14. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................64 Figure 15. Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz ..............................................64 Figure 16. Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V .....................................................65 Figure 17. Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................65 Figure 18. HSE external clocksource .....................................................................................................66 Figure 19. HSE oscillator circuit diagram ...............................................................................................67 Figure 20. Typical HSI frequency variation vs VDD @ 4 temperatures ..................................................69 Figure 21. Typical LSI frequency variation vs VDD @ 4 temperatures ...................................................69 Figure 22. Typical VIL and VIH vs VDD @ 4 temperatures ......................................................................72 Figure 23. Typical pull-up resistance vs VDD @ 4 temperatures ............................................................73 Figure 24. Typical pull-up current vs VDD @ 4 temperatures .................................................................73 Figure 25. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................75 Figure 26. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................75 Figure 27. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................76 Figure 28. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................76 Figure 29. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................77 Figure 30. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................77 Figure 31. Typ. VDD - VOH@ VDD = 5 V (standard ports) .......................................................................78 Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ...................................................................78 Figure 33. Typ. VDD - VOH@ VDD = 5 V (high sink ports) .......................................................................79 Figure 34. Typ. VDD - VOH@ VDD = 3.3 V (high sink ports) ....................................................................79 Figure 35. Typical NRST VIL and VIH vs VDD @ 4 temperatures ...........................................................80 Figure 36. Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................81 Figure 37. Typical NRST pull-up current vs VDD @ 4 temperatures ......................................................81 Figure 38. Recommended reset pin protection ......................................................................................82 Figure 39. SPI timing diagram - slave mode and CPHA = 0 ..................................................................84 Figure 40. SPI timing diagram - slave mode and CPHA = 1 ..................................................................84 (1) Figure 41. SPI timing diagram - master mode ...................................................................................85 2 Figure 42. Typical application with I C bus and timing diagram ............................................................89 Figure 43. ADC accuracy characteristics ...............................................................................................89 Figure 44. Typical application with ADC ................................................................................................90 Figure 45. 32-pin low profile quad flat package (7 x 7) ..........................................................................94 Figure 46. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ............................................96 Figure 47. 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) ................................97 6/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 List of figures Figure 48. 32-lead shrink plastic DIP (400 ml) package ........................................................................98 Figure 49. 20-pin, 4.40 mm body, 0.65 mm pitch .................................................................................101 Figure 50. 20-lead, plastic small outline (300 mils) package ...............................................................101 Figure 51. Recommended footprint for on-board emulation ................................................................102 Figure 52. Recommended footprint without on-board emulation .........................................................103 Figure 53. STM8S103x access line ordering information scheme ......................................................106 DocID15441 Rev 9 7/117 Introduction 1 STM8S103K3 STM8S103F3 STM8S103F2 Introduction This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016). * information on programming, erasing and protection of the internal Flash memory * For please refer to the STM8S Flash programming manual (PM0051). information on the debug and SWIM (single wire interface module) refer to the STM8 * For SWIM communication protocol and debug module user manual (UM0470). information on the STM8 core, please refer to the STM8 CPU programming manual * For (PM0044). 8/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 2 Description Description The STM8S103x access line 8-bit microcontrollers offer 8 Kbytes Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual (RM0016) refers to devices in this family as low-density. They provide the following benefits: performance, robustness, and reduced system cost. Device performance and robustness are ensured by advanced core and peripherals made in a state-of-the art technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system. The system cost is reduced thanks to an integrated true data EEPROM for up to 300 kwrite/erase cycles and a high system integration level with internal clock oscillators, watchdog and brown-out reset. Full documentation is offered as well as a wide choice of development tools. Table 1: STM8S103xx access line features Device STM8S103K3 STM8S103F3 STM8S103F2 Pin count 32 20 20 Maximum number of GPIOs (I/Os) 28 16 16 Ext. interrupt pins 27 16 16 Timer CAPCOM channels 7 7 7 Timer complementary outputs 3 2 2 A/D converter channels 4 5 5 High sink I/Os 21 12 12 Low density Flash program memory (bytes) 8K 8K 4K Data EEPROM (bytes) 640 640 RAM (bytes) 1K 1K (1) (1) (1) 640 1K 2 Peripheral set (1) Multipurpose timer (TIM1), SPI, I C, UART window WDG,independent WDG, ADC, PWM timer (TIM2), 8-bit timer (TIM4) No read-while-write (RWW) capability DocID15441 Rev 9 9/117 Block diagram 3 STM8S103K3 STM8S103F3 STM8S103F2 Block diagram Figure 1: Block diagram Reset block XTAL 1-16 MHz Clock controller Reset Reset RC int. 16 MHz Detector POR BOR RC int. 128 kHz Clock to peripherals and core Window WDG STM8 core Independent WDG Single wire debug interf. 8 Kbytes program Flash Debug/SWIM 400 Kbit/s 8 Mbit/s LIN master SPI emul. I2 C SPI Address and data bus 640 bytes data EEPROM 1 Kbyte RAM 16-bit advanced control timer (TIM1) UART1 16-bit general purpose timer (TIM2) 10/117 Up to 5 channels ADC1 1/2/4 kHz beep Beeper 8-bit basic timer (TIM4) AWU timer DocID15441 Rev 9 Up to 4 CAPCOM channels +3 complementary outputs Up to 3 CAPCOM channels STM8S103K3 STM8S103F3 STM8S103F2 4 Product overview Product overview The following section intends to give an overview of the basic features of the device functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. Architecture and registers Harvard architecture * * 3-stage pipeline * 32-bit wide program memory bus - single cycle fetching for most instructions Y 16-bit index registers - enabling indexed addressing modes with or without offset * Xandandread-modify-write type data manipulations 8-bit accumulator * * 24-bit program counter - 16-Mbyte linear memory space * 16-bit stack pointer - access to a 64 K-level stack * 8-bit condition code register - 7 condition flags for the result of the last instruction Addressing 20 addressing modes * indirect addressing mode for look-up tables located anywhere in the address * Indexed space * Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2-byte average instruction size * * Standard data movement and logic/arithmetic functions * 8-bit by 8-bit multiplication * 16-bit by 8-bit and 16-bit by 16-bit division * Bit manipulation * Data transfer between stack and accumulator (push/pop) with direct stack access * Data transfer using the X and Y registers or direct memory-to-memory transfers 4.2 Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming. DocID15441 Rev 9 11/117 Product overview STM8S103K3 STM8S103F3 STM8S103F2 SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers. R/W to RAM and peripheral registers in real-time * * R/W access to all resources by stalling the CPU * Breakpoints on all program-memory instructions (software breakpoints) * Two advanced breakpoints, 23 predefined configurations 4.3 Interrupt controller * Nested interrupts with three software priority levels * 32 interrupt vectors with hardware priority * Up to 27 external interrupts on 6 vectors including TLI * Trap and reset interrupts 4.4 Flash program and data EEPROM memory * 8 Kbytes of Flash program single voltage Flash memory * 640 bytes true data EEPROM * User option byte area Write protection (WP) Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes. To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to the figure below. The size of the UBC is programmable through the UBC option byte, in increments of 1 page (64-byte block) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: Main program memory: Up to 8 Kbytes minus UBC * * User-specific boot code (UBC): Configurable up to 8 Kbytes The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot 12/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Product overview program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines. Figure 2: Flash memory organization Data EEPROM memory Data memory area ( 640 bytes) Option bytes UBC area Remains write protected during IAP Low density Flash program memory (8 Kbytes) Programmable area from 64 bytes(1 page) up to 8 Kbytes (in 1 page steps) Program memory area Write access possible for IAP Read-out protection (ROP) The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. 4.5 Clock controller The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. * clock switching: Clock sources can be changed safely on the fly in run mode * Safe through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching. management: To reduce power consumption, the clock controller can stop the * Clock clock to the core, individual peripherals or memory. clock sources: Four different clock sources can be used to drive the master * Master clock: - 1-16 MHz high-speed external crystal (HSE) DocID15441 Rev 9 13/117 Product overview - STM8S103K3 STM8S103F3 STM8S103F2 Up to 16 MHz high-speed user-external clock (HSE user-ext) 16 MHz high-speed internal RC oscillator (HSI) 128 kHz low-speed internal RC (LSI) clock: After reset, the microcontroller restarts by default with an internal 2 MHz * Startup clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. security system (CSS): This feature can be enabled by software. If an HSE clock * Clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated. main clock output (CCO): This outputs an external clock for use by the * Configurable application. Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers Bit Peripheral Bit clock Peripheral Bit clock Peripheral Bit clock Peripheral clock PCKEN17 TIM1 PCKEN13 UART1 PCKEN27 Reserved PCKEN23 ADC PCKEN16 Reserved PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 I C PCKEN24 Reserved PCKEN20 Reserved 4.6 2 Power management For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset. * halt mode with regulator on: In this mode, the CPU and peripheral clocks are * Active stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset. halt mode with regulator off: This mode is the same as active halt with regulator * Active on, except that the main voltage regulator is powered off, so the wake up time is slower. mode: In this mode the microcontroller uses the least power. The CPU and peripheral * Halt clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset. 4.7 Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. 14/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Product overview Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application perfectly. The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 s up to 64 ms. 2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register. Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 s to 1 s. 4.8 Auto wakeup counter * Used for auto wakeup from active halt mode * Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock * LSI clock can be internally connected to TIM1 input capture channel 1 for calibration 4.9 Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. The beeper output port is only available through the alternate function remap option bit AFR7. 4.10 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver 16-bit up, down and up/down autoreload counter with 16-bit prescaler * independent capture/compare channels (CAPCOM) configurable as input capture, * Four output compare, PWM generation (edge and center aligned mode) and single pulse mode output * Synchronization module to control the timer with external signals DocID15441 Rev 9 15/117 Product overview STM8S103K3 STM8S103F3 STM8S103F2 * Break input to force the timer outputs into a defined state * Three complementary outputs with adjustable dead time * Encoder mode * Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break 4.11 TIM2 - 16-bit general purpose timer * 16-bit autoreload (AR) up-counter * 15-bit prescaler adjustable to fixed power of 2 ratios 1...32768 * 3 individually configurable capture/compare channels * PWM mode * Interrupt sources: 3 x input capture/output compare, 1 x overflow/update 4.12 TIM4 - 8-bit basic timer * 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 * Clock source: CPU clock * Interrupt source: 1 x overflow/update Table 3: TIM timer features Timer Counter size (bits) Prescaler Counting mode CAPCOM channels Complem. Ext. outputs trigger TIM1 16 Any integer from 1 to 65536 Up/down 4 3 Yes TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No 4.13 Timer synchronization/ chaining No Analog-to-digital converter (ADC1) The STM8S103xx family products contain a 10-bit successive approximation A/D converter (ADC1) with up to 5 external multiplexed input channels and the following main features: Input voltage range: 0 to VDD * * Conversion time: 14 clock cycles * Single and continuous and buffered continuous conversion modes * Buffer size (n x 10 bits) where n = number of input channels * Scan mode for single and continuous conversion of a sequence of channels 16/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Product overview * Analog watchdog capability with programmable upper and lower thresholds * Analog watchdog interrupt * External trigger input * Trigger from TIM1 TRGO * End of conversion (EOC) interrupt 4.14 Communication interfaces The following communication interfaces are implemented: UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA mode, single wire mode, LIN2.1 master capability * * SPI : Full and half-duplex, 8 Mbit/s * IC: Up to 400 Kbit/s 4.14.1 UART1 Main features One Mbit/s full duplex SCI * * SPI emulation * High precision baud rate generator * Smartcard emulation * IrDA SIR encoder decoder * LIN master mode * Single wire half duplex mode Asynchronous communication (UART mode) Full duplex communication - NRZ standard format (mark/space) * transmit and receive baud rates up to 1 Mbit/s (f /16) and capable of * Programmable following any standard baud rate regardless of the input frequency * Separate enable bits for transmitter and receiver receiver wakeup modes: * TwoAddress bit (MSB) - Idle line (interrupt) * Transmission error detection with interrupt generation * Parity control CPU Synchronous communication Full duplex synchronous transfers * * SPI master operation * 8-bit data communication * Maximum speed: 1 Mbit/s at 16 MHz (f CPU/16) DocID15441 Rev 9 17/117 Product overview STM8S103K3 STM8S103F3 STM8S103F2 LIN master mode Emission: Generates 13-bit synch break frame * * Reception: Detects 11-bit break frame 4.14.2 SPI * Maximum speed: 8 Mbit/s (f /2) both for master and slave * Full duplex synchronous transfers * Simplex synchronous transfers on two lines with a possible bidirectional data line * Master or slave operation - selectable by hardware or software * CRC calculation * 1 byte Tx and Rx buffer * Slave/master selection input pin MASTER 4.14.3 IC master features: * IC Clock generation - Start and stop generation slave features: * IC Programmable I2C address detection - Stop bit detection * Generation and detection of 7-bit/10-bit addressing and general call different communication speeds: * Supports - Standard speed (up to 100 kHz) - Fast speed (up to 400 kHz) 18/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 5 Pinout and pin description Pinout and pin description Table 4: Legend/abbreviations for pinout tables Type I= Input, O = Output, S = Power supply Level Input CM = CMOS Output HS = High sink Output speed O1 = Slow (up to 2 MHz) O2 = Fast (up to 10 MHz) O3 = Fast/slow programmability with slow as default state after reset O4 = Fast/slow programmability with fast as default state after reset Port and control configuration Reset state Input float = floating, wpu = weak pull-up Output T = True open drain, OD = Open drain, PP = Push pull Bold X (pin state after internal reset release). Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release. DocID15441 Rev 9 19/117 Pinout and pin description 5.1 STM8S103K3 STM8S103F3 STM8S103F2 STM8S103Kx UFQFPN32/LQFP32/SDIP32 pinout and pin description PB7 PF4 PD1 (HS)/SWIM PD2 (HS) [TIM2_CH3] PD3 (HS)/TIM2_CH2/ADC_ETR PD4 (HS)/BEEP/TIM2_CH1 PD5 (HS)/UART1_TX PD0 (HS)/ TIM1_BKIN [CLK_CCO] PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4/CLK_CCO PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1/UART1_CK PE5 (HS)/SPI_NSS TIM1_CH1N/AIN0/(HS) PB0 [SPI_NSS] TIM2_CH3/(HS) PA3 TIM1_CH2N/ AIN1/(HS) PB1 VDD TIM1_CH3N/ AIN2/(HS) PB2 VSS VCAP TIM1_ETR/AIN3/(HS) PB3 OSCOUT/PA2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 I2C_SCL/(T) PB4 OSCIN/PA1 1 2 3 4 5 6 7 8 PB6 I2C_SDA/ (T) PB5 NRST PD6 (HS)/UART1_RX PD7 (HS)/TLI [TIM1_CH4] Figure 3: STM8S103Kx UFQFPN32/LQFP32 pinout 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 20/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Pinout and pin description Figure 4: STM8S103Kx SDIP32 pinout [TIM2_CH2] ADC_ETR/(HS) PD3 BEEP/TIM2_CH1/(HS) PD4 UART1_TX(/HS) PD5 UART1_RX/(HS) PD6 [TIM1_CH4] TLI/(HS) PD7 NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD [SPI_NSS] TIM2_CH3/(HS) PA3 PF4 PB7 PB6 I2C_SDA/(T) PB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PD2 (HS) [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM1_BKIN [CLK_CCO] PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PC5 (HS)/SPI_SCK PC4( HS)/TIM1_CH4/CLK_CCO PC3 (HS)/TIM1_CH3 PC2( HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1/UART1_CK PE5/SPI_NSS PB0 (HS)/TIM1_CH1N/AIN0 PB1 (HS)/TIM1_CH2N/AIN1 PB2 (HS)/TIM1_CH3N/AIN2 PB3 (HS)/TIM1_ETR/AIN3 PB4 (T)/I2C_SCL 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). Table 5: UFQFPN32/LQFP32/SDIP32 pin description SDIP 32 LQFP/ UFQFP 32 Input Pin name Output Main function Default alternate Type (after function Ext. High floating wpu (1) Speed OD PP reset) interrupt sink 6 1 NRST I/O X 7 2 PA1/ (2) OSCIN I/O X X X O1 X X Port A1 Resonator/ crystal in 8 3 PA2/ OSCOUT I/O X X X O1 X X Port A2 Resonator/ crystal out 9 4 VSS S Digital ground 10 5 VCAP S 1.8 V regulator capacitor 11 6 VDD S Digital power supply 12 7 PA3/ TIM2_CH3 [SPI_NSS] I/O X X Alternate function after remap [option bit] Reset X HS O3 X DocID15441 Rev 9 X Port A3 Timer 2 channel 3 SPI master/ slave select [AFR1] 21/117 Pinout and pin description SDIP 32 LQFP/ UFQFP 32 STM8S103K3 STM8S103F3 STM8S103F2 Input Pin name Output Type Main function Default alternate (after function Ext. High floating wpu (1) Speed OD PP reset) interrupt sink 13 8 PF4 I/O X X O1 X X Port F4 14 9 PB7 I/O X X X O1 X X Port B7 15 10 PB6 I/O X X X O1 X X Port B6 16 11 PB5/ 2 I C_SDA I/O X X O1 (3) T Port B5 2 I C data 17 12 PB4/ 2 I C_SCL I/O X X O1 (3) T Port B4 2 I C clock 18 13 PB3/AIN3/ TIM1_ETR I/O X X X HS O3 X X Port B3 Analog input 3/ Timer 1 external trigger 19 14 PB2/AIN2/ TIM1_CH3N I/O X X X HS O3 X X Port B2 Analog input 2/ Timer 1 - inverted channel 3 20 15 PB1/AIN1/ TIM1_CH2N I/O X X X HS O3 X X Port B1 Analog input 1/ Timer 1 - inverted channel 2 21 16 PB0/AIN0/ TIM1_CH1N I/O X X X HS O3 X X Port B0 Analog input 0/ Timer 1 - inverted channel 1 22 17 PE5/ I/O X X X HS O3 X X Port E5 SPI master/slave select SPI_NSS 23 18 PC1/ TIM1_CH1/ UART1_CK I/O X X X HS O3 X X Port C1 Timer 1 - channel 1 UART1 clock 24 19 PC2/ TIM1_CH2 I/O X X X HS O3 X X Port C2 Timer 1 - channel 2 25 20 PC3/ TIM1_CH3 I/O X X X HS O3 X X Port C3 Timer 1 - channel 3 26 21 PC4/ TIM1_CH4/ CLK_CCO I/O X X X HS O3 X X Port C4 Timer 1 - channel 4 /configurable clock output 27 22 PC5/ SPI_SCK I/O X X X HS O3 X X Port C5 SPI clock 28 23 PC6/ SPI_MOSI I/O X X X HS O3 X X Port C6 SPI master out/slave in 22/117 DocID15441 Rev 9 Alternate function after remap [option bit] STM8S103K3 STM8S103F3 STM8S103F2 SDIP 32 LQFP/ UFQFP 32 Input Pin name Pinout and pin description Output Type Main function Default alternate (after function Ext. High floating wpu (1) Speed OD PP reset) interrupt sink 29 24 PC7/ SPI_MISO I/O X X X HS O3 X X Port C7 SPI master in/ slave out 30 25 PD0/ TIM1_BKIN [CLK_CCO] I/O X X X HS O3 X X Port D0 Timer 1 - break input 31 26 PD1/ SWIM (4) I/O X X X HS O4 X X Port D1 SWIM data interface 32 27 PD2 [TIM2_CH3] I/O X X X HS O3 X X Port D2 1 28 PD3/ TIM2_CH2/ ADC_ETR I/O X X X HS O3 X X Port D3 Timer 2 - channel 2/ADC external trigger 2 29 PD4/BEEP/ TIM2_CH1 I/O X X X HS O3 X X Port D4 Timer 2 - channel 1/BEEP output 3 30 PD5/ UART1_TX I/O X X X HS O3 X X Port D5 UART1 data transmit 4 31 PD6/ UART1_RX I/O X X X HS O3 X X Port D6 UART1 data receive 5 32 PD7/ TLI [TIM1_CH4] I/O X X X HS O3 X X Port D7 Top level interrupt Alternate function after remap [option bit] Configurable clock output [AFR5] Timer 2 channel 3[AFR1] Timer 1 channel 4 [AFR6] (1) I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings (see Electrical characteristics). (2) When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt is used in the application. (3) In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented). (4) The PD1 pin is in input pull-up during the reset phase and after internal reset release. DocID15441 Rev 9 23/117 Pinout and pin description STM8S103K3 STM8S103F3 STM8S103F2 5.2 STM8S103Fx TSSOP20/SO20/UFQFPN20 pinout and pin description 5.2.1 STM8S103Fx TSSOP20/SO20 pinout Figure 5: STM8S103Fx TSSOP20/SO20 pinout UART1_CK/TIM2_CH1/BEEP/(HS) PD4 1 20 PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR UART1_TX/AIN5/(HS) PD5 2 19 PD2 (HS)/AIN3 [TIM2_CH3] UART1_RX/AIN6/(HS) PD6 3 18 PD1 (HS)/SWIM NRST 4 17 PC7 (HS)/SPI_MISO [TIM1_CH2] OSCIN/PA1 5 16 PC6 (HS)/SPI_MOSI [TIM1_CH1] OSCOUT/PA2 6 15 PC5 (HS)/SPI_SCK [TIM2_CH1] VSS 7 14 PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2 [TIM1_CH2N] VCAP 8 13 PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N] VDD 9 12 PB4 (T)/I2C_SCL [ADC_ETR] 10 11 PB5 (T)/I2C_SDA [TIM1_BKIN] [SPI_NSS] TIM2_CH3/(HS) PA3 1. HS high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 24/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 5.2.2 Pinout and pin description STM8S103Fx UFQFPN20 pinout 19 18 17 PD2 (HS)/AIN3 [TIM2_CH3] PD5 (HS)/AIN5/UART1_TX PD4 (HS)/BEEP / TIM2_CH1/UART1_CK 20 PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR PD6 (HS)/AIN6/UART1_RX Figure 6: STM8S103Fx UFQFPN20-pin pinout 16 15 PD1(HS)/SWIM OSCIN/PA1 2 14 PC7 (HS)/SPI_MISO [TIM1_CH2] OSCOUT/PA2 3 13 PC6 (HS)/SPI_MOSI [TIM1_CH1] VSS 4 12 PC5 (HS)/SPI_SCK [TIM2_CH1] VCAP 5 11 PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2 [TIM1_CH2N] 7 8 [ADC_ETR] I2C_SCL/(T) PB4 9 10 [TIM1_CH1N] [TLI] TIM1_CH3/(HS) PC3 VDD 6 [TIM1_BKIN] I2C_SDA/(T) PB5 1 [SPI_NSS] TIM2_CH3/(HS) PA3 NRST 1. HS high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 5.2.3 STM8S103Fx TSSOP20/SO20/UFQFPN20 pin description Table 6: STM8S103Fx pin description Pin no. Input Pin name Output Type TSSOP/SO20 UFQFPN20 floating wpu Ext. interr. High sink Speed OD (1) PP Main function (after reset) Default alternate function 1 18 PD4/ BEEP/ TIM2_ CH1/ UART1 _CK I/O X X X HS O3 X X Port D4 Timer 2 channel 1/BEEP output/ UART1 clock 2 19 PD5/ AIN5/ UART1 _TX I/O X X X HS O3 X X Port D5 Analog input 5/ UART1 data transmit DocID15441 Rev 9 Alternate function after remap [option bit] 25/117 Pinout and pin description STM8S103K3 STM8S103F3 STM8S103F2 Pin no. Input Pin name Output Type TSSOP/SO20 UFQFPN20 floating wpu 3 20 PD6/ AIN6/ UART1 _RX I/O 4 1 NRST I/O 5 2 PA1/ OSCIN 6 3 7 (2) X X Ext. interr. X High sink Speed OD (1) HS O3 X PP X X Main function (after reset) Port D6 Default alternate function Analog input 6/ UART1 data receive Reset I/O X X X O1 X X Port A1 Resonator/ crystal in PA2/ OSCOUT I/O X X X O1 X X Port A2 Resonator/ crystal out 4 VSS S Digital ground 8 5 VCAP S 1.8 V regulator capacitor 9 6 VDD S Digital power supply 10 7 PA3/ TIM2_ CH3 [SPI_ NSS] I/O X 11 8 2 PB5/ I C_ SDA [TIM1_ BKIN] I/O X 12 9 2 PB4/ I C_ SCL I/O X 13 10 PC3/ TIM1_CH3 [TLI] [TIM1_ CH1N] I/O X X X 14 11 PC4/ CLK_CCO/ TIM1_ CH4/AIN2/[TIM1_ CH2N] I/O X X 15 12 PC5/ SPI_SCK [TIM2_ CH1] I/O X 16 13 PC6/ SPI_MOSI [TIM1_ CH1] I/O 17 14 PC7/ SPI_MISO [TIM1_ CH2] 18 15 19 20 X Alternate function after remap [option bit] X HS O3 X X O1 T (3) Port B5 2 I C data X O1 T (3) Port B4 2 I C clock HS O3 X X Port C3 Timer 1 channel 3 Top level interrupt [AFR3] Timer 1 inverted channel 1 [AFR7] X HS O3 X X Port C4 Configurable clock output/Timer 1 - channel 4/Analog input 2 Timer 1 - inverted channel 2 [AFR7] X X HS O3 X X Port C5 SPI clock Timer 2 - channel 1 [AFR0] X X X HS O3 X X Port C6 SPI master out/slave in Timer 1 - channel 1 [AFR0] I/O X X X HS O3 X X Port C7 SPI master in/ slave out Timer 1 - channel 2 [AFR0] PD1/ SWIM I/O X X X HS O4 X X Port D1 SWIM data interface 16 PD2/AIN3/[TIM2_ CH3] I/O X X X HS O3 X X Port D2 Analog input 3 17 PD3/ AIN4/ TIM2_ CH2/ ADC_ ETR I/O X X X HS O3 X X Port D3 Analog input 4/ Timer 2 channel 2/ADC external trigger (1) X Port A3 Timer 2 channel 3 SPI master/ slave select [AFR1] Timer 1 - break input [AFR4] ADC external trigger [AFR4] Timer 2 - channel 3 [AFR1] I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings. (2) When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if halt/active-halt is used in the application. (3) In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented). 26/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 5.3 Pinout and pin description Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016). DocID15441 Rev 9 27/117 Memory and register map STM8S103K3 STM8S103F3 STM8S103F2 6 Memory and register map 6.1 Memory map Figure 7: Memory map 0x00 0000 RAM (1 Kbyte) 0x00 03FF 0x00 0800 513 bytes stack Reserved 0x00 3FFF 0x00 4000 0x00 427F 0x00 4280 0x00 47FF 0x00 4800 0x00 480A 0x00 480B 0x00 4864 0x00 4865 0x00 4870 0x00 4871 0x00 4FFF 0x00 5000 640 bytes data EEPROM Reserved Option bytes Reserved Unique ID Reserved GPIO and periph. reg. 0x00 57FF 0x00 5800 Reserved 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 0x00 9FFF 0x00 A000 CPU/SWIM/debug/ITC registers 32 interrupt vectors Flash program memory (8 Kbytes) Reserved 0x02 7FFF 28/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Memory and register map 6.2 Register map 6.2.1 I/O port hardware register map Table 7: I/O port hardware register map Address Reset status Register label Register name 0x00 5000 PA_ODR Port A data output latch register 0x00 5001 PA_IDR Port A input pin value register PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PB_IDR Port C input pin value register PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x02 0x00 5013 PD_CR2 Port D control register 2 0x00 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0x00 5016 PE_DDR Port E data direction register 0x00 0x00 5017 PE_CR1 Port E control register 1 0x00 0x00 5002 0x00 5007 0x00 500C 0x00 5011 Block Port A Port B Port C Port D 0x00 (1) 0xXX (1) 0xXX (1) 0xXX (1) 0xXX (1) 0xXX Port E DocID15441 Rev 9 29/117 Memory and register map Address Block STM8S103K3 STM8S103F3 STM8S103F2 Reset status Register label Register name PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 0x00 5018 Port E Port F 0x00 501B (1) 0xXX (1) Depends on the external circuitry. 6.2.2 General hardware register map Table 8: General hardware register map Address Block Register name Reset status 0x00 501E to 0x00 5059 Reserved area (60 bytes) 0x00 505A Flash FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary control register 0xFF 2 0x00 505D FLASH _FPR Flash protection register 0x00 0x00 505E FLASH _NFPR Flash complementary protection register 0xFF 0x00 505F FLASH _IAPSR Flash in-application programming status register 0x00 0x00 5060 to 0x00 5061 30/117 Register label Reserved area (2 bytes) DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Memory and register map Address Block Register label Register name 0x00 5062 Flash FLASH _PUKR Flash program memory unprotection 0x00 register 0x00 5063 Reserved area (1 byte) 0x00 5064 Flash 0x00 5065 to 0x00 509F Reserved area (59 bytes) 0x00 50A0 ITC FLASH _DUKR Reset status Data EEPROM unprotection register 0x00 EXTI_CR1 External interrupt control register 1 0x00 EXTI_CR2 External interrupt control register 2 0x00 Reset status register 0xXX CLK_ICKR Internal clock control register 0x01 CLK_ECKR External clock control register 0x00 CLK_CMSR Clock master status register 0xE1 0x00 50C4 CLK_SWR Clock master switch register 0xE1 0x00 50C5 CLK_SWCR Clock switch control register 0xXX 0x00 50C6 CLK_CKDIVR Clock divider register 0x18 0x00 50C7 CLK_PCKENR1 Peripheral clock gating register 1 0xFF 0x00 50C8 CLK_CSSR Clock security system register 0x00 0x00 50A1 0x00 50A2 to 0x00 50B2 Reserved area (17 bytes) 0x00 50B3 RST 0x00 50B4 to 0x00 50BF Reserved area (12 bytes) 0x00 50C0 CLK 0x00 50C1 RST_SR 0x00 50C2 Reserved area (1 byte) 0x00 50C3 C DocID15441 Rev 9 (1) 31/117 Memory and register map Address Block STM8S103K3 STM8S103F3 STM8S103F2 Register label Register name Reset status 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF 0x00 50CC CLK_HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CD CLK_SWIMCCR SWIM clock control register 0bXXXX XXX0 WWDG_CR WWDG control register 0x7F WWDG_WR WWDR window register 0x7F IWDG_KR IWDG key register 0xXX 0x00 50E1 IWDG_PR IWDG prescaler register 0x00 0x00 50E2 IWDG_RLR IWDG reload register 0xFF AWU_CSR1 AWU control/status register 1 0x00 0x00 50F1 AWU_APR AWU asynchronous prescaler buffer 0x3F register 0x00 50F2 AWU_TBR AWU timebase selection register 0x00 BEEP_CSR BEEP control/status register 0x1F 0x00 50CE to 0x00 50D0 ReservLK ed area (3 bytes) 0x00 50D1 WWDG 0x00 50D2 0x00 50D3 to 00 50DF Reserved area (13 bytes) 0x00 50E0 IWDG 0x00 50E3 to 0x00 50EF Reserved area (13 bytes) 0x00 50F0 AWU 0x00 50F3 32/117 BEEP DocID15441 Rev 9 (2) STM8S103K3 STM8S103F3 STM8S103F2 Memory and register map Address Block Register label Register name Reset status 0x00 50F4 to 0x00 50FF Reserved area (12 bytes) 0x00 5200 SPI SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI_ICR SPI interrupt control register 0x00 0x00 5203 SPI_SR SPI status register 0x02 0x00 5204 SPI_DR SPI data register 0x00 0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF 0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF 0x00 5208 to 0x00 520F Reserved area (8 bytes) 0x00 5210 I C 2 2 0x00 2 0x00 2 0x00 2 0x00 2 0x00 2 0x00 2 0x00 I2C_CR1 I C control register 1 0x00 5211 I2C_CR2 I C control register 2 0x00 5212 I2C_FREQR I C frequency register 0x00 5213 I2C_OARL I C Own address register low 0x00 5214 I2C_OARH I C Own address register high 0x00 5215 Reserved 0x00 5216 I2C_DR I C data register 0x00 5217 I2C_SR1 I C status register 1 DocID15441 Rev 9 33/117 Memory and register map Address Block STM8S103K3 STM8S103F3 STM8S103F2 Register label Register name 0x00 5218 I2C_SR2 I C status register 2 0x00 5219 I2C_SR3 I C status register 3 0x00 521A I2C_ITR I C interrupt control register 0x00 521B I2C_CCRL I C Clock control register low 0x00 521C I2C_CCRH I C Clock control register high 0x00 521D I2C_TRISER I C TRISE register 0x00 521E I2C_PECR Reset status 2 0x00 2 0x0X 2 0x00 2 0x00 2 0x00 2 0x02 I C packet error checking register 2 0x00 UART1_SR UART1 status register 0xC0 0x00 5231 UART1_DR UART1 data register 0xXX 0x00 5232 UART1_BRR1 UART1 baud rate register 1 0x00 0x00 5233 UART1_BRR2 UART1 baud rate register 2 0x00 0x00 5234 UART1_CR1 UART1 control register 1 0x00 0x00 5235 UART1_CR2 UART1 control register 2 0x00 0x00 5236 UART1_CR3 UART1 control register 3 0x00 0x00 5237 UART1_CR4 UART1 control register 4 0x00 0x00 5238 UART1_CR5 UART1 control register 5 0x00 0x00 5239 UART1_GTR UART1 guard time register 0x00 0x00 523A UART1_PSCR UART1 prescaler register 0x00 0x00 521F to 0x00 522F Reserved area (17 bytes) 0x00 5230 UART1 34/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Memory and register map Address Block Register label Register name Reset status 0x00 523B to 0x00 523F Reserved area (21 bytes) 0x00 5250 TIM1 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture/compare mode register 0x00 1 0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode register 0x00 2 0x00 525A TIM1_CCMR3 TIM1 capture/compare mode register 0x00 3 0x00 525B TIM1_CCMR4 TIM1 capture/compare mode register 0x00 4 0x00 525C TIM1_CCER1 TIM1 capture/compare enable register 1 0x00 0x00 525D TIM1_CCER2 TIM1 capture/compare enable register 2 0x00 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 DocID15441 Rev 9 35/117 Memory and register map Address Block STM8S103K3 STM8S103F3 STM8S103F2 Register label Register name Reset status 0x00 525F TIM1_CNTRL TIM1 counter low 0x00 0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF 0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 capture/compare register 1 high 0x00 0x00 5266 TIM1_CCR1L TIM1 capture/compare register 1 low 0x00 0x00 5267 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00 0x00 5269 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00 0x00 526A TIM1_CCR3L TIM1 capture/compare register 3 low 0x00 0x00 526B TIM1_CCR4H TIM1 capture/compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 capture/compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead-time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 TIM2 control register 1 0x00 0x00 5270 to 0x00 52FF Reserved area (147 bytes) 0x00 5300 TIM2 36/117 TIM2_CR1 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Address Block Memory and register map Register label Register name Reset status 0x00 5301 Reserved 0x00 5302 Reserved 0x00 5303 TIM2_IER TIM2 Interrupt enable register 0x00 0x00 5304 TIM2_SR1 TIM2 status register 1 0x00 0x00 5305 TIM2_SR2 TIM2 status register 2 0x00 0x00 5306 TIM2_EGR TIM2 event generation register 0x00 0x00 5307 TIM2_CCMR1 TIM2 capture/compare mode register 0x00 1 0x00 5308 TIM2_CCMR2 TIM2 capture/compare mode register 0x00 2 0x00 5309 TIM2_CCMR3 TIM2 capture/compare mode register 0x00 3 0x00 530A TIM2_CCER1 TIM2 capture/compare enable register 1 0x00 0x00 530B TIM2_CCER2 TIM2 capture/compare enable register 2 0x00 0x00 530C TIM2_CNTRH TIM2 counter high 0x00 0x00 530D TIM2_CNTRL TIM2 counter low 0x00 0x00 530E TIM2_PSCR TIM2 prescaler register 0x00 0x00 530F TIM2_ARRH TIM2 auto-reload register high 0xFF 0x00 5310 TIM2_ARRL TIM2 auto-reload register low 0xFF 0x00 5311 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00 DocID15441 Rev 9 37/117 Memory and register map Address Block STM8S103K3 STM8S103F3 STM8S103F2 Register label Register name 0x00 5312 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00 0x00 5313 TIM2_CCR2H TIM2 capture/compare reg. 2 high 0x00 5314 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00 0x00 5315 TIM2_CCR3H TIM2 capture/compare register 3 high 0x00 0x00 5316 TIM2_CCR3L TIM2 capture/compare register 3 low 0x00 0x00 5317 to 0x00 533F Reserved area (43 bytes) 0x00 5340 TIM4 TIM4_CR1 Reset status 0x00 TIM4 control register 1 0x00 0x00 5341 Reserved 0x00 5342 Reserved 0x00 5343 TIM4_IER TIM4 interrupt enable register 0x00 0x00 5344 TIM4_SR TIM4 status register 0x00 0x00 5345 TIM4_EGR TIM4 event generation register 0x00 0x00 5346 TIM4_CNTR TIM4 counter 0x00 0x00 5347 TIM4_PSCR TIM4 prescaler register 0x00 0x00 5348 TIM4_ARR TIM4 auto-reload register 0xFF ADC data buffer registers 0x00 0x00 5349 to 0x00 53DF Reserved area (153 bytes) 0x00 53E0 to 0x00 53F3 ADC1 0x00 53F4 to 0x00 53FF Reserved area (12 bytes) 38/117 ADC _DBxR DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Memory and register map Address Block Register label Register name Reset status 0x00 5400 ADC1 ADC _CSR ADC control/status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configuration register 2 0x00 0x00 5403 ADC_CR3 ADC configuration register 3 0x00 0x00 5404 ADC_DRH ADC data register high 0xXX 0x00 5405 ADC_DRL ADC data register low 0xXX 0x00 5406 ADC_TDRH ADC Schmitt trigger disable register 0x00 high 0x00 5407 ADC_TDRL ADC Schmitt trigger disable register 0x00 low 0x00 5408 ADC_HTRH ADC high threshold register high 0x03 0x00 5409 ADC_HTRL ADC high threshold register low 0xFF 0x00 540A ADC_LTRH ADC low threshold register high 0x00 0x00 540B ADC_LTRL ADC low threshold register low 0x00 0x00 540C ADC_AWSRH ADC analog watchdog status register 0x00 high 0x00 540D ADC_AWSRL ADC analog watchdog status register 0x00 low 0x00 540E ADC _AWCRH ADC analog watchdog control register high 0x00 0x00 540F ADC_AWCRL ADC analog watchdog control register low 0x00 DocID15441 Rev 9 39/117 Memory and register map STM8S103K3 STM8S103F3 STM8S103F2 Address Block Register label 0x00 5410 to 0x00 57FF Reserved area (1008 bytes) Register name Reset status (1) Depends on the previous reset source. (2) Write only register. 6.2.3 CPU/SWIM/debug module/interrupt controller registers Table 9: CPU/SWIM/debug module/interrupt controller registers Address Register label Register name Reset status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CCR Condition code register 0x28 0x00 7F05 Block (1) CPU 0x00 7F0B to 0x00 7F5F 0x00 7F60 Reserved area (85 bytes) CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF ITC_SPR3 Interrupt software priority register 3 0xFF 0x00 7F73 ITC_SPR4 Interrupt software priority register 4 0xFF 0x00 7F74 ITC_SPR5 Interrupt software priority register 5 0xFF 0x00 7F72 40/117 CPU ITC DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Address Block Memory and register map Register label Register name Reset status 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF 0x00 7F78 to 0x00 7F79 0x00 7F80 Reserved area (2 bytes) SWIM SWIM_CSR 0x00 7F81 to 0x00 7F8F SWIM control status register 0x00 Reserved area (15 bytes) 0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM debug module control register 1 0x00 0x00 7F97 DM_CR2 DM debug module control register 2 0x00 0x00 7F98 DM_CSR1 DM debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register 0xFF 0x00 7F95 DM 0x00 7F9B to 0x00 7F9F (1) Reserved area (5 bytes) Accessible by debug module only DocID15441 Rev 9 41/117 Interrupt vector mapping 7 STM8S103K3 STM8S103F3 STM8S103F2 Interrupt vector mapping Table 10: Interrupt mapping IRQ Source no. block RESET TRAP Description Wakeup from Wakeup from Vector address halt mode active-halt mode Reset Yes Yes 0x00 8000 Software interrupt - - 0x00 8004 External top level interrupt - - 0x00 8008 0 TLI 1 AWU Auto wake up from halt - Yes 0x00 800C 2 CLK Clock controller - - 0x00 8010 3 EXTI0 Port A external interrupts Yes Yes 0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTI4 Port E external interrupts Yes Yes 0x00 8024 8 Reserved - - 0x00 8028 9 Reserved - - 0x00 802C End of transfer Yes Yes 0x00 8030 TIM1 TIM1 update/ overflow/ underflow/ trigger/ break - - 0x00 8034 12 TIM1 TIM1 capture/ compare - - 0x00 8038 13 TIM2 TIM2 update/ overflow - - 0x00 803C 14 TIM2 TIM2 capture/ compare - - 0x00 8040 15 Reserved - - 0x00 8044 16 Reserved - - 0x00 8048 10 11 SPI (1) (1) 17 UART1 Tx complete - - 0x00 804C 18 UART1 Receive register DATA FULL - - 0x00 8050 19 I C I C interrupt Yes Yes 0x00 8054 20 Reserved - - 0x00 8058 21 Reserved - - 0x00 805C ADC1 end of conversion/ analog watchdog interrupt - - 0x00 8060 22 42/117 2 ADC1 2 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Interrupt vector mapping IRQ Source no. block Description Wakeup from Wakeup from Vector address halt mode active-halt mode 23 TIM4 TIM4 update/ overflow - - 0x00 8064 24 Flash EOP/WR_PG_DIS - - 0x00 8068 0x00 806C to 0x00 807C Reserved (1) Except PA1 DocID15441 Rev 9 43/117 Option bytes 8 STM8S103K3 STM8S103F3 STM8S103F2 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in the table below. Option bytes can also be modified `on the fly' by the application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM). Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 11: Option bytes Addr. Option name Option Option bits byte no. 7 6 5 4 3 2 1 0 Factory default setting 0x4800 Read-out protection (ROP) OPT0 ROP [7:0] 0x00 0x4801 User boot code(UBC) OPT1 UBC [7:0] 0x00 NOPT1 NUBC [7:0] 0xFF Alternate function remapping (AFR) OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF Miscell. option OPT3 Reserved HSI TRIM LSI_ EN IWDG _HW WWDG _HW WWDG _HALT 0x00 NOPT3 Reserved NHSI TRIM NLSI_ EN NIWDG _HW NWWDG _HW NWW G_HALT 0xFF OPT4 Reserved EXT CLK CKAWU SEL PRS C1 PRS C0 0x00 NOPT4 Reserved NEXT CLK NCKA WUSEL NPRSC1 NPR SC0 0xFF OPT5 HSECNT [7:0] 0x00 NOPT5 NHSECNT [7:0] 0xFF 0x4802 0x4803 0x4804 0x4805h 0x4806 0x4807 Clock option 0x4808 0x4809 HSE clock startup 0x480A 0x00 Table 12: Option byte description Option byte no. OPT0 Description ROP[7:0] Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) 44/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Option byte no. Option bytes Description Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. OPT1 UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Page 0 defined as UBC, memory write-protected 0x02: Pages 0 to 1 defined as UBC, memory write-protected. Page 0 and 1 contain the interrupt vectors. ... 0x7F: Pages 0 to 126 defined as UBC, memory write-protected Other values: Pages 0 to 127 defined as UBC, memory write-protected Note: Refer to the family reference manual (RM0016) section on Flash write protection for more details. OPT2 AFR[7:0] Refer to following section for alternate function remapping decriptions of bits [7:2] and [1:0] respectively. OPT3 HSITRIM:High speed internal clock trimming register size 0: 3-bit trimming supported in CLK_HSITRIMR register 1: 4-bit trimming supported in CLK_HSITRIMR register LSI_EN:Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source IWDG_HW: Independent watchdog 0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware WWDG_HW: Window watchdog activation 0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware WWDG_HALT: Window watchdog reset on halt DocID15441 Rev 9 45/117 Option bytes STM8S103K3 STM8S103F3 STM8S103F2 Option byte no. Description 0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active OPT4 EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN CKAWUSEL:Auto wake-up unit/clock 0: LSI clock source selected for AWU 1: HSE clock with prescaler selected as clock source for for AWU PRSC[1:0] AWU clock prescaler 0x: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler OPT5 HSECNT[7:0]:HSE crystal oscillator stabilization time 0x00: 2048 HSE cycles 0xB4: 128 HSE cycles 0xD2: 8 HSE cycles 0xE1: 0.5 HSE cycles 8.1 Alternate function remapping bits Table 13: STM8S103K alternate function remapping bits for 32-pin devices Option byte no. OPT2 (1) Description AFR7 Alternate function remapping option 7 Reserved. AFR6 Alternate function remapping option 6 (2) 0: AFR6 remapping option inactive: Default alternate function . 1: Port D7 alternate function = TIM1_CH4. AFR5 Alternate function remapping option 5 (2) 0: AFR5 remapping option inactive: Default alternate function . 46/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Option byte no. Option bytes (1) Description 1: Port D0 alternate function = CLK_CCO. AFR[4:2] Alternate function remapping options 4:2 Reserved. AFR1 Alternate function remapping option 1 (2) 0: AFR1 remapping option inactive: Default alternate functions . 1: Port A3 alternate function = SPI_NSS; port D2 alternate function = TIM2_CH3. AFR0 Alternate function remapping option 0 Reserved. (1) Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and AFR0. (2) Refer to pinout description. Table 14: STM8S103F alternate function remapping bits for 20-pin devices Option byte no. OPT2 Description AFR7 Alternate function remapping option 7 0: AFR7 remapping option inactive: Default alternate (1) functions . 1: Port C3 alternate function = TIM1_CH1N; port C4 alternate function = TIM1_CH2N. AFR6 Alternate function remapping option 6 Reserved. AFR5 Alternate function remapping option 5 Reserved. AFR4 Alternate function remapping option 4 0: AFR4 remapping option inactive: Default alternate (1) functions . 1: Port B4 alternate function = ADC_ETR; port B5 alternate function = TIM1_BKIN. AFR3 Alternate function remapping option 3 0: AFR3 remapping option inactive: Default alternate (1) function . 1: Port C3 alternate function = TLI. AFR2 Alternate function remapping option 2 DocID15441 Rev 9 47/117 Option bytes STM8S103K3 STM8S103F3 STM8S103F2 Option byte no. Description Reserved (2) AFR1 Alternate function remapping option 1 0: AFR1 remapping option inactive: Default alternate (1) functions . 1: Port A3 alternate function = SPI_NSS; port D2 alternate function = TIM2_CH3. (2) AFR0 Alternate function remapping option 0 0: AFR0 remapping option inactive: Default alternate (1) functions . 1: Port C5 alternate function = TIM2_CH1; port C6 alternate function = TIM1_CH1; port C7 alternate function = TIM1_CH2. (1) Refer to pinout description. (2) Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and AFR0. 48/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 9 Unique ID Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. The unique device identifier is ideally suited: For use as serial numbers * use as security keys to increase the code security in the program memory while using * For and combining this unique ID with software cryptograhic primitives and protocols before programming the internal memory. * To activate secure boot processes Table 15: Unique ID registers (96 bits) Address Content description 0x4865 0x4866 0x4867 Unique ID bits 7 6 5 4 3 1 0 U_ID[7:0] X co-ordinate on the wafer U_ID[15:8] U_ID[23:16] 0x4868 Y co-ordinate on the wafer 0x4869 Wafer number U_ID[39:32] U_ID[31:24] 0x486A U_ID[47:40] 0x486B U_ID[55:48] 0x486C U_ID[63:56] 0x486D 2 Lot number U_ID[71:64] 0x486E U_ID[79:72] 0x486F U_ID[87:80] 0x4870 U_ID[95:88] DocID15441 Rev 9 49/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 10.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 5 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ). 10.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in the following figure. Figure 8: Pin loading conditions STM8 PIN 50 pF 50/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 10.1.5 Electrical characteristics Pin input voltage The input voltage measurement on a pin of the device is described in the following figure. Figure 9: Pin input voltage STM8 PIN VIN 10.2 Absolute maximum ratings Stresses above those listed as `absolute maximum ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 16: Voltage characteristics Symbol Ratings Min VDDx - VSS Supply voltage VIN Input voltage on true open drain pins (1) 6.5 VSS - 0.3 6.5 VSS - 0.3 VDD + 0.3 Variations between different power pins - 50 Variations between all the different ground pins - 50 (2) (2) |VSSx - VSS| VESD (1) Unit -0.3 Input voltage on any other pin |VDDx - VDD| Max V mV Electrostatic discharge voltage See "Absolute maximum ratings (electrical sensitivity)" All power (VDD) and ground (VSS) pins must always be connected to the external power supply (2) IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected DocID15441 Rev 9 51/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Table 17: Current characteristics Symbol Ratings IVDD (1) Max (2) 100 (2) Total current into VDD power lines (source) IVSS Total current out of VSS ground lines (sink) 80 IIO Output current sunk by any I/O and control pin 20 IINJ(PIN) Output current source by any I/Os and control pin - 20 Injected current on NRST pin 4 Injected current on OSCIN pin 4 mA (3) (4) (5) 4 Injected current on any other pin I INJ(PIN) Unit (3) (5) 20 Total injected current (sum of all I/O and control pins) (1) Data based on characterization results, not tested in production. (2) All power (VDD) and ground (VSS) pins must always be connected to the external supply. (3) IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected (4) ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy. (5) When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device. Table 18: Thermal characteristics 52/117 Symbol Ratings Value TSTG Storage temperature range TJ Maximum junction temperature Unit -65 to +150 C DocID15441 Rev 9 150 STM8S103K3 STM8S103F3 STM8S103F2 10.3 Electrical characteristics Operating conditions Table 19: General operating conditions Symbol Parameter fCPU Internal CPU clock frequency VDD Standard operating voltage (1) VCAP Conditions Min Max 0 16 MHz 2.95 5.5 V 470 3300 nF - 0.3 - 15 nH TSSOP20 - 238 SO20W - 220 Power dissipation at TA = 85 C UFQFPN20 - 220 for suffix 6 LQFP32 - 330 UFQFPN32 - 526 SDIP32 - 330 TSSOP20 - 59 SO20W - 55 Power dissipation at TA = 125 C UFQFPN20 - 55 for suffix 3 LQFP32 - 83 UFQFPN32 - 132 SDIP32 - 83 -40 85 -40 125 6 suffix version -40 105 3 suffix version -40 130 CEXT: capacitance of external capacitor Unit (2) ESR of external at 1 MHz capacitor ESL of external capacitor PD (3) mW TA Ambient temperature for 6 suffix Maximum power dissipation version TA Ambient temperature for 3 suffix Maximum power dissipation version TJ C Junction temperature range DocID15441 Rev 9 53/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 (1) Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range. (2) This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator. (3) To calculate PDmax(TA), use the formula PDmax =(TJmax- TA)/JA (see Thermal characteristics ) with the value for TJmax given in the previous table and the value for JA given in Thermal characteristics. Figure 10: fCPUmax versus VDD f CPU (MHz) Functionality 16 not guaranteed in this area 12 Functionality guaranteed @TA-40 to 125 C 8 4 0 2.95 4.0 5.0 5.5 Supply voltage Table 20: Operating conditions at power-up/power-down Symbol tVDD Parameter Conditions VDD rise time rate Min Typ Max 2 - 2 - -- - 1.7 Unit s/V (1) VDD fall time rate tTEMP Reset release delay VDD rising VIT+ Power-on reset threshold 2.6 2.7 2.85 VIT- Brown-out reset threshold 2.5 2.65 2.8 VHYS(BOR) Brown-out reset hysteresis - 70 - ms V mV (1) Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the minimum ooperating voltage (VDD min) when the tTEMP delay has elapsed. 10.3.1 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit the series inductance to less than 15 nH. 54/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 11: External capacitor CEXT C ESL ESR RLeak 1. ESR is the equivalent series resistance and ESL is the equivalent inductance. 10.3.2 Supply current characteristics The current consumption is measured as described in Pin input voltage. 10.3.2.1 Total current consumption in run mode The MCU is placed under the following conditions: All I/O pins in input mode with a static value at VDD or VSS (no load) * peripherals are disabled (clock stopped by peripheral clock gating registers) except if * All explicitly mentioned. Subject to general operating conditions for VDD and TA. Table 21: Total current consumption with code execution in run mode at VDD = 5 V Symbol Parameter Conditions Typ HSE crystal osc. (16 MHz) fCPU = fMASTER = IDD(RUN) Supply current fCPU = fMASTER/128 = in run mode, 125 kHz code executed from RAM fCPU = fMASTER/128 = 15.625 kHz fCPU = fMASTER = 128 kHz Supply current in run mode, fCPU = fMASTER = code executed 16 MHz from Flash 2.3 - 2 2.35 HSI RC osc. (16 MHz) 1.7 2 HSE user ext. clock (16 MHz) 0.86 - HSI RC osc. (16 MHz) 0.7 0.87 HSI RC osc. (16 MHz/8) 0.46 0.58 LSI RC osc. (128 kHz) 0.41 0.55 HSE crystal osc. (16 MHz) 4.5 HSE user ext. clock (16 MHz) 4.3 4.75 HSI RC osc. (16 MHz) 3.7 4.5 HSE user ext. clock (16 MHz) 16 MHz (1) Max DocID15441 Rev 9 Unit mA 55/117 Electrical characteristics Symbol Parameter STM8S103K3 STM8S103F3 STM8S103F2 Conditions Typ fCPU = fMASTER = (2) 2 MHz IDD(RUN) fCPU = fMASTER/128 = Supply current 125 kHz in run mode, code executed f CPU = fMASTER/128 = from Flash 15.625 kHz fCPU = fMASTER = 128 kHz (1) Max HSI RC osc. (16 MHz/8) 0.84 1.05 HSI RC osc. (16 MHz) 0.72 0.9 Unit mA HSI RC osc. (16 MHz/8) 0.46 0.58 LSI RC osc. (128 kHz) 0.42 0.57 (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. Table 22: Total current consumption with code execution in run mode at VDD = 3.3 V Symbol Parameter Conditions Typ HSE crystal osc. (16 MHz) fCPU = fMASTER = 16 MHz Supply current fCPU = fMASTER/ in run mode, 128 = 125 kHz code executed from RAM fCPU = fMASTER/ 128 = 15.625 kHz IDD(RUN) fCPU = fMASTER = 128 kHz 1.8 - 2 2.3 HSI RC osc. (16 MHz) 1.5 2 HSE user ext. clock (16 MHz) 0.81 - HSI RC osc. (16 MHz) 0.7 0.87 HSI RC osc. (16 MHz/8) 0.46 0.58 LSI RC osc. (128 kHz) 0.41 0.55 4 - HSE user ext. clock (16 MHz) 3.9 4.7 HSI RC osc. (16 MHz) 3.7 4.5 HSI RC osc. (16 MHz/8) 0.84 1.05 HSI RC osc. (16 MHz) 0.72 0.9 HSE user ext. clock (16 MHz) 16 MHz Supply current in run mode, code executed f CPU = fMASTER = from Flash 2 MHz fCPU = fMASTER/ 56/117 Unit mA HSE crystal osc. (16 MHz) fCPU = fMASTER = (1) Max (2) DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter Electrical characteristics Conditions Typ (1) Max Unit 128 = 125 kHz fCPU = fMASTER/ 128 = 15.625 kHz fCPU = fMASTER = 128 kHz HSI RC osc. (16 MHz/8) 0.46 0.58 LSI RC osc. (128 kHz) 0.42 0.57 (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. 10.3.2.2 Total current consumption in wait mode Table 23: Total current consumption in wait mode at VDD = 5 V Symbol Parameter Conditions fCPU = fMASTER = 16 MHz IDD(WFI) Typ HSE crystal osc. (16 MHz) 1.6 - HSE user ext. clock (16 MHz) 1.1 1.3 HSI RC osc. (16 MHz) 0.89 1.1 0.7 0.88 fCPU = fMASTER/128 = Supply HSI RC osc. (16 MHz) current in 125 kHz wait mode fCPU = fMASTER/128 = (2) HSI RC osc. (16 MHz/8) 15.625 kHz fCPU = fMASTER = 128 kHz (1) Max mA LSI RC osc. (128 kHz) (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. Unit 0.45 0.57 0.4 0.54 Table 24: Total current consumption in wait mode at VDD = 3.3 V Symbol IDD(WFI) Parameter Supply current in wait mode Conditions Typ fCPU = fMASTER = HSE crystal osc. 16 MHz (16 MHz) DocID15441 Rev 9 1.1 Max - (1) Unit mA 57/117 Electrical characteristics Symbol Parameter STM8S103K3 STM8S103F3 STM8S103F2 Conditions Typ Max (1) Unit HSE user ext. clock (16 MHz) 1.1 1.3 0.89 1.1 0.7 0.88 0.45 0.57 0.4 0.54 HSI RC osc. (16 MHz) fCPU = fMASTER/ 128 = HSI RC osc. 125 kHz (16 MHz) fCPU = fMASTER/ 128 = HSI RC osc. (2) 15.625 kHz (16 MHz/8) fCPU = fMASTER= LSI RC osc. 128 kHz (128 kHz) (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. 10.3.2.3 Total current consumption in active halt mode Table 25: Total current consumption in active halt mode at VDD = 5 V Conditions Main voltage regulator (2) (MVR) Flash mode Supply current IDD(AH) in active halt mode On Operating mode Supply current IDD(AH) in active halt mode On Operating mode Symbol Parameter (3) Clock source Typ Max Max at 85 at 125 Unit C C (1) (1) HSE crystal osc. (16 MHz) 1030 - - 200 260 300 LSI RC osc. (128 kHz) A Supply current in active halt mode On Power-down mode Supply current IDD(AH) in active halt mode On Power-down mode IDD(AH) 58/117 HSE crystal osc. (16 MHz) 970 - - 150 200 230 LSI RC osc. (128 kHz) DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Conditions Symbol Parameter Main voltage regulator (2) (MVR) Supply current IDD(AH) in active halt mode (3) Flash mode Max Max at 85 at 125 Unit C C Typ Clock source (1) (1) LSI RC osc. Operating mode (128 kHz) 66 85 110 10 20 40 Off IDD(AH) Supply current in active halt mode LSI RC osc. Power-down mode (128 kHz) (1) Data based on characterization results, not tested in production (2) Configured by the REGAH bit in the CLK_ICKR register. (3) Configured by the AHALT bit in the FLASH_CR1 register. Table 26: Total current consumption in active halt mode at VDD = 3.3 V Conditions Symbol Parameter IDD(AH) Supply current in active halt mode Main voltage regulator (2) (MVR) On (3) Flash mode Clock source HSE crystal Operating mode osc. (16 MHz) Typ Max at 85 C Max at 125 C Unit (1) (1) 550 - - 200 260 290 970 - - 150 200 230 66 80 105 10 18 35 A LSI RC osc. IDD(AH) Supply current in active halt mode IDD(AH) Operating mode On Power-down mode IDD(AH) IDD(AH) IDD(AH) Supply current in active halt mode (128 kHz) HSE crystal osc. (16 MHz) (128 kHz) Operating mode LSI RC osc. Off Power-down mode A LSI RC osc. (128 kHz) (1) Data based on characterization results, not tested in production (2) Configured by the REGAH bit in the CLK_ICKR register. (3) Configured by the AHALT bit in the FLASH_CR1 register. DocID15441 Rev 9 59/117 Electrical characteristics 10.3.2.4 STM8S103K3 STM8S103F3 STM8S103F2 Total current consumption in halt mode Table 27: Total current consumption in halt mode at VDD = 5 V Symbol Parameter Conditions Supply current in halt mode Flash in operating mode, HSI clock after wakeup IDD(H) (1) Typ Max at (1) 85 C 63 Max at (1) Unit 125 C 75 105 A Flash in power-down mode, HSI clock after wakeup 6.0 20 55 Data based on characterization results, not tested in production Table 28: Total current consumption in halt mode at VDD = 3.3 V Symbol Parameter Conditions Typ Supply current in halt mode Flash in operating mode, HSI clock after wakeup 60 IDD(H) (1) Max at Max at (1) (1) Unit 85 C 125 C 75 100 A Flash in power-down mode, HSI 4.5 clock after wakeup 17 30 Data based on characterization results, not tested in production 10.3.2.5 Low power mode wakeup times Table 29: Wakeup times Symbol Parameter Wakeup time from tWU(WFI) 0 to 16 MHz - mode fCPU = fMASTER = 16 MHz Wakeup time active MVR voltage halt mode to run regulator (3) (4) Flash in operating (5) mode (after Wakeup time active MVR voltage Flash in HSI halt mode to run regulator (after mode (4) on (5) mode DocID15441 Rev 9 Unit See (2) note HSI on power-down (1) Max 0.56 mode (3) 60/117 Typ wait mode to run (3) tWU(AH) Conditions (6) 1 (6) 2 wakeup) wakeup) (6) 3 - s STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter Conditions Wakeup time active MVR voltage halt mode to run regulator (3) (4) Typ Flash in operating (5) mode Wakeup time active MVR voltage Flash in HSI halt mode to run regulator (after power-down (5) off Wakeup time from Flash in operating mode mode (6) - (6) - 48 50 wakeup) (5) halt mode to run (3) Unit wakeup) mode mode (5) Flash in power-down mode (1) Data guaranteed by design, not tested in production. (2) tWU(WFI) = 2 x 1/fmaster + 6 x 1/fCPU. (3) Measured from interrupt event to interrupt vector fetch. (4) Configured by the REGAH bit in the CLK_ICKR register. (5) Configured by the AHALT bit in the FLASH_CR1 register. (6) Plus 1 LSI clock depending on synchronization. 10.3.2.6 (after off (4) (1) Max HSI mode (3) tWU(H) Electrical characteristics 52 - 54 - Total current consumption and timing in forced reset state Table 30: Total current consumption and timing in forced reset state Symbol Parameter Conditions IDD(R) Supply current in reset VDD = 5 V 400 - VDD = 3.3 V 300 - - 150 (2) state tRESETBL (1) Max Unit A Reset pin release to vector fetch (1) Data guaranteed by design, not tested in production. (2) Characterized with all I/Os tied to VSS. 10.3.2.7 Typ s Current consumption of on-chip peripherals Subject to general operating conditions for VDD and TA. DocID15441 Rev 9 61/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 HSI internal RC/fCPU = fMASTER = 16 MHz, VDD = 5 V Table 31: Peripheral current consumption Symbol Parameter Typ. IDD(TIM1) TIM1 supply current IDD(TIM2) TIM2 supply current IDD(TIM4) TIM4 timer supply current IDD(UART1) UART1 supply current IDD(SPI) SPI supply current IDD(I2C) I C supply current IDD(ADC1) ADC1 supply current when converting (1) 210 (1) 130 50 (1) 120 (2) 2 Unit (2) 45 (2) 65 (3) A 1000 (1) Data based on a differential IDD measurement between reset configuration and timer counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production. (2) Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not tested in production. (3) Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. Not tested in production. 10.3.2.8 Current consumption curves The following figures show typical current consumption measured with code executing in RAM. 62/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 12: Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz Figure 13: Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V DocID15441 Rev 9 63/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Figure 14: Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz Figure 15: Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz 64/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 16: Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V Figure 17: Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz 10.3.3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for VDD and TA. Table 32: HSE user external clock characteristics Symbol Parameter fHSE_ext User external clock source frequency 0 16 OSCIN input pin high level voltage 0.7 x VDD VDD + 0.3 V OSCIN input pin low level voltage VSS 0.3 x VDD -1 +1 VHSEH (1) VHSEL (1) ILEAK_HSE Conditions Min Max Unit MHz V OSCIN input leakage current VSS < VIN < VDD DocID15441 Rev 9 A 65/117 Electrical characteristics (1) STM8S103K3 STM8S103F3 STM8S103F2 Data based on characterization results, not tested in production. Figure 18: HSE external clocksource V HSEH V HSEL External clock source fHSE OSCIN STM8 HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 33: HSE oscillator characteristics Symbol Parameter Conditions fHSE External high speed Feedback resistor (1) C Typ 1 oscillator frequency RF Min Max Unit 16 MHz 220 k Recommended load 20 (2) capacitance IDD(HSE) HSE oscillator power consumption pF C = 20 pF, 6 (startup) fOSC = 16 MHz 1.6 (stabilized) (3) mA gm C = 10 pF, 6 (startup) fOSC =16 MHz 1.2 (stabilized) Oscillator 5 transconductance tSU(HSE) 66/117 (3) (4) Startup time VDD is stabilized DocID15441 Rev 9 mA/V 1 ms STM8S103K3 STM8S103F3 STM8S103F2 (1) Electrical characteristics C is approximately equivalent to 2 x crystal Cload. (2) The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value. Refer to crystal manufacturer for more details (3) Data based on characterization results, not tested in production. (4) tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Figure 19: HSE oscillator circuit diagram Rm f HSE to core Lm CO RF CL1 Cm OSCIN gm Resonator Consumption control Resonator OSCOUT CL2 STM8 HSE oscillator critical g m equation 2 2 gmcrit= (2 x x fHSE) x Rm(2Co + C) Rm: Notional resistance (see crystal specification) Lm: Notional inductance (see crystal specification) Cm: Notional capacitance (see crystal specification) Co: Shunt capacitance (see crystal specification) CL1= CL2 = C: Grounded external capacitance gm >> gmcrit 10.3.4 Internal clock sources and timing characteristics Subject to general operating conditions for VDD and TA. High speed internal RC oscillator (HSI) Table 34: HSI oscillator characteristics Symbol Parameter fHSI Frequency Conditions Min Typ - DocID15441 Rev 9 16 Max Unit - MHz 67/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter ACCHSI Accuracy of HSI User-trimmed with oscillator Conditions Min Typ Max CLK_HSITRIMR register for Unit (3) 1.0 - - Accuracy of HSI VDD = 5 V, TA = 25C -1.0 - 1.0 oscillator (factory V = 5 V, 25 C DD calibrated) T 85 C -2.0 - 2.0 given VDD and TA (1) conditions (2) % A 2.95 VDD 5.5 V,-40 C TA 125 C tsu(HSI) (2) (2) -3.0 - 3.0 - - 1.0 - 170 250 HSI oscillator wakeup time including (3) s (2) A calibration IDD(HSI) HSI oscillator power consumption (1) Refer to application note. (2) Data based on characterization results, not tested in production. (3) Guaranteed by design, not tested in production. 68/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 20: Typical HSI frequency variation vs VDD @ 4 temperatures Low speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA. Table 35: LSI oscillator characteristics Symbol Parameter fLSI Frequency tsu(LSI) IDD(LSI) Min Typ Max Unit 110 128 150 kHz LSI oscillator wake-up time - - 7 s LSI oscillator power consumption - 5 - A Figure 21: Typical LSI frequency variation vs VDD @ 4 temperatures DocID15441 Rev 9 69/117 Electrical characteristics 10.3.5 STM8S103K3 STM8S103F3 STM8S103F2 Memory characteristics RAM and hardware registers Table 36: RAM and hardware registers Symbol Parameter VRM Data retention mode (1) Conditions Min Unit Halt mode (or reset) VIT-max (2) V (1) Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production. (2) Refer to the Operating conditions section for the value of VIT-max Flash program memory/data EEPROM memory Table 37: Flash program memory/data EEPROM memory Symbol Parameter VDD Conditions (1) Typ 2.95 - 5.5 - 6 6.6 Min Max Unit Operating voltage (all modes, execution/ fCPU 16 MHz V write/erase) tprog Standard programming time (including erase) for byte/word/block (1 byte/ 4 bytes/64 bytes) ms Fast programming time for - 3 3.33 - 3 3.33 TA = +85 C 100 000 - - TA = +125 C 300 000 1M - TRET = 55C 20 - - 1 block (64 bytes) terase Erase time for 1 block (64 bytes) NRW (2) Erase/write cycles (program memory) cycles Erase/write cycles (2) (data memory) tRET Data retention (program and data memory) after 10k erase/write cycles at TA = +55 C 70/117 DocID15441 Rev 9 years STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Symbol Parameter Conditions Typ Max 1 - - - 2 - (1) Min Unit Data retention (data memory) after 300k erase/write cycles at TRET = 85C TA = +125 C IDD Supply current (Flash programming or erasing mA for 1 to 128 bytes) (1) Data based on characterization results, not tested in production. (2) The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. 10.3.6 I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 38: I/O static characteristics Symbol Parameter Conditions VIL Input low level voltage VDD = 5 V Min Typ Max Unit 0.3 x -0.3 - VDD V VIH Input high level voltage Vhys Hysteresis Rpu Pull-up resistor tR, tF Rise and fall time (1) (10 % - 90 %) VDD = 5 V, VIN = VSS VDD + 0.7 x VDD - - 700 - mV 30 55 80 k - - 35 - - 125 - - 20 0.3 Fast I/Os Load = 50 pF Standard and high sink I/Os (3) (3) ns Load = 50 pF Fast I/Os DocID15441 Rev 9 (3) 71/117 Electrical characteristics Symbol STM8S103K3 STM8S103F3 STM8S103F2 Parameter Conditions Min Typ Max Unit - - 50 (3) (2) Load = 20 pF Standard and high sink I/Os Load = 20 pF Ilkg Digital input leakage current VSS VIN VDD - - 1 Ilkg ana Analog input leakage current VSS VIN VDD - - 250 - - 1 Ilkg(inj) Leakage current in adjacent I/O Injection current 4 mA (1) (2) (2) A nA A Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. (2) Data based on characterisation results, not tested in production. (3) Data guaranteed by design. Figure 22: Typical VIL and VIH vs VDD @ 4 temperatures 72/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 23: Typical pull-up resistance vs VDD @ 4 temperatures Figure 24: Typical pull-up current vs VDD @ 4 temperatures Table 39: Output driving current (standard ports) Symbol Parameter Conditions Output low level with 8 pins sunk IIO= 10 mA, VDD = 5 V VOL Output low level with 4 pins sunk IIO = 4 mA, VDD = 3.3 V VOH Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V DocID15441 Rev 9 Min Max - 2.0 - 2.8 (1) 1.0 Unit V - 73/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter Conditions Output high level with 4 pins sourced IIO = 4 mA, VDD = 3.3 V (1) Min Max (1) 2.1 Unit - Data based on characterization results, not tested in production Table 40: Output driving current (true open drain ports) Symbol (1) Parameter Conditions Max VOL Output low level with 2 pins sunk IIO = 10 mA, VDD = 5 V VOL Output low level with 2 pins sunk IIO = 10 mA, VDD = 3.3 V 1.5 VOL Output low level with 2 pins sunk IIO = 20 mA, VDD = 5 V 2.0 Unit 1 .0 (1) V (1) Data based on characterization results, not tested in production Table 41: Output driving current (high sink ports) Symbol VOL Parameter Conditions Output low level with 8 pins sunk IIO = 10 mA, VDD = 5 V Output low level with 4 pins sunk IIO = 10 mA, VDD = 3.3 V VOL Output low level with 4 pins sunk IIO = 20 mA, VDD = 5 V Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V VOH Output high level with 4 pins sourced IIO = 10 mA, VDD = 3.3 V Output high level with 4 pins sourced IIO = 20 mA, VDD = 5 V (1) 74/117 Data based on characterization results, not tested in production DocID15441 Rev 9 Min Max Unit - 0.8 V (1) - 1.0 - 1.5 (1) 4.0 - (1) - (1) - 2.1 3.3 V STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 25: Typ. VOL @ VDD = 5 V (standard ports) Figure 26: Typ. VOL @ VDD = 3.3 V (standard ports) DocID15441 Rev 9 75/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Figure 27: Typ. VOL @ VDD = 5 V (true open drain ports) Figure 28: Typ. VOL @ VDD = 3.3 V (true open drain ports) 76/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 29: Typ. VOL @ VDD = 5 V (high sink ports) Figure 30: Typ. VOL @ VDD = 3.3 V (high sink ports) DocID15441 Rev 9 77/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Figure 31: Typ. VDD - VOH@ VDD = 5 V (standard ports) Figure 32: Typ. VDD - VOH @ VDD = 3.3 V (standard ports) 78/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 33: Typ. VDD - VOH@ VDD = 5 V (high sink ports) Figure 34: Typ. VDD - VOH@ VDD = 3.3 V (high sink ports) 10.3.7 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 42: NRST pin characteristics Symbol Parameter Conditions VIL(NRST) NRST input low (1) Min -0.3 level voltage DocID15441 Rev 9 Typ Max - 0.3 x VDD Unit V 79/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter Conditions VIH(NRST) NRST input high (1) level voltage VOL(NRST) IOL=2 mA Typ (2) Unit - VDD + 0.3 - - 0.5 30 55 80 - - 75 (1) NRST pull-up Max 0.7 x VDD NRST output low level voltage RPU(NRST) Min k resistor tI FP(NRST) NRST input filtered (3) pulse ns tIN FP(NRST) NRST input not (3) 500 - - 20 - - filtered pulse tOP(NRST) NRST output pulse (3) (1) Data based on characterization results, not tested in production. (2) The RPU pull-up equivalent resistor is based on a resistive transistor (3) Data guaranteed by design, not tested in production. Figure 35: Typical NRST VIL and VIH vs VDD @ 4 temperatures 80/117 DocID15441 Rev 9 s STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 36: Typical NRST pull-up resistance vs VDD @ 4 temperatures Figure 37: Typical NRST pull-up current vs VDD @ 4 temperatures The reset network shown in the following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below VIL(NRST) max. (see Table 38: I/O static characteristics ), otherwise the reset is not taken into account internally. For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. Minimum recommended capacity is 100 nF. DocID15441 Rev 9 81/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Figure 38: Recommended reset pin protection STM8 VDD RPU External reset circuit NRST Internal reset Filter 0.1 F (optional) 10.3.8 SPI serial peripheral interface Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 43: SPI characteristics Symbol Parameter fSCK1/ SPI clock tc(SCK) frequency fSCK1/ fSCK1/ tc(SCK) (1) Conditions 0 SPI clock frequency tr(SCK) SPI clock rise and Capacitive load: C = 30 pF tf(SCK) fall time (3) NSS setup time Max Slave mode NSS hold time Slave mode MHz (2) MHz 7 - 25 4x - 70 - tw(SCKH) (3) SCK high and low Master mode tSCK/ tSCK/ tw(SCKL) (3) time 2 - 15 2 +15 tsu(MI) (3) Data input setup Master mode 5 - tsu(SI) (3) time Slave mode 5 - th(MI) (3) Data input hold Master mode 7 - time Slave mode 10 - th(SI) 82/117 (3) 8 0 tMASTER th(NSS) Unit Master mode tc(SCK) tsu(NSS) Min (3) DocID15441 Rev 9 ns STM8S103K3 STM8S103F3 STM8S103F2 Symbol ta(SO) (3) (4) Electrical characteristics Parameter (1) Conditions Data output (3) (5) Data output (3) th(SO) th(MO) (3) (3) (3) tMASTER Slave mode 25 Data output valid Slave mode time tv(MO) Unit 3x - disable time tv(SO) Max Slave mode access time tdis(SO) Min (after enable edge) - - (2) 65 Data output valid Master mode time (after enable edge) Data output hold Slave mode time (after enable edge) Data output hold Master mode time (after enable edge) - 30 (2) - (2) - 27 11 (1) Parameters are given by selecting 10 MHz I/O output frequency. (2) Data characterization in progress. (3) Values based on design simulation and/or characterization results, and not tested in production. (4) Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. (5) Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. DocID15441 Rev 9 83/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Figure 39: SPI timing diagram - slave mode and CPHA = 0 NSS input SCK Input tSU(NSS) CPHA= 0 CPOL=0 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT M SB IN B I T1 IN LSB IN th(SI) ai14134 Figure 40: SPI timing diagram - slave mode and CPHA = 1 NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) M SB IN B I T1 IN LSB IN ai14135 1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD. 84/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics (1) Figure 41: SPI timing diagram - master mode High NSS input SCK intput SCK output tc(SCK) CPHA= 0 CPOL=0 CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136b 1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD. 10.3.9 2 I C interface characteristics 2 Table 44: I C characteristics Symbol Parameter 2 (2) Max (2) Max Min - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time 0 (3) - 0 (4) 900 tr(SCL) tf(SDA) tf(SCL) Unit (2) 4.7 tr(SDA) SCL clock low time Fast mode I C (2) Min tw(SCLL) 2 (1) Standard mode I C s (3) SDA and SCL rise time - 1000 - 300 SDA and SCL fall time - 300 - 300 th(STA) START condition hold time 4.0 - 0.6 - tsu(STA) Repeated START condition setup time 4.7 - 0.6 - ns s DocID15441 Rev 9 85/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter 2 (2) STOP condition setup time tw(STO:STA) STOP to START condition time (bus free) Cb Fast mode I C (2) Min tsu(STO) 2 (1) Standard mode I C Max (2) Max Min Unit (2) 4.0 - 0.6 - 4.7 - 1.3 - s 400 - 400 pF Capacitive load for each bus line (1) fMASTER, must be at least 8 MHz to achieve max fast I C speed (400kHz) 2 (2) Data based on standard I C protocol requirement, not tested in production 2 (3) The maximum hold time of the start condition has only to be met if the interface does not stretch the low time (4) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 2 Figure 42: Typical application with I C bus and timing diagram VDD 4.7k VDD 4.7k I2C bus STM8S 100 SDA 100 SCL REPEATED START START tsu(STA) tw(STO:STA) SDA tr(SDA) tf(SDA) tsu(SDA) th(SDA) tr(SCL) tf(SCL) START STOP SCL th(STA) tw(SCLH) tw(SCLL) tsu(STO) ai17490 1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD. 10.3.10 10-bit ADC characteristics Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified. 86/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Table 45: ADC characteristics Symbol Parameter Conditions fADC VDD =2.95 to 5.5 V ADC clock frequency Min Typ Max Unit - 1 4 MHz VDD =4.5 to 5.5 V VAIN (1) Conversion voltage range CADC Internal sample and hold capacitor tS (1) Minimum sampling time fADC = 4 MHz 1 - 6 VSS - VDD V - 3 - pF - 0.75 s fADC = 6 MHz tSTAB Wake-up time from standby tCONV Minimum total conversion time fADC = 4 MHz (including sampling time, 10-bit resolution) fADC = 6 MHz - 0.5 - - 7 - s 3.5 s 2.33 s 14 1/fADC (1) During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming. Table 46: ADC accuracy with RAIN < 10 k , VDD= 5 V Symbol Parameter |ET| Total unadjusted error (2) (1) Conditions Typ Max fADC = 2 MHz 1.6 3.5 fADC = 4 MHz 2.2 4 fADC = 6 MHz 2.4 4.5 fADC = 2 MHz 1.1 2.5 Unit LSB |EO| (2) Offset error DocID15441 Rev 9 87/117 Electrical characteristics Symbol |EG| |ED| |EL| (1) STM8S103K3 STM8S103F3 STM8S103F2 Parameter (2) Gain error (2) Differential linearity error (2) Integral linearity error (1) Conditions Typ Max fADC = 4 MHz 1.5 3 fADC = 6 MHz 1.8 3 fADC = 2 MHz 1.5 3 fADC = 4 MHz 2.1 3 fADC = 6 MHz 2.2 4 fADC = 2 MHz 0.7 1.5 fADC = 4 MHz 0.7 1.5 fADC = 6 MHz 0.7 1.5 fADC = 2 MHz 0.6 1.5 fADC = 4 MHz 0.8 2 fADC = 6 MHz 0.8 2 Unit Data based on characterization results, not tested in production. (2) ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy. Table 47: ADC accuracy with RAIN < 10 k RAIN, VDD = 3.3 V Symbol Parameter |ET| |EO| 88/117 (2) Total unadjusted error (2) Offset error (1) Conditions Typ Max fADC = 2 MHz 1.6 3.5 fADC = 4 MHz 1.9 4 fADC = 2 MHz 1 2.5 DocID15441 Rev 9 Unit LSB STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Symbol Parameter |EG| |ED| |EL| (1) (2) Gain error (2) Differential linearity error (2) Integral linearity error (1) Conditions Typ Max fADC = 4 MHz 1.5 2.5 fADC = 2 MHz 1.3 3 fADC = 4 MHz 2 3 fADC = 2 MHz 0.7 1 fADC = 4 MHz 0.7 1.5 fADC = 2 MHz 0.6 1.5 fADC = 4 MHz 0.8 2 Unit Data based on characterization results, not tested in production. (2) ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in I/O port pin characteristics does not affect the ADC accuracy. Figure 43: ADC accuracy characteristics 1. Example of an actual transfer curve. 2. The ideal transfer curve DocID15441 Rev 9 89/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 3. End point correlation line ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves. EO = Offset error: deviation between the first actual transition and the first ideal one. EG = Gain error: deviation between the last ideal transition and the last actual one. ED = Differential linearity error: maximum deviation between actual steps and the ideal one. EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation line. Figure 44: Typical application with ADC VDD VAIN RAIN AINx VT 0.6 V 10-bit A/D conversion VT 0.6 V CAIN 10.3.11 STM8 IL 1 A CADC EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 10.3.11.1 Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard. * A burst of fast transient voltage (positive and negative) is applied to V and V * FTB: through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with DD SS the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 (EMC design guide for STMicrocontrollers). 10.3.11.2 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. 90/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques for improving microcontroller EMC performance). Table 48: EMS data Symbol Parameter Conditions Level/ class VFESD Voltage limits to be applied on any I/O pin to VDD = 3.3 V, TA = 25 C, fMASTER = 16 MHz (1) 2/B induce a functional (HSI clock), conforming to IEC 61000-4-2 disturbance VEFTB Fast transient voltage burst limits to be applied (1) through 100 pF on VDD VDD= 3.3 V, TA = 25 C ,fMASTER = 16 MHz 4/A (HSI clock),conforming to IEC 61000-4-4 and VSS pins to induce a functional disturbance (1) Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 (EMC guidelines for STM8S microcontrollers). 10.3.11.3 Electromagnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE IEC 61967-2 which specifies the board and the loading of each pin. Table 49: EMI data Conditions Symbol Parameter Peak level SEMI Max fHSE/fCPU General conditions Monitored frequency band 16 MHz/ 16 MHz/ VDD = 5 V 0.1 MHz to TA = 25 C 30 MHz LQFP32 package (1) 30 MHz to DocID15441 Rev 9 8 MHz 16 MHz 5 5 Unit dBV 4 5 91/117 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Conditions Symbol Parameter Max fHSE/fCPU General conditions (1) Monitored frequency band 16 MHz/ 16 MHz/ Conforming to 130 MHz SAE IEC 61967-2 130 MHz to 8 MHz 16 MHz 5 5 2.5 2.5 Unit 1 GHz SAE EMI level (1) SAE EMI level Data based on characterisation results, not tested in production. 10.3.11.4 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, DLU and LU) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. 10.3.11.5 Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated: Human body model. This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181. Table 50: ESD absolute maximum ratings Symbol Ratings Conditions VESD(HBM) Electrostatic discharge TA = 25C, conforming to voltage JESD22-A114 Class Maximum Unit (1) value A 4000 (Human body model) V VESD(CDM) 92/117 Electrostatic discharge TA LQFP32 package = voltage 25C, conforming to (Charge device model) SD22-C101 DocID15441 Rev 9 IV 1000 STM8S103K3 STM8S103F3 STM8S103F2 (1) Electrical characteristics Data based on characterization results, not tested in production 10.3.11.6 Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance: A supply overvoltage (applied to each power supply pin) * injection (applied to each input, output and configurable I/O pin) are performed * Aoncurrent each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 51: Electrical sensitivities Symbol LU Parameter Conditions Static latch-up class (1) Class TA = 25 C A TA = 85 C A TA = 125 C A (1) Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). DocID15441 Rev 9 93/117 Package information 11 STM8S103K3 STM8S103F3 STM8S103F2 Package information In order to meet environmental requirements, ST offers these devices in different grades of (R) (R) ECOPACK packages, depending on their level of environmental compliance. ECOPACK (R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 11.1 32-pin LQFP package mechanical data Figure 45: 32-pin low profile quad flat package (7 x 7) ccc C D D1 D3 24 A A2 17 16 25 L1 b E3 32 E1 E 9 Pin 1 identification L A1 1 K c 8 5V_ME Table 52: 32-pin low profile quad flat package mechanical data Dim. (1) mm Min inches Typ A 94/117 Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.300 c 0.090 D 8.800 D1 6.800 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.370 0.450 0.0118 0.0146 0.0177 0.200 0.0035 9.000 9.200 0.3465 0.3543 0.3622 7.000 7.200 0.2677 0.2756 0.2835 DocID15441 Rev 9 0.0059 0.0079 STM8S103K3 STM8S103F3 STM8S103F2 Dim. Package information (1) mm Min D3 inches Typ Max Min 5.600 Typ Max 0.2205 E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 5.600 0.2205 e 0.800 0.0315 L 0.450 L1 0.750 0.0177 1.000 k 0.0 ccc (1) 0.600 3.5 0.0236 0.0295 0.0394 7.0 0.0 3.5 0.100 7.0 0.0039 Values in inches are converted from mm and rounded to 4 decimal digits DocID15441 Rev 9 95/117 Package information 11.2 STM8S103K3 STM8S103F3 STM8S103F2 32-lead UFQFPN package mechanical data Figure 46: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) AOB8_ME 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground. 4. Dimensions are in millimeters. Table 53: 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data Dim. inches Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0 0.020 0.050 0.0008 0.0020 A3 96/117 (1) mm 0.200 DocID15441 Rev 9 0.0079 STM8S103K3 STM8S103F3 STM8S103F2 Dim. Package information (1) mm inches Min Typ Max Min Typ Max b 0.180 0.250 0.300 0.0071 0.0098 0.0118 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D2 3.200 3.450 3.700 0.1260 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E2 3.200 3.450 3.700 0.1260 0.1358 0.1457 e 0.500 L 0.300 0.0197 0.400 0.500 ddd (1) 11.3 0.1457 0.0118 0.0157 0.080 0.0197 0.0031 Values in inches are converted from mm and rounded to 4 decimal digits. 20-lead UFQFPN package mechanical data Figure 47: 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) D E Pin 1 TOP VIEW L1 D ddd L4 e 10 A3 L2 5 11 e b E 1 15 20 16 L3 A1 BOTTOM VIEW A SIDE VIEW 103_A0A5_ME DocID15441 Rev 9 97/117 Package information STM8S103K3 STM8S103F3 STM8S103F2 1. Drawing is not to scale. Table 54: 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package mechanical data Dim. Min inches Typ Max Min Typ Max D 3.000 0.1181 E 3.000 0.1181 A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 A3 0.152 0.0060 e 0.500 0.0197 L1 0.500 0.550 0.600 0.0197 0.0217 0.0236 L2 0.300 0.350 0.400 0.0118 0.0138 0.0157 L3 0.150 0.0059 L4 0.200 0.0079 b 0.180 ddd 0.050 (1) 11.4 (1) mm 0.250 0.300 0.0071 0.0098 0.0118 0.0020 Values in inches are converted from mm and rounded to 4 decimal digits. SDIP32 package mechanical data Figure 48: 32-lead shrink plastic DIP (400 ml) package Table 55: 32-lead shrink plastic DIP (400 ml) package mechanical data Dim. Min 98/117 (1) mm A 3.556 A1 0.508 inches Typ 3.759 Max 5.080 Min 0.1400 0.0200 DocID15441 Rev 9 Typ 0.1480 Max 0.2000 STM8S103K3 STM8S103F3 STM8S103F2 Dim. Package information (1) mm Min inches Typ Max Min Typ Max A2 3.048 3.556 4.572 0.1200 0.1400 0.1800 B 0.356 0.457 0.584 0.0140 0.0180 0.0230 B1 0.762 1.016 1.397 0.0300 0.0400 0.0550 C 0.203 0.254 0.356 0.0079 0.0100 0.0140 D 27.430 27.940 28.450 1.0799 1.1000 1.1201 E 9.906 10.410 11.050 0.3900 0.4098 0.4350 E1 7.620 8.890 9.398 0.3000 0.3500 0.3700 e 1.778 0.0700 eA 10.160 0.4000 eB L (1) 12.700 2.540 3.048 3.810 0.5000 0.1000 0.1200 0.1500 Values in inches are converted from mm and rounded to 4 decimal digits DocID15441 Rev 9 99/117 Package information 11.5 STM8S103K3 STM8S103F3 STM8S103F2 20-pin TSSOP package mechanical data Figure 49: 20-pin, 4.40 mm body, 0.65 mm pitch D 20 11 c E1 1 E 10 k aaa CP A1 A L A2 L1 b e YA_ME Table 56: 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data Dim. (1) mm Min inches Typ A Min Typ 1.200 A1 0.050 A2 0.800 b Max 0.0472 0.150 0.0020 1.050 0.0315 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 D 6.400 6.500 6.600 0.2520 0.2559 0.2598 E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1 4.300 4.400 4.500 0.1693 0.1732 0.1772 e L L1 100/117 Max 1.000 0.650 0.450 0.600 0.0059 0.0394 0.0413 0.0256 0.750 1.000 DocID15441 Rev 9 0.0177 0.0236 0.0394 0.0295 STM8S103K3 STM8S103F3 STM8S103F2 Dim. (1) mm inches Min k Package information Typ 0.0 aaa (1) 11.6 Max Min 8.0 0.0 Typ Max 8.0 0.100 0.0039 Values in inches are converted from mm and rounded to 4 decimal digits 20-pin SO package mechanical data Figure 50: 20-lead, plastic small outline (300 mils) package D 20 11 h x 45 C E 1 H 10 A B A1 e ddd A1 k L Z7_ME Table 57: 20-lead, plastic small outline (300 mils) mechanical data Dim. (1) mm Min inches Typ Max Min Typ Max A 2.350 2.650 0.0925 0.1043 A1 0.100 0.300 0.0039 0.0118 B 0.330 0.510 0.013 0.0201 C 0.230 0.320 0.0091 0.0126 D 12.600 13.000 0.4961 0.5118 E 7.400 7.600 0.2913 0.2992 e 1.270 DocID15441 Rev 9 0.0500 101/117 Package information Dim. STM8S103K3 STM8S103F3 STM8S103F2 (1) mm inches Min Typ Min Typ 10.000 10.650 0.3937 0.4193 h 0.250 0.750 0.0098 0.0295 L 0.400 1.270 0.0157 0.0500 k 0.0 8.0 0.0 8.0 (1) 0.100 0.0039 Values in inches are converted from mm and rounded to 4 decimal digits UFQFPN recommended footprint Figure 51: Recommended footprint for on-board emulation 0.5mm 0.8mm [0.032"] 4mm [0.157"] 0.5mm 1.65mm [0.065"] 0.9mm [0.035"] 0.3mm [0.012"] 4mm [0.157"] ai15319 Bottom view 1. Drawing is not to scale 102/117 Max H ddd 11.7 Max DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Package information Figure 52: Recommended footprint without on-board emulation 1. Drawing is not to scale 2. Dimensions are in millimeters DocID15441 Rev 9 103/117 Thermal characteristics 12 STM8S103K3 STM8S103F3 STM8S103F2 Thermal characteristics The maximum chip junction temperature (TJ max) must never exceed the values given in Operating conditions. The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x JA) Where: TAmax is the maximum ambient temperature in C * * is the package junction-to-ambient thermal resistance in C/W * P is the sum of P and P (PDmax = P + P ) * Ppower. is the product of I andV , expressed in Watts. This is the maximum chip internal * P represents the maximum power dissipation on output pins JA Dmax INTmax INTmax I/Omax DD INTmax I/Omax DD I/Omax Where: PI/Omax = (VOL*IOL) + ((VDD-VOH)*IOH), taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application. Table 58: Thermal characteristics (1) Symbol Parameter Value Unit JA Thermal resistance junction-ambient 84 C/W TSSOP20 - 4.4 mm JA Thermal resistance junction-ambient 91 SO20W (300 mils) JA Thermal resistance junction-ambient 90 UFQFPN20 - 3 x 3 mm JA Thermal resistance junction-ambient 60 LQFP32 - 7 x 7 mm JA Thermal resistance junction-ambient 38 UFQFPN32 - 5 x 5 mm JA Thermal resistance junction-ambient 60 SDIP32 - 400 mils (1) Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. 104/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 12.1 Thermal characteristics Reference document JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org. 12.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code. The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions: Maximum ambient temperature TAmax= 75 C (measured according to JESD51-2) * * I = 8 mA, V = 5 V * Maximum 20 I/Os used at the same time in output at low level with DDmax DD IOL = 8 mA, VOL= 0.4 V * PINTmax = 8 mA x 5 V = 400 mW Amax PDmax = 400 mW + 64 mW Thus: PDmax = 464 mW TJmax for LQFP32 can be calculated as follows, using the thermal resistance JA: TJmax = 75 C + (60 C/W x 464 mW) = 75 C + 27.8 C = 102.8 C This is within the range of the suffix 6 version parts (-40 < TJ < 105 C). In this case, parts must be ordered at least with the temperature range suffix 6. DocID15441 Rev 9 105/117 Ordering information 13 STM8S103K3 STM8S103F3 STM8S103F2 Ordering information Figure 53: STM8S103x access line ordering information scheme Example: STM8 S 103 K 3 T 6 TR Product class STM8 microcontroller Family type S = Standard Sub-family type 10x = Access line 103 sub-family Pin count K = 32 pins F = 20 pins Program memory size 3 = 8 Kbytes 2 = 4 Kbytes Package type 1 B = SDIP T = LQFP U = UFQFPN P = TSSOP M = SO Temperature range 3 = -40 C to 125 C 6 = -40 C to 85 C Package pitch Blank = 0.5 or 0.65 mm(2) C = 0.8 mm(3) Packing No character = Tray or tube TR = Tape and reel 1. A dedicated ordring information scheme will be released if, in the future, memory programming service (FastROM) is required The letter "P" will be added after STM8S. Three unique letters identifying the customer application code will also be visible in the codification. Example: STM8SP103K3MACTR. 2. UFQFPN, TSSOP, and SO packages. 3. LQFP package. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you. 13.1 STM8S103 FASTROM microcontroller option list (last update: April 2010) Customer 106/117 ............................................................................................. DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Ordering information Address ............................................................................................. Contact ............................................................................................. Phone no. ............................................................................................. a Reference FASTROM code ............................................................................................. Preferable format for programing code is .Hex (.s19 is accepted) If data EEPROM programing is required, a seperate file must be sent with the requested data. Important: See the option byte section in the datasheet for authorized option byte combinations and a detailed explanation. Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and AFR0. Device type/memory size/package (check only one option) FASTROM device 4 Kbyte LQFP32 UFQFPN20 8 Kbyte [ ] STM8S103K3 [ ] STM8S103F2 UFQFPN32 [ ] STM8S103F3 [ ] STM8S103K3 TSSOP20 [ ] STM8S103F2 [ ] STM8S103F3 SO20W [ ] STM8S103F2 [ ] STM8S103F3 Conditioning (check only one option) [ ] Tape & reel or [ ] Tray Special marking (check only one option) [ ] No [ ] Yes Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character counts are: UFQFPN20: 1 line of 4 characters max: "_ _ _ _" UFQFPN32: 1 line of 7 characters max: "_ _ _ _ _ _ _" LQFP32: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _" TSSOP20/SO20: 1 line of 10 characters max: "_ _ _ _ _ _ _ _ _ _" Three characters are reserved for code identification. Temperature range [ ] -40C to +85C or [ ] -40C to +125C Padding value for unused program memory (check only one option) a [ ]0xFF Fixed value [ ]0x83 TRAP instruction opcode [ ]0x75 Illegal opcode (causes a reset when executed) FASTROM code name is assigned by STMicroelectronics. DocID15441 Rev 9 107/117 Ordering information STM8S103K3 STM8S103F3 STM8S103F2 OPT0 memory readout protection (check only one option) [ ] Disable or [ ] Enable OPT1 user boot code area (UBC) 0x(_ _) fill in the hexadecimal value, refering to the datasheet and the binary format below. UBC, bit0 [ ] 0: Reset [ ] 1: Set UBC bit1 [ ] 0: Reset [ ] 1: Set UBC bit2 [ ] 0: Reset [ ] 1: Set UBC bit3 [ ] 0: Reset [ ] 1: Set UBC bit4 [ ] 0: Reset [ ] 1: Set UBC bit5 [ ] 0: Reset [ ] 1: Set UBC bit6 [ ] 0: Reset [ ] 1: Set UBC bit7 [ ] 0: Reset [ ] 1: Set OPT2 alternate function remapping for STM8S103K Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and AFR0. AFR0 AFR1 (check only one option) Reserved [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description [ ] 1: Port A3 alternate function = SPI_NSS and port D2 alternate function = TIM2_CH3 108/117 AFR2 Reserved AFR3 Reserved AFR4 Reserved DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 AFR5 (check only one option) Ordering information [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description [ ] 1: Port D0 alternate function = CLK_CCO AFR6 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description [ ] 1: Port D7 alternate function = TIM1_CH4 AFR7 Reserved OPT2 alternate function remapping for STM8S103F Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and AFR0. AFR0 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description [ ] 1: Port C5 alternate function = TIM2_CH1, port C6 alternate function = TIM1_CH1, and port C7 alternate function = TIM1_CH2 AFR1 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description [ ] 1: Port A3 alternate function = SPI_NSS and port D2 alternate function = TIM2_CH3 AFR2 AFR3 (check only one option) Reserved [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description [ ] 1: Port C3 alternate function = TLI AFR4 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description [ ] 1: Port B4 alternate function = ADC_ETR and port B5 alternate function = TIM1_BKIN AFR5 Reserved AFR6 Reserved AFR7 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description [ ] 1: Port C3 alternate function = TIM1_CH1N and port C4 alternate function = TIM1_CH2N OPT3 watchdog WWDG_HALT [ ] 0: No reset generated on halt if WWDG active DocID15441 Rev 9 109/117 Ordering information (check only one option) WWDG_HW (check only one option) IWDG_HW (check only one option) LSI_EN (check only one option) HSITRIM (check only one option) STM8S103K3 STM8S103F3 STM8S103F2 [ ] 1: Reset generated on halt if WWDG active [ ] 0: WWDG activated by software [ ] 1: WWDG activated by hardware [ ] 0: IWDG activated by software [ ] 1: IWDG activated by hardware [ ] 0: LSI clock is not available as CPU clock source [ ] 1: LSI clock is available as CPU clock source [ ] 0: 3-bit trimming supported in CLK_HSITRIMR register [ ] 1: 4-bit trimming supported in CLK_HSITRIMR register OPT4 wakeup PRSC (check only one option) [ ] for 16 MHz to 128 kHz prescaler [ ] for 8 MHz to 128 kHz prescaler [ ] for 4 MHz to 128 kHz prescaler CKAWUSEL (check only one option) EXTCLK (check only one option) [ ] LSI clock source selected for AWU [ ] HSE clock with prescaler selected as clock source for for AWU [ ] External crystal connected to OSCIN/OSCOUT [ ] External clock signal on OSCIN OPT5 crystal oscillator stabilization HSECNT (check only one option) [ ] 2048 HSE cycles [ ] 128 HSE cycles [ ] 8 HSE cycles [ ] 0.5 HSE cycles OPT6 is reserved Comments: ........................................................................................................... Supply operating range ........................................................................................................... in the application: 110/117 Notes: ........................................................................................................... Date: ........................................................................................................... Signature: ........................................................................................................... DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 14 STM8 development tools STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 14.1 Emulation and in-circuit debugging tools The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller. For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers. STice key features Occurrence and time profiling and code coverage (new features) * * Advanced breakpoints with up to 4 levels of conditions * Data breakpoints * Program and data trace recording up to 128 KB records * Read/write on the fly of memory during emulation * In-circuit debugging/programming via SWIM protocol * 8-bit probe analyzer * 1 input and 2 output triggers * Power supply follower managing application voltages between 1.62 to 5.5 V that allows you to specify the components you need to meet your development * Modularity requirements and adapt to future requirements by free software tools that include integrated development environment (IDE), * Supported programming software interface and assembler for STM8. 14.2 Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8, which are available in a free version that outputs up to 16 Kbytes of code. DocID15441 Rev 9 111/117 STM8 development tools 14.2.1 STM8S103K3 STM8S103F3 STM8S103F2 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST Visual Develop - Full-featured integrated development environment from ST, featuring Seamless integration of C and ASM toolsets * * Full-featured debugger * Project management * Syntax highlighting editor * Integrated programming interface * Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer (STVP) - Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8 microcontroller's Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences. 14.2.2 C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. Available toolchains include: Cosmic C compiler for STM8 - Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.cosmic-software.com. * C compiler for STM8 - Available in a free version that outputs up to * Raisonance 16 Kbytes of code. For more information, see www.raisonance.com. assembler linker - Free assembly toolchain included in the STVD toolset, which * STM8 allows you to assemble and link your application source code. 14.3 Programming tools During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family. 112/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 15 Revision history Revision history Table 59: Document revision history Date 02-Mar-2009 10-Apr-2009 Revision 1 2 Changes Initial revision Added Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers. Updated Auto wakeup counter. Modified description of PB4 and PB5 (removed X in PP column) and added footnote concerning HS I/Os in VFQFPN32/LQFP32 pin description and STM8S103Kx UFQFPN32/LQFP32/SDIP32 pinout and pin description. Removed TIM3 and UART from Table 10: Interrupt mapping. Updated VCAP specifications in VCAP external capacitor. Corrected block size in Table 37: Flash program memory/data EEPROM memory. Updated Electrical characteristics. Updated Table 58: Thermal characteristics. 10-Jun-2009 3 Document status changed from "preliminary data" to "datasheet". Replaced WFQFPN20 package with UFQFPN package. Replaced `VFQFN' with `VFQFPN'. Added bullet point on the unique identifier to Features. Updated Auto wakeup counter. Updated wpu and PP status of PB5/12C_SDA and PB4/12C_SCL pins in VFQFPN32/LQFP32 pin description and STM8S103Fx TSSOP20/SO20/UFQFPN20 pin description. Removed Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin access line devices. Updated Figure 7: Memory map. Updated reset status of port D CR1 register in Table 7: I/O port hardware register map. Updated alternate function remapping descriptions in Table 13: STM8S103K alternate function remapping bits for 32-pin devices and Table 14: STM8S103F alternate function remapping bits for 20-pin devices. Added Unique ID. DocID15441 Rev 9 113/117 Revision history Date STM8S103K3 STM8S103F3 STM8S103F2 Revision Changes Updated Table 19: General operating conditions. Updated name of Figure. Typical HSI accuracy at VDD = 5V vs 5 temperatures. Updated Table 43: SPI characteristics and added TBD data. Added max values to Table 46: ADC accuracy with RAIN < 10 k , VDD= 5 V and Table 47: ADC accuracy with RAIN < 10 k RAIN, VDD = 3.3 V in the 10-bit ADC characteristics. Updated EMC characteristics. 16-Oct-2009 4 Replaced VFQFPN32 package by UFQFPN32 package. Clock controller: replaced "TIM2" and "TIM3" with "reserved" and "TIM2" respectively in "Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers" table. Total current consumption in halt mode: changed the maximum current consumption limit at 125 C (and VDD = 5 V) from 35 A to 55 A. Functional EMS (electromagnetic susceptibility) : "ESD" changed to "FESD" (functional); added name of AN1709; replaced "IEC 1000" with "IEC 61000". Designing hardened software to avoid noise problems: replaced "IEC 1000" with "IEC 61000", added title of AN1015, and added footnote to EMS data table. Electromagnetic interference (EMI): replaced "J 1752/3" with "IEC 61967-2" and updated data of the EMI data table. Selecting the product temperature range: changed the value of LQFP32 7x7 mm thermal resistance from 59 C/W to 60 C/W. Added STM8S103 FASTROM microcontroller option list. 22-Apr-2010 5 Added VFQFPN32 and SO20 packages. Updated Px_IDR reset value in Table 7: I/O port hardware register map. Operating conditions: updated VCAP and ESR low limit, added ESL parameter, and Note 1 below Table 19: General operating conditions. Updated ACCHSI in Table 34: HSI oscillator characteristics table. Modified IDD(H) in Table 27: Total current consumption in halt mode at VDD = 5 V and Table 28: Total current consumption in halt mode at VDD = 3.3 V. Removed note 3 related to Accuracy of HSI oscillator. 114/117 DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Date Revision Revision history Changes Updated maximum power dissipation in Table 19: General operating conditions. Updated JA in Table 58: Thermal characteristics. Replaced package pitch digit by VFQFPN/UFQFPN package digit in Figure 53: STM8S103x access line ordering information scheme, and removed note 1. 09-Sep-2010 6 Removed VFQFPN32 package. Removed internal reference voltage from Analog-to-digital converter (ADC1). Updated "reset state" of Table 4: Legend/abbreviations for pinout tables in Pinout and pin description. Added footnote to PD1/SWIM pin in STM8S103Kx UFQFPN32/LQFP32/SDIP32 pinout and pin description. Updated pins 14 and 19 (TSSOP20/SO20) / pins 11 and 16 (UFQFPN20) in STM8S103Fx TSSOP20/SO20/UFQFPN20 pin description. General hardware register map : Standardized all reset state values; updated the reset state values of the RST_SR, CLK_SWCR, CLK_HSITRIMR, CLK_SWIMCCR, IWDG_KR, and ADC_DRx registers in the "General hardware register map" table. Updated AFR2 description of OPT 2 in Table 14: STM8S103F alternate function remapping bits for 20-pin devices. Replaced 0.01 F with 0.1 f in Figure 38: Recommended reset pin protection. 2 Added "Typical application with I C bus and timing diagram in I2C interface characteristics. Updated footnote 1 in Table 46: ADC accuracy with RAIN < 10 k , VDD= 5 V and Table 47: ADC accuracy with RAIN < 10 k RAIN, VDD = 3.3 V . STM8S103 FASTROM microcontroller option list: updated "special marking" section and AFR2 description of OPT2 alternate function remapping for STM8S103F. 32-lead UFQFPN package mechanical data: updated existing footnote and added three additional footnotes. 12-Jul-2011 7 Updated note related to true open-drain outputs in Table 6: STM8S103Fx pin description. Remove CLK_CANCCR register from Table 8: General hardware register map DocID15441 Rev 9 115/117 Revision history Date STM8S103K3 STM8S103F3 STM8S103F2 Revision Changes Added note for Px_IDR registers in Table 7: I/O port hardware register map. Added recommendation concerning NRST pin level, and power consumption sensitive applications, above Figure 38: Recommended reset pin protection. Removed typical HSI accuracy curve in Internal clock sources and timing characteristics. Renamed package type 2 into package pitch and added pitch code "C" in Figure 53: STM8S103x access line ordering information scheme, and added UFQFPN20 in STM8S103 FASTROM microcontroller option list. Updated disclaimer. 04-Apr-2012 8 Updated notes related to VCAP in Table 19: General operating conditions. Added values of tR/tF for 50 pF load capacitance, and updated note in Table 38: I/O static characteristics. Updated typical and maximum values of RPU in Table 38: I/O static characteristics and Table 42: NRST pin characteristics. Changed SCK input to SCK output in SPI serial peripheral interface Modified Figure 47: 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3)to add package top view. 26-Jun-2012 116/117 9 Added SDIP32 package. DocID15441 Rev 9 STM8S103K3 STM8S103F3 STM8S103F2 Please Read Carefully Information in this document is provided solely in connection with ST products. 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