STM8S103K3 STM8S103F3 STM8S103F2
Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data
EEPROM,10-bit ADC, 3 timers, UART, SPI, I²C
LQFP32 7x7 UFQFPN32 5x5
TSSOP20 UFQFPN20 3x3
SO20W 300 mils
SDIP32 400 mils
Features
Core
•16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
•Extended instruction set
Memories
•Program memory: 8 Kbytes Flash; data retention
20 years at 55 °C after 10 kcycles
•Data memory: 640 bytes true data EEPROM;
endurance 300 kcycles
•RAM: 1 Kbytes
Clock, reset and supply management
•2.95 to 5.5 V operating voltage
•Flexible clock control, 4 master clock sources:
-Low power crystal resonator oscillator
-External clock input
-Internal, user-trimmable 16 MHz RC
-Internal low power 128 kHz RC
•Clock security system with clock monitor
•Power management:
-Low power modes (wait, active-halt, halt)
-Switch-off peripheral clocks individually
•Permanently active, low consumption power-on
and power-down reset
Interrupt management
•Nested interrupt controller with 32 interrupts
•Up to 27 external interrupts on 6 vectors
Timers
•Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
•16-bit general purpose timer, with 3 CAPCOM
channels (IC, OC or PWM)
•8-bit basic timer with 8-bit prescaler
•Auto wake-up timer
•Window watchdog and independent watchdog
timers
Communications interfaces
•UART with clock output for synchronous
operation, Smartcard, IrDA, LIN master mode
•SPI interface up to 8 Mbit/s
•I2C interface up to 400 Kbit/s
Analog to digital converter (ADC)
•10-bit, ±1 LSB ADC with up to 5 multiplexed
channels, scan mode and analog watchdog
I/Os
•Up to 28 I/Os on a 32-pin package including 21
high sink outputs
•Highly robust I/O design, immune against current
injection
Development support
•Embedded single wire interface module (SWIM)
for fast on-chip programming and non intrusive
debugging
Unique ID
•96-bit unique key for each device
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DocID15441 Rev 9
June 2012
www.st.com
Contents
1 Introduction ..............................................................................................................8
2 Description ...............................................................................................................9
3 Block diagram ........................................................................................................10
4 Product overview ...................................................................................................11
4.1 Central processing unit STM8 .....................................................................................11
4.2 Single wire interface module (SWIM) and debug module (DM) ..................................11
4.3 Interrupt controller .......................................................................................................12
4.4 Flash program and data EEPROM memory ................................................................12
4.5 Clock controller ............................................................................................................13
4.6 Power management ....................................................................................................14
4.7 Watchdog timers ..........................................................................................................14
4.8 Auto wakeup counter ...................................................................................................15
4.9 Beeper ........................................................................................................................15
4.10 TIM1 - 16-bit advanced control timer .........................................................................15
4.11 TIM2 - 16-bit general purpose timer ..........................................................................16
4.12 TIM4 - 8-bit basic timer ..............................................................................................16
4.13 Analog-to-digital converter (ADC1) ............................................................................16
4.14 Communication interfaces .........................................................................................17
4.14.1 UART1 ...............................................................................................17
4.14.2 SPI .....................................................................................................18
4.14.3 I²C ......................................................................................................18
5 Pinout and pin description ...................................................................................19
5.1 STM8S103Kx UFQFPN32/LQFP32/SDIP32 pinout and pin description .....................20
5.2 STM8S103Fx TSSOP20/SO20/UFQFPN20 pinout and pin description .....................24
5.2.1 STM8S103Fx TSSOP20/SO20 pinout .................................................24
5.2.2 STM8S103Fx UFQFPN20 pinout ........................................................25
5.2.3 STM8S103Fx TSSOP20/SO20/UFQFPN20 pin description ................25
5.3 Alternate function remapping .......................................................................................27
6 Memory and register map .....................................................................................28
6.1 Memory map ................................................................................................................28
6.2 Register map ...............................................................................................................29
6.2.1 I/O port hardware register map ............................................................29
6.2.2 General hardware register map ..........................................................30
6.2.3 CPU/SWIM/debug module/interrupt controller registers .....................40
7 Interrupt vector mapping ......................................................................................42
8 Option bytes ...........................................................................................................44
8.1 Alternate function remapping bits ................................................................................46
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STM8S103K3 STM8S103F3 STM8S103F2Contents
9 Unique ID ................................................................................................................49
10 Electrical characteristics ....................................................................................50
10.1 Parameter conditions .................................................................................................50
10.1.1 Minimum and maximum values .........................................................50
10.1.2 Typical values .....................................................................................50
10.1.3 Typical curves ....................................................................................50
10.1.4 Loading capacitor ...............................................................................50
10.1.5 Pin input voltage .................................................................................51
10.2 Absolute maximum ratings ........................................................................................51
10.3 Operating conditions ..................................................................................................53
10.3.1 VCAP external capacitor ....................................................................54
10.3.2 Supply current characteristics ............................................................55
10.3.3 External clock sources and timing characteristics .............................65
10.3.4 Internal clock sources and timing characteristics ...............................67
10.3.5 Memory characteristics ......................................................................70
10.3.6 I/O port pin characteristics .................................................................71
10.3.7 Reset pin characteristics ....................................................................79
10.3.8 SPI serial peripheral interface ............................................................82
10.3.9 I2C interface characteristics ...............................................................85
10.3.10 10-bit ADC characteristics ................................................................86
10.3.11 EMC characteristics .........................................................................90
11 Package information ............................................................................................94
11.1 32-pin LQFP package mechanical data .....................................................................94
11.2 32-lead UFQFPN package mechanical data .............................................................96
11.3 20-lead UFQFPN package mechanical data .............................................................97
11.4 SDIP32 package mechanical data .............................................................................98
11.5 20-pin TSSOP package mechanical data ................................................................100
11.6 20-pin SO package mechanical data .......................................................................101
11.7 UFQFPN recommended footprint ............................................................................102
12 Thermal characteristics ....................................................................................104
12.1 Reference document ...............................................................................................105
12.2 Selecting the product temperature range ................................................................105
13 Ordering information .........................................................................................106
13.1 STM8S103 FASTROM microcontroller option list ...................................................106
14 STM8 development tools ..................................................................................111
14.1 Emulation and in-circuit debugging tools .................................................................111
14.2 Software tools ..........................................................................................................111
14.2.1 STM8 toolset ....................................................................................112
14.2.2 C and assembly toolchains ..............................................................112
14.3 Programming tools ..................................................................................................112
15 Revision history .................................................................................................113
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ContentsSTM8S103K3 STM8S103F3 STM8S103F2
List of tables
Table 1. STM8S103xx access line features .............................................................................................9
Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14
Table 3. TIM timer features ....................................................................................................................16
Table 4. Legend/abbreviations for pinout tables ...................................................................................19
Table 5. UFQFPN32/LQFP32/SDIP32 pin description ...........................................................................21
Table 6. STM8S103Fx pin description ...................................................................................................25
Table 7. I/O port hardware register map ................................................................................................29
Table 8. General hardware register map ...............................................................................................30
Table 9. CPU/SWIM/debug module/interrupt controller registers .........................................................40
Table 10. Interrupt mapping ...................................................................................................................42
Table 11. Option bytes .........................................................................................................................113
Table 12. Option byte description ...........................................................................................................44
Table 13. STM8S103K alternate function remapping bits for 32-pin devices ........................................46
Table 14. STM8S103F alternate function remapping bits for 20-pin devices ........................................47
Table 15. Unique ID registers (96 bits) .................................................................................................113
Table 16. Voltage characteristics ...........................................................................................................51
Table 17. Current characteristics ...........................................................................................................52
Table 18. Thermal characteristics ..........................................................................................................52
Table 19. General operating conditions .................................................................................................53
Table 20. Operating conditions at power-up/power-down ......................................................................54
Table 21. Total current consumption with code execution in run mode at VDD = 5 V .............................55
Table 22. Total current consumption with code execution in run mode at VDD = 3.3 V ..........................56
Table 23. Total current consumption in wait mode at VDD = 5 V ............................................................57
Table 24. Total current consumption in wait mode at VDD = 3.3 V .........................................................57
Table 25. Total current consumption in active halt mode at VDD = 5 V ..................................................58
Table 26. Total current consumption in active halt mode at VDD = 3.3 V ...............................................59
Table 27. Total current consumption in halt mode at VDD = 5 V .............................................................60
Table 28. Total current consumption in halt mode at VDD = 3.3 V ..........................................................60
Table 29. Wakeup times .........................................................................................................................60
Table 30. Total current consumption and timing in forced reset state ....................................................61
Table 31. Peripheral current consumption .............................................................................................62
Table 32. HSE user external clock characteristics .................................................................................65
Table 33. HSE oscillator characteristics .................................................................................................66
Table 34. HSI oscillator characteristics ..................................................................................................67
Table 35. LSI oscillator characteristics ...................................................................................................69
Table 36. RAM and hardware registers ..................................................................................................70
Table 37. Flash program memory/data EEPROM memory ....................................................................70
Table 38. I/O static characteristics .........................................................................................................71
Table 39. Output driving current (standard ports) ..................................................................................73
Table 40. Output driving current (true open drain ports) ........................................................................74
Table 41. Output driving current (high sink ports) ..................................................................................74
Table 42. NRST pin characteristics ........................................................................................................79
Table 43. SPI characteristics ..................................................................................................................82
Table 44. I2C characteristics ..................................................................................................................85
Table 45. ADC characteristics ................................................................................................................87
Table 46. ADC accuracy with RAIN < 10 kΩ , VDD= 5 V .........................................................................87
Table 47. ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V ..............................................................88
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Table 48. EMS data ................................................................................................................................91
Table 49. EMI data .................................................................................................................................91
Table 50. ESD absolute maximum ratings .............................................................................................92
Table 51. Electrical sensitivities .............................................................................................................93
Table 52. 32-pin low profile quad flat package mechanical data ............................................................94
Table 53. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data .............................96
Table 54. 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package mechanical data ....98
Table 55. 32-lead shrink plastic DIP (400 ml) package mechanical data ..............................................98
Table 56. 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data .......................................................101
Table 57. 20-lead, plastic small outline (300 mils) mechanical data ....................................................101
Table 58. Thermal characteristics ........................................................................................................104
Table 59. Document revision history ....................................................................................................113
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List of tablesSTM8S103K3 STM8S103F3 STM8S103F2
List of figures
Figure 1. Block diagram .........................................................................................................................10
Figure 2. Flash memory organization ....................................................................................................13
Figure 3. STM8S103Kx UFQFPN32/LQFP32 pinout .............................................................................20
Figure 4. STM8S103Kx SDIP32 pinout .................................................................................................21
Figure 5. STM8S103Fx TSSOP20/SO20 pinout ....................................................................................24
Figure 6. STM8S103Fx UFQFPN20-pin pinout .....................................................................................25
Figure 7. Memory map ...........................................................................................................................28
Figure 8. Pin loading conditions .............................................................................................................50
Figure 9. Pin input voltage .....................................................................................................................51
Figure 10. fCPUmax versus VDD ..............................................................................................................54
Figure 11. External capacitor CEXT .......................................................................................................55
Figure 12. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz .............................................63
Figure 13. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V ....................................................63
Figure 14. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................64
Figure 15. Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz ..............................................64
Figure 16. Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V .....................................................65
Figure 17. Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................65
Figure 18. HSE external clocksource .....................................................................................................66
Figure 19. HSE oscillator circuit diagram ...............................................................................................67
Figure 20. Typical HSI frequency variation vs VDD @ 4 temperatures ..................................................69
Figure 21. Typical LSI frequency variation vs VDD @ 4 temperatures ...................................................69
Figure 22. Typical VIL and VIH vs VDD @ 4 temperatures ......................................................................72
Figure 23. Typical pull-up resistance vs VDD @ 4 temperatures ............................................................73
Figure 24. Typical pull-up current vs VDD @ 4 temperatures .................................................................73
Figure 25. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................75
Figure 26. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................75
Figure 27. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................76
Figure 28. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................76
Figure 29. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................77
Figure 30. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................77
Figure 31. Typ. VDD - VOH@ VDD = 5 V (standard ports) .......................................................................78
Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ...................................................................78
Figure 33. Typ. VDD - VOH@ VDD = 5 V (high sink ports) .......................................................................79
Figure 34. Typ. VDD - VOH@ VDD = 3.3 V (high sink ports) ....................................................................79
Figure 35. Typical NRST VIL and VIH vs VDD @ 4 temperatures ...........................................................80
Figure 36. Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................81
Figure 37. Typical NRST pull-up current vs VDD @ 4 temperatures ......................................................81
Figure 38. Recommended reset pin protection ......................................................................................82
Figure 39. SPI timing diagram - slave mode and CPHA = 0 ..................................................................84
Figure 40. SPI timing diagram - slave mode and CPHA = 1 ..................................................................84
Figure 41. SPI timing diagram - master mode(1) ...................................................................................85
Figure 42. Typical application with I2C bus and timing diagram ............................................................89
Figure 43. ADC accuracy characteristics ...............................................................................................89
Figure 44. Typical application with ADC ................................................................................................90
Figure 45. 32-pin low profile quad flat package (7 x 7) ..........................................................................94
Figure 46. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ............................................96
Figure 47. 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) ................................97
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STM8S103K3 STM8S103F3 STM8S103F2List of figures
Figure 48. 32-lead shrink plastic DIP (400 ml) package ........................................................................98
Figure 49. 20-pin, 4.40 mm body, 0.65 mm pitch .................................................................................101
Figure 50. 20-lead, plastic small outline (300 mils) package ...............................................................101
Figure 51. Recommended footprint for on-board emulation ................................................................102
Figure 52. Recommended footprint without on-board emulation .........................................................103
Figure 53. STM8S103x access line ordering information scheme ......................................................106
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List of figuresSTM8S103K3 STM8S103F3 STM8S103F2
Introduction1
This datasheet contains the description of the device features, pinout, electrical characteristics,
mechanical data and ordering information.
•For complete information on the STM8S microcontroller memory, registers and peripherals,
please refer to the STM8S microcontroller family reference manual (RM0016).
•For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051).
•For information on the debug and SWIM (single wire interface module) refer to the STM8
SWIM communication protocol and debug module user manual (UM0470).
•For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
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STM8S103K3 STM8S103F3 STM8S103F2Introduction
Description2
The STM8S103x access line 8-bit microcontrollers offer 8 Kbytes Flash program memory,
plus integrated true data EEPROM. The STM8S microcontroller family reference manual
(RM0016) refers to devices in this family as low-density. They provide the following benefits:
performance, robustness, and reduced system cost.
Device performance and robustness are ensured by advanced core and peripherals made
in a state-of-the art technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs
with separate clock source, and a clock security system.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300
kwrite/erase cycles and a high system integration level with internal clock oscillators, watchdog
and brown-out reset.
Full documentation is offered as well as a wide choice of development tools.
Table 1: STM8S103xx access line features
STM8S103F2STM8S103F3STM8S103K3Device
202032Pin count
161628Maximum number of GPIOs (I/Os)
161627Ext. interrupt pins
777Timer CAPCOM channels
223Timer complementary outputs
554A/D converter channels
121221High sink I/Os
4K8K8K
Low density Flash program
memory (bytes)
640(1)
640(1)
640(1)
Data EEPROM (bytes)
1K1K1KRAM (bytes)
Multipurpose timer (TIM1), SPI, I2C, UART window
WDG,independent WDG, ADC, PWM timer (TIM2), 8-bit
timer (TIM4)
Peripheral set
(1) No read-while-write (RWW) capability
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DescriptionSTM8S103K3 STM8S103F3 STM8S103F2
Block diagram3
Figure 1: Block diagram
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
STM8 core
Debug/SWIM
SPI
UART1
16-bit general purpose
AWU timer
Reset block
Reset
POR BOR
Clock controller
Detector
Clock to peripherals and core
8 Mbit/s
LIN master
Address and data bus
Window WDG
8 Kbytes
640 bytes
1 Kbyte
ADC1
4 CAPCOM
Reset
400 Kbit/s
Single wire
debug interf.
SPI emul.
channels +3
program
Flash
16-bit advanced
control timer (TIM1)
8-bit basic timer
data EEPROM
RAM
Up to
Beeper
1/2/4 kHz
beep
Independent WDG
(TIM4)
3 CAPCOM
channels
Up to
complementary
outputs
timer (TIM2)
Up to 5
channels
I2C
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STM8S103K3 STM8S103F3 STM8S103F2Block diagram
Product overview4
The following section intends to give an overview of the basic features of the device functional
modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
Central processing unit STM84.1
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
•Harvard architecture
•3-stage pipeline
•32-bit wide program memory bus - single cycle fetching for most instructions
•X and Y 16-bit index registers - enabling indexed addressing modes with or without offset
and read-modify-write type data manipulations
•8-bit accumulator
•24-bit program counter - 16-Mbyte linear memory space
•16-bit stack pointer - access to a 64 K-level stack
•8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
•20 addressing modes
•Indexed indirect addressing mode for look-up tables located anywhere in the address
space
•Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
•80 instructions with 2-byte average instruction size
•Standard data movement and logic/arithmetic functions
•8-bit by 8-bit multiplication
•16-bit by 8-bit and 16-bit by 16-bit division
•Bit manipulation
•Data transfer between stack and accumulator (push/pop) with direct stack access
•Data transfer using the X and Y registers or direct memory-to-memory transfers
Single wire interface module (SWIM) and debug module (DM)4.2
The single wire interface module and debug module permits non-intrusive, real-time in-circuit
debugging and fast memory programming.
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Product overviewSTM8S103K3 STM8S103F3 STM8S103F2
SWIM
Single wire interface module for direct access to the debug module and memory programming.
The interface can be activated in all device operation modes. The maximum data transmission
speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator.
Beside memory and peripherals, also CPU operation can be monitored in real-time by means
of shadow registers.
•R/W to RAM and peripheral registers in real-time
•R/W access to all resources by stalling the CPU
•Breakpoints on all program-memory instructions (software breakpoints)
•Two advanced breakpoints, 23 predefined configurations
Interrupt controller4.3
•Nested interrupts with three software priority levels
•32 interrupt vectors with hardware priority
•Up to 27 external interrupts on 6 vectors including TLI
•Trap and reset interrupts
Flash program and data EEPROM memory4.4
•8 Kbytes of Flash program single voltage Flash memory
•640 bytes true data EEPROM
•User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid unintentional
overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of memory
known as UBC (user boot code). Refer to the figure below.
The size of the UBC is programmable through the UBC option byte, in increments of 1 page
(64-byte block) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
•Main program memory: Up to 8 Kbytes minus UBC
•User-specific boot code (UBC): Configurable up to 8 Kbytes
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
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STM8S103K3 STM8S103F3 STM8S103F2Product overview
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Figure 2: Flash memory organization
UBC area
Program memory area
Data memory area ( 640 bytes)
Remains write protected during IAP
Data
EEPROM
memory
Write access possible for IAP
Option bytes
Programmable
bytes(1 page)
up to 8 Kbytes
(in 1 page steps)
area from 64
Low density
Flash program
memory
(8 Kbytes)
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program and data memory. Even
if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
Clock controller4.5
The clock controller distributes the system clock (fMASTER) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.
Features
•Clock prescaler: To get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
•Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.
•Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
•Master clock sources: Four different clock sources can be used to drive the master
clock:
-1-16 MHz high-speed external crystal (HSE)
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-Up to 16 MHz high-speed user-external clock (HSE user-ext)
-16 MHz high-speed internal RC oscillator (HSI)
-128 kHz low-speed internal RC (LSI)
•Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz
clock (HSI/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
•Clock security system (CSS): This feature can be enabled by software. If an HSE clock
failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an
interrupt can optionally be generated.
•Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Peripheral
clock
BitPeripheral
clock
BitPeripheral
clock
BitPeripheral
clock
Bit
ADCPCKEN23ReservedPCKEN27UART1PCKEN13TIM1PCKEN17
AWUPCKEN22ReservedPCKEN26ReservedPCKEN12ReservedPCKEN16
ReservedPCKEN21ReservedPCKEN25SPIPCKEN11TIM2PCKEN15
ReservedPCKEN20ReservedPCKEN24I2CPCKEN10TIM4PCKEN14
Power management4.6
For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.
•Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
•Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake up
unit (AWU). The main voltage regulator is kept powered on, so current consumption is
higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup
is triggered by the internal AWU interrupt, external interrupt or reset.
•Active halt mode with regulator off: This mode is the same as active halt with regulator
on, except that the main voltage regulator is powered off, so the wake up time is slower.
•Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral
clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by
external event or reset.
Watchdog timers4.7
The watchdog system is based on two independent timers providing maximum security to
the applications.
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STM8S103K3 STM8S103F3 STM8S103F2Product overview
Activation of the watchdog timers is controlled by option bytes or by software. Once activated,
the watchdogs cannot be disabled by the user program without performing a reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually generated
by external interferences or by unexpected logical conditions, which cause the application
program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to
64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
Auto wakeup counter4.8
•Used for auto wakeup from active halt mode
•Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
•LSI clock can be internally connected to TIM1 input capture channel 1 for calibration
Beeper4.9
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit AFR7.
TIM1 - 16-bit advanced control timer4.10
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
•16-bit up, down and up/down autoreload counter with 16-bit prescaler
•Four independent capture/compare channels (CAPCOM) configurable as input capture,
output compare, PWM generation (edge and center aligned mode) and single pulse mode
output
•Synchronization module to control the timer with external signals
15/117DocID15441 Rev 9
Product overviewSTM8S103K3 STM8S103F3 STM8S103F2
•Break input to force the timer outputs into a defined state
•Three complementary outputs with adjustable dead time
•Encoder mode
•Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
TIM2 - 16-bit general purpose timer4.11
•16-bit autoreload (AR) up-counter
•15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
•3 individually configurable capture/compare channels
•PWM mode
•Interrupt sources: 3 x input capture/output compare, 1 x overflow/update
TIM4 - 8-bit basic timer4.12
•8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
•Clock source: CPU clock
•Interrupt source: 1 x overflow/update
Table 3: TIM timer features
Timer
synchronization/
chaining
Ext.
trigger
Complem.
outputs
CAPCOM
channels
Counting
mode
Prescaler
Counter
size (bits)
Timer
No
Yes34Up/down
Any integer
from 1 to
65536
16TIM1
No03Up
Any power of
2 from 1 to
32768
16TIM2
No00Up
Any power of
2 from 1 to
128
8TIM4
Analog-to-digital converter (ADC1)4.13
The STM8S103xx family products contain a 10-bit successive approximation A/D converter
(ADC1) with up to 5 external multiplexed input channels and the following main features:
•Input voltage range: 0 to VDD
•Conversion time: 14 clock cycles
•Single and continuous and buffered continuous conversion modes
•Buffer size (n x 10 bits) where n = number of input channels
•Scan mode for single and continuous conversion of a sequence of channels
DocID15441 Rev 916/117
STM8S103K3 STM8S103F3 STM8S103F2Product overview
•Analog watchdog capability with programmable upper and lower thresholds
•Analog watchdog interrupt
•External trigger input
•Trigger from TIM1 TRGO
•End of conversion (EOC) interrupt
Communication interfaces4.14
The following communication interfaces are implemented:
•UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA
mode, single wire mode, LIN2.1 master capability
•SPI : Full and half-duplex, 8 Mbit/s
•I²C: Up to 400 Kbit/s
UART14.14.1
Main features
•One Mbit/s full duplex SCI
•SPI emulation
•High precision baud rate generator
•Smartcard emulation
•IrDA SIR encoder decoder
•LIN master mode
•Single wire half duplex mode
Asynchronous communication (UART mode)
•Full duplex communication - NRZ standard format (mark/space)
•Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of
following any standard baud rate regardless of the input frequency
•Separate enable bits for transmitter and receiver
•Two receiver wakeup modes:
-Address bit (MSB)
-Idle line (interrupt)
•Transmission error detection with interrupt generation
•Parity control
Synchronous communication
•Full duplex synchronous transfers
•SPI master operation
•8-bit data communication
•Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)
17/117DocID15441 Rev 9
Product overviewSTM8S103K3 STM8S103F3 STM8S103F2
LIN master mode
•Emission: Generates 13-bit synch break frame
•Reception: Detects 11-bit break frame
SPI4.14.2
•Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
•Full duplex synchronous transfers
•Simplex synchronous transfers on two lines with a possible bidirectional data line
•Master or slave operation - selectable by hardware or software
•CRC calculation
•1 byte Tx and Rx buffer
•Slave/master selection input pin
I²C4.14.3
•I²C master features:
-Clock generation
-Start and stop generation
•I²C slave features:
-Programmable I2C address detection
-Stop bit detection
•Generation and detection of 7-bit/10-bit addressing and general call
•Supports different communication speeds:
-Standard speed (up to 100 kHz)
-Fast speed (up to 400 kHz)
DocID15441 Rev 918/117
STM8S103K3 STM8S103F3 STM8S103F2Product overview
Pinout and pin description5
Table 4: Legend/abbreviations for pinout tables
I= Input, O = Output, S = Power supplyType
CM = CMOS
InputLevel
HS = High sinkOutput
O1 = Slow (up to 2 MHz)
Output speed
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
float = floating, wpu = weak pull-upInputPort and control
configuration T = True open drain, OD = Open drain, PP =
Push pull
Output
Bold X(pin state after internal reset release).
Reset state
Unless otherwise specified, the pin state is the same during the reset
phase and after the internal reset release.
19/117DocID15441 Rev 9
Pinout and pin descriptionSTM8S103K3 STM8S103F3 STM8S103F2
STM8S103Kx UFQFPN32/LQFP32/SDIP32 pinout and pin
description
5.1
Figure 3: STM8S103Kx UFQFPN32/LQFP32 pinout
I2C_SCL/(T) PB4
TIM1_ETR/AIN3/(HS) PB3
TIM1_CH3N/ AIN2/(HS) PB2
TIM1_CH2N/ AIN1/(HS) PB1
TIM1_CH1N/AIN0/(HS) PB0
PB7
PB6
I2C_SDA/ (T) PB5
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
VCAP
VDD
[SPI_NSS] TIM2_CH3/(HS) PA3
PF4
NRST
OSCIN/PA1
OSCOUT/PA2
VSS PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1/UART1_CK
PE5 (HS)/SPI_NSS
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4/CLK_CCO
PD3 (HS)/TIM2_CH2/ADC_ETR
PD2 (HS) [TIM2_CH3]
PD1 (HS)/SWIM
PD0 (HS)/ TIM1_BKIN [CLK_CCO]
PD7 (HS)/TLI [TIM1_CH4]
PD6 (HS)/UART1_RX
PD5 (HS)/UART1_TX
PD4 (HS)/BEEP/TIM2_CH1
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
DocID15441 Rev 920/117
STM8S103K3 STM8S103F3 STM8S103F2Pinout and pin description
Figure 4: STM8S103Kx SDIP32 pinout
8
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
[TIM2_CH2] ADC_ETR/(HS) PD3
BEEP/TIM2_CH1/(HS) PD4
UART1_TX(/HS) PD5
UART1_RX/(HS) PD6
[TIM1_CH4] TLI/(HS) PD7
OSCIN/PA1
OSCOUT/PA2
VSS
VCAP
VDD
[SPI_NSS] TIM2_CH3/(HS) PA3
PB6 PB3 (HS)/TIM1_ETR/AIN3
PB2 (HS)/TIM1_CH3N/AIN2
PB1 (HS)/TIM1_CH2N/AIN1
PB0 (HS)/TIM1_CH1N/AIN0
PE5/SPI_NSS
PC1 (HS)/TIM1_CH1/UART1_CK
PC2( HS)/TIM1_CH2
PC3 (HS)/TIM1_CH3
PC4( HS)/TIM1_CH4/CLK_CCO
PC5 (HS)/SPI_SCK
PC6 (HS)/SPI_MOSI
PC7 (HS)/SPI_MISO
PD0 (HS)/TIM1_BKIN [CLK_CCO]
PD1 (HS)/SWIM
PD2 (HS) [TIM2_CH3]
PB7
I2C_SDA/(T) PB5
NRST
PF4
PB4 (T)/I2C_SCL
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
Table 5: UFQFPN32/LQFP32/SDIP32 pin description
Alternate
function after
remap [option
bit]
Default alternate
function
Main
function
(after
reset)
OutputInput
Type
Pin
name
LQFP/
UFQFP
32
SDIP
32 PPODSpeed
High
sink(1)
Ext.
interrupt
wpufloating
ResetXI/ONRST16
Resonator/ crystal inPort A1XXO1XXXI/OPA1/
OSCIN(2)
27
Resonator/ crystal outPort A2XXO1XXXI/OPA2/
OSCOUT
38
Digital groundSVSS
49
1.8 V regulator capacitorSVCAP510
Digital power supplySVDD
611
SPI master/
slave select
[AFR1]
Timer 2 channel 3Port A3XXO3HSXXXI/OPA3/
TIM2_CH3
[SPI_NSS]
712
21/117DocID15441 Rev 9
Pinout and pin descriptionSTM8S103K3 STM8S103F3 STM8S103F2
Alternate
function after
remap [option
bit]
Default alternate
function
Main
function
(after
reset)
OutputInput
Type
Pin
name
LQFP/
UFQFP
32
SDIP
32 PPODSpeed
High
sink(1)
Ext.
interrupt
wpufloating
Port F4XXO1XXI/OPF4813
Port B7XXO1XXXI/OPB7914
Port B6XXO1XXXI/OPB61015
I2C dataPort B5
T(3)
O1XXI/OPB5/
I2C_SDA
1116
I2C clockPort B4
T(3)
O1XXI/OPB4/
I2C_SCL
1217
Analog input 3/ Timer
1 external trigger
Port B3XXO3HSXXXI/OPB3/AIN3/
TIM1_ETR
1318
Analog input 2/ Timer
1 - inverted channel 3
Port B2XXO3HSXXXI/OPB2/AIN2/
TIM1_CH3N
1419
Analog input 1/ Timer
1 - inverted channel 2
Port B1XXO3HSXXXI/OPB1/AIN1/
TIM1_CH2N
1520
Analog input 0/ Timer
1 - inverted channel 1
Port B0XXO3HSXXXI/OPB0/AIN0/
TIM1_CH1N
1621
SPI master/slave
select
Port E5XXO3HSXXXI/OPE5/
SPI_NSS
1722
Timer 1 - channel 1
UART1 clock
Port C1XXO3HSXXXI/OPC1/
TIM1_CH1/
UART1_CK
1823
Timer 1 - channel 2Port C2XXO3HSXXXI/OPC2/
TIM1_CH2
1924
Timer 1 - channel 3Port C3XXO3HSXXXI/OPC3/
TIM1_CH3
2025
Timer 1 - channel 4
/configurable clock
output
Port C4XXO3HSXXXI/OPC4/
TIM1_CH4/
CLK_CCO
2126
SPI clockPort C5XXO3HSXXXI/OPC5/
SPI_SCK
2227
SPI master out/slave
in
Port C6XXO3HSXXXI/OPC6/
SPI_MOSI
2328
DocID15441 Rev 922/117
STM8S103K3 STM8S103F3 STM8S103F2Pinout and pin description
Alternate
function after
remap [option
bit]
Default alternate
function
Main
function
(after
reset)
OutputInput
Type
Pin
name
LQFP/
UFQFP
32
SDIP
32 PPODSpeed
High
sink(1)
Ext.
interrupt
wpufloating
SPI master in/ slave
out
Port C7XXO3HSXXXI/OPC7/
SPI_MISO
2429
Configurable
clock output
[AFR5]
Timer 1 - break inputPort D0XXO3HSXXXI/OPD0/
TIM1_BKIN
[CLK_CCO]
2530
SWIM data interfacePort D1XXO4HSXXXI/OPD1/
SWIM
2631
(4)
Timer 2 -
channel
3[AFR1]
Port D2XXO3HSXXXI/OPD2
[TIM2_CH3]
2732
Timer 2 - channel
2/ADC external
trigger
Port D3XXO3HSXXXI/OPD3/
TIM2_CH2/
ADC_ETR
281
Timer 2 - channel
1/BEEP output
Port D4XXO3HSXXXI/OPD4/BEEP/
TIM2_CH1
292
UART1 data transmitPort D5XXO3HSXXXI/OPD5/
UART1_TX
303
UART1 data receivePort D6XXO3HSXXXI/OPD6/
UART1_RX
314
Timer 1 -
channel 4
[AFR6]
Top level interruptPort D7XXO3HSXXXI/OPD7/ TLI
[TIM1_CH4]
325
(1) I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total
driven current must respect the absolute maximum ratings (see Electrical characteristics).
(2) When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking
up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt
is used in the application.
(3)In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not
implemented).
(4)The PD1 pin is in input pull-up during the reset phase and after internal reset release.
23/117DocID15441 Rev 9
Pinout and pin descriptionSTM8S103K3 STM8S103F3 STM8S103F2
STM8S103Fx TSSOP20/SO20/UFQFPN20 pinout and pin
description
5.2
STM8S103Fx TSSOP20/SO20 pinout5.2.1
Figure 5: STM8S103Fx TSSOP20/SO20 pinout
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
UART1_CK/TIM2_CH1/BEEP/(HS) PD4
NRST
VDD
VCAP
VSS
OSCOUT/PA2
PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR
PD1 (HS)/SWIM
PB4 (T)/I2C_SCL [ADC_ETR]
PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N]
PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2 [TIM1_CH2N]
PC5 (HS)/SPI_SCK [TIM2_CH1]
12
11
9
10
[SPI_NSS] TIM2_CH3/(HS) PA3
PD2 (HS)/AIN3 [TIM2_CH3]
OSCIN/PA1
PB5 (T)/I2C_SDA [TIM1_BKIN]
UART1_TX/AIN5/(HS) PD5
UART1_RX/AIN6/(HS) PD6
PC6 (HS)/SPI_MOSI [TIM1_CH1]
PC7 (HS)/SPI_MISO [TIM1_CH2]
1. HS high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
DocID15441 Rev 924/117
STM8S103K3 STM8S103F3 STM8S103F2Pinout and pin description
STM8S103Fx UFQFPN20 pinout5.2.2
Figure 6: STM8S103Fx UFQFPN20-pin pinout
2
1
3
4
5
6 7 8 9
11
12
13
14
15
16171819
VCAP
VSS
OSCOUT/PA2
OSCIN/PA1
[SPI_NSS] TIM2_CH3/(HS) PA3
NRST
PD4 (HS)/BEEP / TIM2_CH1/UART1_CK
PD5 (HS)/AIN5/UART1_TX
PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR
PD2 (HS)/AIN3 [TIM2_CH3]
PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2 [TIM1_CH2N]
PC5 (HS)/SPI_SCK [TIM2_CH1]
PC6 (HS)/SPI_MOSI [TIM1_CH1]
PC7 (HS)/SPI_MISO [TIM1_CH2]
PD1(HS)/SWIM
[TIM1_BKIN] I2C_SDA/(T) PB5
10
[TIM1_CH1N] [TLI] TIM1_CH3/(HS) PC3
PD6 (HS)/AIN6/UART1_RX
20
VDD
[ADC_ETR] I2C_SCL/(T) PB4
1. HS high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
STM8S103Fx TSSOP20/SO20/UFQFPN20 pin description5.2.3
Table 6: STM8S103Fx pin description
Alternate function
after remap [option
bit]
Default
alternate
function
Main
function
(after
reset)
OutputInput
TypePin name
Pin no.
PPODSpeed
High sink
(1)
Ext.
interr.
wpufloatingUFQFPN20TSSOP/SO20
Timer 2 -
channel
Port D4XXO3HSXXXI/OPD4/ BEEP/
TIM2_ CH1/
UART1 _CK
181
1/BEEP output/
UART1 clock
Analog input 5/
UART1 data
transmit
Port D5XXO3HSXXXI/OPD5/ AIN5/
UART1 _TX
192
25/117DocID15441 Rev 9
Pinout and pin descriptionSTM8S103K3 STM8S103F3 STM8S103F2
Alternate function
after remap [option
bit]
Default
alternate
function
Main
function
(after
reset)
OutputInput
TypePin name
Pin no.
PPODSpeed
High sink
(1)
Ext.
interr.
wpufloatingUFQFPN20TSSOP/SO20
Analog input 6/
UART1 data
receive
Port D6XXO3HSXXXI/OPD6/ AIN6/
UART1 _RX
203
ResetXI/ONRST14
Resonator/
crystal in
Port A1XXO1XXXI/O
PA1/ OSCIN (2)
25
Resonator/
crystal out
Port A2XXO1XXXI/OPA2/ OSCOUT36
Digital groundSVSS
47
1.8 V regulator capacitorSVCAP58
Digital power supplySVDD
69
SPI master/ slave
select [AFR1]
Timer 2
channel 3
Port A3XXO3HSXXXI/OPA3/ TIM2_ CH3
[SPI_ NSS]
710
Timer 1 - break
input [AFR4]
I2C dataPort B5T
(3)
O1XXI/OPB5/ I2C_ SDA
[TIM1_ BKIN]
811
ADC external
trigger [AFR4]
I2C clockPort B4T
(3)
O1XXI/OPB4/ I2C_ SCL912
Top level interrupt
[AFR3] Timer 1 -
Timer 1 -
channel 3
Port C3XXO3HSXXXI/OPC3/ TIM1_CH3
[TLI] [TIM1_
CH1N]
1013
inverted channel 1
[AFR7]
Timer 1 - inverted
channel 2 [AFR7]
Configurable
clock
output/Timer 1
Port C4XXO3HSXXXI/OPC4/ CLK_CCO/
TIM1_
CH4/AIN2/[TIM1_
CH2N]
1114
- channel
4/Analog input
2
Timer 2 - channel 1
[AFR0]
SPI clockPort C5XXO3HSXXXI/OPC5/ SPI_SCK
[TIM2_ CH1]
1215
Timer 1 - channel 1
[AFR0]
SPI master
out/slave in
Port C6XXO3HSXXXI/OPC6/ SPI_MOSI
[TIM1_ CH1]
1316
Timer 1 - channel 2
[AFR0]
SPI master in/
slave out
Port C7XXO3HSXXXI/OPC7/ SPI_MISO
[TIM1_ CH2]
1417
SWIM data
interface
Port D1XXO4HSXXXI/OPD1/ SWIM1518
Timer 2 - channel 3
[AFR1]
Analog input 3Port D2XXO3HSXXXI/OPD2/AIN3/[TIM2_
CH3]
1619
Analog input 4/
Timer 2 -
Port D3XXO3HSXXXI/OPD3/ AIN4/ TIM2_
CH2/ ADC_ ETR
1720
channel 2/ADC
external trigger
(1) I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute
maximum ratings.
(2) When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output
state of PA1 is not driven. It is recommended to use PA1 only in input mode if halt/active-halt is used in the application.
(3) In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented).
DocID15441 Rev 926/117
STM8S103K3 STM8S103F3 STM8S103F2Pinout and pin description
Alternate function remapping5.3
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. When the remapping option is active, the default alternate function is no
longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO
section of the family reference manual, RM0016).
27/117DocID15441 Rev 9
Pinout and pin descriptionSTM8S103K3 STM8S103F3 STM8S103F2
Memory and register map6
Memory map6.1
Figure 7: Memory map
0x00 9FFF
Flash program memory
(8 Kbytes)
0x00 0000 RAM
0x00 03FF
(1 Kbyte)
513 bytes stack
0x00 4000
0x00 427F 640 bytes data EEPROM
Reserved
Reserved
Reserved
0x00 4280
0x00 A000
0x02 7FFF
0x00 47FF
0x00 8000 32 interrupt vectors
0x00 807F
GPIO and periph. reg.
0x00 5000
0x00 57FF
0x00 5800
0x00 7FFF
0x00 480B
0x00 4FFF
0x00 7EFF CPU/SWIM/debug/ITC
registers
0x00 7F00
Reserved
Reserved
Option bytes
0x00 480A
0x00 4800
0x00 0800
0x00 3FFF
0x00 8080
Reserved
Unique ID
0x00 4864
0x00 4865
0x00 4870
0x00 4871
DocID15441 Rev 928/117
STM8S103K3 STM8S103F3 STM8S103F2Memory and register map
Register map6.2
I/O port hardware register map6.2.1
Table 7: I/O port hardware register map
Reset
status
Register nameRegister labelBlockAddress
0x00Port A data output latch registerPA_ODR
Port A
0x00 5000
0xXX(1)
Port A input pin value registerPA_IDR0x00 5001
0x00Port A data direction registerPA_DDR0x00 5002
0x00Port A control register 1PA_CR10x00 5003
0x00Port A control register 2PA_CR20x00 5004
0x00Port B data output latch registerPB_ODR
Port B
0x00 5005
0xXX(1)
Port B input pin value registerPB_IDR0x00 5006
0x00Port B data direction registerPB_DDR0x00 5007
0x00Port B control register 1PB_CR10x00 5008
0x00Port B control register 2PB_CR20x00 5009
0x00Port C data output latch registerPC_ODR
Port C
0x00 500A
0xXX(1)
Port C input pin value registerPB_IDR0x00 500B
0x00Port C data direction registerPC_DDR0x00 500C
0x00Port C control register 1PC_CR10x00 500D
0x00Port C control register 2PC_CR20x00 500E
0x00Port D data output latch registerPD_ODR
Port D
0x00 500F
0xXX(1)
Port D input pin value registerPD_IDR0x00 5010
0x00Port D data direction registerPD_DDR0x00 5011
0x02Port D control register 1PD_CR10x00 5012
0x00Port D control register 2PD_CR20x00 5013
0x00Port E data output latch registerPE_ODR
Port E
0x00 5014
0xXX(1)
Port E input pin value registerPE_IDR0x00 5015
0x00Port E data direction registerPE_DDR0x00 5016
0x00Port E control register 1PE_CR10x00 5017
29/117DocID15441 Rev 9
Memory and register mapSTM8S103K3 STM8S103F3 STM8S103F2
Reset
status
Register nameRegister labelBlockAddress
0x00Port E control register 2PE_CR2Port E0x00 5018
0x00Port F data output latch registerPF_ODR
Port F
0x00 5019
0xXX(1)
Port F input pin value registerPF_IDR0x00 501A
0x00Port F data direction registerPF_DDR0x00 501B
0x00Port F control register 1PF_CR10x00 501C
0x00Port F control register 2PF_CR20x00 501D
(1)Depends on the external circuitry.
General hardware register map6.2.2
Table 8: General hardware register map
Reset
status
Register nameRegister labelBlockAddress
Reserved area (60 bytes)0x00 501E to
0x00 5059
0x00Flash control register 1FLASH_CR1
Flash0x00 505A
0x00Flash control register 2FLASH_CR20x00 505B
0xFFFlash complementary control register
2
FLASH_NCR20x00 505C
0x00Flash protection registerFLASH _FPR0x00 505D
0xFFFlash complementary protection
register
FLASH _NFPR0x00 505E
0x00Flash in-application programming
status register
FLASH _IAPSR0x00 505F
Reserved area (2 bytes)0x00 5060 to
0x00 5061
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STM8S103K3 STM8S103F3 STM8S103F2Memory and register map
Reset
status
Register nameRegister labelBlockAddress
0x00Flash program memory unprotection
register
FLASH _PUKRFlash0x00 5062
Reserved area (1 byte)0x00 5063
0x00Data EEPROM unprotection registerFLASH _DUKRFlash0x00 5064
Reserved area (59 bytes)0x00 5065 to
0x00 509F
0x00External interrupt control register 1EXTI_CR1ITC0x00 50A0
0x00External interrupt control register 2EXTI_CR20x00 50A1
Reserved area (17 bytes)0x00 50A2 to
0x00 50B2
0xXX(1)
Reset status registerRST_SRRST0x00 50B3
Reserved area (12 bytes)0x00 50B4 to
0x00 50BF
0x01Internal clock control registerCLK_ICKRCLK0x00 50C0
0x00External clock control registerCLK_ECKR0x00 50C1
Reserved area (1 byte)0x00 50C2
0xE1Clock master status registerCLK_CMSRC0x00 50C3
0xE1Clock master switch registerCLK_SWR0x00 50C4
0xXXClock switch control registerCLK_SWCR0x00 50C5
0x18Clock divider registerCLK_CKDIVR0x00 50C6
0xFFPeripheral clock gating register 1CLK_PCKENR10x00 50C7
0x00Clock security system registerCLK_CSSR0x00 50C8
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Memory and register mapSTM8S103K3 STM8S103F3 STM8S103F2
Reset
status
Register nameRegister labelBlockAddress
0x00Configurable clock control registerCLK_CCOR0x00 50C9
0xFFPeripheral clock gating register 2CLK_PCKENR20x00 50CA
0x00HSI clock calibration trimming
register
CLK_HSITRIMR0x00 50CC
0bXXXX
XXX0
SWIM clock control registerCLK_SWIMCCR0x00 50CD
ReservLK ed area (3 bytes)0x00 50CE to
0x00 50D0
0x7FWWDG control registerWWDG_CRWWDG0x00 50D1
0x7FWWDR window registerWWDG_WR0x00 50D2
Reserved area (13 bytes)0x00 50D3 to 00
50DF
0xXX(2)
IWDG key registerIWDG_KRIWDG0x00 50E0
0x00IWDG prescaler registerIWDG_PR0x00 50E1
0xFFIWDG reload registerIWDG_RLR0x00 50E2
Reserved area (13 bytes)0x00 50E3 to
0x00 50EF
0x00AWU control/status register 1AWU_CSR1AWU0x00 50F0
0x3FAWU asynchronous prescaler buffer
register
AWU_APR0x00 50F1
0x00AWU timebase selection registerAWU_TBR0x00 50F2
0x1FBEEP control/status registerBEEP_CSRBEEP0x00 50F3
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STM8S103K3 STM8S103F3 STM8S103F2Memory and register map
Reset
status
Register nameRegister labelBlockAddress
Reserved area (12 bytes)0x00 50F4 to
0x00 50FF
0x00SPI control register 1SPI_CR1SPI0x00 5200
0x00SPI control register 2SPI_CR20x00 5201
0x00SPI interrupt control registerSPI_ICR0x00 5202
0x02SPI status registerSPI_SR0x00 5203
0x00SPI data registerSPI_DR0x00 5204
0x07SPI CRC polynomial registerSPI_CRCPR0x00 5205
0xFFSPI Rx CRC registerSPI_RXCRCR0x00 5206
0xFFSPI Tx CRC registerSPI_TXCRCR0x00 5207
Reserved area (8 bytes)0x00 5208 to
0x00 520F
0x00I2C control register 1I2C_CR1I2C0x00 5210
0x00I2C control register 2I2C_CR20x00 5211
0x00I2C frequency registerI2C_FREQR0x00 5212
0x00I2C Own address register lowI2C_OARL0x00 5213
0x00I2C Own address register highI2C_OARH0x00 5214
Reserved0x00 5215
0x00I2C data registerI2C_DR0x00 5216
0x00I2C status register 1I2C_SR10x00 5217
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Memory and register mapSTM8S103K3 STM8S103F3 STM8S103F2
Reset
status
Register nameRegister labelBlockAddress
0x00I2C status register 2I2C_SR20x00 5218
0x0XI2C status register 3I2C_SR30x00 5219
0x00I2C interrupt control registerI2C_ITR0x00 521A
0x00I2C Clock control register lowI2C_CCRL0x00 521B
0x00I2C Clock control register highI2C_CCRH0x00 521C
0x02I2C TRISE registerI2C_TRISER0x00 521D
0x00I2C packet error checking registerI2C_PECR0x00 521E
Reserved area (17 bytes)0x00 521F to
0x00 522F
0xC0UART1 status registerUART1_SRUART10x00 5230
0xXXUART1 data registerUART1_DR0x00 5231
0x00UART1 baud rate register 1UART1_BRR10x00 5232
0x00UART1 baud rate register 2UART1_BRR20x00 5233
0x00UART1 control register 1UART1_CR10x00 5234
0x00UART1 control register 2UART1_CR20x00 5235
0x00UART1 control register 3UART1_CR30x00 5236
0x00UART1 control register 4UART1_CR40x00 5237
0x00UART1 control register 5UART1_CR50x00 5238
0x00UART1 guard time registerUART1_GTR0x00 5239
0x00UART1 prescaler registerUART1_PSCR0x00 523A
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STM8S103K3 STM8S103F3 STM8S103F2Memory and register map
Reset
status
Register nameRegister labelBlockAddress
Reserved area (21 bytes)0x00 523B to
0x00 523F
0x00TIM1 control register 1TIM1_CR1TIM10x00 5250
0x00TIM1 control register 2TIM1_CR20x00 5251
0x00TIM1 slave mode control registerTIM1_SMCR0x00 5252
0x00TIM1 external trigger registerTIM1_ETR0x00 5253
0x00TIM1 interrupt enable registerTIM1_IER0x00 5254
0x00TIM1 status register 1TIM1_SR10x00 5255
0x00TIM1 status register 2TIM1_SR20x00 5256
0x00TIM1 event generation registerTIM1_EGR0x00 5257
0x00TIM1 capture/compare mode register
1
TIM1_CCMR10x00 5258
0x00TIM1 capture/compare mode register
2
TIM1_CCMR20x00 5259
0x00TIM1 capture/compare mode register
3
TIM1_CCMR30x00 525A
0x00TIM1 capture/compare mode register
4
TIM1_CCMR40x00 525B
0x00TIM1 capture/compare enable
register 1
TIM1_CCER10x00 525C
0x00TIM1 capture/compare enable
register 2
TIM1_CCER20x00 525D
0x00TIM1 counter highTIM1_CNTRH0x00 525E
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Memory and register mapSTM8S103K3 STM8S103F3 STM8S103F2
Reset
status
Register nameRegister labelBlockAddress
0x00TIM1 counter lowTIM1_CNTRL0x00 525F
0x00TIM1 prescaler register highTIM1_PSCRH0x00 5260
0x00TIM1 prescaler register lowTIM1_PSCRL0x00 5261
0xFFTIM1 auto-reload register highTIM1_ARRH0x00 5262
0xFFTIM1 auto-reload register lowTIM1_ARRL0x00 5263
0x00TIM1 repetition counter registerTIM1_RCR0x00 5264
0x00TIM1 capture/compare register 1 highTIM1_CCR1H0x00 5265
0x00TIM1 capture/compare register 1 lowTIM1_CCR1L0x00 5266
0x00TIM1 capture/compare register 2 highTIM1_CCR2H0x00 5267
0x00TIM1 capture/compare register 2 lowTIM1_CCR2L0x00 5268
0x00TIM1 capture/compare register 3 highTIM1_CCR3H0x00 5269
0x00TIM1 capture/compare register 3 lowTIM1_CCR3L0x00 526A
0x00TIM1 capture/compare register 4 highTIM1_CCR4H0x00 526B
0x00TIM1 capture/compare register 4 lowTIM1_CCR4L0x00 526C
0x00TIM1 break registerTIM1_BKR0x00 526D
0x00TIM1 dead-time registerTIM1_DTR0x00 526E
0x00TIM1 output idle state registerTIM1_OISR0x00 526F
Reserved area (147 bytes)0x00 5270 to
0x00 52FF
0x00TIM2 control register 1TIM2_CR1TIM20x00 5300
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STM8S103K3 STM8S103F3 STM8S103F2Memory and register map
Reset
status
Register nameRegister labelBlockAddress
Reserved0x00 5301
Reserved0x00 5302
0x00TIM2 Interrupt enable registerTIM2_IER0x00 5303
0x00TIM2 status register 1TIM2_SR10x00 5304
0x00TIM2 status register 2TIM2_SR20x00 5305
0x00TIM2 event generation registerTIM2_EGR0x00 5306
0x00TIM2 capture/compare mode register
1
TIM2_CCMR10x00 5307
0x00TIM2 capture/compare mode register
2
TIM2_CCMR20x00 5308
0x00TIM2 capture/compare mode register
3
TIM2_CCMR30x00 5309
0x00TIM2 capture/compare enable
register 1
TIM2_CCER10x00 530A
0x00TIM2 capture/compare enable
register 2
TIM2_CCER20x00 530B
0x00TIM2 counter highTIM2_CNTRH0x00 530C
0x00TIM2 counter lowTIM2_CNTRL0x00 530D
0x00TIM2 prescaler registerTIM2_PSCR0x00 530E
0xFFTIM2 auto-reload register highTIM2_ARRH0x00 530F
0xFFTIM2 auto-reload register lowTIM2_ARRL0x00 5310
0x00TIM2 capture/compare register 1 highTIM2_CCR1H0x00 5311
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Memory and register mapSTM8S103K3 STM8S103F3 STM8S103F2
Reset
status
Register nameRegister labelBlockAddress
0x00TIM2 capture/compare register 1 lowTIM2_CCR1L0x00 5312
0x00TIM2 capture/compare reg. 2 highTIM2_CCR2H0x00 5313
0x00TIM2 capture/compare register 2 lowTIM2_CCR2L0x00 5314
0x00TIM2 capture/compare register 3 highTIM2_CCR3H0x00 5315
0x00TIM2 capture/compare register 3 lowTIM2_CCR3L0x00 5316
Reserved area (43 bytes)0x00 5317 to
0x00 533F
0x00TIM4 control register 1TIM4_CR1TIM40x00 5340
Reserved0x00 5341
Reserved0x00 5342
0x00TIM4 interrupt enable registerTIM4_IER0x00 5343
0x00TIM4 status registerTIM4_SR0x00 5344
0x00TIM4 event generation registerTIM4_EGR0x00 5345
0x00TIM4 counterTIM4_CNTR0x00 5346
0x00TIM4 prescaler registerTIM4_PSCR0x00 5347
0xFFTIM4 auto-reload registerTIM4_ARR0x00 5348
Reserved area (153 bytes)0x00 5349 to
0x00 53DF
0x00ADC data buffer registersADC _DBxRADC10x00 53E0 to
0x00 53F3
Reserved area (12 bytes)0x00 53F4 to
0x00 53FF
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STM8S103K3 STM8S103F3 STM8S103F2Memory and register map
Reset
status
Register nameRegister labelBlockAddress
0x00ADC control/status registerADC _CSRADC10x00 5400
0x00ADC configuration register 1ADC_CR10x00 5401
0x00ADC configuration register 2ADC_CR20x00 5402
0x00ADC configuration register 3ADC_CR30x00 5403
0xXXADC data register highADC_DRH0x00 5404
0xXXADC data register lowADC_DRL0x00 5405
0x00ADC Schmitt trigger disable register
high
ADC_TDRH0x00 5406
0x00ADC Schmitt trigger disable register
low
ADC_TDRL0x00 5407
0x03ADC high threshold register highADC_HTRH0x00 5408
0xFFADC high threshold register lowADC_HTRL0x00 5409
0x00ADC low threshold register highADC_LTRH0x00 540A
0x00ADC low threshold register lowADC_LTRL0x00 540B
0x00ADC analog watchdog status register
high
ADC_AWSRH0x00 540C
0x00ADC analog watchdog status register
low
ADC_AWSRL0x00 540D
0x00ADC analog watchdog control
register high
ADC _AWCRH0x00 540E
0x00ADC analog watchdog control
register low
ADC_AWCRL0x00 540F
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Memory and register mapSTM8S103K3 STM8S103F3 STM8S103F2
Reset
status
Register nameRegister labelBlockAddress
Reserved area (1008 bytes)0x00 5410 to
0x00 57FF
(1)Depends on the previous reset source.
(2)Write only register.
CPU/SWIM/debug module/interrupt controller registers6.2.3
Table 9: CPU/SWIM/debug module/interrupt controller registers
Reset statusRegister nameRegister labelBlockAddress
0x00AccumulatorA
CPU(1)
0x00 7F00
0x00Program counter extendedPCE0x00 7F01
0x00Program counter highPCH0x00 7F02
0x00Program counter lowPCL0x00 7F03
0x00X index register highXH0x00 7F04
0x00X index register lowXL0x00 7F05
0x00Y index register highYH0x00 7F06
0x00Y index register lowYL0x00 7F07
0x03Stack pointer highSPH0x00 7F08
0xFFStack pointer lowSPL0x00 7F09
0x28Condition code registerCCR0x00 7F0A
Reserved area (85 bytes)
0x00 7F0B to
0x00 7F5F
0x00Global configuration registerCFG_GCRCPU0x00 7F60
0xFFInterrupt software priority register 1ITC_SPR1
ITC
0x00 7F70
0xFFInterrupt software priority register 2ITC_SPR20x00 7F71
0xFFInterrupt software priority register 3ITC_SPR30x00 7F72
0xFFInterrupt software priority register 4ITC_SPR40x00 7F73
0xFFInterrupt software priority register 5ITC_SPR50x00 7F74
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STM8S103K3 STM8S103F3 STM8S103F2Memory and register map
Reset statusRegister nameRegister labelBlockAddress
0xFFInterrupt software priority register 6ITC_SPR60x00 7F75
0xFFInterrupt software priority register 7ITC_SPR70x00 7F76
0xFFInterrupt software priority register 8ITC_SPR80x00 7F77
Reserved area (2 bytes)
0x00 7F78 to
0x00 7F79
0x00SWIM control status registerSWIM_CSRSWIM0x00 7F80
Reserved area (15 bytes)
0x00 7F81 to
0x00 7F8F
0xFFDM breakpoint 1 register extended
byte
DM_BK1RE
DM
0x00 7F90
0xFFDM breakpoint 1 register high byteDM_BK1RH0x00 7F91
0xFFDM breakpoint 1 register low byteDM_BK1RL0x00 7F92
0xFFDM breakpoint 2 register extended
byte
DM_BK2RE0x00 7F93
0xFFDM breakpoint 2 register high byteDM_BK2RH0x00 7F94
0xFFDM breakpoint 2 register low byteDM_BK2RL0x00 7F95
0x00DM debug module control register 1DM_CR10x00 7F96
0x00DM debug module control register 2DM_CR20x00 7F97
0x10DM debug module control/status
register 1
DM_CSR10x00 7F98
0x00DM debug module control/status
register 2
DM_CSR20x00 7F99
0xFFDM enable function registerDM_ENFCTR0x00 7F9A
Reserved area (5 bytes)0x00 7F9B to
0x00 7F9F
(1) Accessible by debug module only
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Memory and register mapSTM8S103K3 STM8S103F3 STM8S103F2
Interrupt vector mapping7
Table 10: Interrupt mapping
Vector addressWakeup from
active-halt mode
Wakeup from
halt mode
DescriptionSource
block
IRQ
no.
0x00 8000YesYesResetRESET
0x00 8004--Software interruptTRAP
0x00 8008--External top level interruptTLI0
0x00 800CYes-Auto wake up from haltAWU1
0x00 8010--Clock controllerCLK2
0x00 8014Yes(1)
Yes(1)
Port A external interruptsEXTI03
0x00 8018YesYesPort B external interruptsEXTI14
0x00 801CYesYesPort C external interruptsEXTI25
0x00 8020YesYesPort D external interruptsEXTI36
0x00 8024YesYesPort E external interruptsEXTI47
0x00 8028--Reserved8
0x00 802C--Reserved9
0x00 8030YesYesEnd of transferSPI10
0x00 8034--TIM1 update/ overflow/ underflow/
trigger/ break
TIM1
11
0x00 8038--TIM1 capture/ compareTIM112
0x00 803C--TIM2 update/ overflowTIM213
0x00 8040--TIM2 capture/ compareTIM214
0x00 8044--Reserved15
0x00 8048--Reserved16
0x00 804C--Tx completeUART117
0x00 8050--Receive register DATA FULLUART118
0x00 8054YesYesI2C interruptI2C19
0x00 8058--Reserved20
0x00 805C--Reserved21
0x00 8060--ADC1 end of conversion/ analog
watchdog interrupt
ADC1
22
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STM8S103K3 STM8S103F3 STM8S103F2Interrupt vector mapping
Vector addressWakeup from
active-halt mode
Wakeup from
halt mode
DescriptionSource
block
IRQ
no.
0x00 8064--TIM4 update/ overflowTIM423
0x00 8068--EOP/WR_PG_DISFlash24
0x00 806C to
0x00 807C
Reserved
(1) Except PA1
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Interrupt vector mappingSTM8S103K3 STM8S103F3 STM8S103F2
Option bytes8
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 11: Option bytes
Factory
default
setting
Option bitsOption
byte no.
Option
name
Addr.
01234567
0x00ROP [7:0]OPT0Read-out
protection
(ROP)
0x4800
0x00UBC [7:0]OPT1User boot
code(UBC)
0x4801
0xFFNUBC [7:0]NOPT10x4802
0x00AFR0AFR1AFR2AFR3AFR4AFR5
AFR6AFR7OPT2Alternate
function
0x4803
0xFFNAFR0NAFR1NAFR2NAFR3NAFR4NAFR5NAFR6NAFR7NOPT20x4804 remapping
(AFR)
0x00WWDG
_HALT
WWDG
_HW
IWDG
_HW
LSI_ ENHSI
TRIM
ReservedOPT3Miscell.
option
0x4805h
0xFFNWW
G_HALT
NWWDG
_HW
NIWDG
_HW
NLSI_
EN
NHSI
TRIM
ReservedNOPT30x4806
0x00PRS C0PRS C1CKAWU
SEL
EXT CLKReservedOPT4Clock
option
0x4807
0xFFNPR
SC0
NPRSC1NCKA
WUSEL
NEXT
CLK
ReservedNOPT40x4808
0x00HSECNT [7:0]OPT5HSE clock
startup
0x4809
0xFFNHSECNT [7:0]NOPT50x480A
Table 12: Option byte description
DescriptionOption byte no.
ROP[7:0] Memory readout protection (ROP)
OPT0
0xAA: Enable readout protection (write access via SWIM protocol)
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STM8S103K3 STM8S103F3 STM8S103F2Option bytes
DescriptionOption byte no.
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
UBC[7:0] User boot code area
OPT1
0x00: no UBC, no write-protection
0x01: Page 0 defined as UBC, memory write-protected
0x02: Pages 0 to 1 defined as UBC, memory write-protected.
Page 0 and 1 contain the interrupt vectors.
...
0x7F: Pages 0 to 126 defined as UBC, memory write-protected
Other values: Pages 0 to 127 defined as UBC, memory
write-protected
Note: Refer to the family reference manual (RM0016) section on
Flash write protection for more details.
AFR[7:0]
OPT2
Refer to following section for alternate function remapping decriptions
of bits [7:2] and [1:0] respectively.
HSITRIM:High speed internal clock trimming register size
OPT3
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN:Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
45/117DocID15441 Rev 9
Option bytesSTM8S103K3 STM8S103F3 STM8S103F2
DescriptionOption byte no.
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
EXTCLK: External clock selection
OPT4
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL:Auto wake-up unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]:HSE crystal oscillator stabilization time
OPT5
0x00: 2048 HSE cycles
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
Alternate function remapping bits8.1
Table 13: STM8S103K alternate function remapping bits for 32-pin devices
Description(1)
Option byte no.
AFR7 Alternate function remapping option 7
OPT2
Reserved.
AFR6 Alternate function remapping option 6
0: AFR6 remapping option inactive: Default alternate function(2).
1: Port D7 alternate function = TIM1_CH4.
AFR5 Alternate function remapping option 5
0: AFR5 remapping option inactive: Default alternate function(2).
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STM8S103K3 STM8S103F3 STM8S103F2Option bytes
Description(1)
Option byte no.
1: Port D0 alternate function = CLK_CCO.
AFR[4:2] Alternate function remapping options 4:2
Reserved.
AFR1 Alternate function remapping option 1
0: AFR1 remapping option inactive: Default alternate functions(2).
1: Port A3 alternate function = SPI_NSS; port D2 alternate function
= TIM2_CH3.
AFR0 Alternate function remapping option 0
Reserved.
(1) Do not use more than one remapping option in the same port. It is forbidden to enable
both AFR1 and AFR0.
(2) Refer to pinout description.
Table 14: STM8S103F alternate function remapping bits for 20-pin devices
DescriptionOption byte no.
AFR7 Alternate function remapping option 7
OPT2
0: AFR7 remapping option inactive: Default alternate
functions(1).
1: Port C3 alternate function = TIM1_CH1N; port C4
alternate function = TIM1_CH2N.
AFR6 Alternate function remapping option 6
Reserved.
AFR5 Alternate function remapping option 5
Reserved.
AFR4 Alternate function remapping option 4
0: AFR4 remapping option inactive: Default alternate
functions(1).
1: Port B4 alternate function = ADC_ETR; port B5
alternate function = TIM1_BKIN.
AFR3 Alternate function remapping option 3
0: AFR3 remapping option inactive: Default alternate
function(1).
1: Port C3 alternate function = TLI.
AFR2 Alternate function remapping option 2
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Option bytesSTM8S103K3 STM8S103F3 STM8S103F2
DescriptionOption byte no.
Reserved
AFR1 Alternate function remapping option 1(2)
0: AFR1 remapping option inactive: Default alternate
functions(1).
1: Port A3 alternate function = SPI_NSS; port D2
alternate function = TIM2_CH3.
AFR0 Alternate function remapping option 0(2)
0: AFR0 remapping option inactive: Default alternate
functions(1).
1: Port C5 alternate function = TIM2_CH1; port C6
alternate function = TIM1_CH1; port C7 alternate
function = TIM1_CH2.
(1) Refer to pinout description.
(2) Do not use more than one remapping option in the same port. It is forbidden to enable
both AFR1 and AFR0.
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STM8S103K3 STM8S103F3 STM8S103F2Option bytes
Unique ID9
The devices feature a 96-bit unique device identifier which provides a reference number that
is unique for any device and in any context. The 96 bits of the identifier can never be altered
by the user.
The unique device identifier can be read in single bytes and may then be concatenated using
a custom algorithm.
The unique device identifier is ideally suited:
•For use as serial numbers
•For use as security keys to increase the code security in the program memory while using
and combining this unique ID with software cryptograhic primitives and protocols before
programming the internal memory.
•To activate secure boot processes
Table 15: Unique ID registers (96 bits)
Unique ID bitsContent
description
Address
01234567
U_ID[7:0]
X co-ordinate
on the wafer
0x4865
U_ID[15:8]0x4866
U_ID[23:16]
Y co-ordinate
on the wafer
0x4867
U_ID[31:24]0x4868
U_ID[39:32]Wafer number0x4869
U_ID[47:40]
Lot number
0x486A
U_ID[55:48]0x486B
U_ID[63:56]0x486C
U_ID[71:64]0x486D
U_ID[79:72]0x486E
U_ID[87:80]0x486F
U_ID[95:88]0x4870
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Unique IDSTM8S103K3 STM8S103F3 STM8S103F2
Electrical characteristics10
Parameter conditions10.1
Unless otherwise specified, all voltages are referred to VSS.
Minimum and maximum values10.1.1
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at TA= 25 °C and TA= TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on characterization,
the minimum and maximum values refer to sample tests and represent the mean value plus
or minus three times the standard deviation (mean ± 3 Σ).
Typical values10.1.2
Unless otherwise specified, typical data are based on TA= 25 °C, VDD = 5 V. They are given
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 Σ).
Typical curves10.1.3
Unless otherwise specified, all typical curves are given only as design guidelines and are not
tested.
Loading capacitor10.1.4
The loading conditions used for pin parameter measurement are shown in the following figure.
Figure 8: Pin loading conditions
STM8 PIN
50 pF
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
Pin input voltage10.1.5
The input voltage measurement on a pin of the device is described in the following figure.
Figure 9: Pin input voltage
STM8 PIN
VIN
Absolute maximum ratings10.2
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 16: Voltage characteristics
UnitMaxMinRatingsSymbol
V
6.5-0.3
Supply voltage(1)
VDDx - VSS
6.5VSS - 0.3
Input voltage on true open drain pins(2)
VIN
VDD + 0.3VSS - 0.3
Input voltage on any other pin(2)
mV
50-
Variations between different power pins
|VDDx - VDD|
50-
Variations between all the different ground
pins
|VSSx - VSS|
See "Absolute
maximum ratings
(electrical sensitivity)"
Electrostatic discharge voltage
VESD
(1) All power (VDD) and ground (VSS) pins must always be connected to the external power supply
(2) IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
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Electrical characteristicsSTM8S103K3 STM8S103F3 STM8S103F2
Table 17: Current characteristics
Unit
Max(1)
RatingsSymbol
mA
100
Total current into VDD power lines (source)(2)
IVDD
80
Total current out of VSS ground lines (sink)(2)
IVSS
20
Output current sunk by any I/O and control pin
IIO
- 20
Output current source by any I/Os and control pin
± 4
Injected current on NRST pin
IINJ(PIN)
(3) (4)
± 4
Injected current on OSCIN pin
± 4
Injected current on any other pin(5)
± 20
Total injected current (sum of all I/O and control pins)(5)
ΣI INJ(PIN)
(3)
(1) Data based on characterization results, not tested in production.
(2) All power (VDD) and ground (VSS) pins must always be connected to the external supply.
(3) IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
(4) ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on
another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins
which may potentially inject negative current. Any positive injection current within the limits specified for
IINJ(PIN) and ΣIINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy.
(5) When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum
of the positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 18: Thermal characteristics
UnitValueRatingsSymbol
°C
-65 to +150Storage temperature rangeTSTG
150Maximum junction temperatureTJ
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
Operating conditions10.3
Table 19: General operating conditions
UnitMaxMinConditionsParameterSymbol
MHz160Internal CPU clock frequencyfCPU
V5.52.95Standard operating voltageVDD
nF3300470
CEXT: capacitance of
external capacitor
VCAP(1)
Ω0.3-
at 1 MHz(2)
ESR of external
capacitor
nH15-
ESL of external
capacitor
mW
238-TSSOP20
Power dissipation at TA= 85 °C
for suffix 6
PD
(3)
220-SO20W
220-UFQFPN20
330-LQFP32
526-UFQFPN32
330-SDIP32
59-TSSOP20
Power dissipation at TA= 125 °C
for suffix 3
55-SO20W
55-UFQFPN20
83-LQFP32
132-UFQFPN32
83-SDIP32
°C
85-40
Maximum power dissipationAmbient temperature for 6 suffix
version
TA
125-40
Maximum power dissipationAmbient temperature for 3 suffix
version
TA
105-406 suffix version
Junction temperature range
TJ
130-403 suffix version
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Electrical characteristicsSTM8S103K3 STM8S103F3 STM8S103F2
(1) Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter
dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum
value must be respected for the full application range.
(2)This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.
(3)To calculate PDmax(TA), use the formula PDmax =(TJmax- TA)/ΘJA (see Thermal characteristics ) with the
value for TJmax given in the previous table and the value for ΘJA given in Thermal characteristics.
Figure 10: fCPUmax versus VDD
16
12
8
4
02.95 4.0 5.0 5.5
fCPU (MHz)
Functionality guaranteed
@TA-40 to 125 °C
Supply voltage
Functionality
not
guaranteed
in this area
Table 20: Operating conditions at power-up/power-down
UnitMaxTypMinConditionsParameterSymbol
μs/V
∞-2VDD rise time rate
tVDD ∞-2VDD fall time rate(1)
ms1.7-- -VDD risingReset release delaytTEMP
V
2.852.72.6Power-on reset thresholdVIT+
2.82.652.5Brown-out reset thresholdVIT-
mV-70-Brown-out reset hysteresisVHYS(BOR)
(1) Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the
minimum ooperating voltage (VDD min) when the tTEMP delay has elapsed.
VCAP external capacitor10.3.1
Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit
the series inductance to less than 15 nH.
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
Figure 11: External capacitor CEXT
ESR
RLeak
ESL
C
1. ESR is the equivalent series resistance and ESL is the equivalent inductance.
Supply current characteristics10.3.2
The current consumption is measured as described in Pin input voltage.
Total current consumption in run mode10.3.2.1
The MCU is placed under the following conditions:
•All I/O pins in input mode with a static value at VDD or VSS (no load)
•All peripherals are disabled (clock stopped by peripheral clock gating registers) except if
explicitly mentioned.
Subject to general operating conditions for VDD and TA.
Table 21: Total current consumption with code execution in run mode at VDD = 5 V
Unit
Max(1)
TypConditionsParameterSymbol
mA
-2.3HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
Supply current
in run mode,
code executed
from RAM
IDD(RUN)
2.352HSE user ext. clock (16 MHz)
21.7HSI RC osc. (16 MHz)
-0.86HSE user ext. clock (16 MHz)fCPU = fMASTER/128 =
125 kHz 0.870.7HSI RC osc. (16 MHz)
0.580.46HSI RC osc. (16 MHz/8)
fCPU = fMASTER/128 =
15.625 kHz
0.550.41LSI RC osc. (128 kHz)
fCPU = fMASTER =
128 kHz
4.5HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
Supply current
in run mode,
code executed
from Flash
4.754.3HSE user ext. clock (16 MHz)
4.53.7HSI RC osc. (16 MHz)
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Unit
Max(1)
TypConditionsParameterSymbol
mA
1.050.84HSI RC osc. (16 MHz/8)(2)
fCPU = fMASTER =
2 MHz
Supply current
in run mode,
code executed
from Flash
IDD(RUN)
0.90.72HSI RC osc. (16 MHz)
fCPU = fMASTER/128 =
125 kHz
0.580.46HSI RC osc. (16 MHz/8)
fCPU = fMASTER/128 =
15.625 kHz
0.570.42LSI RC osc. (128 kHz)
fCPU = fMASTER =
128 kHz
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
Table 22: Total current consumption with code execution in run mode at VDD = 3.3 V
Unit
Max(1)
TypConditionsParameterSymbol
mA
-1.8HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
Supply current
in run mode,
code executed
from RAM
IDD(RUN)
2.32HSE user ext. clock (16 MHz)
21.5HSI RC osc. (16 MHz)
-0.81HSE user ext. clock (16 MHz)fCPU = fMASTER/
128 = 125 kHz 0.870.7HSI RC osc. (16 MHz)
0.580.46HSI RC osc. (16 MHz/8)
fCPU = fMASTER/
128 = 15.625 kHz
0.550.41LSI RC osc. (128 kHz)
fCPU = fMASTER =
128 kHz
-4HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
Supply current
in run mode,
code executed
from Flash
4.73.9HSE user ext. clock (16 MHz)
4.53.7HSI RC osc. (16 MHz)
1.050.84HSI RC osc. (16 MHz/8)(2)
fCPU = fMASTER =
2 MHz
0.90.72HSI RC osc. (16 MHz)fCPU = fMASTER/
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
Unit
Max(1)
TypConditionsParameterSymbol
128 = 125 kHz
0.580.46
HSI RC osc. (16 MHz/8)
fCPU = fMASTER/
128 = 15.625 kHz
0.570.42LSI RC osc. (128 kHz)
fCPU = fMASTER =
128 kHz
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
Total current consumption in wait mode10.3.2.2
Table 23: Total current consumption in wait mode at VDD = 5 V
Unit
Max(1)
TypConditionsParameterSymbol
mA
-1.6HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
Supply
current in
wait mode
IDD(WFI)
1.31.1HSE user ext. clock (16 MHz)
1.10.89HSI RC osc. (16 MHz)
0.880.7HSI RC osc. (16 MHz)
fCPU = fMASTER/128 =
125 kHz
0.570.45HSI RC osc. (16 MHz/8)(2)
fCPU = fMASTER/128 =
15.625 kHz
0.540.4LSI RC osc. (128 kHz)
fCPU = fMASTER =
128 kHz
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
Table 24: Total current consumption in wait mode at VDD = 3.3 V
Unit
Max (1)
TypConditionsParameterSymbol
mA-1.1
HSE crystal osc.
(16 MHz)
fCPU = fMASTER =
16 MHz
Supply current
in wait mode
IDD(WFI)
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Electrical characteristicsSTM8S103K3 STM8S103F3 STM8S103F2
Unit
Max (1)
TypConditionsParameterSymbol
1.31.1
HSE user ext. clock
(16 MHz)
1.10.89
HSI RC osc.
(16 MHz)
0.880.7
HSI RC osc.
(16 MHz)
fCPU = fMASTER/ 128 =
125 kHz
0.570.45
HSI RC osc.
(16 MHz/8)(2)
fCPU = fMASTER/ 128 =
15.625 kHz
0.540.4
LSI RC osc.
(128 kHz)
fCPU = fMASTER=
128 kHz
(1) Data based on characterization results, not tested in production.
(2) Default clock configuration measured with all peripherals off.
Total current consumption in active halt mode10.3.2.3
Table 25: Total current consumption in active halt mode at VDD = 5 V
Unit
Max
at 125
°C
(1)
Max
at 85
°C
(1)
Typ
Conditions
ParameterSymbol Clock sourceFlash mode(3)
Main
voltage
regulator
(MVR)(2)
μA
--1030
HSE crystal osc.
(16 MHz)
Operating modeOn
Supply current
in active halt
mode
IDD(AH)
300260200
LSI RC osc.
(128 kHz)
Operating modeOn
Supply current
in active halt
mode
IDD(AH)
--970
HSE crystal osc.
(16 MHz)
Power-down modeOn
Supply current
in active halt
mode
IDD(AH)
230200150
LSI RC osc.
(128 kHz)
Power-down modeOn
Supply current
in active halt
mode
IDD(AH)
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
Unit
Max
at 125
°C
(1)
Max
at 85
°C
(1)
Typ
Conditions
ParameterSymbol Clock sourceFlash mode(3)
Main
voltage
regulator
(MVR)(2)
1108566
LSI RC osc.
(128 kHz)
Operating mode
Off
Supply current
in active halt
mode
IDD(AH)
402010
LSI RC osc.
(128 kHz)
Power-down mode
Supply current
in active halt
mode
IDD(AH)
(1) Data based on characterization results, not tested in production
(2) Configured by the REGAH bit in the CLK_ICKR register.
(3) Configured by the AHALT bit in the FLASH_CR1 register.
Table 26: Total current consumption in active halt mode at VDD = 3.3 V
Unit
Max at
125 °C
(1)
Max at
85 °C
(1)
Typ
Conditions
ParameterSymbol Clock sourceFlash mode(3)
Main
voltage
regulator
(MVR)(2)
μA--550
HSE crystal
osc. (16 MHz)Operating modeOn
Supply current
in active halt
mode
IDD(AH)
μA
290260200
LSI RC osc.
(128 kHz)
Operating mode
On
Supply current
in active halt
mode
IDD(AH)
--970
HSE crystal
osc. (16 MHz)
Power-down
mode
IDD(AH)
230200150
LSI RC osc.
(128 kHz)
Supply current
in active halt
mode
IDD(AH)
1058066LSI RC osc.
(128 kHz)
Operating mode
Off
IDD(AH)
351810
Power-down
mode
IDD(AH)
(1) Data based on characterization results, not tested in production
(2) Configured by the REGAH bit in the CLK_ICKR register.
(3) Configured by the AHALT bit in the FLASH_CR1 register.
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Total current consumption in halt mode10.3.2.4
Table 27: Total current consumption in halt mode at VDD = 5 V
Unit
Max at
125 °C(1)
Max at
85 °C(1)
TypConditionsParameterSymbol
μA
1057563
Flash in operating mode, HSI
clock after wakeup
Supply current in
halt mode
IDD(H)
55206.0
Flash in power-down mode, HSI
clock after wakeup
(1) Data based on characterization results, not tested in production
Table 28: Total current consumption in halt mode at VDD = 3.3 V
Unit
Max at
125 °C(1)
Max at
85 °C(1)
TypConditionsParameterSymbol
μA
1007560
Flash in operating mode, HSI
clock after wakeup
Supply current in
halt mode
IDD(H)
30174.5
Flash in power-down mode, HSI
clock after wakeup
(1) Data based on characterization results, not tested in production
Low power mode wakeup times10.3.2.5
Table 29: Wakeup times
Unit
Max(1)
TypConditionsParameterSymbol
μs
See
note(2)
-0 to 16 MHz
Wakeup time from
wait mode to run
tWU(WFI)
0.56fCPU = fMASTER = 16 MHzmode(3)
2(6)
1(6)
HSI
(after
Flash in operating
mode(5)
MVR voltage
regulator
on(4)
Wakeup time active
halt mode to run
mode(3)
tWU(AH)
wakeup)
-3(6)
HSI
(after
Flash in
power-down
MVR voltage
regulator
Wakeup time active
halt mode to run
wakeup)mode(5)
on(4)
mode(3)
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
Unit
Max(1)
TypConditionsParameterSymbol
-48(6)
HSI
(after
Flash in operating
mode(5)
MVR voltage
regulator
off(4)
Wakeup time active
halt mode to run
mode(3) wakeup)
-50(6)
HSI
(after
Flash in
power-down
MVR voltage
regulator
Wakeup time active
halt mode to run
wakeup)mode(5)
off(4)
mode(3)
-52Flash in operating mode(5)
Wakeup time from
halt mode to run
tWU(H) -54Flash in power-down mode(5)
mode(3)
(1) Data guaranteed by design, not tested in production.
(2) tWU(WFI) = 2 x 1/fmaster + 6 x 1/fCPU.
(3) Measured from interrupt event to interrupt vector fetch.
(4) Configured by the REGAH bit in the CLK_ICKR register.
(5) Configured by the AHALT bit in the FLASH_CR1 register.
(6) Plus 1 LSI clock depending on synchronization.
Total current consumption and timing in forced reset state10.3.2.6
Table 30: Total current consumption and timing in forced reset state
Unit
Max(1)
TypConditionsParameterSymbol
μA
-400VDD = 5 VSupply current in reset
state(2)
IDD(R)
-300VDD = 3.3 V
μs150-
Reset pin release to
vector fetch
tRESETBL
(1) Data guaranteed by design, not tested in production.
(2) Characterized with all I/Os tied to VSS.
Current consumption of on-chip peripherals10.3.2.7
Subject to general operating conditions for VDD and TA.
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HSI internal RC/fCPU = fMASTER = 16 MHz, VDD = 5 V
Table 31: Peripheral current consumption
UnitTyp.ParameterSymbol
μA
210
TIM1 supply current(1)
IDD(TIM1)
130
TIM2 supply current(1)
IDD(TIM2)
50
TIM4 timer supply current(1)
IDD(TIM4)
120
UART1 supply current(2)
IDD(UART1)
45
SPI supply current(2)
IDD(SPI)
65
I2C supply current(2)
IDD(I2C)
1000
ADC1 supply current when converting(3)
IDD(ADC1)
(1) Data based on a differential IDD measurement between reset configuration and timer counter running
at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
(2) Data based on a differential IDD measurement between the on-chip peripheral when kept under reset
and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling.
Not tested in production.
(3) Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions. Not tested in production.
Current consumption curves10.3.2.8
The following figures show typical current consumption measured with code executing in
RAM.
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
Figure 12: Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz
Figure 13: Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V
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Figure 14: Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz
Figure 15: Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
Figure 16: Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V
Figure 17: Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz
External clock sources and timing characteristics10.3.3
HSE user external clock
Subject to general operating conditions for VDD and TA.
Table 32: HSE user external clock characteristics
UnitMaxMinConditionsParameterSymbol
MHz160
User external clock source
frequency
fHSE_ext
V
VDD + 0.3 V0.7 x VDD
OSCIN input pin high level
voltage
VHSEH
(1)
0.3 x VDD
VSS
OSCIN input pin low level
voltage
VHSEL
(1)
μA+1-1
VSS < VIN < VDD
OSCIN input leakage currentILEAK_HSE
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Electrical characteristicsSTM8S103K3 STM8S103F3 STM8S103F2
(1) Data based on characterization results, not tested in production.
Figure 18: HSE external clocksource
VHSEH
VHSEL
External clock
source OSCIN
fHSE
STM8
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 33: HSE oscillator characteristics
UnitMaxTypMinConditionsParameterSymbol
MHz161
External high speed
oscillator frequency
fHSE
kΩ220
Feedback resistorRF
pF20
Recommended load
capacitance(2)
C(1)
mA
6 (startup)
C = 20 pF,
HSE oscillator power
consumption
IDD(HSE)
1.6 (stabilized)(3)
fOSC = 16 MHz
6 (startup)
C = 10 pF,
1.2 (stabilized)(3)
fOSC =16 MHz
mA/V5
Oscillator
transconductance
gm
ms1
VDD is stabilizedStartup timetSU(HSE)
(4)
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
(1) C is approximately equivalent to 2 x crystal Cload.
(2) The oscillator selection can be optimized in terms of supply current using a high quality resonator with
small Rmvalue. Refer to crystal manufacturer for more details
(3) Data based on characterization results, not tested in production.
(4) tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16
MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
Figure 19: HSE oscillator circuit diagram
OSCOUT
OSCIN
fHSE to core
CL1
CL2
RF
STM8
Resonator Consumption
control
gm
Rm
Cm
LmCO
Resonator
HSE oscillator critical g mequation
gmcrit= (2 × Π × fHSE)2× Rm(2Co + C)2
Rm: Notional resistance (see crystal specification)
Lm: Notional inductance (see crystal specification)
Cm: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
CL1= CL2 = C: Grounded external capacitance
gm>> gmcrit
Internal clock sources and timing characteristics10.3.4
Subject to general operating conditions for VDD and TA.
High speed internal RC oscillator (HSI)
Table 34: HSI oscillator characteristics
UnitMaxTypMinConditionsParameterSymbol
MHz-16-
FrequencyfHSI
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UnitMaxTypMinConditionsParameterSymbol
%
1.0(3)
--
User-trimmed with
CLK_HSITRIMR register for
Accuracy of HSI
oscillator
ACCHSI
given VDD and TA
conditions(1)
1.0--1.0
VDD = 5 V, TA= 25°C(2)
Accuracy of HSI
oscillator (factory
2.0--2.0
VDD = 5 V, 25 °C ≤
TA≤ 85 °C
calibrated)
3.0(2)
-
-3.0(2)
2.95 ≤ VDD≤ 5.5 V,-40 °C
≤ TA≤ 125 °C
μs
1.0(3)
--
HSI oscillator
wakeup time
tsu(HSI)
including
calibration
μA
250(2)
170-
HSI oscillator
power
IDD(HSI)
consumption
(1) Refer to application note.
(2) Data based on characterization results, not tested in production.
(3) Guaranteed by design, not tested in production.
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
Figure 20: Typical HSI frequency variation vs VDD @ 4 temperatures
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for VDD and TA.
Table 35: LSI oscillator characteristics
UnitMaxTypMinParameterSymbol
kHz150128110
FrequencyfLSI
μs7--
LSI oscillator wake-up timetsu(LSI)
μA-5-
LSI oscillator power consumptionIDD(LSI)
Figure 21: Typical LSI frequency variation vs VDD @ 4 temperatures
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Memory characteristics10.3.5
RAM and hardware registers
Table 36: RAM and hardware registers
UnitMinConditionsParameterSymbol
V
VIT-max
(2)
Halt mode (or reset)
Data retention mode(1)
VRM
(1) Minimum supply voltage without losing data stored in RAM (in halt mode or under reset)
or in hardware registers (only in halt mode). Guaranteed by design, not tested in production.
(2) Refer to the Operating conditions section for the value of VIT-max
Flash program memory/data EEPROM memory
Table 37: Flash program memory/data EEPROM memory
UnitMaxTyp
Min(1)
ConditionsParameterSymbol
V5.5-2.95
fCPU ≤ 16 MHz
Operating voltage
(all modes, execution/
write/erase)
VDD
ms
6.66-
Standard programming time
(including erase) for
tprog
byte/word/block (1 byte/
4 bytes/64 bytes)
3.333-
Fast programming time for
1 block (64 bytes)
3.333-
Erase time for 1 block
(64 bytes)
terase
cycles
--
100
000
TA= +85 °C
Erase/write cycles(2)
(program memory)
NRW
-1 M
300
000
TA= +125 °C
Erase/write cycles
(data memory)(2)
years--20
TRET = 55°C
Data retention (program
and data memory) after 10k
tRET
erase/write cycles at
TA= +55 °C
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
UnitMaxTyp
Min(1)
ConditionsParameterSymbol
--1
TRET = 85°C
Data retention (data
memory) after 300k
erase/write cycles at
TA= +125 °C
mA-2-
Supply current (Flash
programming or erasing
IDD
for 1 to 128 bytes)
(1) Data based on characterization results, not tested in production.
(2) The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes
even when a write/erase operation addresses a single byte.
I/O port pin characteristics10.3.6
General characteristics
Subject to general operating conditions for VDD and TAunless otherwise specified. All unused
pins must be kept at a fixed voltage: using the output mode of the I/O for example or an
external pull-up or pull-down resistor.
Table 38: I/O static characteristics
UnitMaxTypMinConditionsParameterSymbol
V
0.3 x
VDD
--0.3
VDD = 5 V
Input low level voltage
VIL
VDD +
0.3
-
0.7 x
VDD
Input high level voltage
VIH
mV-700-
Hysteresis(1)
Vhys
kΩ805530
VDD = 5 V, VIN = VSS
Pull-up resistor
Rpu
ns
35 (3)
--
Fast I/Os
Load = 50 pF
Rise and fall time
(10 % - 90 %)
tR, tF
125 (3)
--
Standard and high sink
I/Os
Load = 50 pF
20(3)
--
Fast I/Os
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UnitMaxTypMinConditionsParameterSymbol
Load = 20 pF
50 (3)
--
Standard and high sink
I/Os
Load = 20 pF
μA
±1 (2)
--
VSS ≤ VIN ≤VDD
Digital input leakage current
Ilkg
nA
±250 (2)
--
VSS ≤ VIN ≤ VDD
Analog input leakage current
Ilkg ana
μA
±1 (2)
--
Injection current ±4 mA
Leakage current in adjacent
I/O
Ilkg(inj)
(1) Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not
tested in production.
(2)Data based on characterisation results, not tested in production.
(3)Data guaranteed by design.
Figure 22: Typical VIL and VIH vs VDD @ 4 temperatures
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Figure 23: Typical pull-up resistance vs VDD @ 4 temperatures
Figure 24: Typical pull-up current vs VDD @ 4 temperatures
Table 39: Output driving current (standard ports)
UnitMaxMinConditionsParameterSymbol
V
2.0-
IIO= 10 mA,
VDD = 5 V
Output low level with 8 pins sunk
VOL
1.0(1)
-
IIO = 4 mA,
VDD = 3.3 V
Output low level with 4 pins sunk
-2.8
IIO = 10 mA,
VDD = 5 V
Output high level with 8 pins sourced
VOH
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UnitMaxMinConditionsParameterSymbol
-
2.1(1)
IIO = 4 mA,
VDD = 3.3 V
Output high level with 4 pins sourced
(1) Data based on characterization results, not tested in production
Table 40: Output driving current (true open drain ports)
UnitMaxConditionsParameterSymbol
V
1 .0
IIO = 10 mA, VDD = 5 V
Output low level with 2 pins sunk
VOL
1.5(1)
IIO = 10 mA, VDD = 3.3
V
Output low level with 2 pins sunk
VOL
2.0(1)
IIO = 20 mA, VDD = 5 V
Output low level with 2 pins sunk
VOL
(1) Data based on characterization results, not tested in production
Table 41: Output driving current (high sink ports)
UnitMaxMinConditionsParameterSymbol
V0.8-
IIO = 10 mA,
VDD = 5 V
Output low level with 8 pins sunk
VOL
V
1.0(1)
-
IIO = 10 mA,
VDD = 3.3 V
Output low level with 4 pins sunk
VOL
1.5(1)
-
IIO = 20 mA,
VDD = 5 V
Output low level with 4 pins sunk
-4.0
IIO = 10 mA,
VDD = 5 V
Output high level with 8 pins sourced
VOH -
2.1(1)
IIO = 10 mA,
VDD = 3.3 V
Output high level with 4 pins sourced
-
3.3(1)
IIO = 20 mA,
VDD = 5 V
Output high level with 4 pins sourced
(1) Data based on characterization results, not tested in production
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Figure 25: Typ. VOL @ VDD = 5 V (standard ports)
Figure 26: Typ. VOL @ VDD = 3.3 V (standard ports)
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Figure 27: Typ. VOL @ VDD = 5 V (true open drain ports)
Figure 28: Typ. VOL @ VDD = 3.3 V (true open drain ports)
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Figure 29: Typ. VOL @ VDD = 5 V (high sink ports)
Figure 30: Typ. VOL @ VDD = 3.3 V (high sink ports)
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Figure 31: Typ. VDD - VOH@ VDD = 5 V (standard ports)
Figure 32: Typ. VDD - VOH @ VDD = 3.3 V (standard ports)
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
Figure 33: Typ. VDD - VOH@ VDD = 5 V (high sink ports)
Figure 34: Typ. VDD - VOH@ VDD = 3.3 V (high sink ports)
Reset pin characteristics10.3.7
Subject to general operating conditions for VDD and TAunless otherwise specified.
Table 42: NRST pin characteristics
UnitMaxTypMinConditionsParameterSymbol
V0.3 x VDD
--0.3
NRST input low
VIL(NRST)
level voltage(1)
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UnitMaxTypMinConditionsParameterSymbol
VDD + 0.3-0.7 x VDD
IOL=2 mA
NRST input high
VIH(NRST)
level voltage (1)
0.5--
NRST output low
VOL(NRST)
level voltage (1)
kΩ805530
NRST pull-up
RPU(NRST)
resistor(2)
ns
75--
NRST input filtered
tI FP(NRST)
pulse(3)
--500
NRST input not
tIN FP(NRST)
filtered pulse(3)
μs--
20
NRST output
pulse (3)
tOP(NRST)
(1) Data based on characterization results, not tested in production.
(2) The RPU pull-up equivalent resistor is based on a resistive transistor
(3) Data guaranteed by design, not tested in production.
Figure 35: Typical NRST VIL and VIH vs VDD @ 4 temperatures
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
Figure 36: Typical NRST pull-up resistance vs VDD @ 4 temperatures
Figure 37: Typical NRST pull-up current vs VDD @ 4 temperatures
The reset network shown in the following figure protects the device against parasitic resets.
The user must ensure that the level on the NRST pin can go below VIL(NRST) max. (see Table
38: I/O static characteristics ), otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry,
attention must be taken to the charge/discharge time of the external capacitor to fulfill the
external devices reset timing conditions. Minimum recommended capacity is 100 nF.
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Figure 38: Recommended reset pin protection
External
reset
circuit
(optional) 0.1 μF
NRST
VDD
RPU
Filter Internal reset
STM8
SPI serial peripheral interface10.3.8
Unless otherwise specified, the parameters given in the following table are derived from tests
performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions.
tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 43: SPI characteristics
UnitMaxMin
Conditions(1)
ParameterSymbol
MHz80
Master modeSPI clock
frequency
fSCK1/
tc(SCK)
MHz7(2)
0
SPI clock frequencyfSCK1/ tc(SCK)
fSCK1/
tc(SCK)
ns
25-
Capacitive load: C = 30 pFSPI clock rise and
fall time
tr(SCK)
tf(SCK)
-
4 x
tMASTER
Slave modeNSS setup timetsu(NSS)
(3)
-70Slave modeNSS hold timeth(NSS)
(3)
tSCK/
2 +15
tSCK/
2 - 15
Master modeSCK high and low
time
tw(SCKH)
(3)
tw(SCKL)
(3)
-5Master modeData input setup
time
tsu(MI)
(3)
tsu(SI)
(3) -5Slave mode
-7Master modeData input hold
time
th(MI)
(3)
th(SI)
(3) -10Slave mode
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UnitMaxMin
Conditions(1)
ParameterSymbol
3 x
tMASTER
-
Slave modeData output
access time
ta(SO)
(3) (4)
-25
Slave modeData output
disable time
tdis(SO)
(3) (5)
65(2)
-
Slave mode
(after enable edge)
Data output valid
time
tv(SO)
(3)
30-
Master mode
(after enable edge)
Data output valid
time
tv(MO)
(3)
-27(2)
Slave mode
(after enable edge)
Data output hold
time
th(SO)
(3)
-11(2)
Master mode
(after enable edge)
Data output hold
time
th(MO)
(3)
(1) Parameters are given by selecting 10 MHz I/O output frequency.
(2) Data characterization in progress.
(3) Values based on design simulation and/or characterization results, and not tested in
production.
(4) Min time is for the minimum time to drive the output and the max time is for the maximum
time to validate the data.
(5) Min time is for the minimum time to invalidate the output and the max time is for the
maximum time to put the data in Hi-Z.
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Figure 39: SPI timing diagram - slave mode and CPHA = 0
ai14134
SCK Input
CPHA=0
MOSI
INPUT
MISO
OUTPUT
CPHA=0
MSB O UT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
NSS input
tSU(NSS) tc(SCK) th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK) tdis(SO)
tsu(SI)
th(SI)
Figure 40: SPI timing diagram - slave mode and CPHA = 1
ai14135
SCK Input
CPHA=1
MOSI
INPUT
MISO
OUTPUT
CPHA=1
MSB O UT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
tSU(NSS) tc(SCK) th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK) tdis(SO)
tsu(SI) th(SI)
NSS input
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
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Figure 41: SPI timing diagram - master mode(1)
ai14136b
SCK intput
CPHA=0
MOSI
OUTUT
MISO
INPUT
CPHA=0
MSBIN
MSB OUT
BIT6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
BIT1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL) tr(SCK)
tf(SCK)
th(MI)
High
SCK output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
I2C interface characteristics10.3.9
Table 44: I2C characteristics
Unit
Fast mode I2C(1)
Standard mode I2C
ParameterSymbol
Max(2)
Min(2)
Max(2)
Min(2)
μs
-1.3-4.7SCL clock low timetw(SCLL)
-0.6-4.0SCL clock high timetw(SCLH)
ns
-100-250SDA setup timetsu(SDA)
900(3)
0(4)
-0(3)
SDA data hold timeth(SDA)
300-1000-SDA and SCL rise time
tr(SDA)
tr(SCL)
300-300-SDA and SCL fall time
tf(SDA)
tf(SCL)
μs
-0.6-4.0START condition hold timeth(STA)
-0.6-4.7Repeated START condition setup timetsu(STA)
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Unit
Fast mode I2C(1)
Standard mode I2C
ParameterSymbol
Max(2)
Min(2)
Max(2)
Min(2)
-0.6-4.0STOP condition setup timetsu(STO)
μs-1.3-4.7
STOP to START condition time
(bus free)
tw(STO:STA)
pF400-400Capacitive load for each bus lineCb
(1) fMASTER, must be at least 8 MHz to achieve max fast I2C speed (400kHz)
(2) Data based on standard I2C protocol requirement, not tested in production
(3) The maximum hold time of the start condition has only to be met if the interface does not stretch the
low time
(4) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL
Figure 42: Typical application with I2C bus and timing diagram
tf(SDA) tr(SDA) tsu(SDA) th(SDA)
tf(SCL)
tr(SCL)
tw(SCLL)
tw(SCLH)
th(STA) tsu(STO)
tsu(STA) tw(STO:STA)
SDA
SCL
4.7kΩSDA
SCL
100Ω
100Ω
4.7kΩ
I2C bus
START START
STOP
REPEATED
START
STM8S
VDD VDD
ai17490
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD.
10-bit ADC characteristics10.3.10
Subject to general operating conditions for VDD, fMASTER, and TAunless otherwise specified.
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
Table 45: ADC characteristics
UnitMaxTypMinConditionsParameterSymbol
MHz
4
-
1VDD =2.95 to 5.5 VADC clock frequencyfADC
6
-
1VDD =4.5 to 5.5 V
VVDD
-
VSS
Conversion voltage range(1)
VAIN
pF
-
3
-
Internal sample and hold
capacitor
CADC
μs
-
0.75
-
fADC = 4 MHzMinimum sampling timetS
(1)
-
0.5
-
fADC = 6 MHz
μs
-
7
-
Wake-up time from standbytSTAB
μs3.5fADC = 4 MHzMinimum total conversion time
(including sampling time,
10-bit resolution)
tCONV
μs2.33fADC = 6 MHz
1/fADC
14
(1) During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged
by the external source. The internal resistance of the analog source must allow the
capacitance to reach its final voltage level within tS. After the end of the sample time tS,
changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tSdepend on programming.
Table 46: ADC accuracy with RAIN < 10 kΩ , VDD= 5 V
UnitMax(1)
TypConditionsParameterSymbol
LSB
3.51.6fADC = 2 MHzTotal unadjusted error(2)
|ET|
42.2fADC = 4 MHz
4.52.4fADC = 6 MHz
2.51.1fADC = 2 MHzOffset error(2)
|EO|
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UnitMax(1)
TypConditionsParameterSymbol
31.5fADC = 4 MHz
31.8fADC = 6 MHz
31.5fADC = 2 MHzGain error(2)
|EG|
32.1fADC = 4 MHz
42.2fADC = 6 MHz
1.50.7fADC = 2 MHzDifferential linearity error(2)
|ED|
1.50.7fADC = 4 MHz
1.50.7fADC = 6 MHz
1.50.6fADC = 2 MHzIntegral linearity error(2)
|EL|
20.8fADC = 4 MHz
20.8fADC = 6 MHz
(1) Data based on characterization results, not tested in production.
(2) ADC accuracy vs. negative injection current: Injecting negative current on any of the
analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in the I/O
port pin characteristics section does not affect the ADC accuracy.
Table 47: ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V
UnitMax(1)
TypConditionsParameterSymbol
LSB
3.51.6fADC = 2 MHzTotal unadjusted error(2)
|ET|
41.9fADC = 4 MHz
2.51fADC = 2 MHzOffset error(2)
|EO|
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UnitMax(1)
TypConditionsParameterSymbol
2.51.5fADC = 4 MHz
31.3fADC = 2 MHzGain error(2)
|EG|
32fADC = 4 MHz
10.7fADC = 2 MHzDifferential linearity error(2)
|ED|
1.50.7fADC = 4 MHz
1.50.6fADC = 2 MHzIntegral linearity error(2)
|EL|
20.8fADC = 4 MHz
(1) Data based on characterization results, not tested in production.
(2) ADC accuracy vs. negative injection current: Injecting negative current on any of the
analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in I/O port
pin characteristics does not affect the ADC accuracy.
Figure 43: ADC accuracy characteristics
1. Example of an actual transfer curve.
2. The ideal transfer curve
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3. End point correlation line
ET= Total unadjusted error: maximum deviation between the actual and the ideal transfer
curves.
EO= Offset error: deviation between the first actual transition and the first ideal one.
EG= Gain error: deviation between the last ideal transition and the last actual one.
ED= Differential linearity error: maximum deviation between actual steps and the ideal
one.
EL= Integral linearity error: maximum deviation between any actual transition and the end
point correlation line.
Figure 44: Typical application with ADC
STM8
10-bit A/D
conversion
RAIN
CAIN
VAIN AINx
VDD
VT
0.6 V
VT
0.6 V IL
± 1 µA CADC
EMC characteristics10.3.11
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)10.3.11.1
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
•FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of
the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.
•FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with
the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table
below based on the EMS levels and classes defined in application note AN1709 (EMC design
guide for STMicrocontrollers).
Designing hardened software to avoid noise problems10.3.11.2
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
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Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques
for improving microcontroller EMC performance).
Table 48: EMS data
Level/
class
ConditionsParameterSymbol
2/B (1)
VDD = 3.3 V, TA= 25 °C, fMASTER = 16 MHz
(HSI clock), conforming to IEC 61000-4-2
Voltage limits to be
applied on any I/O pin to
induce a functional
disturbance
VFESD
4/A (1)
VDD= 3.3 V, TA= 25 °C ,fMASTER = 16 MHz
(HSI clock),conforming to IEC 61000-4-4
Fast transient voltage
burst limits to be applied
through 100 pF on VDD
VEFTB
and VSS pins to induce a
functional disturbance
(1)Data obtained with HSI clock configuration, after applying HW recommendations described
in AN2860 (EMC guidelines for STM8S microcontrollers).
Electromagnetic interference (EMI)10.3.11.3
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This emission test is in line with the norm SAE
IEC 61967-2 which specifies the board and the loading of each pin.
Table 49: EMI data
Unit
Conditions
ParameterSymbol Max fHSE/fCPU
(1)
Monitored
frequency band
General
conditions 16 MHz/
16 MHz
16 MHz/
8 MHz
dBμV
55
0.1 MHz to
VDD = 5 V
TA= 25 °C
Peak level
SEMI 30 MHz
LQFP32
package 54
30 MHz to
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Electrical characteristicsSTM8S103K3 STM8S103F3 STM8S103F2
Unit
Conditions
ParameterSymbol Max fHSE/fCPU
(1)
Monitored
frequency band
General
conditions 16 MHz/
16 MHz
16 MHz/
8 MHz
Conforming to
SAE IEC
61967-2
130 MHz
55
130 MHz to
1 GHz
2.52.5
SAE EMI level
SAE EMI
level
(1) Data based on characterisation results, not tested in production.
Absolute maximum ratings (electrical sensitivity)10.3.11.4
Based on three different tests (ESD, DLU and LU) using specific measurement methods, the
product is stressed to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.
Electrostatic discharge (ESD)10.3.11.5
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied
to the pins of each sample according to each pin combination. The sample size depends on
the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated:
Human body model. This test conforms to the JESD22-A114A/A115A standard. For more
details, refer to the application note AN1181.
Table 50: ESD absolute maximum ratings
UnitMaximum
value(1)
ClassConditionsRatingsSymbol
V
4000A
TA= 25°C, conforming toElectrostatic discharge
VESD(HBM)
JESD22-A114voltage
(Human body model)
1000IV
TALQFP32 package =Electrostatic discharge
VESD(CDM)
25°C, conforming tovoltage
SD22-C101(Charge device model)
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STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics
(1) Data based on characterization results, not tested in production
Static latch-up10.3.11.6
Two complementary static tests are required on 10 parts to assess the latch-up performance:
•A supply overvoltage (applied to each power supply pin)
•A current injection (applied to each input, output and configurable I/O pin) are performed
on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 51: Electrical sensitivities
Class(1)
ConditionsParameterSymbol
ATA= 25 °C
Static latch-up classLU ATA= 85 °C
ATA= 125 °C
(1) Class description: A Class is an STMicroelectronics internal specification. All its limits
are higher than the JEDEC specifications, that means when a device belongs to class A it
exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international
standard).
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Electrical characteristicsSTM8S103K3 STM8S103F3 STM8S103F2
Package information11
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK®packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK®
is an ST trademark.
32-pin LQFP package mechanical data11.1
Figure 45: 32-pin low profile quad flat package (7 x 7)
5V_ME
L
A1 K
L1
c
A
A2
ccc C
D
D1
D3
E3 E1 E
16
17
24
25
b
32
1
Pin 1
identification 8
9
Table 52: 32-pin low profile quad flat package mechanical data
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.06301.600A
0.00590.00200.1500.050A1
0.05710.05510.05311.4501.4001.350A2
0.01770.01460.01180.4500.3700.300b
0.00790.00350.2000.090c
0.36220.35430.34659.2009.0008.800D
0.28350.27560.26777.2007.0006.800D1
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STM8S103K3 STM8S103F3 STM8S103F2Package information
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.22055.600D3
0.36220.35430.34659.2009.0008.800E
0.28350.27560.26777.2007.0006.800E1
0.22055.600E3
0.03150.800e
0.02950.02360.01770.7500.6000.450L
0.03941.000L1
7.0°3.5°0.0°7.0°3.5°0.0°k
0.00390.100ccc
(1) Values in inches are converted from mm and rounded to 4 decimal digits
95/117DocID15441 Rev 9
Package informationSTM8S103K3 STM8S103F3 STM8S103F2
32-lead UFQFPN package mechanical data11.2
Figure 46: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5)
AOB8_ME
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint
life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended
to connect and solder this backside pad to PCB ground.
4. Dimensions are in millimeters.
Table 53: 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.02360.02170.01970.6000.5500.500A
0.00200.00080.0500.0200A1
0.00790.200A3
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STM8S103K3 STM8S103F3 STM8S103F2Package information
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.01180.00980.00710.3000.2500.180b
0.20280.19690.19095.1505.0004.850D
0.14570.12603.7003.4503.200D2
0.20280.19690.19095.1505.0004.850E
0.14570.13580.12603.7003.4503.200E2
0.01970.500e
0.01970.01570.01180.5000.4000.300L
0.00310.080ddd
(1) Values in inches are converted from mm and rounded to 4 decimal digits.
20-lead UFQFPN package mechanical data11.3
Figure 47: 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3)
103_A0A5_ME
11
15
1620
1
5
D
e
be
E
A1 A
ddd
L2
10
L1
A3
L3
L4
D
E
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Pin 1
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Package informationSTM8S103K3 STM8S103F3 STM8S103F2
1. Drawing is not to scale.
Table 54: 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package
mechanical data
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.11813.000D
0.11813.000E
0.02360.02170.01970.6000.5500.500A
0.00200.00080.00000.0500.0200.000A1
0.00600.152A3
0.01970.500e
0.02360.02170.01970.6000.5500.500L1
0.01570.01380.01180.4000.3500.300L2
0.00590.150L3
0.00790.200L4
0.01180.00980.00710.3000.2500.180b
0.00200.050ddd
(1) Values in inches are converted from mm and rounded to 4 decimal digits.
SDIP32 package mechanical data11.4
Figure 48: 32-lead shrink plastic DIP (400 ml) package
Table 55: 32-lead shrink plastic DIP (400 ml) package mechanical data
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.20000.14800.14005.0803.7593.556A
0.02000.508A1
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STM8S103K3 STM8S103F3 STM8S103F2Package information
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.18000.14000.12004.5723.5563.048A2
0.02300.01800.01400.5840.4570.356B
0.05500.04000.03001.3971.0160.762B1
0.01400.01000.00790.3560.2540.203C
1.12011.10001.079928.45027.94027.430D
0.43500.40980.390011.05010.4109.906E
0.37000.35000.30009.3988.8907.620E1
0.07001.778e
0.400010.160eA
0.500012.700eB
0.15000.12000.10003.8103.0482.540L
(1) Values in inches are converted from mm and rounded to 4 decimal digits
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Package informationSTM8S103K3 STM8S103F3 STM8S103F2
20-pin TSSOP package mechanical data11.5
Figure 49: 20-pin, 4.40 mm body, 0.65 mm pitch
YA_ME
1
20
CP
c
L
EE1
D
A2
A
k
eb
10
11
A1
L1
aaa
Table 56: 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.04721.200A
0.00590.00200.1500.050A1
0.04130.03940.03151.0501.0000.800A2
0.01180.00750.3000.190b
0.00790.00350.2000.090c
0.25980.25590.25206.6006.5006.400D
0.25980.25200.24416.6006.4006.200E
0.17720.17320.16934.5004.4004.300E1
0.02560.650e
0.02950.02360.01770.7500.6000.450L
0.03941.000L1
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STM8S103K3 STM8S103F3 STM8S103F2Package information
inches(1)
mmDim.
MaxTypMinMaxTypMin
8.0°0.0°8.0°0.0°k
0.00390.100aaa
(1) Values in inches are converted from mm and rounded to 4 decimal digits
20-pin SO package mechanical data11.6
Figure 50: 20-lead, plastic small outline (300 mils) package
E
20
e
D
C
H
1 10
11
B
Z7_ME
A1 LA1 k
h x 45°
A
ddd
Table 57: 20-lead, plastic small outline (300 mils) mechanical data
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.10430.09252.6502.350A
0.01180.00390.3000.100A1
0.02010.0130.5100.330B
0.01260.00910.3200.230C
0.51180.496113.00012.600D
0.29920.29137.6007.400E
0.05001.270e
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Package informationSTM8S103K3 STM8S103F3 STM8S103F2
inches(1)
mmDim.
MaxTypMinMaxTypMin
0.41930.393710.65010.000H
0.02950.00980.7500.250h
0.05000.01571.2700.400L
8.0°0.0°8.0°0.0°k
0.00390.100ddd
(1) Values in inches are converted from mm and rounded to 4 decimal digits
UFQFPN recommended footprint11.7
Figure 51: Recommended footprint for on-board emulation
Bottom view
4mm
[0.157"]
4mm [0.157"]
0.5mm
0.5mm
0.3mm [0.012"]
0.9mm
[0.035"]
0.8mm
[0.032"]
1.65mm [0.065"]
ai15319
1. Drawing is not to scale
DocID15441 Rev 9102/117
STM8S103K3 STM8S103F3 STM8S103F2Package information
Figure 52: Recommended footprint without on-board emulation
1. Drawing is not to scale
2. Dimensions are in millimeters
103/117DocID15441 Rev 9
Package informationSTM8S103K3 STM8S103F3 STM8S103F2
Thermal characteristics12
The maximum chip junction temperature (TJ max) must never exceed the values given in
Operating conditions.
The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using
the following equation:
TJmax = TAmax + (PDmax x ΘJA)
Where:
•TAmax is the maximum ambient temperature in °C
•ΘJA is the package junction-to-ambient thermal resistance in °C/W
•PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
•PINTmax is the product of IDD andVDD, expressed in Watts. This is the maximum chip internal
power.
•PI/Omax represents the maximum power dissipation on output pins
Where: PI/Omax =Σ (VOL*IOL) + Σ((VDD-VOH)*IOH), taking into account the actual VOL/IOL and
VOH/IOH of the I/Os at low and high level in the application.
Table 58: Thermal characteristics
UnitValueParameter(1)
Symbol
°C/W84Thermal resistance junction-ambient
TSSOP20 - 4.4 mm
ΘJA
91Thermal resistance junction-ambient
SO20W (300 mils)
ΘJA
90Thermal resistance junction-ambient
UFQFPN20 - 3 x 3 mm
ΘJA
60Thermal resistance junction-ambient
LQFP32 - 7 x 7 mm
ΘJA
38Thermal resistance junction-ambient
UFQFPN32 - 5 x 5 mm
ΘJA
60Thermal resistance junction-ambient
SDIP32 - 400 mils
ΘJA
(1)Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural
convection environment.
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STM8S103K3 STM8S103F3 STM8S103F2Thermal characteristics
Reference document12.1
JESD51-2 integrated circuits thermal test method environment conditions - natural convection
(still air). Available from www.jedec.org.
Selecting the product temperature range12.2
When ordering the microcontroller, the temperature range is specified in the order code.
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
•Maximum ambient temperature TAmax= 75 °C (measured according to JESD51-2)
•IDDmax = 8 mA, VDD = 5 V
•Maximum 20 I/Os used at the same time in output at low level with
IOL = 8 mA, VOL= 0.4 V
PINTmax = 8 mA x 5 V = 400 mW
Amax
•PDmax = 400 mW + 64 mW
Thus: PDmax = 464 mW
TJmax for LQFP32 can be calculated as follows, using the thermal resistance ΘJA:
TJmax = 75 °C + (60 °C/W x 464 mW) = 75 °C + 27.8 °C = 102.8 °C
This is within the range of the suffix 6 version parts (-40 < TJ< 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6.
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Thermal characteristicsSTM8S103K3 STM8S103F3 STM8S103F2
Ordering information13
Figure 53: STM8S103x access line ordering information scheme
Pin count
K = 32 pins
F = 20 pins
Example:
Sub-family type
10x = Access line
103 sub-family
Family type
S = Standard
Temperature range
3 = -40 °C to 125 °C
6 = -40 °C to 85 °C
Program memory size
3 = 8 Kbytes
2 = 4 Kbytes
Packing
No character = Tray or tube
TR = Tape and reel
Package pitch
Blank = 0.5 or 0.65 mm(2)
C = 0.8 mm(3)
STM8 S 103 K 3 T 6 TR
Product class
STM8 microcontroller
Package type 1
P = TSSOP
T = LQFP
U = UFQFPN
M = SO
B = SDIP
1. A dedicated ordring information scheme will be released if, in the future, memory
programming service (FastROM) is required The letter "P" will be added after STM8S.
Three unique letters identifying the customer application code will also be visible in the
codification. Example: STM8SP103K3MACTR.
2. UFQFPN, TSSOP, and SO packages.
3. LQFP package.
For a list of available options (e.g. memory size, package) and orderable part numbers or for
further information on any aspect of this device, please go to www.st.com or contact the ST
Sales Office nearest to you.
STM8S103 FASTROM microcontroller option list13.1
(last update: April 2010)
.............................................................................................Customer
DocID15441 Rev 9106/117
STM8S103K3 STM8S103F3 STM8S103F2Ordering information
.............................................................................................Address
.............................................................................................Contact
.............................................................................................Phone no.
.............................................................................................Reference FASTROM codea
Preferable format for programing code is .Hex (.s19 is accepted)
If data EEPROM programing is required, a seperate file must be sent with the requested data.
Important: See the option byte section in the datasheet for authorized option byte
combinations and a detailed explanation. Do not use more than one remapping option
in the same port. It is forbidden to enable both AFR1 and AFR0.
Device type/memory size/package (check only one option)
8 Kbyte4 KbyteFASTROM device
[ ] STM8S103K3LQFP32
[ ] STM8S103F3[ ] STM8S103F2UFQFPN20
[ ] STM8S103K3UFQFPN32
[ ] STM8S103F3[ ] STM8S103F2TSSOP20
[ ] STM8S103F3[ ] STM8S103F2SO20W
Conditioning (check only one option)
[ ] Tape & reel or [ ] Tray
Special marking (check only one option)
[ ] No [ ] Yes
Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character counts
are:
UFQFPN20: 1 line of 4 characters max: "_ _ _ _"
UFQFPN32: 1 line of 7 characters max: "_ _ _ _ _ _ _"
LQFP32: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _"
TSSOP20/SO20: 1 line of 10 characters max: "_ _ _ _ _ _ _ _ _ _"
Three characters are reserved for code identification.
Temperature range
[ ] -40°C to +85°C or [ ] -40°C to +125°C
Padding value for unused program memory (check only one option)
Fixed value[ ]0xFF
TRAP instruction opcode[ ]0x83
Illegal opcode (causes a reset when executed)[ ]0x75
aFASTROM code name is assigned by STMicroelectronics.
107/117DocID15441 Rev 9
Ordering informationSTM8S103K3 STM8S103F3 STM8S103F2
OPT0 memory readout protection (check only one option)
[ ] Disable or [ ] Enable
OPT1 user boot code area (UBC)
0x(_ _) fill in the hexadecimal value, refering to the datasheet and the binary format below.
[ ] 0: Reset
UBC, bit0
[ ] 1: Set
[ ] 0: Reset
UBC bit1
[ ] 1: Set
[ ] 0: Reset
UBC bit2
[ ] 1: Set
[ ] 0: Reset
UBC bit3
[ ] 1: Set
[ ] 0: Reset
UBC bit4
[ ] 1: Set
[ ] 0: Reset
UBC bit5
[ ] 1: Set
[ ] 0: Reset
UBC bit6
[ ] 1: Set
[ ] 0: Reset
UBC bit7
[ ] 1: Set
OPT2 alternate function remapping for STM8S103K
Do not use more than one remapping option in the same port. It is forbidden to enable both
AFR1 and AFR0.
ReservedAFR0
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR1
(check only one option)
[ ] 1: Port A3 alternate function = SPI_NSS and port D2
alternate function = TIM2_CH3
ReservedAFR2
ReservedAFR3
ReservedAFR4
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STM8S103K3 STM8S103F3 STM8S103F2Ordering information
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR5
(check only one option)
[ ] 1: Port D0 alternate function = CLK_CCO
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR6
(check only one option)
[ ] 1: Port D7 alternate function = TIM1_CH4
ReservedAFR7
OPT2 alternate function remapping for STM8S103F
Do not use more than one remapping option in the same port. It is forbidden to enable both
AFR1 and AFR0.
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR0
(check only one option)
[ ] 1: Port C5 alternate function = TIM2_CH1, port C6 alternate
function = TIM1_CH1, and port C7 alternate function =
TIM1_CH2
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR1
(check only one option)
[ ] 1: Port A3 alternate function = SPI_NSS and port D2 alternate
function = TIM2_CH3
Reserved
AFR2
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR3
(check only one option)
[ ] 1: Port C3 alternate function = TLI
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR4
(check only one option)
[ ] 1: Port B4 alternate function = ADC_ETR and port B5 alternate
function = TIM1_BKIN
ReservedAFR5
ReservedAFR6
[ ] 0: Remapping option inactive. Default alternate functions
used. Refer to pinout description
AFR7
(check only one option)
[ ] 1: Port C3 alternate function = TIM1_CH1N and port C4
alternate function = TIM1_CH2N
OPT3 watchdog
[ ] 0: No reset generated on halt if WWDG active
WWDG_HALT
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Ordering informationSTM8S103K3 STM8S103F3 STM8S103F2
(check only one option) [ ] 1: Reset generated on halt if WWDG active
[ ] 0: WWDG activated by software
WWDG_HW
(check only one option) [ ] 1: WWDG activated by hardware
[ ] 0: IWDG activated by software
IWDG_HW
(check only one option) [ ] 1: IWDG activated by hardware
[ ] 0: LSI clock is not available as CPU clock source
LSI_EN
(check only one option) [ ] 1: LSI clock is available as CPU clock source
[ ] 0: 3-bit trimming supported in CLK_HSITRIMR register
HSITRIM
(check only one option) [ ] 1: 4-bit trimming supported in CLK_HSITRIMR register
OPT4 wakeup
[ ] for 16 MHz to 128 kHz prescaler
PRSC
(check only one option) [ ] for 8 MHz to 128 kHz prescaler
[ ] for 4 MHz to 128 kHz prescaler
[ ] LSI clock source selected for AWU
CKAWUSEL
(check only one option) [ ] HSE clock with prescaler selected as clock source for
for AWU
[ ] External crystal connected to OSCIN/OSCOUT
EXTCLK
(check only one option) [ ] External clock signal on OSCIN
OPT5 crystal oscillator stabilization HSECNT (check only one option)
[ ] 2048 HSE cycles
[ ] 128 HSE cycles
[ ] 8 HSE cycles
[ ] 0.5 HSE cycles
OPT6 is reserved
...........................................................................................................Comments:
...........................................................................................................Supply operating range
in the application:
...........................................................................................................Notes:
...........................................................................................................Date:
...........................................................................................................Signature:
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STM8 development tools14
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation boards
and a low-cost in-circuit debugger/programmer.
Emulation and in-circuit debugging tools14.1
The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8
application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers
new advanced debugging capabilities including profiling and coverage to help detect and
eliminate bottlenecks in application execution and dead code when fine tuning an application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to order
exactly what you need to meet your development requirements and to adapt your emulation
system to support existing and future ST microcontrollers.
STice key features
•Occurrence and time profiling and code coverage (new features)
•Advanced breakpoints with up to 4 levels of conditions
•Data breakpoints
•Program and data trace recording up to 128 KB records
•Read/write on the fly of memory during emulation
•In-circuit debugging/programming via SWIM protocol
•8-bit probe analyzer
•1 input and 2 output triggers
•Power supply follower managing application voltages between 1.62 to 5.5 V
•Modularity that allows you to specify the components you need to meet your development
requirements and adapt to future requirements
•Supported by free software tools that include integrated development environment (IDE),
programming software interface and assembler for STM8.
Software tools14.2
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8, which are available in a free version that outputs up
to 16 Kbytes of code.
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STM8 toolset14.2.1
STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com/mcu. This package includes:
ST Visual Develop – Full-featured integrated development environment from ST, featuring
•Seamless integration of C and ASM toolsets
•Full-featured debugger
•Project management
•Syntax highlighting editor
•Integrated programming interface
•Support of advanced emulation features for STice such as code profiling and coverage
ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,
write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and
option bytes. STVP also offers project mode for saving programming configurations and
automating programming sequences.
C and assembly toolchains14.2.2
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
•Cosmic C compiler for STM8 – Available in a free version that outputs up to 16 Kbytes
of code. For more information, see www.cosmic-software.com.
•Raisonance C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.raisonance.com.
•STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which
allows you to assemble and link your application source code.
Programming tools14.3
During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to include
a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated
programming platforms with sockets for programming your STM8.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
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STM8S103K3 STM8S103F3 STM8S103F2STM8 development tools
Revision history15
Table 59: Document revision history
ChangesRevisionDate
Initial revision
1
02-Mar-2009
Added Table 2: Peripheral clock gating bit assignments in
CLK_PCKENR1/2 registers.
2
10-Apr-2009
Updated Auto wakeup counter.
Modified description of PB4 and PB5 (removed X in PP column)
and added footnote concerning HS I/Os in VFQFPN32/LQFP32
pin description and STM8S103Kx UFQFPN32/LQFP32/SDIP32
pinout and pin description.
Removed TIM3 and UART from Table 10: Interrupt mapping.
Updated VCAP specifications in VCAP external capacitor.
Corrected block size in Table 37: Flash program memory/data
EEPROM memory.
Updated Electrical characteristics.
Updated Table 58: Thermal characteristics.
Document status changed from “preliminary data” to
“datasheet”.
3
10-Jun-2009
Replaced WFQFPN20 package with UFQFPN package.
Replaced ‘VFQFN’ with ‘VFQFPN’.
Added bullet point on the unique identifier to Features.
Updated Auto wakeup counter.
Updated wpu and PP status of PB5/12C_SDA and
PB4/12C_SCL pins in VFQFPN32/LQFP32 pin description and
STM8S103Fx TSSOP20/SO20/UFQFPN20 pin description.
Removed Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin
access line devices.
Updated Figure 7: Memory map.
Updated reset status of port D CR1 register in Table 7: I/O port
hardware register map.
Updated alternate function remapping descriptions in Table
13: STM8S103K alternate function remapping bits for 32-pin
devices and Table 14: STM8S103F alternate function
remapping bits for 20-pin devices.
Added Unique ID.
113/117DocID15441 Rev 9
Revision historySTM8S103K3 STM8S103F3 STM8S103F2
ChangesRevisionDate
Updated Table 19: General operating conditions.
Updated name of Figure. Typical HSI accuracy at VDD = 5V
vs 5 temperatures.
Updated Table 43: SPI characteristics and added TBD data.
Added max values to Table 46: ADC accuracy with RAIN < 10
kΩ , VDD= 5 V and Table 47: ADC accuracy with RAIN < 10
kΩ RAIN, VDD = 3.3 V in the 10-bit ADC characteristics.
Updated EMC characteristics.
Replaced VFQFPN32 package by UFQFPN32 package.
4
16-Oct-2009
Clock controller: replaced "TIM2" and "TIM3" with "reserved"
and "TIM2" respectively in "Peripheral clock gating bit
assignments in CLK_PCKENR1/2 registers" table.
Total current consumption in halt mode: changed the maximum
current consumption limit at 125 °C (and VDD = 5 V) from 35
µA to 55 µA.
Functional EMS (electromagnetic susceptibility) : "ESD"
changed to "FESD" (functional); added name of AN1709;
replaced "IEC 1000" with "IEC 61000".
Designing hardened software to avoid noise problems: replaced
"IEC 1000" with "IEC 61000", added title of AN1015, and added
footnote to EMS data table.
Electromagnetic interference (EMI): replaced "J 1752/3" with
"IEC 61967-2" and updated data of the EMI data table.
Selecting the product temperature range: changed the value
of LQFP32 7x7 mm thermal resistance from 59 °C/W to 60
°C/W.
Added STM8S103 FASTROM microcontroller option list.
Added VFQFPN32 and SO20 packages.
522-Apr-2010
Updated Px_IDR reset value in Table 7: I/O port hardware
register map.
Operating conditions: updated VCAP and ESR low limit, added
ESL parameter, and Note 1 below Table 19: General operating
conditions.
Updated ACCHSI in Table 34: HSI oscillator characteristics
table. Modified IDD(H) in Table 27: Total current consumption
in halt mode at VDD = 5 V and Table 28: Total current
consumption in halt mode at VDD = 3.3 V. Removed note 3
related to Accuracy of HSI oscillator.
DocID15441 Rev 9114/117
STM8S103K3 STM8S103F3 STM8S103F2Revision history
ChangesRevisionDate
Updated maximum power dissipation in Table 19: General
operating conditions.
Updated ΘJA in Table 58: Thermal characteristics.
Replaced package pitch digit by VFQFPN/UFQFPN package
digit in Figure 53: STM8S103x access line ordering information
scheme, and removed note 1.
Removed VFQFPN32 package.
609-Sep-2010
Removed internal reference voltage from Analog-to-digital
converter (ADC1).
Updated "reset state" of Table 4: Legend/abbreviations for
pinout tables in Pinout and pin description.
Added footnote to PD1/SWIM pin in STM8S103Kx
UFQFPN32/LQFP32/SDIP32 pinout and pin description.
Updated pins 14 and 19 (TSSOP20/SO20) / pins 11 and 16
(UFQFPN20) in STM8S103Fx TSSOP20/SO20/UFQFPN20
pin description.
General hardware register map : Standardized all reset state
values; updated the reset state values of the RST_SR,
CLK_SWCR, CLK_HSITRIMR, CLK_SWIMCCR, IWDG_KR,
and ADC_DRx registers in the "General hardware register
map" table.
Updated AFR2 description of OPT 2 in Table 14: STM8S103F
alternate function remapping bits for 20-pin devices.
Replaced 0.01 µF with 0.1 µf in Figure 38: Recommended
reset pin protection.
Added "Typical application with I2C bus and timing diagram in
I2C interface characteristics.
Updated footnote 1 in Table 46: ADC accuracy with RAIN <
10 kΩ , VDD= 5 V and Table 47: ADC accuracy with RAIN <
10 kΩ RAIN, VDD = 3.3 V .
STM8S103 FASTROM microcontroller option list: updated
"special marking" section and AFR2 description of OPT2
alternate function remapping for STM8S103F.
32-lead UFQFPN package mechanical data: updated existing
footnote and added three additional footnotes.
Updated note related to true open-drain outputs in Table 6:
STM8S103Fx pin description.
712-Jul-2011
Remove CLK_CANCCR register from Table 8: General
hardware register map
115/117DocID15441 Rev 9
Revision historySTM8S103K3 STM8S103F3 STM8S103F2
ChangesRevisionDate
Added note for Px_IDR registers in Table 7: I/O port hardware
register map.
Added recommendation concerning NRST pin level, and power
consumption sensitive applications, above Figure 38:
Recommended reset pin protection.
Removed typical HSI accuracy curve in Internal clock sources
and timing characteristics.
Renamed package type 2 into package pitch and added pitch
code "C" in Figure 53: STM8S103x access line ordering
information scheme, and added UFQFPN20 in STM8S103
FASTROM microcontroller option list.
Updated disclaimer.
Updated notes related to VCAP in Table 19: General operating
conditions.
804-Apr-2012
Added values of tR/tFfor 50 pF load capacitance, and updated
note in Table 38: I/O static characteristics.
Updated typical and maximum values of RPU in Table 38: I/O
static characteristics and Table 42: NRST pin characteristics.
Changed SCK input to SCK output in SPI serial peripheral
interface
Modified Figure 47: 20-lead, ultra thin, fine pitch quad flat
no-lead package outline (3 x 3)to add package top view.
Added SDIP32 package.926-Jun-2012
DocID15441 Rev 9116/117
STM8S103K3 STM8S103F3 STM8S103F2Revision history
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