DATA SH EET
Product specification
Supersedes data of 2002 May 21 2002 Nov 15
INTEGRATED CIRCUITS
74LVC1G32
Single 2-input OR gate
2002 Nov 15 2
Philips Semiconductors Product specification
Single 2-input OR gate 74LVC1G32
FEATURES
•Wide supply voltage range from 1.65 to 5.5 V
•High noise immunity
•Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V).
•±24 mA output drive (VCC = 3.0 V)
•CMOS low power consumption
•Latch-up performance exceeds 250 mA
•Direct interface with TTL levels
•Inputs accept voltages up to 5 V
•Multiple package options
•ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
•Specified from −40 to +125 °C.
DESCRIPTION
The 74LVC1G32 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Input can be driven from either 3.3 or 5 V devices. This
feature allow the use of these devices in a mixed
3.3 and 5 V environment.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall time.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G32 provides the single 2-input OR function.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f≤2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts;
N = total switching outputs;
Σ(CL×VCC2×fo) = sum of the outputs.
2. The condition is VI= GND to VCC.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay
inputs A, B to output Y VCC = 1.8 V; CL= 30 pF; RL=1kΩ3.1 ns
VCC = 2.5 V; CL= 30 pF; RL= 500 Ω2.1 ns
VCC = 2.7 V; CL= 50 pF; RL= 500 Ω2.5 ns
VCC = 3.3 V; CL= 50 pF; RL= 500 Ω2.1 ns
VCC = 5.0 V; CL= 50 pF; RL= 500 Ω1.7 ns
CIinput capacitance 5 pF
CPD power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 16 pF
2002 Nov 15 3
Philips Semiconductors Product specification
Single 2-input OR gate 74LVC1G32
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
PINNING
INPUT OUTPUT
ABY
LLL
LHH
HLH
HHH
TYPE NUMBER PACKAGE
TEMPERATURE
RANGE PINS PACKAGE MATERIAL CODE MARKING
74LVC1G32GW −40 to +125 °C 5 SC-88A plastic SOT353 VG
74LVC1G32GV −40 to +125 °C 5 SC-74A plastic SOT753 V32
PIN SYMBOL DESCRIPTION
1 B data input B
2 A data input A
3 GND ground (0 V)
4 Y data output Y
5V
CC supply voltage
handbook, halfpage
1
2
3
5
4
MNA163
32
VCC
A
Y
GND
B
Fig.1 Pin configuration.
handbook, halfpage
MNA164
B
AY
2
14
Fig.2 Logic symbol.
2002 Nov 15 4
Philips Semiconductors Product specification
Single 2-input OR gate 74LVC1G32
handbook, halfpage
MNA165
4
≥1
2
1
Fig.3 IEE/IEC logic symbol.
handbook, halfpage
MNA166
B
A
Y
Fig.4 Logic diagram.
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage 1.65 5.5 V
VIinput voltage 0 5.5 V
VOoutput voltage active mode 0 VCC V
VCC = 0 V; Power-down mode 0 5.5 V
Tamb operating ambient temperature −40 +125 °C
tr,t
finput rise and fall times VCC = 1.65 to 2.7 V 0 20 ns/V
VCC = 2.7 to 5.5 V 0 10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5 V
IIK input diode current VI<0 −−50 mA
VIinput voltage note 1 −0.5 +6.5 V
IOK output diode current VO>V
CC or VO<0 −±50 mA
VOoutput voltage active mode; notes 1 and 2 −0.5 VCC + 0.5 V
Power-down mode; notes 1 and 2 −0.5 +6.5 V
IOoutput diode current VO=0toV
CC −±50 mA
ICC, IGND VCC or GND current −±100 mA
Tstg storage temperature −65 +150 °C
PDpower dissipation per package for temperature range from
−40 to +125 °C−250 mW
2002 Nov 15 5
Philips Semiconductors Product specification
Single 2-input OR gate 74LVC1G32
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground=0V).
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
Tamb =−40 to +85 °C
VIH HIGH-level input voltage 1.65 to 1.95 0.65 ×VCC −−V
2.3 to 2.7 1.7 −−V
2.7 to 3.6 2.0 −−V
4.5 to 5.5 0.7 ×VCC −−V
V
IL LOW-level input voltage 1.65 to 1.95 −−0.35 ×VCC V
2.3 to 2.7 −−0.7 V
2.7 to 3.6 −−0.8 V
4.5 to 5.5 −−0.3 ×VCC V
VOL LOW-level output voltage VI=V
IH or VIL
IO= 100 µA 1.65 to 5.5 −−0.1 V
IO= 4 mA 1.65 −−0.45 V
IO=8mA 2.3 −−0.3 V
IO=12mA 2.7 −−0.4 V
IO=24mA 3.0 −−0.55 V
IO=32mA 4.5 −−0.55 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−100 µA 1.65 to 5.5 VCC −0.1 −−V
I
O
=−4 mA 1.65 1.2 −−V
I
O
=−8 mA 2.3 1.9 −−V
I
O
=−12 mA 2.7 2.2 −−V
I
O
=−24 mA 3.0 2.3 −−V
I
O
=−32 mA 4.5 3.8 −−V
I
LI input leakage current VI= 5.5 V or GND 5.5 −±0.1 ±5µA
Ioff power OFF leakage
current VIor VO= 5.5 V 0 −±0.1 ±10 µA
ICC quiescent supply current VI=V
CC or GND;
IO=0 5.5 −0.1 10 µA
∆ICC additional quiescent
supply current per pin VI=V
CC −0.6 V;
IO=0 2.3 to 5.5 −5 500 µA
2002 Nov 15 6
Philips Semiconductors Product specification
Single 2-input OR gate 74LVC1G32
Note
1. All typical values are measured at VCC = 3.3 V and Tamb =25°C.
Tamb =−40 to +125 °C
VIH HIGH-level input voltage 1.65 to 1.95 0.65 ×VCC −−V
2.3 to 2.7 1.7 −−V
2.7 to 3.6 2.0 −−V
4.5 to 5.5 0.7 ×VCC −−V
V
IL LOW-level input voltage 1.65 to 1.95 −−0.35 ×VCC V
2.3 to 2.7 −−0.7 V
2.7 to 3.6 −−0.8 V
4.5 to 5.5 −−0.3 ×VCC V
VOL LOW-level output voltage VI=V
IH or VIL
IO= 100 µA 1.65 to 5.5 −−0.1 V
IO= 4 mA 1.65 −−0.70 V
IO=8mA 2.3 −−0.45 V
IO=12mA 2.7 −−0.60 V
IO=24mA 3.0 −−0.80 V
IO=32mA 4.5 −−0.80 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−100 µA 1.65 to 5.5 VCC −0.1 −−V
I
O
=−4 mA 1.65 0.95 −−V
I
O
=−8 mA 2.3 1.7 −−V
I
O
=−12 mA 2.7 1.9 −−V
I
O
=−24 mA 3.0 2.0 −−V
I
O
=−32 mA 4.5 3.4 −−V
I
LI input leakage current VI= 5.5 V or GND 5.5 −−±100 µA
Ioff power OFF leakage
current VIor VO= 5.5 V 0 −−±200 µA
ICC quiescent supply current VI=V
CC or GND;
IO=0 5.5 −−200 µA
∆ICC additional quiescent
supply current per pin VI=V
CC −0.6 V;
IO=0 2.3 to 5.5 −−5000 µA
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
2002 Nov 15 7
Philips Semiconductors Product specification
Single 2-input OR gate 74LVC1G32
AC CHARACTERISTICS
GND = 0 V; tr=t
f≤2.0 ns.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
Tamb =−40 to +85 °C
tPHL/tPLH propagation
delay A, B to Y see Figs 5 and 6 1.65 to 1.95 1.0 3.1 8.0 ns
2.3 to 2.7 0.5 2.1 5.5 ns
2.7 0.5 2.5 5.5 ns
3.0 to 3.6 0.5 2.1 4.5 ns
4.5 to 5.5 0.5 1.7 4.0 ns
Tamb =−40 to +125 °C
tPHL/tPLH propagation
delay A, B to Y see Figs 5 and 6 1.65 to 1.95 1.0 −10.5 ns
2.3 to 2.7 0.5 −7.0 ns
2.7 0.5 −7.0 ns
3.0 to 3.6 0.5 −6.0 ns
4.5 to 5.5 0.5 −5.5 ns
2002 Nov 15 8
Philips Semiconductors Product specification
Single 2-input OR gate 74LVC1G32
AC WAVEFORMS
handbook, halfpage
MNA615
tPHL tPLH
VM
VM
A, B input
Y output
GND
VI
VOH
VOL
Fig.5 A, B to Y propagation delay times.
VCC VMINPUT
VItr=t
f
1.65 to 1.95 V 0.5 ×VCC VCC ≤2.0 ns
2.3 to 2.7 V 0.5 ×VCC VCC ≤2.0 ns
2.7 V 1.5 V 2.7 V ≤2.5 ns
3.0 to 3.6 V 1.5 V 2.7 V ≤2.5 ns
4.5 to 5.5 V 0.5 ×VCC VCC ≤2.5 ns
VOL and VOH are typical output voltage drop that occur with the output load.
2002 Nov 15 9
Philips Semiconductors Product specification
Single 2-input OR gate 74LVC1G32
handbook, full pagewidth
VEXT
VCC
VIVO
MNA616
D.U.T.
CL
RT
RL
RL
PULSE
GENERATOR
Fig.6 Load circuitry for switching times.
VCC VICLRLVEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
1.65 to 1.95 V VCC 30 pF 1 kΩopen GND 2 ×VCC
2.3 to 2.7 V VCC 30 pF 500 Ωopen GND 2 ×VCC
2.7 V 2.7 V 50 pF 500 Ωopen GND 6 V
3.0 to 3.6 V 2.7 V 50 pF 500 Ωopen GND 6 V
4.5 to 5.5 V VCC 50 pF 500 Ωopen GND 2 ×VCC
Definitions for test circuit:
RL= Load resistor.
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.
2002 Nov 15 10
Philips Semiconductors Product specification
Single 2-input OR gate 74LVC1G32
PACKAGE OUTLINES
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
SOT353
wBM
b
p
D
e
1
e
A
A
1
L
p
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
45
Plastic surface mounted package; 5 leads SOT353
UNIT A1
max bpcD
E (2) e1HELpQywv
mm 0.1 0.30
0.20 2.2
1.8
0.25
0.10 1.35
1.15 0.65
e
1.3 2.2
2.0 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15 0.25
0.15
A
1.1
0.8
97-02-28SC-88A
2002 Nov 15 11
Philips Semiconductors Product specification
Single 2-input OR gate 74LVC1G32
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT753 SC-74A
wBM
b
p
D
e
A
A
1
L
p
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
45
Plastic surface mounted package; 5 leads SOT753
UNIT A1bpcDEH
E
L
p
Qywv
mm 0.100
0.013 0.40
0.25 3.1
2.7
0.26
0.10 1.7
1.3
e
0.95 3.0
2.5 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.6
0.2 0.33
0.23
A
1.1
0.9
02-04-16
2002 Nov 15 12
Philips Semiconductors Product specification
Single 2-input OR gate 74LVC1G32
SOLDERING
Introduction to soldering surface mount packages
Thistextgivesaverybriefinsightto a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurfacemountICs,butitisnotsuitableforfinepitch
SMDs. In these situations reflow soldering is
recommended.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuit boardby screen printing,stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackageswithleadsonfoursides,thefootprintmust
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2002 Nov 15 13
Philips Semiconductors Product specification
Single 2-input OR gate 74LVC1G32
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. Formoredetailed information onthe BGA packages referto the
“(LF)BGAApplication Note
”(AN01026);order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS not suitable(3) suitable
PLCC(4), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(4)(5) suitable
SSOP, TSSOP, VSO not recommended(6) suitable
2002 Nov 15 14
Philips Semiconductors Product specification
Single 2-input OR gate 74LVC1G32
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseorat any other conditions abovethosegivenin the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
2002 Nov 15 15
Philips Semiconductors Product specification
Single 2-input OR gate 74LVC1G32
NOTES
© Koninklijke Philips Electronics N.V. 2002 SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands 613508/03/pp16 Date of release: 2002 Nov 15 Document order number: 9397 750 10073
Philips Semiconductors - PIP - 74LVC1G32; Single 2-input OR gate
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General description
The 74LVC1G32 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families.
Input can be driven from either 3.3 or 5 V devices. This feature allow the use of these devices in a mixed 3.3 and 5 V
environment.
Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.
This device is fully specified for partial power-down applications using Ioff . The Ioff circuitry disables the output,
preventing the damaging backflow current through the device when it is powered down.
The 74LVC1G32 provides the single 2-input OR function.
top
Features
● Wide supply voltage range from 1.65 to 5.5 V
● High noise immunity
● Complies with JEDEC standard:
❍ JESD8-7 (1.65 to 1.95 V)
❍ JESD8-5 (2.3 to 2.7 V)
❍ JESD8B/JESD36 (2.7 to 3.6 V).
● +-24 mA output drive (VCC = 3.0 V)
● CMOS low power consumption
● Latch-up performance exceeds 250 mA
● Direct interface with TTL levels
● Inputs accept voltages up to 5 V
● Multiple package options
● ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
● Specified from -40 to +125 Cel.
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74LVC1G32GW.html (1 of 3) [May-12-2003 2:52:30 PM]
Philips Semiconductors - PIP - 74LVC1G32; Single 2-input OR gate
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Applications
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File
AN10161_2: PicoGate Logic footprints (date 30-Oct-02)
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Datasheet
Type number Title Publication release
date Datasheet status Page count File size
(kB) Datasheet
74LVC1G32 Single 2-
input OR
gate
11/15/2002 Product specification 16 75
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PDF
File
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Parametrics
Type number Package Description Propagation
Delay(ns) Voltage No.
of
Pins
Power
Dissipation
Considerations
Logic
Switching
Levels
Output
Drive
Capability
74LVC1G32GW SOT353
(UMT5)
3.3V
PicoGate 2-
Input OR
Gate
4~6 Low 5 Low Power or
Battery
Applications TTL Medium
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Products, packages, availability and ordering
Type number North American
type number Ordering code
(12NC) Marking/Packing
Download
PDF
File
IC packing info Package Device
status Buy online
74LVC1G32GV 9352 720 13125 Standard Marking
* Reel Pack,
Reverse SOT753 Full production -
74LVC1G32GW 74LVC1G32GW-
G 9352 683 81115 Standard Marking
* Reel Pack,
SMD, 7"
SOT353
(UMT5) Full production
order this
product
online
-
9352 683 81118 Standard Marking
* Reel Pack,
SMD, 13"
SOT353
(UMT5) Full production -
9352 683 81125 Standard Marking
* Reel Pack,
Reverse
SOT353
(UMT5) Full production -
9352 683 81165
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SOT353
(UMT5) Full production -
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