EVAL-ADIN1300FMCZ User Guide UG-1635 One Technology Way * P.O. Box 9106 * Norwood, MA 02062-9106, U.S.A. * Tel: 781.329.4700 * Fax: 781.461.3113 * www.analog.com Evaluating the ADIN1300 Robust, Industrial, Low Latency, and Low Power 10 Mbps, 100 Mbps, and 1 Gbps Ethernet PHY FEATURES GENERAL DESCRIPTION FMC connector for MII interface, MDIO signals, and status signals Accessible, surface-mount configuration resistors and dial switches Operates from a single, external 5 V supply The EVAL-ADIN1300FMCZ allows simplified evaluation of the key features of the ADIN1300 robust, industrial, low latency gigabit, 10 Mbps, 100 Mbps, and 1 Gbps, Ethernet physical layer (PHY). The EVAL-ADIN1300FMCZ is powered by a single, external, 5 V supply rail that can be supplied either via the EXT_5V connector or via the P4 plug. EVALUATION KIT CONTENTS All chip supplies are regulated from the 5 V rail providing supply rails required for AVDD3P3, VDD0P, and VDDIO. EVAL-ADIN1300FMCZ evaluation board MDIO interface dongle EQUIPMENT NEEDED Power supply (choose one of the following): 5 V power supply rail to connect to the EXT_5V connector 5 V barrel adaptor to connect to the P4 plug Ethernet cable USB cable PC running Windows 7 and upward SOFTWARE NEEDED Ethernet PHY software and GUI (available to download on the ADIN1300 product page) The P3 field programmable gate array (FPGA) mezzanine connector (FMC) connector is provided for connection to a master FPGA system for the media access control (MAC) interface and management data input/output (MDIO) control. The P5 connector provides an alternative means for MDIO control. The EVAL-ADIN1300FMCZ is fitted with a 25 MHz crystal (Y1). For complete specifications for the ADIN1300 device, see the ADIN1300 data sheet, which must be consulted in conjunction with this user guide when using the EVAL-ADIN1300FMCZ. DOCUMENTS NEEDED ADIN1300 data sheet PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 30 UG-1635 EVAL-ADIN1300FMCZ User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Link Properties Tab .................................................................... 12 Evaluation Kit Contents ................................................................... 1 Register Access Tab .................................................................... 13 Equipment Needed ........................................................................... 1 Clock Pin Control Tab ............................................................... 13 Software Needed ............................................................................... 1 Loopback Tab .............................................................................. 13 Documents Needed .......................................................................... 1 Testmodes Tab ............................................................................ 13 General Description ......................................................................... 1 Framechecker Tab ...................................................................... 14 Revision History ............................................................................... 2 Cable Diagnostics Tab ............................................................... 14 EVAL-ADIN1300FMCZ with Optional MDIO Interface Dongle Connected.......................................................................................... 3 Activity Window and Linking Status....................................... 15 Evaluation Board Hardware ............................................................ 4 Loading a Script File .................................................................. 16 Power Supplies .............................................................................. 4 Troubleshooting .............................................................................. 17 Power Sequencing ........................................................................ 4 Software Installation Tips.......................................................... 17 Evaluation Board Usage Options ............................................... 4 Software Tips .............................................................................. 17 Jumper Options ............................................................................ 4 Hardware Tips ............................................................................ 17 Clock Options ............................................................................... 4 Layout Guidelines ........................................................................... 18 On-Board EEPROM and LEDs .................................................. 5 Board Stackup ............................................................................. 18 ADIN1300 LED Pin ..................................................................... 5 Ground Planes ............................................................................ 18 MDIO Interface ............................................................................ 5 Isolation Guidelines ................................................................... 18 MDIO Interface Dongle .............................................................. 6 Power Supply Decoupling ......................................................... 18 Configuration Pins Setup ............................................................ 6 MAC Interface ............................................................................ 18 Software Overview ........................................................................... 8 Management Interface ............................................................... 18 Installing the Ethernet PHY Software ....................................... 8 Placement of the TVS Diode .................................................... 18 Initial Setup ................................................................................... 9 Thermal Considerations............................................................ 18 Using the Evaluation Software ...................................................... 10 Evaluation Board Schematics and Artwork ................................ 19 GUI Detailed Overview ................................................................. 11 Ordering Information .................................................................... 27 Board Display Showing Connected EVAL-ADIN1300FMCZ Hardware ..................................................................................... 11 Bill of Materials ........................................................................... 27 Activity Log Information Section ............................................ 15 User Buttons Section .................................................................. 11 REVISION HISTORY 10/2019--Revision 0: Initial Version Rev. 0 | Page 2 of 30 EVAL-ADIN1300FMCZ User Guide UG-1635 21419-001 EVAL-ADIN1300FMCZ WITH OPTIONAL MDIO INTERFACE DONGLE CONNECTED Figure 1. Rev. 0 | Page 3 of 30 UG-1635 EVAL-ADIN1300FMCZ User Guide EVALUATION BOARD HARDWARE POWER SUPPLIES The EVAL-ADIN1300FMCZ operates from a single, external, 5 V supply rail. Apply 5 V either to the P4 plug or to the EXT_5V connector with the JP3 jumper configured for 5 V at Position A. The rest of the EVAL-ADIN1300FMCZ power requirements are generated from the 5 V supply. Two on-board ADP223 devices generate the AVDD3P3, VDDIO, VDD0P9, and DVDD power rails. The default nominal voltages are listed in Table 1. The VDDIO voltage rail defaults to 2.5 V with the installed components, and may be adjusted if other VDDIO voltages are required by changing the value of the R16 resistor accordingly, as shown in Table 1. Table 1. Default Device Power Supply Configuration Supply Rail AVDD3P3 VDDIO VDD0P9 DVDD Nominal Voltage 3.3 V 2.5 V 0.9 V 3.3 V Adjustment Not applicable 1.8 V with R16 = 130 k 2.5 V with R16 = 200 k 3.3 V with R16 = 280 k Not applicable Not applicable Table 2 shows an overview of the EVAL-ADIN1300FMCZ current for various operating modes. chip. In standalone mode, power the EVAL-ADIN1300FMCZ with a 5 V supply at the EXT_5V connector. Alternatively to standalone mode, the EVAL-ADIN1300FMCZ has an FMC low pin count (LPC) connector, which can be plugged into an FPGA development board. When used with an FPGA board, the media independent interfaces (MIIs), clocks, and light emitting diodes (LEDs) can be connected to the FPGA board where the MAC and upper layers can be implemented for evaluation of the ADIN1300 in a full system. JUMPER OPTIONS A number of jumpers on the EVAL-ADIN1300FMCZ must be set for the required operating setup before using the EVALADIN1300FMCZ for evaluation. The default settings and functions of these jumper options are described in Table 3. Table 3. Default Jumper Options and Descriptions Link JP1 JP2 Position Not inserted B (high) JP3 A (5V) Table 2. EVAL-ADIN1300FMCZ Quiescent Current (EXT_5V = 5 V) Board Status On Power-Up In Hardware Power-Down (RESET_N Held Low) 10BASE-Te 100BASE-TX 1000BASE-T Function Do not install (DNI). This jumper sets the write mode of U7. Position A (low): enable writing to the electrically erasable programmable read only memory (EEPROM). Position B (high): WP the EEPROM (default). This jumper sets the 5 V supply source. Set to Position A. Position A (5V): either P4 or EXT_5V is the 5 V supply source (default). Position B (12V): This circuit is not installed. JP3 should always be set to Position A. Typical Quiescent Current 30 mA initially 6.5 mA in energy detect power down (EDPD) mode 6.5 mA CLOCK OPTIONS 50 mA 60 mA 145 mA The crystal oscillators on the EVAL-ADIN1300FMCZ and the MDIO interface dongle include the following: The EVAL-ADIN1300FMCZ provides the option to supply the ADIN1300 clock requirements from either an on-board crystal oscillator, or an external clock applied to the J1 connector. POWER SEQUENCING There is no particular power sequence required for the ADIN1300 device. When using the EVAL-ADIN1300FMCZ with the MDIO interface dongle, there is a known sequence requirement for the MDIO interface dongle. The MDIO interface dongle should be powered from the USB cable prior to connection to the EVALADIN1300FMCZ. Alternatively, if issues are observed, restart the GUI software to resolve any board connection issues. EVALUATION BOARD USAGE OPTIONS The EVAL-ADIN1300FMCZ can be used in two general modes. In standalone mode, the EVAL-ADIN1300FMCZ can be used to evaluate the ADIN1300 in IEEE 802.3 test modes, establish links with a link partner, and evaluate the performance of the Y1 is a 25 MHz crystal connected across the XTAL_I pin and XTAL_O pin of the ADIN1300 on the EVALADIN1300FMCZ. Y2 is a 32.768 kHz crystal used on the MDIO interface dongle for the on-board ADuCM3029. Y3 is a 26 MHz crystal used on the MDIO interface dongle for the on-board ADuCM3029. When a 25 MHz external clock is applied to the J1 connector, the R120 resistor must be populated and the R15 and R119 resistors must be removed to disconnect the Y1 crystal. The 25 MHz clock must be a sine or square wave signal with an input range of 1.8 V to 2.5 V. See the ADIN1300 data sheet for more information. Rev. 0 | Page 4 of 30 EVAL-ADIN1300FMCZ User Guide UG-1635 AVDD3P3 U7 can be programmed with voltage settings to allow the FPGA board to provide the correct voltages on the supply rails. The write address of the EEPROM is 0b[10100 [GA1] [GA0] 0] and the read address is 0b[10100 [GA1] [GA0] 1]. ADIN1300 LED PIN There is one LED pin (LED_0) on the ADIN1300. The LED_0 pin can be configured in various operating modes using the MDIO interface dongle (see the ADIN1300 data sheet). By default, the LED_0 pin LED illuminates when a link is established, and flashes when there is activity. R191 0 S1 Table 4. S1 Switch Positions Jumper JP1 JP2 S4, PHY_CFG0 Mode 3 and Mode 4 Mode 1 and Mode 2 1 LED_0 3 2 R193 10 R110 0 3 Q2 1 R192 100k 2 BC817 MODE 1 AND MODE 2 Figure 2. Hardware LED_0 Pin Configuration MDIO INTERFACE The MDIO interface of the ADIN1300 can be accessed directly through the P5 connector to connect the MDIO interface dongle to the PHY. The MDIO interface dongle also allows interfacing with the EVAL-ADIN1300FMCZ via the Ethernet PHY software graphical user interface (GUI) running on the PC (see Figure 3). POWER EXTERNAL 25MHz CLOCK CRYSTAL RJ45 CONNECTOR The LED_0 pin is a multifunction pin shared with the PHY_CFG0 pin configuration function. Therefore, it can be necessary for the voltage level on the LED_0 pin to be set at a certain value at power-on and reset to configure the ADIN1300 as required. See the ADIN1300 data sheet for more information on the multilevel strapping being used as part of the hardware configuration. The LED_0 pin has a two-pole rotary switch, S1, to allow easy configuration for all modes of the PHY_CFG0 pin (as set by S4). Table 4 describes how S1 should be configured for the appropriate S4 PHY_CFG0 pin setting. The LED_0 pin is driven from the AVDD3P3 supply rail, see Figure 2. DS1 C MAGNETICS MODE SELECT ADIN1300 BOOT STRAP RESISTOR P3 LED0 EVAL-ADIN1300FMCZ OPTIONAL MDIO INTERFACE DONGLE MDIO P5 P7 ADuCM3029 FTDI UART TO USB USB Figure 3. Simplified Overview of EVAL-ADIN1300FMCZ with MDIO Interface Dongle Connected S1 Position 1 2 Rev. 0 | Page 5 of 30 21419-004 The EVAL-ADIN1300FMCZ has two FPGA controllable LEDs and one unprogrammed, I2C EEPROM, U7. A FMC CONNECTOR ON-BOARD EEPROM AND LEDS R43 390 MODE 3 AND MODE 4 21419-003 The ADIN1300 can also be configured to provide a 25 MHz clock output on the CLK25_REF pin, which is available on the FMC connector. The source of this clock is the on-board Y1 crystal. Note that when a pin reset is applied to the ADIN1300, the clock disappears for the duration of the reset and must be reenabled via the Ethernet PHY software following the reset. This clock can be used to synchronously clock the FPGA logic. If a reset for ADIN1300 is required without CLK25_REF stopping, use a software reset instead. Alternatively, the GP_CLK pin is also available on the FMC connector and can be configured to output several different clocks from the ADIN1300. See the ADIN1300 data sheet for more information. UG-1635 EVAL-ADIN1300FMCZ User Guide MDIO INTERFACE DONGLE The MDIO interface dongle is a separate board included in the EVAL-ADIN1300FMCZ evaluation kit. The MDIO interface dongle has an on-board, ADuCM3029 microcontroller and an FDTI Chip FT232RQ, universal asynchronous receive transmitter (UART) to USB interface. The schematic for this hardware is shown in Figure 41. When using the MDIO interface dongle, connect the USB cable to the MDIO interface dongle first, then connect the MDIO interface dongle to the EVALADIN1300FMCZ with the ADuCM3029 facing up (see Figure 4). The MDIO interface dongle has two push-button switches on the underside of the board, S5 and S6, as shown in Figure 5. S5 is for download and reboot purposes. S6 is used to reset the on-board ADuCM3029. BOTTOM S5 Using the MDIO interface dongle allows interaction with the ADIN1300 device via the Ethernet PHY software GUI running on the PC. S6 USB TOP HEADER ADuCM3029 P5 21419-006 ADuCM3029 EVAL-ADIN1300FMCZ MDIO INTERFACE DONGLE USB 21419-005 Figure 5. Overview of MDIO Interface Dongle Figure 4. MDIO Interface Dongle Connection to the USB Cable and EVAL-ADIN1300FMCZ There are two LEDs on the MDIO interface dongle, DS7 and DS8. When the powered USB cable is initially connected to the MDIO interface dongle, DS8 illuminates. When the Ethernet PHY software GUI establishes communication with the EVALADIN1300FMCZ, DS7 and DS8 flash. The LEDs continue to flash while the GUI is active and the EVAL-ADIN1300FMCZ is selected as the local board within the GUI. CONFIGURATION PINS SETUP The EVAL-ADIN1300FMCZ default configuration and configuration options are detailed in Table 5. The ADIN1300 configuration settings can be changed by manipulating the resistors listed in the right column. See the ADIN1300 data sheet for more details on all available configuration options. Figure 6 shows the location of the resistors on the underside of the printed circuit board (PCB) of the EVAL-ADIN1300FMCZ. The speed configuration is configured via two rotary switches, S3 and S4, and the media defined interface configuration is controlled using the S9 switch. Table 5 lists the different switch configurations available. Table 5. EVAL-ADIN1300FMCZ Configuration Settings Configuration Option PHY Address = 0b00000 MDIX Mode Configuration Relevant Pins RXD_3/PHYAD_3 RXD_2/PHYAD_2 RXD_1/PHYAD_1 RXD_0/PHYAD_0 GP_CLK/RX_ER/MDIX_MODE Resistor and Switch Settings R22, R29, R31, R37 = DNI. R23, R30, R32, R38 = DNI. Using internal pull-down resistors. S9 Position1, Mode 1, manual MDI. S9 Position 2, Mode 2, manual MDIX. S9 Position 3, Mode 3, prefer MDIX. S9 Position 4, Mode 4, prefer MDI (default). Rev. 0 | Page 6 of 30 EVAL-ADIN1300FMCZ User Guide MAC Interface Selection Relevant Pins LINK_ST/PHY_CFG1 Resistor and Switch Settings Controlled by S1, S3, and S4 switches to provide the various configuration options (see the ADIN1300 data sheet). LED_0/COL/TX_ER/PHY_CFG0 Default configuration: PHY_CFG1/S3 = 1 or 2. Note that the EVAL-ADIN1300FMCZ boards are shipped in pairs with one board set to 1 and the other set to 2. PHY_CFG0 and S4 = 4, and LED_0 and S1 = 1. R8, R9 = DNI. R27, R28 = DNI. Using internal pull-down resistors results in MAC interface default selection being the reduced gigabit media independent interface (RGMII) MAC interface with 2 ns internal delay on the RXC pin and TXC pin. RX_CTL/RX_DV/CRS_DV/MACIF_SEL1 RXC/RX_CLK/MACIF_SEL0 21419-007 Configuration Option PHY Configuration Downspeed, EDPD, Energy Efficient Ethernet (EEE), Software Power-Down, Forced Speed UG-1635 Figure 6. Configuration Resistor Placement, Underside of PCB Rev. 0 | Page 7 of 30 UG-1635 EVAL-ADIN1300FMCZ User Guide SOFTWARE OVERVIEW 4. INSTALLING THE ETHERNET PHY SOFTWARE The Ethernet PHY software GUI requires the installation of the Ethernet PHY software and the installation of the USB communications drivers. Both installations must be complete before connecting the EVAL-ADIN1300FMCZ to the USB port of the PC to ensure that the evaluation system is properly recognized when connected to the PC. The Ethernet PHY software launches. An overview of what is being installed and recommendations in terms of hardware power-up appears. Read the overview and click Next (see Figure 8). First, install the Ethernet PHY software and the associated documentation (the ADIN1300 data sheet). The installation steps are listed in the following section. The default location for the Ethernet PHY software GUI installation is the C:\Analog Devices folder. 21419-009 When the Ethernet PHY software installation is complete, install the USB communications drivers. The MDIO interface dongle uses the FT232RQ for UART to USB communication. The MDIO interface dongle requires the installation of drivers for the FTDI chip. Locate and install this driver separately. These drivers are available at: www.ftdichip.com/Drivers/CDM/CDM21228_Setup.zip. Ethernet PHY Software GUI Installation Figure 8. Installation Process Overview To install the Ethernet PHY software GUI, take the following steps: 3. A license agreement appears. Read the agreement and click I Agree to allow the installation to proceed (see Figure 9). 21419-010 2. 5. Launch the installer file to begin the Ethernet PHY software installation. If a window appears asking for permission to allow the program to make changes to the PC, click Yes. The welcome window appears (see Figure 7). Click Next. Figure 9. Accepting the License Agreement 21419-008 1. Figure 7. Welcome Window Rev. 0 | Page 8 of 30 EVAL-ADIN1300FMCZ User Guide 6. UG-1635 Select a location to install the Ethernet PHY software and then click Install (see Figure 10). INITIAL SETUP To set up the EVAL-ADIN1300FMCZ and use it with the Ethernet PHY software GUI, take the following steps: 1. 2. 3. 4. 21419-011 5. Figure 10. Installation Location A window appears stating that the installation is complete. Click Finish to continue (see Figure 11). 21419-012 7. Figure 11. Installation Complete 8. The Ethernet PHY software is automatically installed in the Analog Devices folder on the PC. Access the Ethernet PHY software via Windows(R) explorer at C:\Analog Devices\ADIN1300 or from the Start menu. Rev. 0 | Page 9 of 30 Connect a 5 V power supply to the EVAL-ADIN1300FMCZ via the EXT_5V connector or the 5 V barrel connector. Connect the USB cable to the MDIO interface dongle. Connect the USB cable to the PC. When connecting the EVAL-ADIN1300FMCZ to the PC for the first time, the drivers are automatically installed. Wait until the driver installation is complete before proceeding to the next step. Ensure that the ADuCM3029 microcontroller faces up (see Figure 4) and connect the MDIO interface dongle to the EVAL-ADIN1300FMCZ. The MDIO interface dongle is not keyed. Launch the Ethernet PHY software from the Analog Devices folder in the Start menu. UG-1635 EVAL-ADIN1300FMCZ User Guide USING THE EVALUATION SOFTWARE When the Ethernet PHY software is launched, the GUI window shown in Figure 12 appears. Figure 12 shows the GUI features with labels, and Table 6 lists the GUI labels and the corresponding descriptions. Table 6. GUI Label Descriptions 2 3 4 5 6 7 8 9 10 11 12 Description Select Local section. Shows connected evaluation hardware. The board name shown corresponds to the MDIO interface dongle that is connected to the EVAL-ADIN1300FMCZ. User buttons. Link Properties tab. Use this tab to change the PHY configuration. Register Access tab. Allows the user read or write device registers. Clock Pin Control tab. Controls which clock is applied to the GP_CLK pin and enables the CLK25_REF pin. Loopback tab. Controls the various loopback modes. Test Modes tab. Provides access to the various test modes on the device. Framechecker tab. Configures and enables the frame generator and frame checker. Cable Diagnostics tab. Provides easy access to the cable diagnostics features on the device. Activity information window. This window provides an overview of the PHY activity, reads, and writes issued to the device. Activity Log section. Section shows read, write, and status activity for the selected PHY. Dropdown menus to load a script file. These two dropdown menus allow the user to load a script file with a sequence of write commands to load to the device. 21419-013 Label 1 Figure 12. Main GUI Window Rev. 0 | Page 10 of 30 EVAL-ADIN1300FMCZ User Guide UG-1635 GUI DETAILED OVERVIEW Software Power-Down and Power-Up BOARD DISPLAY SHOWING CONNECTED EVAL-ADIN1300FMCZ HARDWARE In the Select Local section (see Figure 12), a unique hardware identifier is shown for each MDIO interface dongle connected to the PC. In the example shown in Figure 13, there are two MDIO interface dongles connected to the same PC (the A62UK21O and AL2YSWGN). The Ethernet PHY software GUI can only communicate with one MDIO interface dongle at a time. To choose which MDIO interface dongle is addressed as the local board in this section, click the appropriate device identifier to select and highlight it. All register controls, displayed link properties, and local board information in other sections of the GUI apply to the selected ADIN1300 device connected to the MDIO interface dongle. Click Software Power Down to place the selected device into software power-down mode where the analog and digital circuits are placed into a low power state. Most clocks are gated off and no link is brought up. Click Software Power Down to enable a software power-down. The button color changes to orange and the button label changes to Software Power Up. Click Software Power Up to exit from the software power-down and restart linking. When the software power-down is asserted, the other buttons for the selected device are grey and disabled. Disable or Enable Linking Click Disable Linking to disable linking when a link is up. The button label changes from Disable Linking to Enable Linking. Click Enable Linking to enable linking. Restart Linking If the software configuration has been changed, click Restart Linking to restart the linking process with the new configuration. If the link has already been established, the link is first brought down and then restarted. Export Registers 21419-014 Click Export Registers to perform a data dump to the Activity Log section. The register dump can be saved to text format for offline review. Right click and click Save as to save the data to a log file. Figure 13. MDIO Interface Dongle Selection USER BUTTONS SECTION 21419-016 Use the buttons in this section to control the basic operation of the GUI and the ADIN1300 device. 21419-015 Figure 15. Activity Log with Export Registers Displayed Figure 14. Basic User Buttons Rev. 0 | Page 11 of 30 UG-1635 EVAL-ADIN1300FMCZ User Guide Reset Speed Mode Click Reset to use the dropdown menu to initiate different resets. The reset options include the following: For the selected device, advertised speed or forced speed can be chosen. The speed selection prepopulates the remaining user controls for the Link Properties tab with the following: 21419-017 Figure 16. Reset Options Subsystem Software Reset with Pin Configuration: click Reset: SubSys (Pin) to perform a reset of the subsystem with the subsystem requesting a new set of hardware configuration pin settings from the chip during the software reset sequence. The GeSftRst bit and the GESftRstCfgEn bit are set to 1. Subsystem Software Reset: click Reset: SubSys to perform a reset of the subsystem with the subsystem requesting previously stored hardware configuration pin settings to be reloaded during the software reset sequence. The GeSftRst bit and the GESftRstCfgEn bit are set to 0. PHY Core Software Reset: click Reset: PHY to perform a reset where the SftRst bit resets the PHY core registers. LINK PROPERTIES TAB 21419-018 The Link Properties tab provides user access to the main linking configurations within the device. This tab has a slider to access all controls. When a control is selected, the GUI provides a prompt describing the function at the bottom of the linking control box (see Figure 17). Figure 17. Link Properties Tab Rev. 0 | Page 12 of 30 Advertised: subset of controls available in advertised mode. The controls include the following: Auto-Negotiated Advertised Speeds: shows the checkbox availability of all autonegotiated advertised speeds available. Select and clear the checkboxes as required. All speed options are available in this section. The default advertised reflects the hardware configuration pins. EEE Advertisement: use the checkboxes to advertise the EEE as a speed option for 1000BASE-T and 100BASE-TX. Downspeed: use the checkbox to enable downspeed, which allows the PHY to change down to a lower speed after a number of attempts to bring up a link at the highest advertised speed. Downspeed Retries: sets the number of times the PHY attempts to bring up a link. The default is four attempts. MDIX: use dropdown menu to choose between Auto MDIX, FixedMDI, or FixedMDIX. Energy Detect PowerDown Mode: use the dropdown menu to choose between Disabled, Enabled, or EnabledWithPeriodicPulseTx. Master/Slave: use the dropdown menu to choose between Master and Slave. The default is Slave. Forced: subset of controls available in forced mode. The controls include the following: Forced Speeds: use the dropdown menu to choose the required speed. MDIX: use the dropdown menu to choose between Auto, FixedMDI, or FixedMDIX. Energy Detect Powerdown Mode: use the dropdown menu to choose between Disabled, Enabled, or EnabledWithPeriodicPulseTx. Master/Slave: use the dropdown menu to choose between Master and Slave. The default is Slave. EVAL-ADIN1300FMCZ User Guide UG-1635 CLOCK PIN CONTROL TAB The Browse tab within the Register Access tab allows the user to review the bank of registers and edit the register fields or bit fields as required (see Figure 18). Use this tab to control which clock is applied to the GP_CLK pin, and to enable the CLK25_REF pin (see Figure 21). 21419-022 REGISTER ACCESS TAB Figure 21. Clock Pin Control Tab LOOPBACK TAB 21419-019 The various loopback modes are available in this tab (see Figure 22). Consult the ADIN1300 data sheet for a full description of each loopback mode. Figure 18. Register Access Tab Full Register Map 21419-023 The Manual tab within the Register Access tab allows the user to perform basic reads from and writes to individual ADIN1300 registers (see Figure 19). Figure 22. Loopback Tab TESTMODES TAB 21419-020 Use this tab to initiate the various test mode functions in the device. Select the appropriate test mode and click Execute Test (see Figure 23). Figure 19. Register Access Tab Figure 20. Activity Log Section Register Access Rev. 0 | Page 13 of 30 21419-024 21419-021 Access the direct register read/write function on the right side of the Activity Log section. To access this function, slide the arrow to the left to expose it (see Figure 20). Figure 23. Test Modes Tab UG-1635 EVAL-ADIN1300FMCZ User Guide FRAMECHECKER TAB CABLE DIAGNOSTICS TAB This tab provides access to the frame generator and frame checker features of the ADIN1300 (see Figure 24). The cable diagnostic feature allows the user to diagnose issues with the link. Various features within the device are available when the link is up, which quantify the quality of the link by measuring features such as the mean squared error (MSE) level and estimated cable length. These measurements are displayed in the main Link Properties tab. Control the number of frames generated by the generator, the frame length, and the content of the frame within this tab. Choose to have the frame generator to either run in burst mode or run continuously. To halt the frame generator when the frame generator is running continuously, use the Terminate button. The features in the Cable Diagnostics tab (see Figure 26) are the features available to run when the link is disabled, such as checking for shorts, checking for opens, and identifying the distance to the first fault (see Figure 28). The LinkEn bit must be clear to run these checks. Use the Loopback button to enable the remote device to loop back the data to the local device. To ensure that the appropriate device is selected, choose which connected board is the local, configure that board to generate frames, then configure the other board in remote loopback. 21419-027 The frame checker information displayed on the screen accumulates the number of frames sent and shows the number of errors observed (see Figure 25). Figure 26. Cable Diagnostics Configuration with Link Up 21419-028 21419-025 Click the Disable Linking button to set the LinkEn bit to 0 to allow diagnostics to be run (see Figure 27 through Figure 29). Figure 27. Cable Diagnostics Configuration when Link is Disabled with Cable Connected to Remote PHY 21419-026 21419-029 Figure 24. Overview of Frame Generator and Frame Checker Figure 28. Cable Diagnostics Configuration with Cable Open Figure 25. Frame Generator Status and Frame Checker Result Rev. 0 | Page 14 of 30 EVAL-ADIN1300FMCZ User Guide UG-1635 ACTIVITY LOG INFORMATION SECTION 21419-030 The activity log reports status information and register write issues to the selected EVAL-ADIN1300FMCZ board (see Figure 32). The activity log captures the activity in the GUI corresponding to the activity on the local PHY, which indicates the various reads, writes, and information on whether a link is established. When the frame generator is enabled, this window shows the frame generator activity. The board identification is recorded with each bit field change to clarify which device is being addressed. Figure 29. Cable Diagnostics Configuration with Cable Crossed ACTIVITY WINDOW AND LINKING STATUS This window displays the current status of the selected PHY chip (as determined in the Select Local section), including whether a link is established, the speed of the link, and the speed mode. The local and remote fields show the advertised speeds available in the local PHY device and also what the remote PHY is returning (see Figure 30). 21419-033 If the user switches between two EVAL-ADIN1300FMCZ boards in the Select Local section, the information shown in these fields will be updated to reflect the information provided from the board defined as local. Figure 32. Activity Log Showing Device Status 21419-031 To clear the activity log, right click and then click Clear. To export the contents of the activity log for offline review, right click and then click Save as. The file saved is a text file with a default location in the Analog Devices > ADIN1300 folder. Figure 30. Board Status Information 21419-032 The GUI displays a color code to show the status of the link depending on how the user has configured the device (see Figure 31). Figure 31. GUI Link Status Rev. 0 | Page 15 of 30 UG-1635 EVAL-ADIN1300FMCZ User Guide The register commands can be loaded with either the register name or the register address, as shown in the simple examples in the file. The commands are loaded sequentially. Create the sequence of write commands using a text editor. Ensure that the exact syntax is copied and match the register names with those in the data sheet to prevent errors reported in the activity log. Give the script a unique name. For when the SftPd Down&Up routine is selected, see the following example: LOADING A SCRIPT FILE The GUI allows the user to load a sequence of register commands from a file. Within the GUI window, there are two dropdown menus under the Activity Log section where the user can select the script file and which section of the script to run. Click a dropdown menu, choose the script by name, and then click the dropdown menu again to load the selected script. The Activity log displays the register writes issued from the script. { Name: SftPd Down&Up, RegisterAccesses: [ { MemoryMap : GEPhy, RegisterName: SftPd, 21419-034 Value: 1 }, { Figure 33. Script File Loading Dropdown Menus MemoryMap : GEPhy, The script file is located in the ADIN1300 folder and is named registers_scripts.json (see Figure 34). RegisterName: SftPd, Value: 0 }, ] 21419-035 }, Figure 34. Script File Location Rev. 0 | Page 16 of 30 EVAL-ADIN1300FMCZ User Guide UG-1635 TROUBLESHOOTING Ethernet PHY software installation tips follow: Always allow the software installation to be completed, and keep in mind that the Ethernet PHY software is a two-part installation including the ADI package installer (GUI and documentation) and the FTDI drivers which can be found at www.ftdichip.com/Drivers/CDM/CDM21228_Setup.zip. The installation may require a restart of the PC. When the MDIO interface dongle is first plugged in via the USB cable, allow the new found hardware wizard to run completely. This step is required prior to starting the Ethernet PHY software. If the EVAL-ADIN1300FMCZ does not appear in the GUI window, ensure that the following steps have been competed: Power is applied to the EVAL-ADIN1300FMCZ. The powered USB connector is connected to the MDIO interface dongle. Both the EVAL-ADIN1300FMCZ and the MDIO interface dongle are connected together. The Ethernet cable is connected. The Ethernet PHY software is launched. In the example shown in Figure 35, the user is advised to reset the MDIO interface dongle through Button S6. There are two buttons on the underside of the MDIO interface dongle. In this case, the user identifies S6 and reset. This action restarts the MDIO interface dongle. If the S6 restart does not resolve communications, exit the GUI and relaunch the Ethernet PHY software. 21419-036 SOFTWARE INSTALLATION TIPS Figure 35. Example Activity Log when MDIO Interface Dongle is Not Responding HARDWARE TIPS Ensure that power is applied to the MDIO interface dongle and EVAL-ADIN1300FMCZ as previously discussed. Measure the voltage at various points on the EVAL-ADIN1300FMCZ using the DVDD, VDD0P9, 5V, AVDD3P3, and VDDIO test points. Crosscheck the voltages against the information in Table 1. No Link Established If no link is established, take the following steps to assist debug: SOFTWARE TIPS If the Ethernet PHY software does not read any data back, check for any messages in the Activity Log section. There is one known communication bug in the connection of the MDIO interface dongle and EVAL-ADIN1300FMCZ, as discussed in the following section. Ensure that the Ethernet cable is connected properly to the RJ45 connector and between the EVAL-ADIN1300FMCZ boards or PHY pairs. When using two EVAL-ADIN1300FMCZ boards, ensure that both boards are powered. Ensure that the hardware configuration is appropriate for the required linking arrangement. MDIO Interface Dongle Communications, Known Issue LED Not Illuminated, but Link Established Reported in GUI A known behavior when using the MDIO interface dongle with the EVAL-ADIN1300FMCZ is related to the sequence of how the boards are powered and connected together. If the GUI is open, and the user connects the MDIO interface dongle to the EVAL-ADIN1300FMCZ before connecting the USB power to the MDIO interface dongle, the GUI may not properly establish communications with the MDIO interface dongle. By default, LED_0 illuminates when a link is established, and flashes when there is activity. The EVAL-ADIN1300FMCZ is configured for Mode 3 and Mode 4 by default, with S1 in Position 1. If PHY_CFG0 is to be used in Mode 1 or Model 2, change the position of S1 to Position 2, as described in Table 4. The GUI polls for the MDIO interface dongle regularly, and if an error in the MDIO interface dongle communications is found, it is flagged in the Activity Log section and highlighted in red font, as shown in Figure 35. The message also includes a prompt explaining how to resolve the issue. Rev. 0 | Page 17 of 30 UG-1635 EVAL-ADIN1300FMCZ User Guide LAYOUT GUIDELINES The EVAL-ADIN1300FMCZ consists of a 4-layer PCB: the top layer, Layer 2, Layer 3, and the bottom layer. All layers have a copper pour, with an exception around sensitive traces for the MAC and MDI interfaces. Each pair must be routed together with trace widths the same throughout. Trace lengths must be kept equal where possible and any right angles on these traces must be avoided (use curves or 45 angles in the traces). Stubs must be avoided on all signal traces. It is recommended to route traces on the same layer. GROUND PLANES PLACEMENT OF THE TVS DIODE The top and bottom layers of the EVAL-ADIN1300FMCZ mainly carry signal and routing signals from the ADIN1300. The two inner layers are used for ground planes. Layer 2 is a full ground plane. Layer 3 contains primarily of ground with area dedicated to the DVDD and VDDIO power planes. Although the ADIN1300 is a mixed signal device, it only has one type of ground return, GND. It is recommended to place the TVS diode close to the ADIN1300 device to ensure minimal track inductance between the external protection and internal protection within the device. ISOLATION GUIDELINES Transformer Layout No metal layers can be directly underneath the transformer to minimize any noise coupling across the transformer. RJ45 Layout For optimal electromagnetic computability (EMC) performance, use a metal shielded RJ45 connector with the shield connected to chassis ground. There must be an isolation gap between the chassis ground and the IC GND with consistent isolation across all layers. POWER SUPPLY DECOUPLING THERMAL CONSIDERATIONS The ADIN1300 is packaged in an LFCSP package. This package is designed with an exposed paddle which must be soldered to the PCB for mechanical and thermal reasons. The exposed paddle acts to conduct heat away from the package and into the PCB. By incorporating an array of thermal vias in the PCB thermal paddle, heat is dissipated more effectively into the inner metal layers of the PCB. When designing the PCB layout for optimum thermal performance, use a 4 mm x 4 mm array of vias under the paddle. This LFCSP device includes two exposed power bars adjacent to the exposed pad at the top and bottom, highlighted in red in Figure 36. These bars are connected to internal power rails and the area around them is a keep out zone. Keep these areas clear of traces or vias. 0.15 REF From a PCB layout point of view, it is important to locate the decoupling capacitors as close as possible to the power supply and GND pins to minimize the inductance. 0.025 REF 0.30 0.25 0.20 MAC INTERFACE Traces running from the MDI_[x]_P/N pins of the ADIN1300 to the magnetics must be on the same side of the EVALADIN1300FMCZ (no vias), kept as short as possible (less than 1 inch in length), and individual trace impedance of these tracks must be kept below 50 with a differential impedance of 100 for each pair. The same recommendations apply for traces running from the magnetics to the RJ45 connector. Impedance must be kept constant throughout. Any discontinuities can impact signal integrity. PIN 1 40 30 1 10 20 0.785 0.685 0.585 11 BOTTOM VIEW 0.24 0.14 0.04 2.90 2.80 SQ 2.70 EXPOSED PAD 21 0.50 0.40 0.30 MANAGEMENT INTERFACE MDI interface 31 0.50 BSC When routing the MAC interface traces, ensure that the lengths of the pairs are matched. Avoid crossover of the signals where possible. Stubs should be avoided on all signal traces. It is recommended to route traces on the same layer. 2.87 2.77 2.67 0.475 0.375 0.275 21419-037 BOARD STACKUP Figure 36. LFCSP Simplified Package Drawing with Keep Out Area for Power Bars Highlighted (Underside) Rev. 0 | Page 18 of 30 Figure 37. PHY Schematic Rev. 0 | Page 19 of 30 C2 VDD0P9 DNI GND1 1 DNI R106 1k C63 0.01F MDI_3_P MDI_3_N C11 0.1F TVS DIODES TO BE CONNECTED IN SUCH A WAY SO THAT NO STUBS ARE CREATED ONLY ONE SET OF DIODES WILL BE CONNECTED ON THE PCB SP0504SHTG D4 MDI_2_P 1 6 I/O1I/O4 2 5 GND VCC MDI_2_N 3 I/O2 I/O3 4 SP0504SHTG MDI_1_P MDI_1_N R1 3.01k TXD_1 1 TXD_1 TXD_2 2 TXD_2 TXD_3 3 TXD_3 4 5 DVDD_0P9 GND CLK25_REF 6 CLK25_REF RSTN 7 RESET_N XTAL_O 8 XTAL_O XTAL_I 9 XTAL_I/CLK_IN/REF_CLK RSET 10 REXT D3 MDI_0_P 1 6 I/O1I/O4 2 5 GND VCC MDI_0_N 3 I/O2 I/O3 4 PLACE TEST POINT AS CLOSE TO DUT AS POSSIBLE C1 0.1F S2 1 3 2 4 PTS830 GM140 SMTR LFS PLACE CLOSE TO RESET_N PIN 0 RESET R53 0.01F PAD1 AND PAD3 SHOULD HAVE A KEEP OUT AREA AROUND THEM AND SHOULD NOT BE CONNECTED TO ANY NET AVDD3P3 CLK25 1 C41 12pF C12 DNI U1 ADIN1300 30 29 28 27 26 25 24 23 22 21 C28 0.01F RXD_2/PHYAD_2 RXD_3/PHYAD_3 DVDD_0P9 GP_CLK/RX_ER/MDIX_MODE LINK_ST/PHY_CFG1 VDDIO MDIO MDC INT_N/CRS LED_0/COL/TX_ER/PHY_CFG0 C26 0.1F GND2 1 VDDIO C20 MDIO MDC INT_N/CRS GP_CLK/RX_ER LINK_ST C30 4.7F VDD0P9 RXD_2 RXD_3 C27 1F C37 1F C38 4.7F C25 0.01F LED_0 PLACE TEST POINT AS DNI CLOSE TO DUT AS POSSIBLE C23 0.1F VDDIO VDDIO R145 1.5k C36 4.7F R107 1.5k C34 1F AVDD3P3 C22 0.01F R192 100k R193 10k 1 IN/OUT DNI R19 Y1 3 IN/OUT GND 4 2 25.000MEGHZ 1M 1 2 BC817 MODE1 AND MODE 2 MODE3 AND MODE 4 S1 LED_0 3 1 2 CS-4-12XTA 3 Q2 AVDD3P3 LED0 CONFIGURATION C21 0.1F VDD0P9 R9 10k DNI R8 10k DNI C8 GP_CLK/RX_ER DNI VDDIO DNI R27 10k RXC/RX_CLK RX_CTL/RX_DV MACIF_SEL1 MACIF_SEL0 R28 10k DNI VDDIO MAC INTERFACE CONFIGURATION RESISTORS OPTION TO DRIVE XTAL_I FROM EXTERNAL SOURCE (SMA OR FMC) NOTE 0 OHM CONNECTION TO FMC CONNECTOR ON PAGE 4 OF SCHEMATIC R13 DNI 1 R120 DNI EXT_CLK DNI 0 0 J1 C91 5 4 3 2 5-1814832-1 0.1F R15 R119 0 0 DNI R26 C7 0 DNI LED_0 1 C19 0.1F C16 0.01F VDDIO VDD0P9 INT_N 1 VDDIO XTAL_I VDDIO C10 0.1F XTAL_O PAD PAD3 PAD PAD2 PAD PAD1 VDDIO 40 TXD_0 TXD_0 39 TXC/TX_CLK TXC/TX_CLK 38 TX_CTL/TX_EN TX_CTL/TX_EN 37 DVDD_0P9 36 RX_CTL/RX_DV RX_CTL/RX_DV/CRS_DV/MACIF_SEL1 35 RXC/RX_CLK RXC/RX_CLK/MACIF_SEL0 34 RXD_0 RXD_0/PHYAD_0 33 RXD_1 RXD_1/PHYAD_1 32 VDDIO 31 AVDD_3P3 MDI_0_P MDI_0_N MDI_1_P MDI_1_N MDI_2_P MDI_2_N MDI_3_P MDI_3_N AVDD_3P3 11 12 13 14 15 16 17 18 19 20 AVDD3P3 MDI_0_P MDI_0_N MDI_1_P MDI_1_N MDI_2_P MDI_2_N MDI_3_P MDI_3_N AVDD3P3 0.01F C C42 12pF DS1 0.1F R43 A C15 390 DNI R22 10k VDDIO VDDIO S9 1 2 3 4 VDDIO S3 1 2 3 4 MODE4 R206 10k 1 2 3 4 R208 10k R34 10k R51 10k R40 10k AVDD3P3 R115 56k R114 10k PHY_CFG1_MODE3 VDDIO PHY_CFG1_MODE4 VDDIO R209 56k R104 10k R103 56k PHY_CFG0_MODE3 AVDD3P3 R117 56k R116 10k PHY_CFG0_MODE1 R118 PHY_CFG0_MODE2 10k PHY_CFG0_MODE3 PHY_CFG0_MODE4 PHY_CFG0_MODE4 AVDD3P3 NC S4 5 CS-4-14NA PHY_CFG0 6 R33 10k PHY_CFG1_MODE1 R196 0 VDDIO PHY_CFG1_MODE1 PHY_CFG1_MODE2 PHY_CFG1_MODE3 PHY_CFG1_MODE4 R39 56k PHY_CFG1_MODE2 NC 5 CS-4-14NA PHY_CFG16 DNI R195 0 R38 10k DNI DNI R37 10k VDDIO PHY SPEED CONFIGURATION RESISTORS R197 10k VDDIO R31DNI 10k RXD_0 PHY_AD0 R32 10k DNI R24 R207 56k 10k MODE2 MODE3 VDDIO MODE1 MODE2 MODE3 MODE4 MODE1 NC 5 CS-4-14NA 6 MDIX_MODE R194 0 AUTO MDIX CONFIG REGISTERS PHY_CFG0_MODE2 PHY_CFG0_MODE1 LED_0 C17 LINK_ST DNI VDDIO PHY ADDRESS CONFIGURATION RESISTORS R29 10k RXD_3 RXD_2 DNI RXD_1 PHYAD_1 PHY_AD3 PHY_AD2 R23 R30 10k 10k DNI DNI DNI GPCLK 1 LINK_ST 1 C9 EVAL-ADIN1300FMCZ User Guide UG-1635 EVALUATION BOARD SCHEMATICS AND ARTWORK 21419-038 UG-1635 EVAL-ADIN1300FMCZ User Guide 100 DIFFERENTIAL; 5 MIL TRACES, 10 MIL SPACING ( 5 / 10 / 5 ); MATCH AND MINIMIZE TRACE LENGTH TCT0 10 TCT MDI_0_N 11 TD+ T1 MCT 15 MCT0 MX+ 14 MDI_0_P 12 TD- MX- 13 100 DIFFERENTIAL; 5 MIL TRACES, 10 MIL SPACING ( 5 / 10 / 5 ); MATCH AND MINIMIZE TRACE LENGTH CON-MDI_0_N PAIR A CON-MDI_0_P H5007NL TCT1 7 TCT MDI_1_N 8 TD+ T1 MCT 18 MCT1 MX+ 17 9 TD- MDI_1_P P1 CON-MDI_1_N PAIR B MX- 16 1 2 3 4 5 6 7 8 CON-MDI_1_P H5007NL 5 TD+ T1 MCT 21 MCT2 MX+ 20 CON-MDI_2_N 6 TD- MX- 19 PAIR C CON-MDI_2_P TCT2 4 TCT MDI_2_N MDI_2_P H5007NL TCT3 1 TCT MDI_3_N 2 TD+ 3 TD- MDI_3_P T1 MCT 24 MCT3 MX+ 23 CON-MDI_3_N MX- 22 PAIR D CON-MDI_3_P 9 10 SHLD PINS 5406299-1 1 SHIELD DNI 20054 C35 TCT3 R2 75 MCT1 R3 75 0.1F TCT2 C32 0.1F MCT2 R4 75 MCT3 R5 75 C39 0.001F 21419-039 GND3 MCT0 1 TCT1 C29 0.1F 0.1F C24 TCT0 H5007NL DNI Figure 38. Magnetics Rev. 0 | Page 20 of 30 C45 0.01F DNI JP1 5 8 VOUT GND PAD 3 6 PAD BA 5V R10 100k DNI JP3 C43 4.7F DNI PLACE VIN AND VOUT CAPACITORS AS CLOSE AS POSSIBLE TO THE PINS DNI SUPPLY DNI SUPPLY ADP7105ACPZ-5.0 7 PG 4 SS 2 1 DNI U2 SENSE/ADJ EN/UVLO VIN C14 4.7F DNI C31 4.7F 3 ADP7105: 12V TO 5V LDO (MAX O/P CURRENT = 500mA) C13 4.7F DNI 12V_FPGA 1803277 1 2 DNI EXT_12V EXT_12V 1803277 1 2 EXT_5V EXT_5V C99 0.01F DNI VOLTAGE RANGE FROM 4.5V TO 5.5V P4 1A 1B 3 2 C33 0.01F DNI 2 VOUT1 = VOUT2 = VOUT2 = VOUT2 = EN1 EN2 7 VOUT1 VIN 5 VOUT2 ADJ1 ADJ2 GND PAD 3 PAD U4 ADP223ACPZ C44 4.7F AVDD3P3 = 0.5V (1 + 280k/50k) VDDIO = 3.3V = 0.5 (1 + 280k/50k) VDDIO = 2.5V = 0.5 (1 + 200k/50k) (DEFAULT) VDDIO = 1.8V = 0.5 (1 + 130k/50k) C47 4.7F 1 1 2 6 8 4 1k E1 2 C46 4.7F 1 1 2 6 8 4 EN1 EN2 7 VOUT1 VIN 5 VOUT2 ADJ1 ADJ2 GND PAD 3 PAD U5 ADP223ACPZ C51 4.7F C49 4.7F DNI ADP223: PLACE VIN AND VOUT CAPACITORS AS CLOSE AS POSSIBLE TO THE PINS 1k E2 C48 4.7F 0 R65 DNI VDDIO_P 10nH L1 R64 50k R62 280k R54 50k R57 40k R52 50k AVDD3P3 DNI 0 R68 DVDD_N DNI C40 C50 DVDD VDD0P9 DVDD_P 0 R58 DNI VDD0P9_N DVDD SUPPLY RAIL 3.3V FOR LEDS AND H/W PIN CONFIG PULL-UP/DOWN TERMINATIONS 10nH L4 10nH L11 DNI VDD0P9_P CHANGE R16 TO 280K FOR VDDIO = 3.3V CHANGE R16 TO 130K FOR VDDIO = 1.8V VDDIO DNI VDDIO_N TO MEASURE THE CURRENT POPULATE BOTH TEST POINTS AND REMOVE 0 OHM RESISTOR 0 R67 DNI AVDD3P3_N R16 200k VDDIO IS SET UP FOR 2.5V R12 50k R11 280k 10nH 1 SUPPLY L3 1 1 1 1 ADP223: PLACE VIN AND VOUT CAPACITORS AS CLOSE AS POSSIBLE TO THE PINS 1 DNI 1 PLACEHOLDERS FOR ADDITIONAL DECOUPLING ALONG THE SUPPLY TRACE 1 2 Rev. 0 | Page 21 of 30 1 Figure 39. Power Supplies 1 2 1 1 GND4 1 AVDD3P3_P EVAL-ADIN1300FMCZ User Guide UG-1635 21419-040 LED_0 RXC/RX_CLK RX_CTL/RX_DV RXD_0 RXD_1 RXD_2 RXD_3 TXC/TX_CLK TX_CTL/TX_EN TXD_0 TXD_1 TXD_2 TXD_3 3P3_FPGA R47 R46 DS4 DS5 C89 0.01F MDC MDIO R113 0 R144 DNI SSW-104-02-T-D-RA 0 P5 1 3 5 7 3 4 4 3 10nH MDIO MDC C39 C40 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C90 0.01F MDIO_FMC RESET MDC_FMC C53 VDDIO GA0 SCL SDA RXD3 C58 0.1F C57 0.1F R74 0 R72 0 TXCTL TXER DNI C4 0.1F C3 0.1F R210 0 GPCLK LINKST R211 0 R50 10 C52 12V_FPGA RXD_3 LINK_ST C56 4.7F L5 R49 0 GP_CLK/RX_ER LED_0 TX_CTL/TX_EN R80 0 DNI SW_6 R143 1k PTS830 GM140 SMTR LFS 1 2 S8 DNI SW_5 R142 1k VIO PTS830 GM140 SMTR LFS 1 2 S7 R72, R74, RESISTORS TO BE CONNECTED CLOSE TO CONNECTOR TO MINIMIZE STUB WHEN MDIO IS USED WITH THEFMC CONNECTOR LED_A 470 1. 10 SERIES TERMINATION FOR RX SIGNALS, 0 FOR TX SIGNALS 2. ALL TRACKS NEED TO BE LENGTH MATCHED AND SHOULD BE DRAWN AS 50 TRANSMISSION LINES 3. KEEP ROUTING LENGTH TO MINIMUM OUT OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN DNI 1 Rev. 0 | Page 22 of 30 1 Figure 40. FMC Connector DNI VIO PLACE SIGNALS ON AN INNER LAYER WITH GROUND ABOVE AND BELOW STICK GND VIA AROUND GROUP OF RX AND GROUP OF TX LINES 470 LED_B C P3 RXD_1 DNI DNI TXC INT_N RXD1 DNI C6 0.1F GA1 3P3_FPGA R7 0 C5 0.1F C59 0.1F 3P3 AUX R86 10 R87 0 R63 0 SW_1 TXD3 TXD1 LED_FMC R88 0 R6 0 R84 0 TXC/TX_CLK INT_N/CRS TXD_3 TXD_1 LED_0 C92 R89 10 RXC/RX_CLK DNI R150 EXT_CLK RXC 0 EXT_CLK_FMC SSW-104-02-T-D-RA 2 4 6 8 P5 ASP-134604-01 GND DP0_C2M_P DP0_C2M_N GND GND DP0_M2C_P DP0_M2C_N GND GND LA06_P LA06_N GND GND LA10_P LA10_N GND GND LA14_P LA14_N GND GND LA18_P_CC LA18_N_CC GND GND LA27_P LA27_N GND GND SCL SDA GND GND GA0 12P0V GND 12P0V GND 3P3V GND 1 A C GND5 A D38 D39 D40 D31 D32 D33 D34 D35 D36 D37 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 P3 R69 10k GA0 R70 10k GA1 C60 0.1F VIO 1 A0 2 A1 3 A2 4 GND DNI C18 0.1F 8 VCC 7 WP 6 SCL 5 SDA DNI C55 0.1F SCL SDA 3P3 AUX C61 0.1F 1 2 P3 BA JP2 3P3 AUX M20-9990345 3 R75 1k 0.1F C54 ASP-134604-01 GND CLK1_M2C_P CLK1_M2C_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND G39 VADJ G40 GND G1 G2 G3 G4 G5 G6 TXC/TX_CLK R97 TXCLK G7 0 DNI G8 G9 G10 G11 R92 TXD2 TXD_2 G12 0 G13 R90 TXD_0 TXD0 G14 0 SW_2 G15 G16 SW_3 G17 G18 MDIO_FMC G19 MDC_FMC G20 RX_CTL/RX_DV R81 RXCTL/RXDV G21 G22 10 LED_B G23 LED_A G24 G25 G26 R93 RXD2 RXD_2 G27 G28 10 G29 G30 G31 G32 SW_4 G33 G34 IO_SDA G35 SW_5 G36 G37 SW_6 G38 U7 AT24C02D-SSHM-T ASP-134604-01 PG_C2M GND GND GBTCLK0_M2C_P GBTCLK0_M2C_N GND GND LA01_P_CC LA01_N_CC GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO 3P3VAUX TMS TRST_L GA1 3P3V GND 3P3V GND 3P3V VIO INT_N/CRS LED_0 RXD_0 DNI R99 10 C62 0.1F IO_SCL 0 DNI 0 DNI R101 R95 0 R85 R213 GP_CLK/RX_ER RESET H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 RXER H20 H21 10 H22 H23 H24 H25 H26 RXD0 H27 H28 H29 H30 CON-COL H31 H32 CON-CRS H33 H34 H35 H36 H37 H38 H39 H40 P3 ASP-134604-01 VREF_A_M2C PRSNT_M2C_L GND CLK0_M2C_P CLK0_M2C_N GND LA02_P LA02_N GND LA04_P LA04_N GND LA07_P LA07_N GND LA11_P LA11_N GND LA15_P LA15_N GND LA19_P LA19_N GND LA21_P LA21_N GND LA24_P LA24_N GND LA28_P LA28_N GND LA30_P LA30_N GND LA32_P LA32_N GND VADJ 21419-041 UG-1635 EVAL-ADIN1300FMCZ User Guide C64 0.1F L7 120nH R123 100k +3.3V R121 1M "RESET" ADUCM3029 SWD +3.3V TP1 TP2 TP3 TP4 TP5 3 4 R122 4.7k P12 69157-102HLF S6 R124 100k PWRGD P9 DNI R125 1k OPTION TO HOLD IN RESET 1 2 PTS830 GM140 SMTR LFS +3.3V 2 4 13 25 C70 10F L8 C78 0.1F FT232RQ Y2 21 8 C74 0.1F IN/OUT 34 +3.3V U9 SYS_HFXTAL_OUT SYS_LFXTAL_OUT VDCDC_OUT VLDO_OUT 49 VBAT_DIG2 C82 20pF GREEN GND_ANA 64 ADuCM3029BCPZ QFN64_9X9_PAD4_5X4_5 GND_DIG 48 GND_VREFADC PAD 15 PAD 3 5 4 62 63 58 41 46 R132 57 100 ADUCM_RXD SN74LVC1G08DCKR U11 ADUCM_TXD R134 100 R136 100k +3.3V R135 100k R137 1k ADUCM_RESET 0.47F ADUCM_MDIO ADUCM_MDC ADUCM_MDIO_EN ADUCM_MOSI C84 Y C85 +3.3V 0.1F C83 0.47F VCC 1 A GND 2 B R130 100k R133 100 47 50 51 R131 +3.3V 52 100k 35 36 37 45 53 54 55 56 29 30 32 33 31 3 5 9 12 33 R129 0.1F C81 0.1F C80 Y3 3 IN/OUT C79 0.1F GND 4 2 26MEGHZ 1 C73 0.1F C72 10F C75 20pF 1 C77 8pF NON-ISOLATED USB CONNECTION 32.768KHZ 14 VBAT_ADC C69 0.1F 120nH +3.3V C71 8pF SYS_HFXTAL_IN SYS_LFXTAL_IN VREF_ADC SYS_HWRST_N C66 0.1F C76 0.1F 0.1F C67 6 VDCDC_CAP1N SPI1_CS0/GPIO25 7 VDCDC_CAP1P SPI1_MISO/GPIO24 0.1F C68 10 VDCDC_CAP2N SPI1_CLK/GPIO22 11 VDCDC_CAP2P SPI1_CS1/SYS_CLKOUT/GPIO43 16 ADC0_VIN0/GPIO35 SPI1_MOSI/GPIO23 17 ADC0_VIN1/GPIO36 SPI2_CS0/GPIO21 18 ADC0_VIN2/GPIO37 SPI2_MISO/GPIO20 19 ADC0_VIN3/GPIO38 SPI2_MOSI/GPIO19 20 ADC0_VIN4/SPI2_CS3/GPIO39 SPI2_CLK/GPIO18 21 ADC0_VIN5/SPI0_CS2/GPIO40 22 ADC0_VIN6/SPI0_CS3/GPIO41 SPT0_AD0/UART0_SOUT_EN/GPIO12 23 ADC0_VIN7/SPI2_CS2/GPIO42 SPT0_AFS/GPIO32 SPT0_ACLK/GPIO31 39 BPR0_TONE_P/SPI2_CS1/GPIO09 SPT0_ACNV/SP11_CS2/GPIO34 40 BPR0_TONE_N/GPIO08 XINT0_WAKE1/GPIO16 28 GPIO06/SWD0_CLK XINT0_WAKE0/GPIO15 27 GPIO07/SWD0_DATA XINT0_WAKE2/GPIO13 38 GPIO17/SYS_BMODE0 XINT0_WAKE3/TRM2_OUT/GPIO33 42 GPIO28 43 GPIO29 TMR1_OUT/GPIO27 TMR0_OUT/SPI1_RDY/GPIO14 24 I2C0_SDA/GPIO05 26 I2C0_SCL/GPIO04 UART0_RX/GPIO11 UART0_TX/GPIO10 44 SPI0_RDY/GPIO30 R126 59 SPI0_CS1/SYS_CLKIN/SPI1_CS3/GPIO26 SPI0_MOSI/SPT0_BFS/GPIO1 60 SPI0_CS0/SPT0_BCNV/SPI2_RDY/GPIO03 SPI0_CLK/SPT0_BCLK/GPIO0 33 61 SPI0_MISO/SPT0_BD0/GPIO2 C65 4.7F USB_5V USB_UART_DM USB_UART_DP PAD U10 R127 1 19 0 VCCIO VCC 16 18 RESET# 3V3OUT 28 26 TEST OSCO 30 27 OSCI TXD 31 2 RXD DTR# 32 3 RI# RTS# 6 DSR# 22 CBUS0 7 DCD# 21 CBUS1 8 CTS# 10 CBUS2 11 15 USBDM CBUS3 9 14 USBDP CBUS4 EP GND AGND NC 4 17 20 120nH L6 PTS830 GM140 SMTR LFS S5 1 3 2 4 "0 = DOWNLOAD MODE" "1 = BOOT FROM INT. FLASH" +3.3V G1 G2 UX60SC-MB-5S8 1 24 GND PINS 1 1 1 1 1 21 5 12 13 23 25 29 1 2 3 4 5 AC APHHS1005ZGC 33 RED +3.3V DS8 P8 DS7 C A Rev. 0 | Page 23 of 30 APHHS1005SURCK Figure 41. MDIO Interface Dongle L9 ADP124ARHZ-3.3-R7 8 7 6 5 PAD EP VIN VOUT 1 VIN VOUT 2 NC VOUT_SENSE 3 EN GND 4 U12 C88 2.2F +3.3V V_SENSE V_SENSE +3.3V 74AVC1T45GW,125 U14 V_SENSE GND 2 74AVC1T45GW,125 P7 V_SENSE TSW-104-08-T-D-RA DNI P10 C87 0.01F DNI P11 MDIO CONNECTOR IF ADUCM MDIO CONTROL ON SEPARATE BOARD GND 2 R148 VCCA VCCB 0 4 LVL_SHIFT_MDC ADUCM_MDC 3 A B 5 DIR R112 0 LVL_SHIFT_MDC LVL_SHIFT_MDIO ADUCM_RESET +3.3V +3.3V GND 2 74AVC1T45GW,125 6 1 U3 VCCA VCCB 4 ADUCM_MOSI 3 A B 5 DIR R111 0 DNI R149 82k 6 1 U13 VCCA VCCB ADUCM_MDIO 3 4 LVL_SHIFT_MDIO A B ADUCM_MDIO_EN 5 DIR +3.3V ENABLE MDC IN ONE DIRECTION (UC TO PHY) C86 2.2F RESET IS ONLY EVER DRIVEN LOW ALSO, PHY RESET PIN IS 5V TOLERANT 120nH USB_5V 21 43 65 87 VBAT_ANA1 1 VBAT_ANA2 1 VBAT_DIG1 CONNECTIONS TO MAIN PCB R128 EVAL-ADIN1300FMCZ User Guide UG-1635 21419-042 EVAL-ADIN1300FMCZ User Guide 21419-043 UG-1635 21419-044 Figure 42. Schematic Silkscreen, Top Figure 43. Schematic Silkscreen, Bottom Rev. 0 | Page 24 of 30 UG-1635 21419-045 EVAL-ADIN1300FMCZ User Guide 21419-046 Figure 44. Top Layer Figure 45. Layer 2, Ground Layer Rev. 0 | Page 25 of 30 EVAL-ADIN1300FMCZ User Guide 21419-047 UG-1635 21419-048 Figure 46. Layer 3, Power and Ground Layer Figure 47. Bottom Layer Rev. 0 | Page 26 of 30 EVAL-ADIN1300FMCZ User Guide UG-1635 ORDERING INFORMATION BILL OF MATERIALS Table 7. Qty 16 4 Reference Designator C1, C10, C11, C15, C19, C21, C23, C26, C54, C55, C57 to C62 C2, C9, C12, C16, C20, C22, C25, C28, C40, C50, C52, C53, C63, C87, C89, C90 C13, C14, C30, C31, C36, C38, C56 C24, C29, C32, C35 3 C27, C34, C37 1 C39 2 C41, C42 6 C44, C46 to C49, C51 13 1 C64, C66 to C69, C73, C74, C76, C78 to C81, C85 C65 2 C70, C72 2 C71, C77 2 C75, C82 2 C83, C84 2 C86, C88 2 D3, D4 3 1 DS1, DS4, DS5 DS7 Ceramic capacitors, 4.7 F, 25 V, 10%, 1206, X7R Ceramic capacitors, 0.1 F, 50 V, 10%, 0402, X7R Ceramic capacitors, 1 F, 100 V, 10%, 0805, X7S Ceramic capacitor, 0.001 F, 3000 V, 10%, 1812, X7R Ceramic capacitors, 12 pF, 50 V, 1%, 0402, NP0(C0G) Ceramic capacitors, 4.7 F, 10 V, 10%, 0603, X6S Ceramic capacitors, 0.1 F, 50 V, 10%, 0402, X7R Ceramic capacitor, 4.7 F, 50 V, 10%, 0805, X7R Ceramic capacitors, 10 F, 25 V, 10%, 0805, X5R Ceramic capacitors, 8 pF, 16 V, 0.5 pF, 0402, C0G Ceramic capacitors, 20 pF, 16 V, 5%, 0402, C0G Ceramic capacitors, 0.47 F, 35 V, 10%, 0603, X7R Ceramic capacitors,2.2 F, 50 V, 10%, 0805, X7R 6 V, SOT23_6, TVS diode arrays, low capacitor ESD protection 1.7 V, 0805, LEDs, red, clear, 660 nm 2.1 V, 0402, LED, orange, 610 nm 1 DS8 0402, LED, red 2 1 E1, E2 EXT_5V 2 JP2, JP3 5 L1, L3, L4, L5, L11 4 L6 to L9 1 k at 100MHz, L0805, ferrite bead, 0805 PCB connector header, CNHDRRA1X2H285, 3.81 mm PCB connectors, 3-position, male, header, unshrouded, single-row, 2.54 mm pitch 10 nH, 2%, 0603, inductors, high frequency wirewound 120 nH, 25%, 0805, inductors 1 P1 16 5 Description Ceramic capacitors, 0.1 F, 16 V, 10%, 0402, X7R Ceramic capacitors, 0.01 F, 25 V, 10%, 0402, X7R Manufacturer American Technical Ceramics TDK C1005X7R1E103K050EB KEMET C1206C475K3RACTU TDK C1005X7R1H104K050BE TDK C2012X7S2A105K KEMET C1812C102KHRACTU Murata GJM1555C1H120FB01D Murata GRM185C81A475KE11D TDK CGA2B3X7R1H104K050BB Murata GRM21BZ71H475KE15L TDK C2012X5R1E106K085AC AVX Corporation 0402YA8R0DAT2A AVX Corporation 0402YA200JAT2A Taiyo Yuden GMK107B7474KAHT Taiyo Yuden UMK212BB7225KG-T Littelfuse, Inc. SP0504SHTG Lumex Inc. Kingbright Electronic Kingbright Electronic Taiyo Yuden Phoenix Contact SML-LX0805SRC-TR APHHS1005SECK BK2125HS102-T 1803277 Harwin M20-9990345 Murata Manufacturing Murata Manufacturing TE Connectivity LQW18AN10NG10D PCB connector, modular jack assembly, single-port, shielded, RJ45 Rev. 0 | Page 27 of 30 Part Number 530L104KT16T APHHS1005SURCK BLM21BB750SN1B 5406299-1 UG-1635 Qty 1 Reference Designator P12 1 P3 1 P4 1 P5 1 1 1 P7 P8 Q2 1 1 6 2 3 1 3 1 1 1 1 4 1 2 1 6 1 1 R1 R10 R39, R103, 115, R117, R207, R209 R24, R33, R34, R40, R51, R69, R70, R71, R73, R104, R114, R116, R118, R197, R206, R208 R75 to R79, R106, R142, R143 R107, R145 R11, R62 R6, R15, R26, R53, R58, R63, R65, R67, R68, R80, R84, R87, R88, R90, R92, R112, R119, R148, R150, R191, R194, R195, R196, R210 to R213 R72, R74, R113, R144 R12, R52, R54, R64 R121 R122 R123, R124, R130, R131, R135, R136 R125, R137 R126, R128, R129 R127 R132 to R134 R149 R16 R192 R193 R2 to R5 R43 R46, R47 R48 R50, R81, R86, R89, R93, R99 R57 S1 5 S2, S5 to S8 16 8 2 2 27 4 4 1 1 6 EVAL-ADIN1300FMCZ User Guide Description PCB connector, straight, male, 2-pin header PCB connector, single-ended array, male, 160-position, FMC PCB connector, CNCUI-PJ-002A_A, power jack PCB connector, 8-position, socket strip, double-row, right angled, 2.54 mm pitch PCB connector, right angled, male header PCB connector, female, mini USB 2.0 45 V, SOT23-M3, NPN transistor Manufacturer Amphenol FCI Part Number 69157-102HLF Samtec ASP-134604-01 CUI PJ-002AH-SMT-TR Samtec SSW-104-02-T-D-RA TSW-104-08-T-D-RA UX60SC-MB-5S8 BC817 Resistor, 3.01 k, 1%, R0402 Resistor, 100 k, 1%, 0603, Resistors, 56 k, 1%, 0603 Samtec Hirose Electric NXP Semiconductors Panasonic Bourns Multicomp (SPC) Resistors, 10 k, 1%, 0603 Multicomp (SPC) MC0063W0603110K Resistors, 1 k, 1%, 0603 Resistors, 1.5 k, 50 V, 1%, 0603, Resistors, 280 k, 0.1%, 0603 Resistors, 0 , 50 V, 1%, 0402 Multicomp (SPC) Multicomp (SPC) Panasonic Multicomp (SPC) MC0063W060311K MC 0.063W 0603 1% 1K5 ERA-3AEB2803V MC00625W040210R Resistors, 0 , 1%, 0603 Resistors, 50 k, 0.1%, 0603 Resistor, 1 M, 1%, 0201 Resistor, 4.7 k, 25 V, 1%, 0201 Resistors, 100 k, 1%, 0201 Multicomp (SPC) Vishay Panasonic Multicomp (SPC) Panasonic MC0603WG00000T5E-TC PNM0603E5002BST5 ERJ-1GNF1004C MC0201L6F4701SE ERJ-1GNF1003C Resistors, 1 k, 1%, 0201 Resistors, 33 , 1%, 0201 Resistor, 0 , 5%, 0201 Resistors, 100 , 1%, 0201 Resistor, 82 k, 1%, 0603, Resistor, 200 k, 1%, 0603 Resistor, 100 k, 1%, 0603 Resistor, 10 k, 1%, 0402 Resistors, 75 , 1%, 0603 Resistor, 390 , 5%, 0402 Resistors, 470 , 1%, 0402 Resistor, 0 , 500 V, 2512 Resistors, 10 , 1%, 0402 Resistor, 40 K, 0.1%, 0603 Switch, 4-position, surface mount, SM_DIP8-2 Switches, tactile, microminiature top actuated, single-pole, single throw, normally open (SPST-NO) Panasonic Panasonic Bourns Panasonic Multicomp (SPC) Panasonic Yageo Panasonic Panasonic Panasonic Yageo Vishay Multicomp (SPC) Vishay CTS ERJ-1GNF1001C ERJ-1GNF33R0C CR0201-J/-000GLF ERJ-1GNF1000C MC 0.063W 0603 1% 82K. ERJ-3EKF2003V RC0603JR-07100KL ERJ-2RKF1002X ERJ-3EKF75R0V ERJ-2GEJ391X RC0402FR-07470RL CRCW25120000Z0EG MC00625W0402110R PAT0603E4002BST1 219-4MST C&K PTS830 GM140 SMTR LFS Rev. 0 | Page 28 of 30 ERJ-2RKF3011X CR0603-FX-1003ELF MC 0.063W 0603 1% 56K. EVAL-ADIN1300FMCZ User Guide Qty 3 Reference Designator S3, S4, S9 1 T1 1 U1 1 1 1 U10 U11 U12 3 U3, U13, U14 2 U4, U5 1 1 1 U7 U8 U9 1 Y1 1 Y2 1 Y3 UG-1635 Description 16 V, single-pole, 4 throw, rotary switches, SP4T Transformer 1000BASE-T magnetic modules IC robust, low latency gigabit Ethernet PHY IC USB serial UART IC-TTL single-positive and gate, SC70-5 3.3 V complementary metal-oxide semiconductor (CMOS) linear regulator with low quiescent current IC-TTL dual supply transceivers, 3-state Dual 300mA adjustable output, low noise, high power supply rejection ratio (PSRR) voltage regulators I2C compatible serial EEPROM 2-kBit CMOS I2C serial EEPROM, 32-kBit. Ultralow power ARM(R) Cortex(R)-M3 Micro-controller with integrated power management and 256 kB of embedded flash memory 25 MHz, 10 ppm, crystal, 10 pF load capacitor Manufacturer NIDEC COPAL Electronics Pulse Electronics Part Number CS-4-14NA Analog Devices ADIN1300 FTDI CHIP Texas Instruments Analog Devices FT232RQ SN74LVC1G08DCKR ADP124ARHZ-3.3-R7 NXP Semiconductors Analog Devices 74AVC1T45GW,125 ATMEL ONSEMI Analog Devices AT24C02D-SSHM-T CAT24C32WI-GT3 ADUCM3029BCPZ Seiko Epson H5007NL ADP223ACPZ-R7 32.768 kHz, 20 ppm, crystal, 6 pF load capacitor 26 MHz, 30 ppm, crystal, 10 pF load capacitor Abracon Corp. FA128_25.000000MHZ_10.0 _+10-10 ABS07-120-32.768KHZ-T ECS, INC. ECS-260-10-36Q-ES-TR Description Test point, DNI Supplier Keystone Electronics Part Number 1405-2 Ceramic capacitors, 0.01 F, 25 V, 10%, 0402, X7R PCB connector header, 3.81 mm PCB connector, straight SMA Resistors, 0 , 50 V, 1%, 0402 TDK C1005X7R1E103K050EB Phoenix Contact TE Connectivity LTD Multicomp (SPC) 1803277 5-1814832-1 MC00625W040210R Resistors, 0 , R0805 Resistor, 1 M, 1%, 0402 Resistors, 10 k, 1%, 0603 Multicomp (SPC) Panasonic Multicomp (SPC) MC 0.1W 0805 0R ERJ-2RKF1004X MC0063W0603110K Resistor 10 , 1%, R0402 Multicomp (SPC) MC00625W0402110R Table 8. Not Populated Qty 26 3 1 1 7 4 1 12 1 Reference Designator 5V, AVDD3P3_N, AVDD3P3_P, CLK25, DVDD_N, DVDD_P, GND1, GND2, GND3, GND4, GND5, GPCLK, INT_N, LED_0, LINK_ST, MDC, MDIO, P9, P10, P11, SUPPLY, VDD0P9_N, VDD0P9_P, VDDIO_N, VDDIO_P, XTAL_I C33, C45, C99 EXT_12V J1 R49, R95, R97, R101, R110, R111, R120 R138 to R141 R19 R8, R9, R22, R23, R27 to R32, R37, R38 R85 Rev. 0 | Page 29 of 30 UG-1635 Qty 1 Reference Designator U2 1 C43 2 C13, C14 1 JP1 1 SHIELD EVAL-ADIN1300FMCZ User Guide Description 500 mA, low noise low dropout (LDO) regulator with soft start Ceramic capacitors, 4.7 F, 10 V, 10%, 0603, X6S Ceramic capacitors, 4.7 F, 25 V, 10 %, 1206, X7R PCB connector, jumper, straight, male, 2-pin, 2.54 mm pitch PCB connector, 4 mm socket Supplier Analog Devices Part Number ADP7105ACPZ-5.0-R7 Murata GRM185C81A475KE11D KEMET C1206C475K3RACTU Amphenol FCI 69157-102HLF Rapid 20054 I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the "Evaluation Board"), you are agreeing to be bound by the terms and conditions set forth below ("Agreement") unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you ("Customer") and Analog Devices, Inc. ("ADI"), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term "Third Party" includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED "AS IS" AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER'S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI'S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. (c)2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG21419-0-10/19(0) Rev. 0 | Page 30 of 30