To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas
Electronics products or the technology described in this document for any purpose relating to military applications or use by
the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and
technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and
“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as
indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular
application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior
written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way
liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an
application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written
consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-
crime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with
applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
1994, 1996
DATA SHEET
MOS INTEGRATED CIRCUIT
Description
The
µ
PD485505 is a 5,048 words by 8 bits high speed FIFO (First In First Out) line buffer. Its CMOS static circuitry
provides high speed access and low power consumption.
The
µ
PD485505 can be used for one line delay and time axis conversion in high speed facsimile machines and
digital copiers.
Moreover, the
µ
PD485505 can execute read and write operations independently on an asynchronous basis. Thus
the
µ
PD485505 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for
the synchronization of multiple input signals. There are three versions, E, K, P, and L. This data sheet can be applied
to the version P and L. These versions operate with different specifications. Each version is identified with its lot
number (refer to 7. Example of Stamping).
Features
•5,048 words by 8 bits
•Asynchronous read/write operations available
•Variable length delay bits; 21 to 5,048 bits (Cycle time: 25 ns)
15 to 5,048 bits (Cycle time: 35 ns)
•Power supply voltage VCC = 5.0 V ± 0.5 V
•Suitable for sampling one line of A3 size paper (16 dots/mm)
•All input/output TTL compatible
•3-state output
•Full static operation; data hold time = infinity
Ordering Information
Part Number R/W Cycle Time Package
µ
PD485505G-25 25 ns 24-pin PLASTIC SOP
µ
PD485505G-35 35 ns (11.43 mm (450))
µ
PD485505G-25-A 25 ns
µ
PD485505G-35-A 35 ns
Remark Products with -A at the end of the part number are lead-free products.
µ
PD485505
LINE BUFFER
5K-WORD BY 8-BIT
Document No. M10059EJ8V0DS00 (8th edition)
Date Published March 2006 N CP(K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
<R>
<R>
<R>
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
µ
PD485505
2Data Sheet M10059EJ8V0DS
Pin Configuration (Marking side)
24-pin PLASTIC SOP (11.43 mm (450))
[
µ
PD485505G]
[
µ
PD485505G-A]
DOUT0
DOUT1
DOUT2
DOUT3
RE
RSTR
GND
RCK
DOUT4
DOUT5
DOUT6
DOUT7
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIN0
DIN1
DIN2
DIN3
WE
RSTW
VCC
WCK
DIN4
DIN5
DIN6
DIN7
DIN0 - DIN7 : Data Inputs
DOUT0 - DOUT7 : Data Outputs
WCK : Write Clock Input
RCK : Read Clock Input
WE : Write Enable Input
RE : Read Enable Input
RSTW : Reset Write Input
RSTR : Reset Read Input
VCC : +5.0 V Power Supply
GND : Ground
Remark Refer to 5. Package Drawing for the 1-pin index mark.
<R>
µ
PD485505
3
Data Sheet M10059EJ8V0DS
Block Diagram
D
IN0
D
IN1
D
IN2
D
IN3
D
IN4
D
IN5
D
IN6
D
IN7
WE
RSTR
WCK
D
OUT0
D
OUT1
D
OUT2
D
OUT3
D
OUT4
D
OUT5
D
OUT6
D
OUT7
RCK
RSTW
RE
V
CC
GND
Write Address Pointer
Read Address Pointer
Input Buffer
Output Buffer
Memory Cell Array
40,384 bits
(5,048 words by 8 bits)
µ
PD485505
4Data Sheet M10059EJ8V0DS
1. Input/Output Pin Function
Pin
Pin Symbol Pin
Number Name
24 - 21 DIN0 Data
|Input
16 - 13 DIN7
1 - 4 DOUT0 Data
|Output
9 - 12 DOUT7
19 RSTW Reset
Write
Input
6RSTR Reset
Read
Input
20 WE Write
Enable
Input
5RERead
Enable
Input
17 WCK Write
Clock
Input
8RCK Read
Clock
Input
I/O Function
In Write data input pins.
The data inputs are strobed by the rising edge of WCK at the end of a cycle
and the setup and hold times (tDS, tDH) are defined at this point.
Out Read data output pins.
The access time is regulated from the rising edge of RCK at the beginning of a
cycle and defined by tAC.
In Reset input pin for the initialization of the write address pointer.
The state of RSTW is strobed by the rising edge of WCK at the beginning of a
cycle and the setup and hold times (tRS, tRH) are defined.
In Reset input pin for the initialization of the read address pointer.
The state of RSTR is strobed by the rising edge of RCK at the beginning of a
cycle and the setup and hold times (tRS, tRH) are defined.
In Write operation control signal input pin.
When WE is in the disable mode (“H” level), the internal write operation is
inhibited and the write address pointer stops at the current position.
In Read operation control signal input pin.
When RE is in the disable mode (“H” level), the internal read operation is
inhibited and the read address pointer stops at the current position. The output
changes to high impedance.
In Write clock input pin.
When WE is enabled (“L” level), the write operation is executed in
synchronization with the write clock. The write address pointer is incremented
simultaneously.
In Read clock input pin.
When RE is enabled (“L” level), the read operation is executed in synchroniza-
tion with the read clock. The read address pointer is incremented
simultaneously.
µ
PD485505
5
Data Sheet M10059EJ8V0DS
2. Operation Mode
µ
PD485505 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK).
For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK).
2.1 Write Cycle
When the WE input is enabled (“L” level), a write cycle is executed in synchronization with the WCK clock
input.
The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after a one-
line (5,048 bits) delay and write data can be processed with the same clock. Refer to Write Cycle Timing Chart.
When WE is disabled (“H” level) in a write cycle, the write operation is not performed during the cycle which
the WCK rising edge is in the WE = “H” level (tWEW). The WCK does not increment the write address pointer
at this time.
Unless inhibited by WE, the internal write address will automatically wrap around from 5,047 to 0 and begin
incrementing again.
2.2 Read Cycle
When the RE input is enabled (“L” level), a read cycle is executed in synchronization with the RCK clock input
and data is output after tAC. Refer to Read Cycle Timing Chart.
When RE is disabled (“H” level) in a read cycle, the read operation is not performed during the cycle which
the RCK rising edge is in the RE = “H” level (tREW). The RCK does not increment the read address pointer at
this time.
2.3 Write Reset Cycle/Read Reset Cycle
After power up, the
µ
PD485505 requires the initialization of internal circuits because the read and write
address pointers are not defined at that time.
It is necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and
RCK, and then input the RSTW and RSTR signals to initialize the circuit.
Write and read reset cycles can be executed at any time and the address pointer returns zero. Refer to Write
Reset Cycle Timing Chart, Read Reset Cycle Timing Chart.
Remark Write and read reset cycles can be executed at any time and do not depend on the state of RE or WE.
µ
PD485505
6Data Sheet M10059EJ8V0DS
Operation-related Restriction
Following restriction exists to read data written in a write cycle.
Read the written data after an elapse of 1/2 write cycle + tWAR since the write cycle ends (see Figure 2.1).
If tWAR is not satisfied, the output data may undefined.
Figure 2.1 Delay Bits Restriction Timing Chart
Remark This timing chart describes only the delay bits restriction, and does not defines the WE, RE, RSTW, RSTR
signals.
0123
012
0123
0123
WCK
RCK
D
IN
D
OUT
1/2 write cycle
t
WAR
t
AC
High
impedance
High impedance
µ
PD485505
7
Data Sheet M10059EJ8V0DS
3. Electrical Specifications
All voltages are referenced to GND.
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Voltage on any pin relative to GND VT–0.5Note to VCC + 0.5 V
Supply voltage VCC –0.5 to +7.0 V
Output current IO20 mA
Operating ambient temperature TA0 to 70 ˚C
Storage temperature Tstg –55 to +125 ˚C
Note –3.0 V MIN. (Pulse width = 10 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply voltage VCC 4.5 5.0 5.5 V
High level input voltage VIH 2.4
VCC + 0.5
V
Low level input voltage VIL –0.3Note +0.8 V
Operating ambient temperature
TA070˚C
Note –3.0 V MIN. (Pulse width = 10 ns)
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test Condition MIN. TYP. MAX. Unit
Operating current ICC 80 mA
Input leakage current IIVI = 0 to VCC, Other Input 0 V –10 +10
µ
A
Output leakage current IOVO = 0 to VCC,–10 +10
µ
A
DOUT: High impedance
High level output voltage VOH IOH = –1 mA 2.4 V
Low level output voltage VOL IOL = 2 mA 0.4 V
Capacitance (TA = 25 ˚C, f = 1 MHz)
Parameter Symbol Test Condition MIN. TYP. MAX. Unit
Input capacitance CI10 pF
Output capacitance CO10 pF
µ
PD485505
8Data Sheet M10059EJ8V0DS
AC Characteristics (Recommended Operating Conditions unless otherwise noted)Notes 1, 2, 3
Parameter Symbol
µ
PD485505-25
µ
PD485505-35 Unit Notes
MIN. MAX. MIN. MAX.
Write clock cycle time tWCK 25 35 ns
Write clock pulse width tWCW 11 12 ns
Write clock precharge time tWCP 11 12 ns
Read clock cycle time tRCK 25 35 ns
Read clock pulse width tRCW 11 12 ns
Read clock precharge time tRCP 11 12 ns
Access time tAC 18 25 ns
Write data-read delay time tWAR 470 470 ns
Output hold time tOH 55ns
Output low-impedance time tLZ 518525ns4
Output high-impedance time tHZ 518525ns4
Input data setup time tDS 710ns
Input data hold time tDH 33ns
RSTW/RSTR Setup time tRS 710ns5
RSTW/RSTR Hold time tRH 33ns5
RSTW/RSTR Deselected time (1) tRN1 33ns6
RSTW/RSTR Deselected time (2) tRN2 710ns6
WE Setup time tWES 710ns7
WE Hold time tWEH 33ns7
WE Deselected time (1) tWEN1 33ns8
WE Deselected time (2) tWEN2 710ns8
RE Setup time tRES 710ns9
RE Hold time tREH 33ns9
RE Deselected time (1) tREN1 33ns10
RE Deselected time (2) tREN2 710ns10
WE Disable time tWEW 00ms
RE Disable time tREW 00ms
Write reset time tRSTW 00ms
Read reset time tRSTR 00ms
Transition time tT335335ns
µ
PD485505
9
Data Sheet M10059EJ8V0DS
Notes 1. AC measurements assume tT = 5 ns.
2. AC Characteristics test condition
Input Timing Specification
Output Timing Specification
Output Loads for Timing
3. Input timing reference levels = 1.5 V. Output timing reference levels; VOH = 2.0 V, VOL = 0.8 V.
4. tLZ and tHZ are measured at ±200 mV from the steady state voltage. Under any conditions, tLZ ≥ tHZ.
5. If either tRS or tRH is less than the specified value, reset operations are not guaranteed.
6. If either tRN1 or tRN2 is less than the specified value, reset operations may extend to cycles preceding or
following the period of reset operations.
7. If either tWES or tWEH is less than the specified value, write disable operations are not guaranteed.
8. If either tWEN1 or tWEN2 is less than the specified value, internal write disable operations may extend to cycles
preceding or following the period of write disable operations.
9. If either tRES or tREH is less than the specified value, read disable operations are not guaranteed.
10. If either tREN1 or tREN2 is less than the specified value, internal read disable operations may extend to cycles
preceding or following the period of read disable operations.
1.8 kΩ
1.1 kΩ
D
OUT
V
CC
5 pF
(t
LZ
, t
HZ
)
1.8 kΩ
1.1 kΩ
D
OUT
V
CC
30 pF
(t
AC
, t
OH
)
3.0 V
0 V
tT = 5 ns tT = 5 ns
1.5 V Test points
0.8 V
2.0 V
High impedance High impedance
Test points
µ
PD485505
10 Data Sheet M10059EJ8V0DS
Write Cycle Timing Chart
Cycle n Cycle n+1 Cycle n+2 Disable Cycle Cycle n+3
t
WCW
t
WEN1
t
WES
t
WEW
t
WEH
t
WEN2
t
WCP
t
WCK
t
DS
t
DH
(n+1)
(n)
t
DS
t
DH
(n+2) (n+3)
WCK (Input)
WE (Input)
D
IN
(Input)
Remark RSTW = “H” level
Read Cycle Timing Chart
Cycle n Cycle n+1 Cycle n+2 Disable Cycle Cycle n+3
tRCW tREN1 tRES
tREW
tREH tREN2
tRCP
tRCK
(n+1)
(n)
tAC
tOH
(n+2) (n+3)
tHZ tLZ
tAC
tLZ
High impedance
RCK (Input)
RE (Input)
DOUT (Output) High impedance
Remark RSTR = “H” level
µ
PD485505
11
Data Sheet M10059EJ8V0DS
Write Reset Cycle Timing Chart (WE = Active)
Cycle n Reset Cycle Cycle 0 Cycle 1
tRN2tRHtRSTW Note
tRStRN1
“L” Level
tDS tDH tDS tDH
(1)(0)(n)
(n–1)
DIN (Input)
WE (Input)
RSTW (Input)
WCK (Input)
Note In write reset cycle, reset operation is executed even without a reset cycle (tRSTW).
WCK can be input any number of times in a reset cycle.
Write Reset Cycle Timing Chart (WE = Inactive)
Cycle n Disable Cycle Cycle 0
tRN2
tRH
tRSTW
Note
tRS
tRN1
tDS tDH tDS
(0)
(n)
(n–1)
DIN (Input)
WE (Input)
RSTW (Input)
WCK (Input)
Reset Cycle
tWEW
tWEN1 tWES tWEH tWEN2
Note In write reset cycle, reset operation is executed even without a reset cycle (tRSTW).
WCK can be input any number of times in a reset cycle.
µ
PD485505
12 Data Sheet M10059EJ8V0DS
Read Reset Cycle Timing Chart (RE = Active)
Cycle n Reset Cycle Cycle 0 Cycle 1
t
RN2
t
RH
t
RSTR
Note
t
RS
t
RN1
“L” Level
t
AC
t
OH
t
AC
t
OH
(1)
(0)
(n)
(n–1)
D
OUT
(Output)
RE (Input)
RSTR (Input)
RCK (Input)
t
OH
t
AC
t
AC
(0)
Note In read reset cycle, reset operation is executed even without a reset cycle (tRSTR).
RCK can be input any number of times in a reset cycle.
Read Reset Cycle Timing Chart (RE = Inactive)
Cycle n Disable Cycle Cycle 0
tRN2
tRH
tRSTR Note
tRS
tRN1
tHZ tAC
(0)
(n)
(n–1)
DOUT (Output)
RE (Input)
RSTR (Input)
RCK (Input)
tLZ
tREH
tAC
Reset Cycle
tREN1 tRES
tREW
tREN2
High impedance
tOH tOH
Note In read reset cycle, reset operation is executed even without a reset cycle (tRSTR).
RCK can be input any number of times in a reset cycle.
µ
PD485505
13
Data Sheet M10059EJ8V0DS
4. Application
4.1 1 H Delay Line
µ
PD485505 easily allows a 1 H (5,048 bits) delay line (see Figure 4.1).
Figure 4.1 1 H Delay Line Circuit
WCK
D
IN
WE
RSTW
RCK
D
OUT
RE
RSTR
40 MHz Clock Reset
Data OutputData Input
8 8
Figure 4.2 1 H Delay Line Timing Chart
t
WCK
t
RCK
Cycle 0 Cycle 1 Cycle 2
1 H
(5,048 Cycles)
Cycle 5,047
Cycle 0’
2 H
(5,048 Cycles)
t
WCW
t
RCW
t
WCP
t
RCP
t
RS
t
RH
t
DH
t
DS
(0) (1) (2)
(5,046) (5,047)
(0’) (1’)
t
DH
t
OH
t
AC
(0) (1)
(2’) (3’)
(2) (3)
WCK/RCK
(Input)
RSTW /
RSTR
(Input)
D
IN
(Input)
D
OUT
(Output)
t
DS
Cycle 1’ Cycle 2’ Cycle 3’
Write
Cycle 0
Read Cycle 1 Cycle 2 Cycle 3
Remark RE, WE = “L” level
µ
PD485505
14 Data Sheet M10059EJ8V0DS
4.2 n Bit Delay
It is possible to make delay read from the write data with the
µ
PD485505.
(1) Perform a reset operation in the cycle proportionate to the delay length. (Figure 4.3)
(2) Shift the input timing of write reset (RSTW) and read reset (RSTR) depending on the delay length. (Figure 4.4)
(3) Shift the address by disabling RE for the period proportionate to the delay length. (Figure 4.5)
n bit: Delay bits from write cycle to read cycle correspond to a same address cell.
Restrictions
Delay bits n can be set from minimum bits to maximum bits depending on the operating cycle time. Refer
to 2. Operation Mode Operation-related Restriction.
Cycle time MIN. MAX.
25 ns 21 bits 5,048 bits
35 ns 15 bits 5,048 bits
Figure 4.3 n-Bit Delay Line Timing Chart (1)
tWCK
tRCK
Cycle 0 Cycle 1 Cycle 2
1 H
(n Cycles)
Cycle n–1
2 H
(n Cycles)
tWCW
tRCW
tWCP
tRCP
tRS
tRH
tDH
tDS
(0) (1) (n–2) (n–1) (0’) (1’)
tDS
tDH
tOHtAC
(0) (1)
(2’) (3’)
(2) (3)
WCK/RCK
(Input)
DIN
(Input)
DOUT
(Output)
tRS
tRH
(2)
RSTW /
RSTR
(Input)
Cycle 0’
Write
Cycle 0
Read
Cycle 1’
Cycle 1
Cycle 2’
Cycle 2
Cycle 3’
Cycle 3
tWAR
Remark RE, WE = “L” level
µ
PD485505
15
Data Sheet M10059EJ8V0DS
Figure 4.4 n-Bit Delay Line Timing Chart (2)
t
WCK
t
RCK
Cycle 0 Cycle 1 Cycle 2 Cycle n–1
t
WCW
t
RCW
t
WCP
t
RCP
t
RS
t
RH
t
DH
t
DS
(0) (1) (2) (n–2) (n–1) (n) (n+1)
t
DS
t
DH
t
OH
t
AC
(0) (1)
(n+2) (n+3)
(2) (3)
WCK/RCK
(Input)
RSTW
(Input)
D
IN
(Input)
D
OUT
(Output)
Cycle n+1 Cycle n+2 Cycle n+3
t
RH
t
RS
n Cycles
RSTR
(Input)
Cycle n
Write
Cycle 0
Read Cycle 1 Cycle 2 Cycle 3
t
WAR
Remark RE, WE = “L” level
Figure 4.5 n-Bit Delay Line Timing Chart (3)
t
WCK
t
RCK
Cycle 0 Cycle 1 Cycle 2 Cycle n–1
t
WCW
t
RCW
t
WCP
t
RCP
t
RS
t
RH
t
DH
t
DS
(0) (1) (2) (n–2) (n–1) (n) (n+1)
t
DS
t
DH
t
OH
t
AC
(0) (1)
(n+2) (n+3)
(2) (3)
WCK/RCK
(Input)
RSTW/
RSTR
(Input)
D
IN
(Input)
D
OUT
(Output)
Cycle n+1 Cycle n+2 Cycle n+3
t
REH
n Cycles
RE
(Input)
t
REN2
Cycle n
Write
Cycle 0
Read Cycle 1 Cycle 2 Cycle 3
t
WAR
High impedance
Remark WE = “L” level
µ
PD485505
16 Data Sheet M10059EJ8V0DS
4.3 Double-speed Conversion
Figure 4.6 shows an example timing chart of double-speed and twice reading operation (fR = 2fW, 5,048 by
2 cycle) for a write operation (fW = 5,048 cycle).
Caution The read operation collide with the write operation on the same line, last n bits output data
(5,048–n to 5,048) in the first read operation will be undefined (see Figure 4.6 Double-speed
Conversion Timing Chart).
Undefined bits mentioned above depend on the cycle time.
Read cycle time Undefined bits
25 ns 21 bits
35 ns 15 bits
Figure 4.6 Double-speed Conversion Timing Chart
Remark RE, WE = “L” level
1H
(5,048 Cycle)
2H
(5,048 Cycle)
012 5046 5047 0' 1' 2' 5046' 5047' 0"
012 5046 5047 0' 1' 2'
5046' 5047'
0"
1H
(5,048 Cycle)
First read cycle
1H
(5,048 Cycle)
Second read cycle
2H
(5,048 Cycle)
First read cycle
n bits output data will be undefined. n bits output data will be undefined.
012
5046 5047
012
5046 5047
0' 1' 2'
5046' 5047'
0' 1'
tAC
WCK
(Input)
RSTW
(Input)
D
IN
(Input)
RCK
(Input)
RSTR
(Input)
D
OUT
(Output)
µ
PD485505
17
Data Sheet M10059EJ8V0DS
5. Package Drawing
24 13
112
K
F
G
P
detail of lead end
M
S
A
J
H
I
L
E
C
DM
BSN
ITEM
B
C
H
24-PIN PLASTIC SOP (11.43 mm (450))
A
J
D
E
F
G
I
K
L
MILLIMETERS
1.27 (T.P.)
1.27 MAX.
12.2±0.3
15.5±0.2
1.9±0.2
0.42±0.08
0.1±0.1
2.0
2.1±0.2
8.4±0.2
0.17+0.08
−0.07
0.9±0.2
0.12
M
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
N0.10
5°±5°
P
P24GM-50-450A-4
µ
PD485505
18 Data Sheet M10059EJ8V0DS
6. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
µ
PD485505.
Type of Surface Mount Device
µ
PD485505G : 24-pin PLASTIC SOP (11.43 mm (450))
µ
PD485505G-A: 24-pin PLASTIC SOP (11.43 mm (450))
7. Example of Stamping
Letter E in the fifth character position in a lot number signifies version E, letter K, version K, letter P, version
P, and letter L, version L.
JAPAN
D485505
Lot number
<R>
µ
PD485505
19
Data Sheet M10059EJ8V0DS
Revision History
Edition/ Page Type of Location Description
Data This Previous revision (Previous edition → This edition)
edition edition
8th edition/ p.1 p.1 Addition Ordering Information Lead-free products have been added
Mar. 2006 p.2 p.2 Addition Pin Configuration Lead-free products have been added
p.18 p.18 Addition Recommended Soldering Lead-free products have been added
Conditions
µ
PD485505
20 Data Sheet M10059EJ8V0DS
[MEMO]
µ
PD485505
21
Data Sheet M10059EJ8V0DS
[MEMO]
µ
PD485505
22 Data Sheet M10059EJ8V0DS
[MEMO]
µ
PD485505
23
Data Sheet M10059EJ8V0DS
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between VIL (MAX)
and VIH (MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
µ
PD485505
The information in this document is current as of March, 2006. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
