MxX9o6901L SINGLE CHIP SOLID STATE DISK CONTROLLER FEATURE Host Interface Buffer RAM Manager * PCMCIA 2.1 and PC Card ATA standard compatible. - Memory mapped or I/O operation. Compatible with all PC Card Services and Socket Service. * Fast ATA host-to-buffer burst transfer rates up to 20MB/sec. which support PIO mode 4(16.6MB/sec) and DMA mode 2(16.6MB/sec). * Automatic sensing of PCMCIA or True IDE host inter face. * Integrated PCMCIA attribute memory of 256 bytes (CIS) - CIS and Buffer RAM use same SRAM area to simplify internal bus design PCMCIA card configuration register support. Polarity control for Host reset signal. PCMCIA twin card support. * PCMCIA based ATA address decode support. Emulate the IBM task file for PC/AT. Separate status for Host reset signal and Host program reset. Separate Host and Disk interrupt pins. Flash Memory Interface * Support ail the control signals to execute read/ write/ erase operation for flash memory. Flexible Disk Capacity Configuration for series type or linear type flash memory - Upto 32MB(unformatted) capacity for 16 pcs. 16Mbit linear type flash memory. - Upto 1GB(unformatted) capacity for 32 pcs. 256Mbit series type flash memory. Flash Memory Power Down or write protect control support. Flash Memory Ready/Busy status detect. Inverted data bus control to reduce flash memory program/erase operation in DOS FAT and ECC code field. * Optional store firmware in flash memory array w/o external ROM while MXICs MX29F 161 O(linear type) used. - Allow code fetch in Shadow ROM during flash memory program or erase. * Dual port circular Buifer RAM contro] * 1KB data Buffer RAM. * Automatically correct error data in Buffer RAM. - Single word error correct and double word detect. * Provide logic to speed up Buffer RAM access. Support 8 bit as well as 16 bit transfer on host bus. DSP core * High performance MX93011 DSP (21Mips) core. 4KB Internal RAM(direct access). 2KB Internal expansion RAM(indirect access) for store data or shadow ROM space. ICE debugging mode supported to ease system verification. Lower power and automatic power saving operation. - Automatic Standby Mode. (Operating Current < 10mA, VCC=5.5V), wake-up by interrupt signal. - Very Low Operating Current Sleep Mode. (<1mA,VCC=5.5V), wake-up by Host reset signal or Host program reset or ATA command asserted by host. Technology * 128 pin LQFP(14X14X1.4 mm) * 0.6um Low-power, High-speed CMOS technology. * 5Volt + 10% or 3.3Volt + 5%. Utility Support * Provide integrated test environment with 82365SL- compatible adaptor. + Firmware upload from host and allows easy upgrade for custom feature. * Physical devices test cover basic PCB test after assembly and more detial analysis. Logical sector test cover SSD functionality and data transfer test. P/N:PM0546 REV. 1.0, JUN. 25, 1998 38-1GENERAL DESCRIPTION The Macronixs Solid State Disk-controiler MX9691L is a wide-range supply voltage(3.3Volt~5Volt) and fully in- tegrated flash memory controller that provides all the control logic for PCMCIA/True IDE host and flash memory. The MX9691L combines 1KB dual-port buffer and buffer manager, integrated MX93011 DSP core, and a complete host interface for both the PC Card ATA and True IDE standard. The MX9691L provides flexible disk capacity configu- ration and supports ail the control signals to execute read/write/erase operation for linear type or series type flash memory chip. It is typically configured with up to 32MB(unformatted) capacity for 16 pcs. 16Mbit linear flash memory or 1GB(unformatted) capacity for 32 pcs. 256Mbit series type flash memory while capacity extention mode is enabled for series type flash memory used. The MX9691L also provides flexible architecture to implement defect management and wear-leveling by firmware for series type or linear type flash memory. MxX9o601L. In linear mode, the linear type 16 Mbit flash memory is supported, such as MXICs MX29F 1610 etc. In flash memory interface there are two banks of flash memory to be provided. Each bank support 8 pcs. flash memory when linear type flash memory is used. In series mode, the se- ties type 16MBit/S2Mbit/64Mbit/256Mbit flash memory is supported, such as Toshibas TC5816FT/TR or TC58V32FT, Samsungs KM29N16000T/R or KM29N32000TS/RS etc. Each bank support or 16 pcs. flash memory when series type flash memory is used. The MX9691L is fully compliant with the PC Card ATA specification. It includes 256 bytes of integrated attribute memory(for the required Card Information Structure) and four Card Configuration registers. The PCMCIA device driver can access the MX9691Ls ATA command block through four different modes by writing the different modes by writ- ing the configuration index of the attribute memory con- figuration option register. P/N:PMO0546 38-2 REV. 1.0, JUN. 25, 1998Mx<X9691L. PIN CONFIGURATION 6 & 20 28 220 = ric ort =~ Or ited ta RH Hu 4 KR _ i 1 i L 88 BSSESLBSBISSSRRRLKRRKR evH "| 26 7 #38 LiVM 2 i | 86 sia vWH (oT | 66 bia LaS3uH PTO OOF ela SVH 777] LOL za 9VH =] 201 dano 2VH T7] 01 ; tkG #3MH (| Pol ola 9A Li} sot 6a 8VH D7] 901 7 ga #MOl 1 ZOb , #lLHsv1say GND 7} 804 = DOA 6VH [TT] 604 #e304 #4OL (TT ] on _ #3504 #30H [I] tte a #6304 JOOA [7] eth oO #9304 OWH iit | ebb Q) aNd #230H Ci] bl a : #0304 #490H (OTT sit = #304 SLQH [~T7] 9b dOOA 20H (TI zit | #ea04 #AOWINI CT] ett #2304 #Oau! i] ote #0HSV140U dONd _t | oz oa viGH (TJ 12. ike] 9H 1 za 10H daNd SOH | ed ztgH > 9a edH sa MOH Li 3 9d dH ezi) _ 0 rant nHonwoee eereteaan a eee EL L POPE OOEL ul ow t tH EHO RROnR OM OO 23 ee2oShger<**5 EO ET as ia EE ss REV. 1.0, JUN. 25, 1998 38-3 P/N:PM0546PIN DESCRIPTION Host interface MxX9S691L Symbol No. Type Description HA[10:0] 92,94, | Host address line 10-0. 96-97,99 (CMOS) These pins include internal pull-up resistors. 101-103, 106,109, 113 HD[15:0] 84-89, VO Host data line 15-0. 116-117, (TTL) These pins include internal bus holder circuit that keep 121-128 previous state when tri-state. HOE#,HWE# 104,111 I Host memory read/write/mode select : (CMOS) Both pins include internal pull-up resistors that is default in PCMCIA made. lOR#,|OW# 107,110 | Host I/O access. (CMOS) Both pins include internal pull-up resistor. HRESET/HRESET# 100 I The host reset signal, when active, initializes the control/ (CMOS) status registers and stops any command in process. In PCMCIA mode, the signal is active high. In True IDE mode, this signal is active low. This signal include internal pull-down resistor. WAIT/IOCHRDY 98 0,0D WAIT or INPUT CHANNEL READY : In both PCMCIA and (CMOS) True IDE modes, this signal holds host transfers until the controller is ready to respond. RDY/BSY#/ 119 0,Z READY/BUSY or HOST INTERRUPT : In PCMCIA mode, IREQ#/ (CMOS) this signal has two functions. In PCMCIA common memory HOSTINT mode, this signal is ready/busy. It is asserted busy by the reset logic, and can be deasserted by the DSP or represents the ready/ousy bit of ATA status register. In PCMCIA I/O mode, this signal is IREQ#. In True IDE mode, this active high signal is HOSTINT, which, when enable, send an interrupt to the host. P/N:PMO5S46 REV. 1.0, JUN. 25, 1998 38-4MxX<X9691L. Symbol No. Type Description WP/IOCS16# 0,0D (CMOS) WRITE PROTECT or 16-bit /O TRANSFER : In PCMCIA mode, this bit has two functions. In PCMCIA common-memory mode,this signal indicates write protect. In PCMCIA I/O mode, when IOIS16# is asserted low, it indicates that a 16-bit data transfer is active on PCMCIA bus. In True IDE mode, the |OCS16# signal indicates that a 16-bit buffer transfer is active on the host bus. This open drain signal is only driven on assertion(low). REG#/DACK# 95 (CMOS) Attribute memory and I/O select : In PCMCIA mode, this signal is used to select attribute memory and I/O space. In True IDE mode, this signal is used during DMA with the DREQ, IOR# and |OW3# signals to transfer data between the host and the MX9691L. This pin includes an internal pull-up resistor. HCE 1#/ CSIFX# 115 (CMOS) Card enable 1 or Chip select 0:In PCMCIA mode,this signal is card enable 1. This signal can enable either even or odd numbered-address bytes onto HD7:0. In True IDE mode, this signal accesses the MX9691 command block registers. This input is ignored during DMA data transfer, i.e. when the DACK# signal is low. This pin includes an internal pull-up resistor. HCE2#/ CS3FX# 114 (CMOS) Card enable 2 or Chip select 1: In PCMCIA mode,this signal is card enable 2. This signal can enable odd numbered-address bytes onto HD15:8. In True IDE mode, this signal accesses the MX9691L control block registers. This pin includes an internal pull-up resistor. INPACK#/ DREQ 118 (CMOS) Input Acknowledge or DMA request :In PCMCIA mode, this signal is asserted when the MX9691 is configured to respond to I/O card read cycles at all addresses. In True IDE mode, this signal is DREQ and is issued during DMA transfers to indicate that the MX9691L is ready for DMA transfer. SPKR/DASP# V0 (CMOS) Speaker or slave present : In PCMCIA mode, the output-enable for this signal is controlled by the card configuration registers. in True IDE mode, this signal is used as the slave-present detector. STSCHG/ PDIAG# vO (CMOS) Status change or pass diagnostics :In PCMCIA mode, this signal is used to indicate changes in the RDY/BSY#,WP signals in card configuration registers. In True IDE mode, this active low signal is used between two embedded ATA drive to indicate that the drive in slave mode has passed diagnostics. P/N-PMOS46 38-5 REV. 1.0, JUN. 25, 1998M=Iic External Memory Bus Interface MxX9S691L Symbol D[15:0] Al15:0] No. 33-37,39-41, 55-58,60-63 3-5,8-11, 22-24,26-31 Type vO (CMOS) vO (CMOS) Description DSP lO/RAM/ROM/FLASH memory array external data bus. These pins inciude internal pull- up resistors. In Free-run mode, these signals are output that used as DSP IO/RAM/ROM external address. A14-A0 are used for flash memory array address also. In upgrade mode, these address are used for ROM address that controlled by CYH,CYL registers. In \CE-debugging mode,these address are input, asserted by DSP ICE(external MX93011 DSP). And the internal DSP is disabled at this time. These pins include internal pull-up resistors. PCE# 67 VO (TTL) In Free-run mode, this signal is output that is used as external program chip enable. In upgrade mode, this signal is drived to high. In |CE-debugging mode, this signal is input, asserted by DSP ICE(external MX93011 DSP). And the internal DSP is disabled at this time. This pin includes a bus holder circuit. DCE# 0 (TTL) In Free-run mode, this signal is output that is used as external data chip enable. In upgrade mode, this signal is drived to high. In ICE-debugging mode, this signal is input, asserted by DSP ICE(external MX93011 DSP). And the internal DSP is disabled at this time. This pin includes a bus holder circuit. RD# vO (TTL) In Free-run mode, this signal is output that is used as DSP 1O/RAM/ROM external read. In upgrade mode, this signal is output and asserted when the data register is read in host interface. In iCE-debugging mode, this signal is input, as serted by DSP ICE(external MX93011 DSP). And the internal DSP is disabled at this time. This pin includes a bus holder circuit. VO (TTL) in Free-run mode, this signal is output that is used as DSP IO/RAM/ROM external write. In upgrade mode, this signal is drived to high. In ICE-debugging mode, this signal is input, asserted by DSP ICE(external MX93011 DSP). And the internal DSP is disabled at this time. This pin includes a bus holder circuit. NMi# 15 (CMOS) Non maskable interrupt pin. This pin includes an pull-up resistor. INT1# 14 VO (CMOS) In Free-run mode, this signal is input that is used as interrupt pin. Interrupt will be internally asserted aiso when data transfer done, or command end. In ICE-debugging mode, this signal is output and asserted when data transfer done, or command end. This pin includes an pull-up resistor. P/N:PM0546 REV. 1.0, JUN. 25, 1998 38-6Mic MxX9691L. Symbol No. Type Description HOLD# 16 vO in Free-run mode, this signal is input that is used as holding (CMOS) DSP clock down and release bus. Bus hoid will be internally asserted also when upgrade mode enable. In ICE-debug ging mode, this signal is output and asserted when upgrade mode enable. This pin includes an pull-up resistor. HLDA# 3 vO In Free-run mode, this signal is output that is used as ack to (CMOS) HOLD# signal. This signal will be internally sent to PCMCIA/ ATA interface also when upgrade mode enable. In ICE-de bugging mode, this signal is input and ack to HOLD# when upgrade mode enable. XF#/SCTRL# 74 oO Sleep control, this pin can be directly asserted to low while (CMOS) power down bit is set by DSP. This pin is connected to external RC circuit. Default inactive (Logic High). In ICE-debugging mode, this signal is used to reset DSP. Flash Memory Interface Symbol No. Type Description FAI9/CLE 12 oO In linear mode, this signal is used as flash memory chip high (CMOS) address line 19. In series mode, this signal is used as flash memory chip command latch enable. FA18/ALE/ 20 vO In linear mode, this signal is used as flash memory chip high ICEMODE (CMOS) address line 18. In series mode, this signal is used as flash memory chip address latch enable. This signal is also used to select whether the MX9691 initializes in Free-run mode or in ICE-debugging mode at power-on reset. If this pin go high, then the MX9691L will switch to Free-run mode at power-on reset,and if this pin remains low, then the MX9691L will initializes in ICE-debugging mode. This pin includes an internal pull-up resistor. ICE-debugging mode select : ICEMODE=1 > Free-run mode. ICEMODE=0 > ICE-debugging mode. FA17/EROM 21 XQ(CMOS) | This signal is used as flash memory chip high address line 17. This signal is also used to select whether the firmware store in linear type flash memory array or in separate external ROM at power-on reset. If this pin go high, then the firmware will be executed in linear type flash memory array, and if this pin remains low, then the firmware will be executed in separate external ROM. Store firmware in external ROM or linear type Flash memory array select: EROM = 0 > Store in External ROM. EROM = 1 > Siore in flash memory array. This pin includes an internal pull-up resistor. PI REV. 1.0, JUN. 25, 1998 P/N:PM0546 38-7MxX9691 L Symbol FA[16:15)/ ATADET[1:0] Type vO (CMOS) Description This signal is used as flash memory chip high address line 16-15. These signals are also used to select configuration in True IDE mode at power-on reset. ATADET1 is connected to DSPs IPT1. ATADETO is connected to DSPs IPTO. VDD is connected to IPT2. Master/Slave selection in True IDE mode : ATADET1 ATADETO mode selected 1 1 one drive 0 0 master of two drives 1 0 slave of two drives This power-on configuration can be accessed from PCMCIA/ ATA port 601Ch bit3-2. These pins include internal pull-up resistors. RDFLASH1# (CMOS) Flash memory ouptut enable 1 for bank1: This signal will be asserted by flash memory read operation when flash memory read address latch, port 601Dh bit 8= 1(i.e. FA23=1). Note: Flash memory access window is mapped to 32KW data and code space 8000h~ffffh. ROFLASHO# 42 (CMOS) Flash memory ouptut enable 0 for bank0: This signal will be asserted by flash memory read operation when flash memory read address latch, port 601Dh bit 8 = O(i.e. FA23=0). WRFLASH1# 19 (CMOS) Flash memory write enable 7 for bank1: This signal will be asserted by flash memory write operation when flash memory write address latch, port 601 Fh bit 8 = 1(i.e. FA23=1). WRFLASHO# 18 (CMOS) Flash memory write enable 0 for bank0: This signal will be asserted by flash memory write operation when flash memory write address latch, port 601 Fh bit 8 = O(i.e. FA23=0). P/N:PM0546 REV. 1.0, JUN. 25, 1998 38-8MxX96901 L Symbol No. Type Description FCE[7:0}# PWDO#/WP# PWD1#/SE# FRY/FBY# 43-44, 0 46-47 (CMOS) 49-52 32 O (CMOS) 64 oO (CMOS) (CMOS) Flash memory chip enable 7-0 : In linear mode, These signals are decoded from port 601 Dh bit 7-5 when flash memory read or port 601Fh bit 7-5 when flash memory write. Decoding combination : bit7 bit6 bits FCE[7:0}# 0 11111110 11111011 11101111 10111111 11111101 14110111 11011111 1341061 01111111 In series mode, These are decoded from port 601Dh bit 7-5 only when port 601Eh bit 2 is set. In linear mode, this signal is used as deep power-down control of flash memory chips of bank0. PWDO# is active low and aiso locks out erase or program operation providing data protection during power transitions. Power down pin PWD0# will be active if FA23=1. In series mode, this signal is used to protect the device from inadvertent programming or erasing. WP# is active low. In linear mode, this signal is used as deep power-down contro! of flash memory chips of bank1. PWD1# is active low and also locks out erase or program operation providing data protection during power transitions. Power down pin PWDO# will be active if FA23=0. In series mode,this signal is used to spare area control. SE# is active low. Flash memory Ready/busy input: This signal indicate the state of erase or program operation in flash memory chips.This pin includes an internal pull-up resistor. ~a = t= OT 0 0 on? oO + GO + 0 P/N:PM0546 REV. 1.0, JUN. 25, 1998 38-9M=Ic MxX9691L. Control ROM interface Symbol No. Type Description ROMCS#/ 75 oO ROM chip select/Flash memory data buffer enable : FWIN# (CMOS) In Free-run mode, this signal is used as ROM chip enable if firmware that stored in external ROM. In ICE-debugging mode, this signal is used as flash memory data buffer (74640) enable if firmware that stored in flash memory array. ROMWR#/FDIR 76 oO ROM write enable/Flash memory data buffer direction (CMOS) control: in Free-run mode, this signal is used as ROM write enable if firmware that stored in external ROM. In I\CE-debugging mode, this signal is used as flash memory data buffer (74640) direction control if firmware that stored in flash memory array. Miscellaneous Symbol No. Type Description x1 79 | Crystal input. X2 78 0 Crystal ouput. SWAIT# 71 KCMOS Sleep wait, this pin is connected to external RC circuit. Schmitt) N.C. 70 oO No connect. TEST 81 | This signal is used to select the main system clock, either (CMOS) from external clock source if this signal is high or from internal PLL circuit if this signal is low. This pin includes an internal pull-up resistor. PWR_RST# 82 (CMOS Power on reset, CMOS Schmite-triggered: Schmitt) The MX9691L include debouncing circuit to stabilize internal OSP reset signal. LED# 6 0 LED output: (CMOS) This signal is connected to external LED in debugging system to indicate system status. The LED will be turn-on during reset. The contorl firmware will turn off the LED after H/W initialization and pass diagnostics. If system fail, the control firmware will flash the LED to indicate some error occur. This signal will be high if port 601Ch bitO set to 1 or OPTR bit2 set to 1. vec 17,45,53, 5 or 3.3 volt Power pin 72,80,105, 112 GND 7,25,38, Ground pin 48,59,69, 77,91,108, 120 P/N:PMOS46 REV. 1.0, JUN. 25, 1998 38-10M=Ic MxX9691L. Functional and Operation Description Block Diagram Clock External Memory Bus A 4 j Y Clock & Reset MX93011 a 448 Internal . DSP CORE RAM 2KB Interna! Register Bank RAM rt 4 Host Interface _, |. | PCMCIA/ATA | 1KB Buffer | Flash Memory Flash PCMCIA/ATA sf -| interface RAM Control "interface A f 256 Byte Buffer RAM L| ECC Control CIS RAM Control | Logic MX9691L Signal Chip Solid State Disk Controller P/N:PM0546 38-11 REV. 1.0, JUN. 25, 1998Mx9691L. System Memory Map Data Space : Address Function & Usage 0000h~007fh Internal RAM (128W) to store control variables 0080h~07ffh Internal RAM(1920W) for flash memory algorithm usage 0800h~5fffh User define (22kW) 6000h~63ffh VO range(1kW): ATA CTL. use I/O range (6000h~601 fh) 6400h~6fffh User define (8kW) 7000h~73ffh User define (1kW) 7400h~77ffh Internal RAM (1kW) for expansion RAM or shadow ROM space 7800h~7fffh ROM Data space(2kW) 8000h~ffffh Flash memory access windows(32kW) Program Space : Address Function & Usage 0000h~77ffh ROM program space (32kW) 7800h~ 7fffh Unused 8000h~ffffh Flash memory access windows(32kW) Power-on detection * Store firmware in external ROM or Flash memory array FA 7/EROM = 0 > Store in External ROM FA17/EROM = 1 > Store in flash memory array * Master/Slave selection in True IDE mode : FA16/ATADET1 FA15/ATADETO mode selected 1 1 one drive 0 0 master of two drives 1 0 slave of two drives Note : For some customers design the master/slave selection is selected by only one jumper that may be FA16 or FA15. It need to change firmware only. * ICE debugging mode select : FA18/ICEMDOE = 0 ---> ICE-debugging mode FA18/ICEMODE = 1---> Free-run mode, DSP fetch code from external memory bus and execute it. * Flash memory data buffer control ROMCS+# is replaced by FWIN# if ICE-debugging mode & firmware in linear type flash memory array. ROMWR3 is replaced by FDIR if ICE-debugging mode & firmware in linear type flash memory array. * PCMCIA mode or True IDE mode select HOE# Mode 0 True IDE mode 1 PCMCIA mode To enable True IDE mode this input should be grounded by the host. P/N:PMO546 REV. 1.0, JUN. 25, 1998 38-12Mic MxX9so6901L Decoding Configuration of all registers in Host interface * Common Momory Mode Decode Register Address Register Read Enable Register Write Enable CE1# CE2# REG# HA10 HA9:4 HA3:0 HOE#=0 HWE# = 0 0 0 1 0 xh 000xb Read Data Register HD[15:0] Write Data Register HD[15:0] 0 1 1 0 xh 00005 Read Data HD[7:0] Write Data HD[7:0} Even & Odd byte Even & Odd byte 1 0 1 0 xh 0000b Error Status HD[15:8] Features HD[15:8] 0 1 1 0 xh 0001b = Error Status HD{[7:0] Features HD[7:0] 1 0 1 0 xh 0001b Error Status HD[15:8] Features HD[15:8] 0 0 1 0 xh 001xb Sector Count HD[7:0] Sector Count HD[7:0] Sector Number HD[15:8] Sector Number HD[15:8] 0 1 1 0 xh 0010b Sector Count HD[7:0} Sector Count HD[7:0] 0 1 1 0 xh 0011b Sector Number HD[7:0] Sector Number HD[7:0] 1 0 1 0 xh 001ib Sector Number HD[15:8] Sector Number HD[15:8] 0 0 1 0 xh 010xb = Cyl. Low HD[7:0} Cyl. Low HD[7:0] Cly. High HD[15:8] Cly. High HD[15:8] 0 1 1 0 xh 0100b = Cyl. Low HD[7:0] Cyl. Low HD[7:0] 0 1 1 0 xh 0101b = Cly. High HD[7:0] Cly. High HD[7:0] 1 0 1 0 xh 0101b = Cly. High HD[15:8] Cly. High HD[15:8] 0 0 1 0 xh O11xb = Drive/Head HD[7:0] Drive/Head HD{7:0] Ctl. Status HD[15:8] Command HD[15:8] 0 1 1 0 xh 0110b = Drive/Head HD[7:0} Drive/Head HD[7:0] 0 1 1 0 xh Ol11b = Ctl. Status HD[7:0] Command HD[7:0] 1 0 1 0 xh O111b = Ctl. Status HD[15:8] Command HD[15:8] 0 0 1 0 xh 100xb Read Data Register HD[15:0] Write Data Register HD[15:0] (Duplicate) (Duplicate) 0 1 1 0 xh 1000b Read Data HD[7:0] Write Data HD[7:0] Even & Odd byte (Duplicate) Even & Odd byte (Duplicate) 1 0 1 0 xh 100ib Read Data HD[15:8} Write Data HD[15:8] Odd byte (Duplicate) Odd byte (Duplicate) 0 1 1 0 xh 1001b Read Data HD[7:0] Write Data HD[7:0) Odd byte (Duplicate} Odd byte (Duplicate) 0 0 1 0 xh 110xb Undefined HD[7:0] Undefined HD{7:0] Error Status HD[15:8] Features HD[15:8] (Duplicate) (Duplicate) 0 1 1 0 xh 1101b = Error Status HD[7:0] Features HD{7:0] (Duplicate) (Duplicate) 0 0 1 0 xh 111xb = Alternate Ctl. Status HD[7:0] Device Ctl. HD[7:0] Drive/Head HD[15:8] Undefined HD[15:8] 0 1 1 0 xh 1110b = Alternate Ctl. Status HD[7:0] Device Ctl. HD[7:0] P/N:PM0546 REV. 1.0, JUN. 25, 1998 38-13=. MxX9s6901 L. Register Address Register Read Enable Register Write Enable 0 1 1 0 xh 1111b = Drive/Head HD[7:0] Not Used 1 0 1 0 xh 1111b = Drive/Head HD[15:8] Not Used 9) 0 1 1 xh xxxxb Read Data Register HD[15:0] Write Data Register HD[15:0] 0 1 1 1 xh xxx0b Read Data HD[7:0} Write Data HD[7:0] Even & Odd byte Even & Odd byte 0 1 1 1 xh xxx1b Read Data HD[7:0JOdd byte Write Data HD[7:0]Odd byte 1 0 1 1 xh xxx0b Read Data HD[15:8] Odd byte Write Data HD[15:8] Odd byte 1 0 1 1 xh xxx1b Read Data HD[15:8] Odd byte Write Data HD[15:8] Odd byte * Independent I/O Mode Decode Register Address Register Read Enable Register Write Enable CE1# CE2# REG# HA9:4 HA3:0 IOR#=0 lOW# = 0 0 0 0 xh 0000b Read Data Register HD[15:0] | Write Data Register HD[15:0] - 0 1 0 xh 00005 Read Data HD{7:0] Write Data HD[7:0) Even & Odd byte Even & Odd byte 1 0 0 xh 0000b Error Status HD[15:8] Features HD[15:8] 0 1 0 xh 0001b Error Status HD[7:0] Features HD[7:0] 1 0 0 xh 0001b Error Status HD[15:8] Features HD[15:8] 0 1 0 xh 0010b = Sector Count HD[7:0] Sector Count HD[7:0] 0 1 0 xh 0011b Sector Number HD[7:0] Sector Number HD[7:0} 1 0 0 xh 0011b Sector Number HD[15:8] Sector Number HD[15:8] 0 1 0 xh 0100b Cyl. Low HD[7:0] Cyl. Low HD[7:0] 0 1 0 xh 0101b ~~ Cly. High HD[7:0] Cly. High HD[7:0} 1 0 0 xh 010ib = Cly. High HD[15:8] Cly. High HD[15:8] 0 1 0 xh 0110b Drive/Head HD[7:0] Drive/Head HD[?:0] 0 1 0 xh O111b Ctl. Status HD[7:0] Command HD[7:0} 1 0 0 xh O111b Ctl. Status HD[15:8] Command HD[15:8] 0 0 0 xh 1000b Read Data Register Write Data Register HD[15:0](Duplicate) HD[15:0](Duplicate) 0 1 0 xh 1000b Read Data HD{7:0] Write Data HD[7:0] Even & Odd byte (Duplicate) Even & Odd byte (Duplicate) 1 0 0 xh 1001b Read Data HD[15:8]} Write Data HD[15:8] Odd byte (Duplicate) Odd byte (Duplicate) 0 1 0 xh 1001b Read Data HD[7:0] Write Data HD[7:0] Odd byte (Duplicate) Odd byte (Duplicate) 0 1 0 xh 1101b Error Status HD[7:0](Duplicate) Features HD[7:0](Duplicate) 0 1 0 xh 1110b Alternate Ctl. Status HD[7:0] Device Ctl. HD[7:0] 0 1 0 xh 1111b Drive/Head HD[7:0} Not Used 1 0 0 xh 1111b Drive/Head HD[15:8] Not Used PIN:PMO5S46 REV. 1.0, JUN. 25, 1998 38-14Primary ATA Mode Decode MxX9691L Register Address Register Read Enable Register Write Enable CEi# CE2# REG# HAS:0 IOR#=0 _lOW# =0 0 0 0 1F0h Read Data Register HD[15:0] Write Data Register HD[15:0] 0 1 0 1FOh Read Data HD[7:0JEven & Odd byte Write Data HD[7:0]Even & Odd byte 1 0 0 1FOh. Error Status HD[15:8] Features HD[15:8] 0 1 0 1Fih Error Status HD[7:0] Features HD[7:0] 1 0 0 1Fih = Error Status HD[15:8] Features HD[15:8] 0 1 0 1F2h Sector Count HD[7:0] Sector Count HD[7:0] 0 1 0 1F3h Sector Number HD[7:0] Sector Number HD[7:0] 1 0 0 1F3h Sector Number HD[15:8] Sector Number HD[15:8] 0 1 0 1F4h Cyl. Low HD[7:0] Cyl. Low HD[?:0] 0 1 0 1F5h = Cly. High HD[7:0] Cly.. High HD[7:0] 1 0 0 1F5h = Cly. High HD[15:8] Cly. High HD[15:8} 0 1 0 1F6h Drive/Head HD[7:0] Drive/Head HD[7:0] 0 1 0 1F7h = Ctl. Status HD[7:0] Command HD[7:0] 1 0 0 1F7h = Ctl. Status HD[15:8] Command HD[15:8] 0 1 0 3F6h ~s Alternate Ctl. Status HD[7:0] Device Ctl. HD[7:0] 0 1 0 3F7h ~ Drive/Head HD[7:0] Not Used 1 0 0 3F7h Drive/Head HD[15:8] Not Used * Secondary ATA Mode Decode Register Address Register Read Enable Register Write Enable CE1# CE2# REG#H HA9:0 IOR#=0 lOW# = 0 0 0 0 170h Read Data Register HD[15:0] Write Data Register HD[15:0] 0 1 0 170h Read Data HD[7:0]Even & Odd byte Write Data HD[7:0]Even & Odd byte 1 0 0 170h Error Status HD[15:8] Features HD[15:8] 0 1 0 171h Error Status HD[7:0] Features HD[7:0] 1 0 0 171h Error Status HD[15:8] Features HD[15:8] 0 1 0 172h Sector Count HD[7:0] Sector Count HD{[7:0] 0 1 0 173h Sector Number HD[7:0] Sector Number HD[7:0] 1 0 0 173h = Sector Number HD[15:8] Sector Number HD[15:8] 0 1 0 174n Cyl. Low HDJ7:0] Cyl. Low HD[7:0] 0 1 0 175h ~~ Cly. High HD[7:0] Cly. High HD[7:0] 1 0 0 175h == Cly. High HD[15:8] Cly. High HD[15:8] 0 1 0 176h Drive/Head HD[7:0] Drive/Head HD[7:0] 0 1 0 177h Ctl. Status HD[7:0] Command HDj7:0] 1 0 0 17/h Ctl. Status HD[15:8] Command HD[15:8] 0 1 0 376h Alternate Ctl. Status HD[7:0] Device Ctl. HD[7:0] 0 1 0 377h Drive/Head HD[7:0] Not Used 1 0 0 377h Drive/Head HD[15:8] Not Used P/N:PM0546 38-15 REV. 1.0, JUN. 25, 1998Automatic Power Saving Mode There are four power saving modes defined in solid state disk(SSD) system. These four power saving modes are executed by firmware which use DSPs soft-hold and power down function and addition logic circuit to imple- ment it. Active mode: In Active mode the SSD is capable of execution to file read and write operation. Idte mode : In Idle mode the SSD polls the events that include command_in or time_out events. If read/write command is asserted then the SSD will enter the Active mode. Standby mode : The SSD will enter the Standby mode after time_out(1.25ms) event occurs or standby com- mand is asserted. The SSD controller MX9691L will en- ter soft_hold condition. The MX9619 will stop program execution and shut off most circuit activities to save Power Saving Flow MxX9S6901L many power comsumption. The MX9691L will automati- cally wake up and enter the Active mode if any command is asserted. Sleep mode : The SSD will enter the Sleep mode after sleep command is asserted. This is most power saving mode. The SSD controller MX9691L will enter soft _hold condition and stop main clock and then the all system activities will stop. This mode can be waked up by H/W reset, S/W reset or ATA command asserted. The H/W reset will reset all h/w circuits and the Host must reconfigure the SSD before any command is assseted. The S/W reset will set the busy status until the SSD is ready for accepting command, the Host dont need any h/w reinitialization. The duration of H/W and S/W reset must keep enough for main clock stabilization. The ATA command asserted to wake-up latency need the external RC circuit delay for clock stabilization while the Solid State Disk(SSD) had entered sleep mode. Power_up HW Reset S/W Reset Time-out1 or standby cmd Command in Time-out2 or Sleep cmd Command_in Wake-up latency Command in P/N:PM0546 38-16 REV. 1.0, JUN. 25, 1998M= Ic NIX9691L. Registers definition * Registers List Type of Register Location PCMCIA/ATA Interface 6000h, 6001h, 6002h, 6003h, 6004h, 6005h, 6006h, 6007h, 600Bh, 6010h, 601th, 6012h, 6013h, 6019h, 601Ah, 601Bh, 601Ch PC INTERRUPT CONTROL 6009h, 600Ah BUFFER MANAGER AND DMA 6008h, 6014h, 6015h, 6016h, 6017h, 6018h ECC Control 600Ch, 600Dh, 600Eh, 600Fh Flash Memory Interface 601Dh, 601Eh, 601Fh * Register Description Port 6000h : Bit Function Description AT CONTROL/STATUS REGISTER Default reset value : 01h 7 R/W: DRIVE READY (drive 0) 6 R/W: DRIVE SEEK COMPLETE (drive 0) 5 RAW: CORRECTED DATA 4 R: ATA INT. ENABLE 3 R: AT SOFTWARE RESET 2 R/W: HOST INTERRUPT 1 R/W: ERROR BIT 0 RW: BUSY BIT Port 6001h : Bit Function Description Default reset value : 00h 7:0 R/W: ERROR REGISTER (map to command block 1fth) Port 6002h : Bit Function Description Default reset value : Oth 7:0 RW: SECTOR COUNT REGISTER (map to command block 1f2h) Port 6003h : Bit Function Description Default reset value : 0th 7:0 RW: SECTOR NUMBER REGISTER (map to command block 1f3h) : REV. 1.0, JUN. 25, 1998 P/N:PM0546 38-17M=| it MxX9691L Port 6004h : Bit Function Description Defauit reset value : 00h 7:0 R/W: CYCLINDER LOW REGISTER (map to command block 1f4h) Port 6005h : Bit Function Description Default reset value : 00h 7:0 RW: CYCLINDER HIGH REGISTER (map to command block 1f5h) Port 6006h : Bit Function Description Default reset value : AOh 7:0 R/W: DRIVE/HEAD REGISTER (map to command block 1f6h) Port 6007h : Bit Function Description Default reset value : 00h 7:0 R: COMMAND REGISTER (map to command block 1f7h) Port 6008h : Bit Function Description BUFFER RAM SIZE CONTROL REGISTER Defauit reset value : 40h 7 R/W: TEST MODE 1 for HAP/DAP test 0: DISABLE 1: ENABLE 6 R/W: BIT WRITE GATE STATE OF DRIVE 0: ENABLE 1: DISABLE 5 R: PCMCIA or True IDE mode 0: True IDE mode 1: PCMCIA mode 4 R/W: Auto DAP increment 0 : Disable 1: Enable 3 R/W: Shadow ROM conirol 0: Disable 1: Enable 2:0 R/W: BUFFER RAM SIZE CONTROL 00x : 32KW 010: 16KW Ot1: 8BKW 100: 4KW 101: 2KW 110: 1KW 111: 512W P/N:PMO546 REV. 1.0, JUN. 25, 1998 38-18Port 6009h : IMIX969 1 L. Bit Function Description HOST INTERRUPT STATUS Default reset value : 00h R: Power-Down timer time-out detected R: Card configuration register write detected R: CIS accessed detected R: Hreset detected R: PC SRST(or PCMCIA SRST) DETECTED R: PC STATUS READ DETECTED R: PC SELECTION OLPsepoloypeai apa] ~n R: PC TRANSFER DONE Port 600Ah : Bit Function Description HOST INTERRUPT ENABLE Default reset value : 00h R/W: Power-Down timer time-out detected enable. RW: Card configuration register write detected enable RAW: CIS accessed detected enable R/W: Hreset detected enable R/W: PC SRST(PCMCIA SRST) DETECTED ENABLE R/W: PC STATUS READ DETECTED ENABLE R/W: PC SELECTION ENABLE OO] -] Po] oy] AR] oO] Oin R/W: PC TRANSFER DONE ENABLE Port 600Bh : Bit Function Description 7:0 Default reset value : 00h R: Feature register (map to command block 1fih) P/N:PMO0546 38-19 REV. 1.0, JUN. 25, 1998Port 600Ch : Mic MxX9o6901L Bit Function Description ECC CONTROL REGISTER Defauit reset value : 00h 7 RW: ECC FUNCTION SUSPEND 0 : NORMAL 1: SUSPEND 6 R/W: CORRECTION SPEED SELECT 0: FULL SPEED (Max. Clock frequency) 1: HALF SPEED (1/2 Max. Clock frequency) 5 RW: ENCODE/DECODE FUNCTION SELECTION 0: ENCODE 1: DECODE 4 RW: RESET ECC CIRCUIT 0: RESET 1: NORMAL 3 R: UNCORRECTABLE ERROR FLAG 2 R: CORRECTABLE ERROR FLAG 1 R: CORRECTION DONE FLAG 0 R/W: START ECC CORRECT FUNCTION ENABLE/DISABLE 0: DISABLE 1: ENABLE Port 600Dh : Bit Function Description Default reset value : 0000h 15:0 R/W : ECC 0 REGISTER Port 600Eh : Bit Function Description Default reset value : 0000h 15:0 RAW : ECC 1 REGISTER Port 600Fh : Bit Function Description Default reset value : 0000h 15:0 R/W : ECC 2 REGISTER Port 6010h : Bit Function Description Default reset value : 00h 7:0 R: Configuration Option register (map to attribute memory 200h) P/N:PM0546 38-20 REV. 1.0, JUN. 25, 1998M=Ic MxX9691 L Port 6011h: Bit Function Description Default reset value : 00h 7:0 R: Card Configuration and status register (map to attribute memory 202h) Port 6012h : Bit Function Description Default reset value : OCh 7:0 R: Pin replacement register (map to attribute memory 204h) Port 6013h : Bit Function Description Default reset value : 00h 7:0 R: Socket and copy register (map to attribute memory 206h) Port 6014h: Bit Function Description Default reset value : 0000h 15:0 R/W : HOST ADDRESS POINTER Port 6015h: Bit Function Description Default reset value : 00ffh 15:0 R/W : AT STOP POINTER Port 6016h: Bit Function Description Default reset value : 0000h 15:0 R/W : DISK ADDRESS POINTER Port 6017h: Bit Function Description DMA CONTROL REGISTER Default reset value : 08h 7 R/W: DRIVE READY (drive 1) 6 R/W: DRIVE SEEK COMPLETE (drive 1) 5 R/W: set BSY upon XFER done 0 : DISABLE 1: ENABLE 4 RAW: ENABLE AUTO INTERRUPTS - AT ONLY 0 : DISABLE 1 : ENABLE P/N:PM0546 38-21 REV. 1.0, JUN. 25, 1998vVM=Ic MxX9691L. Port601 7h: Bit Function Description 3 R/W: BUFFER RAM CHIP ENABLE 0: ENABLE 1: DISABLE 2 R/W: HOST BUS DIRECTION 0: START BUFFER ---> AT BUS 1: START AT BUS ---> BUFFER WHEN SET 1 R: A COMPLETION OF AT DMA XFER 0 RAW: START DATA TRANSFER BETWEEN AT BUS AND BUFFER RAM 0: DISABLE 1: ENABLE Port 6018h: Bit Function Description 15:0 R/W : ACCESS PORT INTO BUFFER RAM Port 6019h: Bit Function Description PCMCIA control register 7 R: True IDE made 6 R: Common memory mode 5 R: /O mode 4 R/W: host ready 3 RW: no drive address 2 RMW: Internal registers write pulse width 0 : 2 system clock 1:1 system clock 1 R/W: Reserved. 0 R/W: Reserved. P/N:PM0546 REV. 1.0, JUN. 25, 1998 38-22M=Iit Mx96914L. Port 601Ah : _ Bit Function Description Auxi_ctl_1 reg. Default reset value : 00h 7 R/W : DASP . 6 RW : Host Interrupt level mode or pulse mode select 0: Level mode 1: Pulse mode 5 RW : PDIAG 4 R/W : DASP output enable 3 R/W: write protect enable 0: Disable 1: Enable 2 RW: PDIAG output enable 1 R/W: master/slave mode enable 0: Disable 1: Enable 0 RW: master/salve of True IDE mode 0: master 1: slave Port 601Bh: Bit Function Description Auxi_ctl_2 reg. Default reset value : 00h 74 Reserved. 3 R/W: Reserved. 2 R/W: Deep power down control for automatic wake-up function from sleep mode. 0 : Disable 1: Enable 1 R/W: Reserved. 0 RW: Disk interrupt polarity 0: Low active 1: High active P/N:PMO0546 38-23 REV. 1.0, JUN. 25, 1998Port 601Ch : Mic Mx9691 L Bit Function Description 15 Auxi_ctl_3 reg. Default reset value : 0000h Reserved. 14 RW : Test mode 2 for timer 0 : Normal mode 1: Test mode enable 13 R:DRQ 12 R: Time out status 1: Time out event occurence af} R/W: Timer enable/disable 0: Disable 1: Enable 10:9 R/W: Power-down timer time-out select for 25MHz main clock 00 : 16 x 1.28 = 20.48 sec. 01: 8x 1.28 = 10.24 sec. 10: 4x 1.28 = 5.12 sec. 11: 2x 1.28 = 2.56 sec. R : ICE-debugging mode detected 0 : ICE-debugging mode 1 : Free-run mode. R/W : inverted data bus for access flash memory. 0: Inverted. 1: Non-inverted. R: External ROM detect. 0: Firmware stored in external ROM. 1: Firmware stored in linear type flash memory array. 5:4 R/W: Shadow ROM space control 00 : 512 bytes, Range: 7400h ~ 74ffh 01: 1Kbytes, Range: 7400h ~ 75ffh 10: 1.5Kbytes, Range: 7400h ~ 76ffh 11: 2Kbytes, Range: 7400h ~ 77ffh 3:2 R : Master/Slave mode detect in True IDE mode 00 : Master of two drives 10 : Slave of two drives 11 : One drive R/W: PIO/DMA mode select 0: PIO mode. 1: DMA mode. R/W: LED output P/N:PM0546 38-24 REV. 1.0, JUN. 25, 1998M=ic Mx9691L. Port 601Dh : Bit Function Description Default reset value : 0000h 9:0 RW : Flash memory Read address FA[24:15] latch in linear mode When data space 8000h ~ ffffh is read, the output of the flash memory read address latch will be used. The definitions for this register in series mode Default reset value : 0000h 9 Reserved. 8 Bank select in capacity extension mode 0 : BankO selected. 1: Bank selected. 7:5 R/W: FCE select for series mode 000: FCEO 001: FCE2 010: FCE4 011: FCE6 100: FCE1 101: FCE3 110: FCE5 111: FCE7 4 RW: Command latch enable (FA19/CLE) 0 : Disable 1: Enable 3 R/W: Address latch enable (FA18/ALE) 0: Disable 1: Enable 2:0 Reserved Port 601Eh: Bit Function Description Flash memory control register Default reset value : O8Ah 7 R/W: Flash memory deep power down control 0 in linear mode or Write protect in series mode 0: Enable 1: Disable 6 R : Ready / Busy status 0: BUSY 1: READY P/N:PMO546 REV. 1.0, JUN. 25, 1998 38-25M=ic MxX9691L. Port 601Eh : Bit Function Description 5:4 R/W: Flash memory type select 00 : Reserved. 01 : 16M flash memory /Bank 1 select in linear mode or capacity extension mode selected in series mode. 10: Reserved 11: Reserved R/W: Flash memory deep power down control 1 in linear mode or Spare area enable in series mode. 0: Enable 1: Disable R/W: CE# enable for series mode 0: Disable 1: Enable R/W: Series or linear mode select 0: linear mode 1: Series mode RMW: Flash memory write pulse width control 0: 1 system clock 1: 2 system clock Port 601Fh: Bit Function Description Default reset value : 0000h R/W : Flash memory Write address FA[24:15] latch in linear mode When data space 8000h ~ ffffh is write or program space 8000h ~ ffffh is read, the output of the flash memory write address latch will be used. The definitions for this register in series mode Reserved. Bank select in capacity extension mode 0 : Bank selected. 1 : Bank selected. 7:0 Reserved. P/N:PM0546 REV. 1.0, JUN. 25, 1998 38-26M=Ic ELECTRICAL SPECIFICATIONS DC Characteristics 1 : Ta = OC to 70 C, VCC = 5V+10% MxX9691L. Symbol Parameter Min) Max = Units Conditions vec Power Supply voltage 4.5 5.5 Vv VIL1 Input Low voltage (TTL) 0.8 V VCC=5V ViH1 Input High voltage (TTL) 2.0 Vv VCC=5V ViL2 Input Low voltage (CMOS) 1.2 Vv VCC=5V VIH2 Input High voltage (CMOS) 3.5 Vv VCC=5V VOL Output Low voltage 0.4 Vv lOL=8mA VOH Output High voltage 2.5 Vv IOH=-8mA ICC1 Supply Current 1 40 mA f=25Mhz, Active mode, CL=Opf, VCC=5.5Volt, Temperature= 0C ICC2 Supply Current 2 30 mA f = 25Mhz, Idle mode, CL = Opf, VCC=5.5Volt, Temperature= 0C ICC3 Supply Currect 3 12 mA f = 25Mhz, Standby mode, CL = Opf, VCC=5.5Volt, Temperature= 0C Icc4 Supply Current 4 1 mA f = OMhz, Sleep mode, CL = Opf, VCC=5.5Volt, Temperature= 0C IL. Input Leakage 10 uA 0< VIN < VCC CIN input Capacitance 14 pf VIN=0V COUT Output Capacitance 16 pf VOUT=0V Note : During transitions, inputs may undershoot to -2.0V for periods less than 20ns and overshoot to VCC + 2.0V for periods less than 20ns. P/N:PM0546 38-27 REV. 1.0, JUN. 25, 1998M=Ic DC Characteristics 2 : Ta = 0C to 70 C, VCC = 3.3V45% Mx9o601L. Symbol Parameter Min Max Units Conditions VCC Power Supply voltage 3.1 3.5 Vv VILi Input Low voltage(TTL) 08 Vv VCC=3.3V VIH1 Input High valtage(TTL) 2.0 v VCC=3.3V VIL2 Input Low voltage(CMOS) 0.9 Vv VCC=3.3V VIH2 Input High voltage(CMOS) 27 Vv VOC=3.3V VOL Output Low voltage 04 Vv lOL=4mA VOH Output High voltage 22 Vv IOH=-4mA ICC1 Supply Current 1 20 mA f=16Mhz, Active mode, CL=Opf, VCC=3.5Volt, Temperature= 0C Icc2 Supply Current 2 15 mA f = 16Mhz, Idle mode, CL = Opf, CC=3.5Volt, Temperature= 0C ICC3 Supply Currect 3 5 mA f = 16Mhz, Standby mode, CL = Opf, VCC=3.5Volt, Temperature= 0C ICC4 Supply Current 4 0.5 mA. f = OMhz, Sleep mode, CL = Opf, VCC=3.5Volt, Temperature= 0C IL Input Leakage +10 uA 0< VIN < VCC CIN Input Capacitance 14 pf VIN=0V COUT Output Capacitance 16 pf VOUT=0V Note : During transitions, inputs may undershoot to -2.0V for periods less than 20ns and overshoot to VCC + 2.0V for periods le: ss than 20ns. P/N:PM0546 38-28 REV. 1.0, JUN. 25, 1998M=Ic Mx9691L. AC Characteristics Condition : Ta=0 C to 70 C, VCC = 5V+10% or VCC = 3.3V45% DSP Interface Timing : VCC = 5V1H10% Symbol Description Min. Typ. Max. Units Tw In ICE mode, WR# pulse duration when the data are 4Tc accessed by external DSP. Trd In ICE mode, RD# to output delay when the dataare __ 34 ns accessed by external DSP. Tes Chip select access cycle 1.5Tc 4.5Tc ns Taa Address access cycle 1.5Tc 4.5Tc ns Trds Data setup time before RD# high 12 ns Tdh Data hold time after RD# high 0 ns VCC = 3.3V15% Symbol Description Min. Typ. Max. Units Tw In ICE mode, WR# pulse duration when the data are 4Tc accessed by external DSP. Trd In ICE mode, RD# to output delay when the data are 34 ns accessed by external DSP. Tes Chip select access cycle 1.5Tc 4.5Tc ns Taa Address access cycle 1.5Tc 4.5Tc ns Trds Data setup time before RD# high ns Tdh Data hold time after RD# high ns PIN:PMOS46 REV. 1.0, JUN. 25, 1998 38-29M=Ic MxX9691L A[15:0] xX x DCE# fo | WR# D[15:0) DCE# << aN p ne Tid RD# too D[15:0] XK xX 7 DCE#/PCE# Tes : Lf Taa AL18:0] x : xX RD# D[15:0] P/N:PMO0546 38-30 REV. 1.0, JUN. 25, 1998Mic Power Reset Timing VCC = 5V+10% or VCC = 3.3V15% MxX9o6901L Symbol Description Min. Typ. Max. Units Twirst) Reset low pulse width 3Tc ns Clock Timing VCC = 5V+10% Symbol Description Min. Typ. Max. Units Te(c) Clock cycle time 40 ns Tipd(c) Clock low pulse duration(Tc=40ns) 16 24 ns Thpd(c) Clock high pulse duration(Tc=40ns) 16 24 ns VCC =3.3V+5% Symbol Description Min. Typ. Max. Units Te(c) Clock cycle time 62.5 ns Tipd{c) Clock low pulse duration(Tc=62.5ns) 2 375 ns Thpd(c) Clock high pulse duration(Tc=62.5ns) 25 375 ns PWR RST# + Tits) oKn 4 NOK NNN P/N:PMO546 38-31 REV. 1.0, JUN. 25, 1998Interrupt Timing VCC = 5V+10% NMX9691 L. Symbol Description Min. Typ. Max. Units Tw INT 1# low pulse duration 1.5Te ns Tf INT 1# fall time 10 ns VCC =3.3VL5% Symbol Description Min. Typ. Max. Units Tw INT1# low pulse duration 1.5Tc ns Tf INT 1# fall time ns HOLD# Timing VCC = 5V+10% or VOC = 3.3V45% Symbol Description Min. Typ. Max. Units Td({al-h) HLDA# low to address tri-state 0 ns Td(hh-ha) HOLD# high to HLDA# high 0 0.5Tc O.5Tc+10 ns Ten(ah-a) Address driven after HLDA# high 0.5Tc-10 0.5Tc Te ns INT1 ; _ Tw HLDA# A[15:0] y + Td{hh-ha) | } ~~ f : by : ' 4 + : if a ' Ne Ten(ah-a) pt tg P/N:PM0546 38-32 REV. 1.0, JUN. 25, 1998N= Ic Mx9691L. PCMCIA Bus Timing 1: Common Memory and Attribute memory Access Timing VCC = 5V+H10% Symbol Parameter Min (ns} Max (ns) T1 Read cycle time 60 T2 Chip enable setup time before output enable 0 T3 Output data enable time from HOE# 31 T4 Chip disable hold time following output disable 15 T5 Output data disable time following HOE# 10.5 T6 Write cycle time 60 T7 Chip enable setup time before HWE# 0 T8 Write pulse width of HWE# 40 T9 Chip disable hold time following write disable 2 T10 Data setup time before HWE# 0 11 Data hold time following HWE# 25 VCC =3.3V 5% Symbol Parameter Min (ns) Max (ns) T1 Read cycle time 90 T2 Chip enable setup time before output enable 0 T3 Output data enable time from HOE# 47 T4 Chip disable hold time following output disable 3 T5 Output data disable time following HOE# 17 T6 Write cycle time 90 17 Chip enable setup time before HWE# 0 T8 Write pulse width of HWE# 60 T9 Chip disable hold time following write disable 25 T10 Data setup time before HWE# 0 T11 Data hold time following HWE# 3 P/N:PMO546 REV. 1.0, JUN. 25, 1998 38-33_ MxX9691L. Common Memory and Attribute Memory Read Timing ' 1 HA[10:0] : : el Fe Pe CE[2:1]# < _ T2 : ' , ' TS HOE# 3 ! t : + Ths De: Common Memory and Attribute Memory WriteTiming : 16 HA[10:0] REG# x X CEl2:1]# << 7 i TT T8 > itT9 <--> -_$< | HWE# : From : T14 HD[15:0] xX xX << T10 P/N:PM0546 REV. 1.0, JUN. 25, 1998 38-34PCMCIA Bus Timing 2: I/O mode Access Timing VCC = 5V+10% MxX9SG690TL. Symbol Parameter Min (ns) Max (ns) T1 Address hold time following IOR# 2 T2 REG# setup time before IOR# 0 T3 REG# hold time following IOR# 0 T4 CE# setup time before IOR# 0 T5 IOR# pulse width 60 T6 CE# hold time following |OR# 2 T7 Address setup time before iOR# 0 T8 INPACK delay from !OR# falling edge 10 T9 INPACK delay from IOR# rising edge 10.5 T10 1O1S16 falling delay after Address changed 14 T11 Data delay after IOR# falling 32 T12 IO1S16 rising delay after Address changed 125 T13 Data hold time following |OR# 20 714 Address hold time following (OW# 3 T15 REG# setup time before |IOW# 0 T16 REG# hold time following |OW# 0 T17 CE# setup time before IOW# 0 T18 lOW# pulse with 60 T19 CE# hold time following IOW# 2 T20 Address setup time before IOW# 0 T21 IOIS16 rising delay after Address changed 10.5 T22 101816 falling delay after Address changed 14 T23 Data setup time before IOW# 0 T24 Data hold time following iOW# 25 P/N:PM0546 REV. 1.0, JUN. 25, 1998 38-35VCC = 3.3V+5% Mx9691L. Symbol Parameter Min (ns) Max (ns) T1 Address hold time following |\OR# 2 T2 REG# setup time before IOR# 0 T3 REG# hoid time following IOR# 0 T4 CE# setup time before IOR# 0 T5 lOR# pulse width 90 T6 CE# hold time following lIOR# 2 T7 Address setup time before IOR# 0 T8 INPACK delay from IOR# falling edge 18 T9 INPACK delay from fOR# rising edge 18 T10 101816 falling delay after Address changed 23.5 T11 Data delay after |OR# falling 47 T12 1O1S16 rising delay after Address changed 20 T13 Data hold time following IOR# 31 T14 Address hold time following |OW# 4 T15 REG# setup time before t(OW# 0 T16 REG# hold time following lOW# 0 117 CE# setup time before lOW# 0 T18 tOW# pulse with 90 T19 CE# hold time following lOW# 25 T20 Address setup time before (OW# 0 T21 IO1S16 rising delay after Address changed 20 T22 1O1S16 falling delay after Address changed 23.5 T23 Data setup time before tOW# 0 T24 Data hold time following |OW# 3 P/N:PM0546 REV. 1.0, JUN. 25, 1998 38-36MxX9691L. ID Read Timing HA10:0} T13 REG# CE[2:1]# jOR# INPACK# loiS16# HD[15:0] 1/O Write Timing HA[10:0] T19 ~ T18 REG# CE[2:1]# low#t 10ls16# HD[15:0] REV. 1.0, JUN. 25, 1998 38-37 P/N:PM0546Mx9s6oTL Flash Memory Interface Timing VCC = 5V110% Symbol Parameter Min Max Units Tw(a-ce) FCE# fall time after DSP address decode when write 55 15 ns Twas FCE# setup time before WRFLASH# falling edge 10 29.5 ns Tw(wrflash}) WRFLASH# low pulse duration 1Tc ns Tr(a-ce) FCE# fall time after DSP address decode when read 5.5 15 ns Tr(rd-oe) RDFLASH# fall time after RD# falling edge 45 115 ns VCC =3.3V15% Symbol Parameter Min Max Units Tw(a-ce) FCE# fall time after DSP address decode when write 8 24.5 ns Twas FCE# setup time before WRFLASH# falling edge 145 49 ns Tw(wrflash) WRFLASH# low pulse duration 1Tc ns Tr(a-ce) FCE# fall time after DSP address decode when read 8 24.5 ns Tr(rd-oe) RDFLASH# fall time after RD# falling edge 6.5 20 ns [Note]: Theses timing are only for 1-system clock of flash memory write pulse is employed (601 E[0]=0). If 2-system clock of pulse width is selected (601 E[0]=1), the minimum time of Tw(wrflash) is 2Tc. Fiash memory write timing A[15:0] YC xX <>! Tw(a-ce) FCEI7:0] ONS we Nr le pi Tw(wrilash) WRFLASH# TN Flash memory Read timing AI15:0] x , x : Tr(a-ce) FCEI7:0} OOS RDFLASH# a P/N:PM0546 38-38 REV. 1.0, JUN. 25, 1998M=Ic Mx9691L Latchup Characteristics Min. Max. Input Voltage with respect to GND on all VCC pins -2.0V 12.0V Input Voltage with respect to GND on all I/O pins -2.0V VCC+2.0V Current -100mA +100mA Includes all pins expect GND. Test conditions: VCC=5.0V, one pin at a time. " REV. 1.0, JUN. 25, 1998 P/N:PM0546 48-39