IS61/64WV25616FALL IS61/64WV25616FBLL APRIL 2018 256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM KEY FEATURES DESCRIPTION High-speed access time: 8, 10ns, 12ns Low Active Current: 35mA (Max., 10ns, I-temp) Low Standby Current: 10 mA (Max., I-temp) Single power supply - 1.65V-2.2V VDD (IS61/64WV25616FALL) - 2.4V-3.6V VDD (IS61/64WV25616FBLL) Three state outputs Data Control for upper and lower bytes Industrial and Automotive temperature support Lead-free available FUNCTIONAL BLOCK DIAGRAM DECODER A0 - A17 256K x 16 MEMORY ARRAY The ISSI IS61/64WV25616FALL/FBLL are high-speed, low power, 4M bit static RAMs organized as 256K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power devices. When CS# is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE#) controls both writing and reading of the memory. A data byte allows Upper Byte (UB#) and Lower Byte (LB#) access. The IS61/64WV25616FALL/FBLL are packaged in the JEDEC standard 48-ball mini BGA (6mm x 8mm), 44-pin 400mil SOJ, and 44-pin TSOP (TYPE II) VDD GND I/O0 - I/O7 I/O8 - I/O15 CS# OE# WE# UB# LB# I/O DATA CIRCUIT COLUMN I/O CONTROL CIRCUIT Copyright (c) 2018 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 1 IS61/64WV25616FALL IS61/64WV25616FBLL PIN CONFIGURATIONS 48-Ball mini BGA(6mm x 8mm), (Package Code : B) 48-Ball mini BGA (6mm x 8mm) , Switched IO (Package Code : B2) 1 2 3 4 5 6 LB# OE# A0 A1 A2 NC A B I/O8 UB# A3 A4 CS# I/O0 C I/O9 I/O10 A5 A6 I/O1 D VSS I/O11 A17 A7 E VDD I/O12 NC F I/O14 I/O13 G I/O15 H NC A 1 2 3 4 5 6 LB# OE# A0 A1 A2 NC B I/O0 UB# A3 A4 CS# I/O8 I/O2 C I/O1 I/O2 A5 A6 I/O10 I/O9 I/O3 VDD D VSS I/O3 A17 A7 I/O11 VDD A16 I/O4 VSS E VDD I/O4 NC A16 I/O12 VSS A14 A15 I/O5 I/O6 F I/O6 I/O5 A14 A15 I/O13 I/O14 NC A12 A13 WE# I/O7 G I/O7 NC A12 A13 WE# I/O15 A8 A9 A10 A11 NC H NC A8 A9 A10 A11 NC 44-Pin TSOP-II and SOJ, (Package Code : T and K) A0 1 44 A17 A1 2 43 A16 A2 3 42 A15 A3 4 41 OE# A4 5 40 UB# CS# 6 39 LB# I/O0 7 38 I/O15 I/O1 I/O2 8 9 37 36 I/O14 I/O13 I/O12 I/O3 10 35 VDD 11 34 VSS VSS 12 33 VDD I/O4 13 32 I/O11 I/O5 I/O6 14 31 I/O10 15 30 I/O9 I/O7 16 29 I/O8 WE# 17 28 NC A5 18 27 A14 A6 A7 19 26 A13 20 25 A12 A8 21 24 A11 A9 22 23 A10 Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 PIN DESCRIPTIONS A0-A17 I/O0-I/O15 CS# OE# WE# LB# NC Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection VDD VSS Power Ground UB# 2 IS61/64WV25616FALL IS61/64WV25616FBLL FUNCTION DESCRIPTION SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM has three different modes supported. Each function is described below with Truth Table. STANDBY MODE Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-15) are placed in a high impedance state. CMOS input in this mode will maximize saving power. WRITE MODE Write operation issues with Chip selected (CS#) and Write Enable (WE#) input LOW. The input and output pins (I/O015) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB# and LB# enables a byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written into the location. READ MODE Read operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input HIGH. When OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB# being LOW, data from memory appears on I/O8-15. In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. TRUTH TABLE Mode CS# WE# OE# LB# UB# I/O0-I/O7 I/O8-I/O15 VDD Current Not Selected H X X X X High-Z High-Z ISB1, ISB2 L H H L L High-Z High-Z L H H H L High-Z High-Z L H L L H DOUT High-Z L H L H L High-Z DOUT L H L L L DOUT DOUT L L X L H DIN High-Z L L X H L High-Z DIN L L X L L DIN DIN Output Disabled Read Write ICC Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 ICC ICC 3 IS61/64WV25616FALL IS61/64WV25616FBLL POWER UP INITIALIZATION The device includes on-chip voltage sensor used to launch POWER-UP initialization process. When VDD reaches stable level, the device requires 150us of tPU (Power-Up Time) to complete its self-initialization process. When initialization is complete, the device is ready for normal operation. tPU 150 us Stable VDD VDD Device Initialization Device for Normal Operation 0V Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 4 IS61/64WV25616FALL IS61/64WV25616FBLL ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol Vt er m Parameter Terminal Voltage with Respect to VSS Value -0.5 to VDD + 0.5V Unit V VDD V DD Related to VSS -0.3 to 4.0 V tStg Storage Temperature -65 to +150 PT Power Dissipation 1.0 C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. . PIN CAPACITANCE (1) Parameter Symbol Input capacitance DQ capacitance (IO0-IO15) CIN CI/O Test Condition TA = 25C, f = 1 MHz, VDD = VDD(typ) Max Units 6 8 pF pF Note: 1. These parameters are guaranteed by design and tested by a sample basis only. OPERATING RANGE(1) Range Ambient Temperature PART NUMBER IS61WV25616FALL Commercial 0C to +70C IS61WV25616FBLL IS61WV25616FALL Industrial Automotive (A3) -40C to +85C -40C to +125C IS61WV25616FBLL IS64WV25616FALL IS64WV25616FBLL Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 VDD 1.65V - 2.2V 2.4V - 3.6V 3.3V+/-10% 1.65V - 2.2V 2.4V - 3.6V 3.3V+/-10% 1.65V - 2.2V 2.4V - 3.6V SPEED (MAX) 10 ns 8ns 10 ns 8ns 10 ns 5 IS61/64WV25616FALL IS61/64WV25616FBLL AC TEST CONDITIONS (OVER THE OPERATING RANGE) Parameter Input Pulse Level Unit (1.65V~2.2V) 0V to VDD Unit (2.4V~3.6V) 0V to VDD Unit (3.3V +/-10%) 0V to VDD 1.5 ns 1/2 VDD 13500 10800 VDD 1.5 ns 1/2 VDD 319 353 VDD Refer to Figure 1 and 2 1.5 ns 1/2 VDD 319 353 VDD Input Rise and Fall Time Output Timing Reference Level R1 (ohm) R2 (ohm) VTM (V) Output Load Conditions AC TEST LOADS FIGURE 1 FIGURE 2 R1 VTM TM V Zo = 50 ohm Output 50 ohm VDD/2 30 pF, Including jig and scope Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 OUTPUT 5pF, Including jig and scope R2R2 6 IS61/64WV25616FALL IS61/64WV25616FBLL DC ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS (OVER THE OPERATING RANGE) IS61/64WV25616FALL (VDD = 1.65V - 2.2V) Symbol VOH VOL VIH(1) VIL(1) ILI ILO Note: 1. Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions I OH = -0.1 mA IOL = 0.1 mA GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 1.4 -- 1.4 -0.2 -1 -1 Max. -- 0.2 VDD + 0.2 0.4 1 1 Unit V V V V A A VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested. IS61/64WV25616FBLL (VDD = 2.4V - 3.6V) Symbol VOH VIH(1) Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage VIL(1) Input LOW Voltage VOL ILI ILO Note: 1. 2.4V 2.7V 2.4V 2.7V 2.4V 2.7V 2.4V 2.7V ~ ~ ~ ~ ~ ~ ~ ~ 2.7V 3.6V 2.7V 3.6V 2.7V 3.6V 2.7V 3.6V Input Leakage Output Leakage Test Conditions V DD = Min., I OH = -1.0 mA V DD = Min., I OH = -4.0 mA V DD = Min., IOL = 2.0 mA V DD = Min., I OL = 8.0 mA VSS < VIN < VDD VSS < VIN < VDD, Output Disabled Min. 2.0 2.2 -- -- 2.0 2.0 -0.3 -0.3 -2 -2 Max. Unit -- V 0.4 0.4 V VDD + 0.3 V 0.6 0.8 2 2 V A A VIL(min) = -0.3V DC ; VIL(min) = -2.0V AC (pulse width 2.0ns). Not 100% tested. VIH (max) = VDD + 0.3V DC ; VIH(max) = VDD + 2.0V AC (pulse width 2.0ns). Not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 7 IS61/64WV25616FALL IS61/64WV25616FBLL POWER SUPPLY CHARACTERISTICS-II FOR POWER (OVER THE OPERATING RANGE) Symbol Parameter Test Conditions ICC VDD Dynamic Operating Supply Current VDD = MAX, IOU T = 0 mA, f = fMAX ICC1 Operating Supply Current ISB1 TTL Standby Current (TTL Inputs) ISB2 CMOS Standby Current (CMOS Inputs) Notes: 1. 2. 3. VDD = MAX, IOUT = 0 mA, f = 0 VDD = MAX, VIN = VIH or VIL CS# VIH , f = 0 VDD = MAX, CS# VDD - 0.2V VIN VDD - 0.2V , or VIN 0.2V ,f=0 Grade Com. Ind. Auto. Com. Ind. Auto. Com. Ind. Auto. Com. Ind. Auto. Typ. (2) -8(3) Max. 40 45 20 25 15 20 8 -10 Max. 30 35 40 20 25 35 15 20 30 8 -12 Max. 30 35 40 20 25 35 15 20 30 8 10 10 10 - 20 20 Unit mA mA mA mA 3 At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input line change. Typical value indicate the value for the center of distribution, measured at VDD = 3.0V/1.8V, TA = 25 C, and not 100% tested. 8ns is at VDD=3.3V +/-10% Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 8 IS61/64WV25616FALL IS61/64WV25616FBLL AC CHARACTERISTICS (OVER OPERATING RANGE) READ CYCLE AC CHARACTERISTICS(1) Parameter Symbol Read Cycle Time Address Access Time Output Hold Time CS# Access Time OE# Access Time tRC tAA tOHA tACE tDOE OE# to High-Z Output OE# to Low-Z Output CS# to High-Z Output CS# to Low-Z Output UB#, LB# Access Time UB#, LB# to High-Z Output UB#, LB# to Low-Z Output Notes: 1. 2. 3. -8(3) -10 -12 unit notes Min Min Min Min Min Max 8 2.0 - 8 8 4.5 10 2.5 - 10 10 6 12 2.5 - 12 12 7 ns ns ns ns ns tHZOE tLZOE tHZCE tLZCE tBA tHZB 0 0 0 3 0 3 3 5.5 3 0 0 0 3 0 5 5 6 5 0 0 0 3 0 6 6 7 6 ns ns ns ns ns ns 2 2 2 2 tLZB 0 - 0 - 0 - ns 2 2 Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of VDD/2, input pulse levels of 0V to VDD and output loading specified in Figure 1. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 8ns is at VDD=3.3V +/-10% AC WAVEFORMS READ CYCLE NO. 1(1,2) (ADDRESS CONTROLLED, CS# = OE# = UB# = LB# = LOW, WE# = HIGH) tRC Address tAA tOHA DQ 0-15 PREVIOUS DATA VALID tOHA DATA VALID Notes: 1. The device is continuously selected. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 9 IS61/64WV25616FALL IS61/64WV25616FBLL READ CYCLE NO. 2(1) (OE# CONTROLLED, WE# = HIGH) tRC ADDRESS tAA tOHA tDOE OE# tHZOE tLZOE CS# tACS tHZCS tLZCS UB#,LB# tHZB tBA tLZB DOUT HIGH-Z LOW-Z DATA VALID Note: 1. Address is valid prior to or coincident with CS# LOW transition. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 10 IS61/64WV25616FALL IS61/64WV25616FBLL WRITE CYCLE AC CHARACTERISTICS(1) Parameter Symbol Write Cycle Time CS# to Write End Address Setup Time to Write End UB#,LB# to Write End Address Hold from Write End Address Setup Time WE# Pulse Width WE# Pulse Width (OE# = LOW) Data Setup to Write End Data Hold from Write End WE# LOW to High-Z Output WE# HIGH to Low-Z Output Notes: 1 2 3 -8(3) -10 Min Max Min Max tWC tSCS tAW tPWB tHA tSA 8 6.5 6.5 6.5 0 0 - 10 8 8 8 0 0 tPWE1 tPWE2 tSD tHD tHZWE tLZWE 6.5 8 5 0 2 3.5 - 8 10 6 0 2 -12 unit Min Max - 12 9 9 9 0 0 - ns ns ns ns ns ns 4 - 9 12 7 0 2 5 - ns ns ns ns ns ns notes 2 The internal write time is defined by the overlap of CS# = LOW, UB# or LB# = LOW, and WE# = LOW. All conditions must be in valid states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. tPWE > tHZWE + tSD when OE# is LOW. 8ns is at VDD=3.3V +/-10% Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 11 IS61/64WV25616FALL IS61/64WV25616FBLL AC WAVEFORMS WRITE CYCLE NO. 1(1) (CS# CONTROLLED, OE# = HIGH OR LOW) tWC ADDRESS tSCS tSA tHA CS# tAW tPWE WE# tPWB UB#,LB# tHZWE HIGH-Z DOUT DATA UNDEFINED tSD DIN Note: 1. tLZWE tHD DATA IN VALID I/O will assume the High-Z state if CS# = VIH or OE# = VIH. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 12 IS61/64WV25616FALL IS61/64WV25616FBLL WRITE CYCLE NO. 2(1) (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE) tWC ADDRESS tSCS tHA CS# tAW WE# tPWE tSA tPWB UB#,LB# OE# tHZOE DATA UNDEFINED DOUT HIGH-Z (1) tHD tSD DATA IN VALID DIN Note: 1. tHZOE is the time DOUT goes to High-Z after OE# goes high. During this period the I/Os are in output state. Do not apply input signals. WRITE CYCLE NO. 3(1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE) tWC ADDRESS OE# = LOW CS#=LOW tHA tAW tPWE2 WE# tSA UB#,LB# tPWB tHZWE DOUT tLZWE HIGHZ DATA UNDEFINED tSD DIN Note: 1. tHD DATA IN VALID I/O will assume the High-Z state if CS# = VIH or OE# = VIH. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 13 IS61/64WV25616FALL IS61/64WV25616FBLL WRITE CYCLE NO. 4(1, 2, 3) (UB# & LB# Controlled, CS# = OE# = LOW) tWC tWC ADDRESS ADDRESS 1 ADDRESS 2 CS#=LOW OE#=LOW tSA tHA tSA tHA WE# tPWB UB#, LB# tPWB WORD 1 WORD 2 tHZWE DOUT tLZWE HIGH-Z DATA UNDEFINED tHD tSD DIN Notes: 1 2 3 DATA IN VALID DATA IN VALID If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. Due to the restriction of note1, OE# is recommended to be HIGH during write period. WE# stays LOW in this example. If WE# toggles, tPWE and tHZWE must be considered. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 14 IS61/64WV25616FALL IS61/64WV25616FBLL DATA RETENTION CHARACTERISTICS(2) Symbol Parameter VDR VDD for Data Retention Data Retention Current IDR Test Condition OPTION Min. VDD = 2.4V to 3.6V 2.0 Typ. Max. Unit - See Data Retention Waveform V VDD = 1.65V to 2.2V 1.2 Com. - 3 (1) 8 Ind. - - 10 Auto - - 20 VDD= VDR (min), CS# VDD - 0.2V, VIN 0.2V or VIN VDD - 0.2V - mA tSDR Data Retention Setup Time See Data Retention Waveform 0 - - ns tRDR Recovery Time See Data Retention Waveform tRC - - ns Notes: 1. 2. Typical value indicates the value for the center of distribution, measured at VDD = VDR (min.), TA = 25 C and not 100% tested. VDD power down slope must be longer than 100 us/volt when enter into Data Retention Mode. DATA RETENTION WAVEFORM (CS# CONTROLLED) tSDR Data Retention Mode tRDR VDD VDR CS# CS# > VDD - 0.2V GND Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 15 IS61/64WV25616FALL IS61/64WV25616FBLL ORDERING INFORMATION Commercial Range: 0C to +70C, Voltage Range: 2.4V to 3.6V Speed (ns) 10 (8) Note: 1. Order Part No. Package IS61WV25616FBLL-10TL TSOP (Type II) , Lead-free Speed = 8ns when VDD = 3.3V +/-10%. Speed = 10ns when VDD = 2.4V to 3.6V Industrial Range: -40C to +85C, Voltage Range: 1.65V to 2.2V Speed (ns) Order Part No. Package 10 IS61WV25616FALL-10BI 48-ball mini BGA (6mm x 8mm) 10 IS61WV25616FALL-10BLI 48-ball mini BGA (6mm x 8mm), Lead-free 10 IS61WV25616FALL-10B2I 48-ball mini BGA (6mm x 8mm), Switched IO 10 IS61WV25616FALL-10B2LI 48-ball mini BGA (6mm x 8mm), Switched IO, Lead-free 10 IS61WV25616FALL-10TLI TSOP (Type II) , Lead-free Industrial Range: -40C to +85C, Voltage Range: 2.4V to 3.6V Speed (ns)(1) Order Part No. Package 10 (8) IS61WV25616FBLL-10BI 48-ball mini BGA (6mm x 8mm) 10 (8) IS61WV25616FBLL-10BLI 48-ball mini BGA (6mm x 8mm), Lead-free 10 (8) IS61WV25616FBLL-10B2I 48-ball mini BGA (6mm x 8mm), Switched IO 10 (8) IS61WV25616FBLL-10B2LI 48-ball mini BGA (6mm x 8mm), Switched IO, Lead-free 10 (8) IS61WV25616FBLL-10TLI TSOP (Type II) , Lead-free 10 (8) IS61WV25616FBLL-10KLI 400-mil SOJ, Lead-free Note: 1. Speed = 8ns when VDD = 3.3V +/-10%. Speed = 10ns when VDD = 2.4V to 3.6V Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 16 IS61/64WV25616FALL IS61/64WV25616FBLL Automotive (A3) Range: -40C to +125C, Voltage Range: 1.65V to 2.2V Speed (ns) Order Part No. Package 12 IS64WV25616FALL-12BA3 48-ball mini BGA (6mm x 8mm) 12 IS64WV25616FALL-12BLA3 48-ball mini BGA (6mm x 8mm), Lead-free 12 IS64WV25616FALL-12B2A3 48-ball mini BGA (6mm x 8mm), Switched IO 12 IS64WV25616FALL-12B2LA3 48-ball mini BGA (6mm x 8mm), Switched IO, Lead-free 12 IS64WV25616FALL-12CTLA3 TSOP (Type II) , Copper Lead-frame, Lead-free Automotive (A3) Range: -40C to +125C, Voltage Range: 2.4V to 3.6V Speed (ns) Order Part No. Package 10 IS64WV25616FBLL-10BA3 48-ball mini BGA (6mm x 8mm) 10 IS64WV25616FBLL-10BLA3 48-ball mini BGA (6mm x 8mm), Lead-free 10 IS64WV25616FBLL-10B2A3 48-ball mini BGA (6mm x 8mm), Switched IO 10 IS64WV25616FBLL-10B2LA3 48-ball mini BGA (6mm x 8mm), Switched IO, Lead-free 10 IS64WV25616FBLL-10CTLA3 TSOP (Type II) , Copper Lead-frame, Lead-free Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 17 IS61/64WV25616FALL IS61/64WV25616FBLL PACKAGE INFORMATION Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 18 IS61/64WV25616FALL IS61/64WV25616FBLL Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 19 IS61/64WV25616FALL IS61/64WV25616FBLL Integrated Silicon Solution, Inc.- www.issi.com Rev. A 04/27/2018 20