IS61/64WV25616FALL
IS61/64WV25616FBLL
Integrated Silicon Solution, Inc.- www.issi.com 1
Rev. A
04/27/2018
256Kx16 HIGH SPEED AYNCHRONOUS
CMOS STATIC RAM
KEY FEATURES
High-speed access time: 8, 10ns, 12ns
Low Active Current: 35mA (Max., 10ns, I-temp)
Low Standby Current: 10 mA (Max., I-temp)
Single power supply
– 1.65V-2.2V VDD (IS61/64WV25616FALL)
– 2.4V-3.6V VDD (IS61/64WV25616FBLL)
Three state outputs
Data Control for upper and lower bytes
Industrial and Automotive temperature support
Lead-free available
FUNCTIONAL BLOCK DIAGRAM
COLUMN I/O
OE#
CS#
UB#
WE# CONTROL
CIRCUIT
I/O
DATA
CIRCUIT
256K x 16
MEMORY
ARRAY
DECODER
VDD
GND
A0 – A17
I/O0 – I/O7
LB#
I/O8 – I/O15
DESCRIPTION
The ISSI IS61/64WV25616FALL/FBLL are high-speed, low
power, 4M bit static RAMs organized as 256K words by 16
bits. It is fabricated using ISSI's high-performance CMOS
technology.
This highly reliable process coupled with innovative circuit
design techniques, yields high-performance and low power
devices.
When CS# is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE#) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB#) and Lower Byte (LB#)
access.
The IS61/64WV25616FALL/FBLL are packaged in the
JEDEC standard 48-ball mini BGA (6mm x 8mm), 44-pin
400mil SOJ, and 44-pin TSOP (TYPE II)
Copyright © 2018 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
APRIL 2018
IS61/64WV25616FALL
IS61/64WV25616FBLL
Integrated Silicon Solution, Inc.- www.issi.com 2
Rev. A
04/27/2018
PIN CONFIGURATIONS
48-Ball mini BGA(6mm x 8mm),
(Package Code : B)
LB# A0OE# A1 A2 NC
I/O8 A3UB# A4 CS# I/O0
I/O9 A5I/O10 A6 I/O1 I/O2
VSS A17I/O11 A7 I/O3 VDD
VDD NCI/O12 A16 I/O4 VSS
I/O14 A14I/O13 A15 I/O5 I/O6
I/O15 A12NC A13 WE# I/O7
NC A9A8 A10 A11 NC
1 2 3 4 5 6
A
B
C
D
E
F
G
H
48-Ball mini BGA (6mm x 8mm) , Switched IO
(Package Code : B2)
LB# A0OE# A1 A2 NC
I/O0 A3UB# A4 CS# I/O8
I/O1 A5I/O2 A6 I/O10 I/O9
VSS A17I/O3 A7 I/O11 VDD
VDD NCI/O4 A16 I/O12 VSS
I/O6 A14I/O5 A15 I/O13 I/O14
I/O7 A12NC A13 WE# I/O15
NC A9A8 A10 A11 NC
1 2 3 4 5 6
A
B
C
D
E
F
G
H
44-Pin TSOP-II and SOJ, (Package Code : T and K)
A0
A1
A2
A3
A4
CS#
I/O0
I/O1
I/O2
I/O3
VDD
VSS
I/O4
I/O5
I/O6
I/O7
WE#
A5
A6
A7
A8
A9
A17
A16
A15
OE#
UB#
LB#
I/O15
I/O14
I/O13
I/O12
VDD
VSS
I/O11
I/O10
I/O9
I/O8
A14
A13
A12
A11
A10
1
2
3
4
5
6
7
8
9
10
12
11
13
14
15
16
32
31
30
29
28
27
26
25
24
23
21
22
20
19
18
17
42
41
40
39
38
37
36
35
34
33
44
43
NC
PIN DESCRIPTIONS
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control
(I/O0-I/O7)
Upper-byte Control
(I/O8-I/O15)
No Connection
Power
Ground
IS61/64WV25616FALL
IS61/64WV25616FBLL
Integrated Silicon Solution, Inc.- www.issi.com 3
Rev. A
04/27/2018
FUNCTION DESCRIPTION
SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM
has three different modes supported. Each function is described below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-15) are placed in a high
impedance state. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (CS#) and Write Enable (WE#) input LOW. The input and output pins (I/O0-
15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB# and LB# enables a
byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified
on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written into the location.
READ MODE
Read operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input HIGH. When OE# is LOW, output
buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a
byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB# being LOW, data from
memory appears on I/O8-15.
In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
TRUTH TABLE
Mode
CS#
WE#
OE#
LB#
UB#
I/O0-I/O7
I/O8-I/O15
VDD Current
Not Selected
H
X
X
X
X
High-Z
High-Z
ISB1, ISB2
Output Disabled
L
H
H
L
L
High-Z
High-Z
ICC
L
H
H
H
L
High-Z
High-Z
Read
L
H
L
L
H
DOUT
High-Z
ICC
L
H
L
H
L
High-Z
DOUT
L
H
L
L
L
DOUT
DOUT
Write
L
L
X
L
H
DIN
High-Z
ICC
L
L
X
H
L
High-Z
DIN
L
L
X
L
L
DIN
DIN
IS61/64WV25616FALL
IS61/64WV25616FBLL
Integrated Silicon Solution, Inc.- www.issi.com 4
Rev. A
04/27/2018
POWER UP INITIALIZATION
The device includes on-chip voltage sensor used to launch POWER-UP initialization process.
When VDD reaches stable level, the device requires 150us of tPU (Power-Up Time) to complete its self-initialization
process.
When initialization is complete, the device is ready for normal operation.
tPU 150 us
VDD
Stable VDD
0V Device Initialization Device for Normal Operation
IS61/64WV25616FALL
IS61/64WV25616FBLL
Integrated Silicon Solution, Inc.- www.issi.com 5
Rev. A
04/27/2018
ABSOLUTE MAXIMUM RATINGS
AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
Vterm
Terminal Voltage with Respect to VSS
–0.5 to VDD + 0.5V
V
VDD
VDD Related to VSS
–0.3 to 4.0
V
tStg
Storage Temperature
–65 to +150
C
PT
Power Dissipation
1.0
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
.
PIN CAPACITANCE (1)
Parameter
Symbol
Test Condition
Max
Units
Input capacitance
CIN
TA = 25°C, f = 1 MHz, VDD = VDD(typ)
6
pF
DQ capacitance (IO0–IO15)
CI/O
8
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
OPERATING RANGE(1)
Range
Ambient
Temperature
PART NUMBER
VDD
SPEED (MAX)
Commercial
0C to +70C
IS61WV25616FALL
1.65V – 2.2V
10 ns
IS61WV25616FBLL
2.4V – 3.6V
3.3V+/-10%
8ns
Industrial
-40C to +85C
IS61WV25616FALL
1.65V – 2.2V
10 ns
IS61WV25616FBLL
2.4V – 3.6V
3.3V+/-10%
8ns
Automotive (A3)
-40C to +125C
IS64WV25616FALL
1.65V – 2.2V
10 ns
IS64WV25616FBLL
2.4V – 3.6V
IS61/64WV25616FALL
IS61/64WV25616FBLL
Integrated Silicon Solution, Inc.- www.issi.com 6
Rev. A
04/27/2018
AC TEST CONDITIONS (OVER THE OPERATING RANGE)
Parameter
Unit
(1.65V~2.2V)
Unit
(2.4V~3.6V)
Unit
(3.3V +/-10%)
Input Pulse Level
0V to VDD
0V to VDD
0V to VDD
Input Rise and Fall Time
1.5 ns
1.5 ns
1.5 ns
Output Timing Reference Level
½ VDD
½ VDD
½ VDD
R1 (ohm)
13500
319
319
R2 (ohm)
10800
353
353
VTM (V)
VDD
VDD
VDD
Output Load Conditions
Refer to Figure 1 and 2
AC TEST LOADS
Output
Zo = 50 ohm 50 ohm
30 pF,
Including
jig
and scope
VDD/2
R1
R2
VTM
OUTPUT 5pF,
Including
jig
and scope
R1
R2
VTM
OUTPUT 5pF,
Including
jig
and scope
FIGURE 1 FIGURE 2
IS61/64WV25616FALL
IS61/64WV25616FBLL
Integrated Silicon Solution, Inc.- www.issi.com 7
Rev. A
04/27/2018
DC ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
(OVER THE OPERATING RANGE)
IS61/64WV25616FALL (VDD = 1.65V – 2.2V)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = -0.1 mA
1.4
—
V
VOL
Output LOW Voltage
IOL = 0.1 mA
—
0.2
V
VIH
(1)
Input HIGH Voltage
1.4
VDD + 0.2
V
VIL
(1)
Input LOW Voltage
–0.2
0.4
V
ILI
Input Leakage
GND < VIN < VDD
–1
1
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
µA
Note:
1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested.
IS61/64WV25616FBLL (VDD = 2.4V – 3.6V)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH
Voltage
2.4V ~ 2.7V
VDD = Min., IOH = -1.0 mA
2.0
—
V
2.7V ~ 3.6V
VDD = Min., IOH = -4.0 mA
2.2
VOL
Output LOW
Voltage
2.4V ~ 2.7V
VDD = Min., IOL = 2.0 mA
—
0.4
V
2.7V ~ 3.6V
VDD = Min., IOL = 8.0 mA
—
0.4
VIH
(1)
Input HIGH Voltage
2.4V ~ 2.7V
2.0
VDD + 0.3
V
2.7V ~ 3.6V
2.0
VIL
(1)
Input LOW Voltage
2.4V ~ 2.7V
–0.3
0.6
V
2.7V ~ 3.6V
–0.3
0.8
ILI
Input Leakage
VSS < VIN < VDD
–2
2
µA
ILO
Output Leakage
VSS < VIN < VDD, Output Disabled
–2
2
µA
Note:
1. VIL(min) = -0.3V DC ; VIL(min) = -2.0V AC (pulse width 2.0ns). Not 100% tested.
VIH (max) = VDD + 0.3V DC ; VIH(max) = VDD + 2.0V AC (pulse width 2.0ns). Not 100% tested.
IS61/64WV25616FALL
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Rev. A
04/27/2018
POWER SUPPLY CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Grade
-8(3)
Max.
-10
Max.
-12
Max.
Unit
ICC
VDD Dynamic Operating
Supply Current
VDD = MAX, IOU T = 0 mA, f = fMAX
Com.
40
30
30
mA
Ind.
45
35
35
Auto.
-
40
40
ICC1
Operating Supply
Current
VDD = MAX,
IOUT = 0 mA, f = 0
Com.
20
20
20
mA
Ind.
25
25
25
Auto.
-
35
35
ISB1
TTL Standby Current
(TTL Inputs)
VDD = MAX,
VIN = VIH or VIL
CS# ≥ VIH , f = 0
Com.
15
15
15
mA
Ind.
20
20
20
Auto.
-
30
30
ISB2
CMOS Standby Current
(CMOS Inputs)
VDD = MAX,
CS# ≥ VDD - 0.2V
VIN ≥ VDD - 0.2V , or VIN ≤ 0.2V
, f = 0
Com.
8
8
8
mA
Ind.
10
10
10
Auto.
-
20
20
Typ. (2)
3
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input line change.
2. Typical value indicate the value for the center of distribution, measured at VDD = 3.0V/1.8V, TA = 25 °C, and not 100% tested.
3. 8ns is at VDD=3.3V +/-10%
IS61/64WV25616FALL
IS61/64WV25616FBLL
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Rev. A
04/27/2018
AC CHARACTERISTICS
(OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
(1)
Parameter
Symbol
-8(3)
-10
-12
unit
notes
Min
Min
Min
Min
Min
Max
Read Cycle Time
tRC
8
-
10
-
12
-
ns
Address Access Time
tAA
-
8
-
10
-
12
ns
Output Hold Time
tOHA
2.0
-
2.5
-
2.5
-
ns
CS# Access Time
tACE
-
8
-
10
-
12
ns
OE# Access Time
tDOE
-
4.5
-
6
-
7
ns
OE# to High-Z Output
tHZOE
0
3
0
5
0
6
ns
2
OE# to Low-Z Output
tLZOE
0
-
0
-
0
-
ns
2
CS# to High-Z Output
tHZCE
0
3
0
5
0
6
ns
2
CS# to Low-Z Output
tLZCE
3
-
3
-
3
-
ns
2
UB#, LB# Access Time
tBA
-
5.5
-
6
-
7
ns
UB#, LB# to High-Z Output
tHZB
0
3
0
5
0
6
ns
2
UB#, LB# to Low-Z Output
tLZB
0
-
0
-
0
-
ns
2
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of VDD/2, input pulse levels of 0V to VDD and output
loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. 8ns is at VDD=3.3V +/-10%
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (ADDRESS CONTROLLED, CS# = OE# = UB# = LB# = LOW, WE# = HIGH)
tRC
Address
DQ 0-15
tOHA tOHA
tAA
PREVIOUS DATA VALID DATA VALID
Notes:
1. The device is continuously selected.
IS61/64WV25616FALL
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Rev. A
04/27/2018
READ CYCLE NO. 2(1) (OE# CONTROLLED, WE# = HIGH)
OE#
CS#
DOUT
tAA
ADDRESS
tRC
tOHA
tDOE
tLZOE
tACS
tLZCS
tHZOE
tHZCS
HIGH-Z DATA VALID
tLZB tHZB
tBA
UB#,LB#
LOW-Z
Note:
1. Address is valid prior to or coincident with CS# LOW transition.
IS61/64WV25616FALL
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Integrated Silicon Solution, Inc.- www.issi.com 11
Rev. A
04/27/2018
WRITE CYCLE AC CHARACTERISTICS
(1)
Parameter
Symbol
-8(3)
-10
-12
unit
notes
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
8
-
10
-
12
-
ns
CS# to Write End
tSCS
6.5
-
8
-
9
-
ns
Address Setup Time to Write End
tAW
6.5
-
8
-
9
-
ns
UB#,LB# to Write End
tPWB
6.5
-
8
-
9
-
ns
Address Hold from Write End
tHA
0
-
0
-
0
-
ns
Address Setup Time
tSA
0
-
0
-
0
-
ns
WE# Pulse Width
tPWE1
6.5
-
8
-
9
-
ns
WE# Pulse Width (OE# = LOW)
tPWE2
8
-
10
-
12
-
ns
2
Data Setup to Write End
tSD
5
-
6
-
7
-
ns
Data Hold from Write End
tHD
0
-
0
-
0
-
ns
WE# LOW to High-Z Output
tHZWE
-
3.5
-
4
-
5
ns
WE# HIGH to Low-Z Output
tLZWE
2
-
2
-
2
-
ns
Notes:
1 The internal write time is defined by the overlap of CS# = LOW, UB# or LB# = LOW, and WE# = LOW. All conditions must be in valid states
to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
2 tPWE > tHZWE + tSD when OE# is LOW.
3 8ns is at VDD=3.3V +/-10%
IS61/64WV25616FALL
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Integrated Silicon Solution, Inc.- www.issi.com 12
Rev. A
04/27/2018
AC WAVEFORMS
WRITE CYCLE NO. 1(1) (CS# CONTROLLED, OE# = HIGH OR LOW)
ADDRESS
CS#
WE#
UB#,LB#
DOUT
DIN
tWC
tHA
tAW tPWE
tPWB
tSA
tHZWE tLZWE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
tSCS
Note:
1. I/O will assume the High-Z state if CS# = VIH or OE# = VIH.
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Rev. A
04/27/2018
WRITE CYCLE NO. 2(1) (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE)
ADDRESS
CS#
WE#
UB#,LB#
DOUT
DIN
tWC
tHA
tAW tPWE
tPWB
tSA
tHZOE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
tSCS
(1)
OE#
Note:
1. tHZOE is the time DOUT goes to High-Z after OE# goes high. During this period the I/Os are in output state. Do not apply input signals.
WRITE CYCLE NO. 3(1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE)
tWC
tHA
tAW
tPWE2
tSA
tHZWE tLZWE
HIGHZ
tSD tHD
DATA UNDEFINED
DATA IN VALID
ADDRESS
CS#=LOW
WE#
DOUT
DIN
OE# = LOW
tPWB
UB#,LB#
Note:
1. I/O will assume the High-Z state if CS# = VIH or OE# = VIH.
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Rev. A
04/27/2018
WRITE CYCLE NO. 4(1, 2, 3) (UB# & LB# Controlled, CS# = OE# = LOW)
ADDRESS
WE#
DOUT
DIN
tSA
tHZWE
tPWB
tHA
DATA IN
VALID
ADDRESS 1 ADDRESS 2
tWC
DATA IN
VALID
DATA UNDEFINED tHD
tSD
HIGH-Z tLZWE
WORD 1 WORD 2
UB#, LB#
tHA
OE#=LOW
CS#=LOW
tSA
tPWB
tWC
Notes:
1 If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
2 Due to the restriction of note1, OE# is recommended to be HIGH during write period.
3 WE# stays LOW in this example. If WE# toggles, tPWE and tHZWE must be considered.
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Integrated Silicon Solution, Inc.- www.issi.com 15
Rev. A
04/27/2018
DATA RETENTION CHARACTERISTICS
(2)
Symbol
Parameter
Test Condition
OPTION
Min.
Typ.
Max.
Unit
VDR
VDD for Data
Retention
See Data Retention Waveform
VDD = 2.4V to 3.6V
2.0
-
V
VDD = 1.65V to 2.2V
1.2
-
IDR
Data Retention
Current
VDD= VDR (min),
CS# ≥ VDD – 0.2V,
VIN ≤ 0.2V or VIN ≥ VDD - 0.2V
Com.
-
3 (1)
8
mA
Ind.
-
-
10
Auto
-
-
20
tSDR
Data Retention
Setup Time
See Data Retention Waveform
0
-
-
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC
-
-
ns
Notes:
1. Typical value indicates the value for the center of distribution, measured at VDD = VDR (min.), TA = 25 °C and not 100% tested.
2. VDD power down slope must be longer than 100 us/volt when enter into Data Retention Mode.
DATA RETENTION WAVEFORM (CS# CONTROLLED)
GND
CS#
VDR
VDD
CS# > VDD – 0.2V
Data Retention Mode
tSDR tRDR
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Integrated Silicon Solution, Inc.- www.issi.com 16
Rev. A
04/27/2018
ORDERING INFORMATION
Commercial Range: 0°C to +70°C, Voltage Range: 2.4V to 3.6V
Speed (ns)
Order Part No.
Package
10 (8)
IS61WV25616FBLL-10TL
TSOP (Type II) , Lead-free
Note:
1. Speed = 8ns when VDD = 3.3V +/-10%. Speed = 10ns when VDD = 2.4V to 3.6V
Industrial Range: -40°C to +85°C, Voltage Range: 1.65V to 2.2V
Speed (ns)
Order Part No.
Package
10
IS61WV25616FALL-10BI
48-ball mini BGA (6mm x 8mm)
10
IS61WV25616FALL-10BLI
48-ball mini BGA (6mm x 8mm), Lead-free
10
IS61WV25616FALL-10B2I
48-ball mini BGA (6mm x 8mm), Switched IO
10
IS61WV25616FALL-10B2LI
48-ball mini BGA (6mm x 8mm), Switched IO, Lead-free
10
IS61WV25616FALL-10TLI
TSOP (Type II) , Lead-free
Industrial Range: -40°C to +85°C, Voltage Range: 2.4V to 3.6V
Speed (ns)(1)
Order Part No.
Package
10 (8)
IS61WV25616FBLL-10BI
48-ball mini BGA (6mm x 8mm)
10 (8)
IS61WV25616FBLL-10BLI
48-ball mini BGA (6mm x 8mm), Lead-free
10 (8)
IS61WV25616FBLL-10B2I
48-ball mini BGA (6mm x 8mm), Switched IO
10 (8)
IS61WV25616FBLL-10B2LI
48-ball mini BGA (6mm x 8mm), Switched IO, Lead-free
10 (8)
IS61WV25616FBLL-10TLI
TSOP (Type II) , Lead-free
10 (8)
IS61WV25616FBLL-10KLI
400-mil SOJ, Lead-free
Note:
1. Speed = 8ns when VDD = 3.3V +/-10%. Speed = 10ns when VDD = 2.4V to 3.6V
IS61/64WV25616FALL
IS61/64WV25616FBLL
Integrated Silicon Solution, Inc.- www.issi.com 17
Rev. A
04/27/2018
Automotive (A3) Range: –40°C to +125°C, Voltage Range: 1.65V to 2.2V
Speed (ns)
Order Part No.
Package
12
IS64WV25616FALL-12BA3
48-ball mini BGA (6mm x 8mm)
12
IS64WV25616FALL-12BLA3
48-ball mini BGA (6mm x 8mm), Lead-free
12
IS64WV25616FALL-12B2A3
48-ball mini BGA (6mm x 8mm), Switched IO
12
IS64WV25616FALL-12B2LA3
48-ball mini BGA (6mm x 8mm), Switched IO, Lead-free
12
IS64WV25616FALL-12CTLA3
TSOP (Type II) , Copper Lead-frame, Lead-free
Automotive (A3) Range: –40°C to +125°C, Voltage Range: 2.4V to 3.6V
Speed (ns)
Order Part No.
Package
10
IS64WV25616FBLL-10BA3
48-ball mini BGA (6mm x 8mm)
10
IS64WV25616FBLL-10BLA3
48-ball mini BGA (6mm x 8mm), Lead-free
10
IS64WV25616FBLL-10B2A3
48-ball mini BGA (6mm x 8mm), Switched IO
10
IS64WV25616FBLL-10B2LA3
48-ball mini BGA (6mm x 8mm), Switched IO, Lead-free
10
IS64WV25616FBLL-10CTLA3
TSOP (Type II) , Copper Lead-frame, Lead-free
IS61/64WV25616FALL
IS61/64WV25616FBLL
Integrated Silicon Solution, Inc.- www.issi.com 18
Rev. A
04/27/2018
PACKAGE INFORMATION
IS61/64WV25616FALL
IS61/64WV25616FBLL
Integrated Silicon Solution, Inc.- www.issi.com 19
Rev. A
04/27/2018
IS61/64WV25616FALL
IS61/64WV25616FBLL
Integrated Silicon Solution, Inc.- www.issi.com 20
Rev. A
04/27/2018