DAC8164
24-BitShiftRegister
SYNC
SCLK
DIN
DataBufferA DACRegisterA
DataBufferB DACRegisterB
DataBufferC DACRegisterC
DataBufferD DACRegisterD
AVDD
VREF REF
H/V OUT
Buffer
Control
Register
Control
ControlLogic
2.5V
Reference
Power-Down
ControlLogic
14-BitDAC
14-BitDAC
14-BitDAC
14-BitDAC
V A
OUT
V B
OUT
V C
OUT
V D
OUT
GND LDAC ENABLEA1A0
DAC8164
IOVDD VREFL
DAC8164
www.ti.com
SBAS410B FEBRUARY 2008REVISED MAY 2011
14-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output
DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference
Check for Samples: DAC8164
1FEATURES DESCRIPTION
The DAC8164 is a low-power, voltage-output,
234Relative Accuracy: 1LSB four-channel, 14-bit digital-to-analog converter (DAC).
Glitch Energy: 0.15nV-s The device includes a 2.5V, 2ppm/°C internal
Internal Reference: reference (enabled by default), giving a full-scale
output voltage range of 2.5V. The internal reference
2.5V Reference Voltage (enabled by default) has an initial accuracy of 0.004% and can source up
0.004% Initial Accuracy (typ) to 20mA at the VREFH/VREFOUT pin. The device is
2ppm/°C Temperature Drift (typ) monotonic, provides very good linearity, and
minimizes undesired code-to-code transient voltages
5ppm/°C Temperature Drift (max) (glitch). The DAC8164 uses a versatile 3-wire serial
20mA Sink/Source Capability interface that operates at clock rates up to 50MHz.
Power-On Reset to Zero-Scale The interface is compatible with standard SPI,
QSPI, Microwire, and digital signal processor
Ultra-Low Power Operation: 1mA at 5V (DSP) interfaces.
Wide Power Supply Range: +2.7V to +5.5V The DAC8164 incorporates a power-on-reset circuit
14-Bit Monotonic Over Temperature Range that ensures the DAC output powers up at zero-scale
Settling Time: 10μsto±0.006% Full-Scale and remains there until a valid code is written to the
Range (FSR) device. The device contains a power-down feature,
Low-Power Serial Interface with accessed over the serial interface, that reduces the
Schmitt-Triggered Inputs: Up to 50MHz current consumption of the device to 1.3μA at 5V.
Power consumption is 2.6mW at 3V, reducing to
On-Chip Output Buffer Amplifier with 1.4μW in power-down mode. The low power
Rail-to-Rail Operation consumption, internal reference, and small footprint
1.8V to 5.5V Logic Compatibility make this device ideal for portable, battery-operated
Temperature Range: 40°C to +105°Cequipment.
The DAC8164 is drop-in and functionally compatible
APPLICATIONS with the DAC7564 and DAC8564, and functionally
compatible with the DAC7565,DAC8165 and
Portable Instrumentation DAC8565. All these devices are available in a
Closed-Loop Servo-Control TSSOP-16 package.
Process Control, PLCs
Data Acquisition Systems
Programmable Attenuation
PC Peripherals
RELATED
DEVICES 16-BIT 14-BIT 12-BIT
Pin and
Functionally DAC8564 DAC8164 DAC7564
Compatible
Functionally DAC8565 DAC8165 DAC7565
Compatible
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SPI, QSPI are trademarks of Motorola, Inc.
3Microwire is a trademark of National Semiconductor.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©20082011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DAC8164
SBAS410B FEBRUARY 2008REVISED MAY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
RELATIVE DIFFERENTIAL REFERENCE SPECIFIED
ACCURACY NONLINEARITY DRIFT PACKAGE- PACKAGE TEMPERATURE PACKAGE
PRODUCT (LSB) (LSB) (ppm/°C) LEAD DESIGNATOR RANGE MARKING
DAC8164A ±4±1 25 TSSOP-16 PW 40°C to +105°C DAC8164
DAC8164B ±2±1 25 TSSOP-16 PW 40°C to +105°C DAC8164B
DAC8164C ±4±1 5 TSSOP-16 PW 40°C to +105°C DAC8164
DAC8164D ±2±1 5 TSSOP-16 PW 40°C to +105°C DAC8164D
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted). DAC8164 UNIT
AVDD to GND 0.3 to +6 V
Digital input voltage to GND 0.3 to +VDD + 0.3 V
VOUT to GND 0.3 to +VDD + 0.3 V
VREF to GND 0.3 to +VDD + 0.3 V
Operating temperature range 40 to +125 °C
Storage temperature range 65 to +150 °C
Junction temperature range (TJmax) +150 °C
Power dissipation (TJmax TA)/θJA W
Thermal impedance, θJA +118 °C/W
Thermal impedance, θJC +29 °C/W
Human body model (HBM) 4000 V
ESD rating Charged device model (CDM) 1500 V
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2Copyright ©20082011, Texas Instruments Incorporated
DAC8164
www.ti.com
SBAS410B FEBRUARY 2008REVISED MAY 2011
ELECTRICAL CHARACTERISTICS
At AVDD = 2.7V to 5.5V and 40°C to +105°C range (unless otherwise noted). DAC8164
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
Resolution 14 Bits
Measured by the line DAC8164A, DAC8164C ±1±4 LSB
Relative accuracy passing through DAC8164B, DAC8164D ±1±2 LSB
codes 120 and 16200
Differential nonlinearity 14-bit monotonic ±0.3 ±1 LSB
Offset error ±5±8 mV
Offset error drift ±1μV/°C
Measured by the line passing through codes 120 and
16200.
Full-scale error ±0.2 ±0.5 % of FSR
Gain error ±0.05 ±0.2 % of FSR
AVDD = 5V ±1ppm of
Gain temperature coefficient FSR/°C
AVDD = 2.7V ±2
PSRR Power-supply rejection ratio Output unloaded 1 mV/V
OUTPUT CHARACTERISTICS(2)
Output voltage range 0 VREF V
To ±0.006% FSR, 0080h to 3F40h, RL= 2k,8 10
0pF <CL<200pF
Output voltage settling time μs
RL= 2k, CL= 500pF 12
Slew rate 2.2 V/μs
RL=470
Capacitive load stability pF
RL= 2k1000
Code change glitch impulse 1LSB change around major carry 0.15 nV-s
Digital feedthrough SCLK toggling, SYNC high 0.15 nV-s
Channel-to-channel dc crosstalk Full-scale swing on adjacent channel 0.25 LSB
Channel-to-channel ac crosstalk 1kHz full-scale sine wave, outputs unloaded 100 dB
DC output impedance At mid-code input 1
Short-circuit current 50 mA
Coming out of power-down mode, AVDD = 5V 2.5
Power-up time μs
Coming out of power-down mode, AVDD = 3V 5
AC PERFORMANCE(2)
SNR 87 dB
THD 78 dB
TA= +25°C, BW = 20kHz, VDD = 5V, fOUT = 1kHz.
First 19 harmonics removed for SNR calculation.
SFDR 79 dB
SINAD 77 dB
DAC output noise density TA= +25°C, at mid-code input, fOUT = 1kHz 120 nV/Hz
DAC output noise TA= +25°C, at mid-code input, 0.1Hz to 10Hz 6 μVPP
REFERENCE
AVDD = 5.5V 360 μA
Internal reference current consumption AVDD = 3.6V 348 μA
External VREF = 2.5V, if internal reference is disabled,
External reference current 80 μA
all four channels active
Reference input range VREFH voltage VREFL<VREFH, AVDD (VREFH + VREFL) /2 >1.2V 0 AVDD V
Reference input range VREFL voltage VREFL<VREFH, AVDD (VREFH + VREFL) /2 >1.2V 0 AVDD/2 V
Reference input impedance 31 k
(1) Linearity calculated using a reduced code range of 120 to 16200; output unloaded.
(2) Ensured by design or characterization; not production tested.
Copyright ©20082011, Texas Instruments Incorporated 3
DAC8164
SBAS410B FEBRUARY 2008REVISED MAY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At AVDD = 2.7V to 5.5V and 40°C to +105°C range (unless otherwise noted). DAC8164
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE OUTPUT
Output voltage TA= +25°C 2.4975 2.5 2.5025 V
Initial accuracy TA= +25°C0.1 ±0.004 0.1 %
DAC8164A, DAC8164B(3) 5 25
Output voltage temperature drift ppm/°C
DAC8164C, DAC8164D(4) 2 5
Output voltage noise f = 0.1Hz to 10Hz 12 μVPP
TA= +25°C, f = 1MHz, CL= 0μF 50
Output voltage noise density TA= +25°C, f = 1MHz, CL= 1μF 20 nV/Hz
(high-frequency noise) TA= +25°C, f = 1MHz, CL= 4μF 16
Load regulation, sourcing(5) TA= +25°C 30 μV/mA
Load regulation, sinking(5) TA= +25°C 15 μV/mA
Output current load capability(6) ±20 mA
Line regulation TA= +25°C 10 μV/V
Long-term stability/drift (aging)(5) TA= +25°C, time = 0 to 1900 hours 50 ppm
First cycle 100
Thermal hysteresis(5) ppm
Additional cycles 25
LOGIC INPUTS(6)
Input current ±1μA
2.7V IOVDD 5.5V 0.3 ×IOVDD
VINL Logic input LOW voltage V
1.8V IOVDD 2.7V 0.1 ×IOVDD
2.7V IOVDD 5.5V 0.7 ×IOVDD
VINH Logic input HIGH voltage V
1.8V IOVDD 2.7V 0.95 ×IOVDD
Pin capacitance 3 pF
POWER REQUIREMENTS
AVDD 2.7 5.5 V
IOVDD 1.8 5.5 V
IOIDD (6) 10 20 μA
AVDD = IOVDD = 3.6V to 5.5V 1 1.6
VINH = IOVDD and VINL = GND
Normal mode mA
AVDD = IOVDD = 2.7V to 3.6V 0.95 1.5
VINH = IOVDD and VINL = GND
IDD (7) AVDD = IOVDD = 3.6V to 5.5V 1.3 3.5
VINH = IOVDD and VINL = GND
All power-down modes μA
AVDD = IOVDD = 2.7V to 3.6V 0.5 2.5
VINH = IOVDD and VINL = GND
AVDD = IOVDD = 3.6V to 5.5V 3.6 8.8
VINH = IOVDD and VINL = GND
Normal mode mW
AVDD = IOVDD = 2.7V to 3.6V 2.6 5.4
VINH = IOVDD and VINL = GND
Power
Dissipation (7) AVDD = IOVDD = 3.6V to 5.5V 4.7 19
VINH = IOVDD and VINL = GND
All power-down modes μW
AVDD = IOVDD = 2.7V to 3.6V 1.4 9
VINH = IOVDD and VINL = GND
TEMPERATURE RANGE
Specified performance 40 +105 °C
(3) Reference is trimmed and tested at room temperature, and is characterized from 40°C to +120°C.
(4) Reference is trimmed and tested at two temperatures (+25°C and +105°C), and is characterized from 40°C to +120°C.
(5) Explained in more detail in the Application Information section of this data sheet.
(6) Ensured by design or characterization; not production tested.
(7) Input code = 8192, reference current included, no load.
4Copyright ©20082011, Texas Instruments Incorporated
V A
OUT LDAC
ENABLE
A1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DAC8164
V B
OUT
V H/V OUT
REF REF
AVDD
V L
REF
GND
V C
OUT
V D
OUT
A0
IOVDD
DIN
SCLK
SYNC
DAC8164
www.ti.com
SBAS410B FEBRUARY 2008REVISED MAY 2011
PIN CONFIGURATIONS
PW PACKAGE
TSSOP-16
(Top View)
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1 VOUTA Analog output voltage from DAC A
2 VOUTB Analog output voltage from DAC B
VREFH/
3 Positive reference input / reference output 2.5V if internal reference used.
VREFOUT
4 AVDD Power-supply input, 2.7V to 5.5V
5 VREFL Negative reference input
6 GND Ground reference point for all circuitry on the part
7 VOUTC Analog output voltage from DAC C
8 VOUTD Analog output voltage from DAC D
Level-triggered control input (active low). This input is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output
9 SYNC updates following the 24th clock. If SYNC is taken high before the 24th clock edge, the rising edge of SYNC acts as
an interrupt, and the write sequence is ignored by the DAC8164. Schmitt-Trigger logic input.
10 SCLK Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input.
Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input.
11 DIN Schmitt-Trigger logic input.
12 IOVDD Digital input-output power supply
13 A0 Address 0sets device address; see Table 5.
14 A1 Address 1sets device address; see Table 5.
15 ENABLE The enable pin (active low) connects the SPI interface to the serial port
16 LDAC Load DACs; rising edge triggered, loads all DAC registers
Copyright ©20082011, Texas Instruments Incorporated 5
SCLK 1
24
SYNC
DIN DB23 DB0 DB23
t10
t6
t3
t2
t1
t7
t5
t4
t8
ENABLE
t9
t13
t12
t11
LDAC
t14
t15
DAC8164
SBAS410B FEBRUARY 2008REVISED MAY 2011
www.ti.com
SERIAL WRITE OPERATION
6Copyright ©20082011, Texas Instruments Incorporated
DAC8164
www.ti.com
SBAS410B FEBRUARY 2008REVISED MAY 2011
TIMING REQUIREMENTS(1) (2)
At AVDD = IOVDD= 2.7V to 5.5V and 40°C to +105°C range (unless otherwise noted). DAC8164
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOVDD = AVDD = 2.7V to 3.6V 40
t1(3) SCLK cycle time ns
IOVDD = AVDD = 3.6V to 5.5V 20
IOVDD = AVDD = 2.7V to 3.6V 20
t2SCLK HIGH time ns
IOVDD = AVDD = 3.6V to 5.5V 10
IOVDD = AVDD = 2.7V to 3.6V 20
t3SCLK LOW time ns
IOVDD = AVDD = 3.6V to 5.5V 10
IOVDD = AVDD = 2.7V to 3.6V 0
t4SYNC to SCLK rising edge setup time ns
IOVDD = AVDD = 3.6V to 5.5V 0
IOVDD = AVDD = 2.7V to 3.6V 5
t5Data setup time ns
IOVDD = AVDD = 3.6V to 5.5V 5
IOVDD = AVDD = 2.7V to 3.6V 4.5
t6Data hold time ns
IOVDD = AVDD = 3.6V to 5.5V 4.5
IOVDD = AVDD = 2.7V to 3.6V 0
t7SCLK falling edge to SYNC rising edge ns
IOVDD = AVDD = 3.6V to 5.5V 0
IOVDD = AVDD = 2.7V to 3.6V 40
t8Minimum SYNC HIGH time ns
IOVDD = AVDD = 3.6V to 5.5V 20
IOVDD = AVDD = 2.7V to 3.6V 130
t924th SCLK falling edge to SYNC falling edge ns
IOVDD = AVDD = 3.6V to 5.5V 130
IOVDD = AVDD = 2.7V to 3.6V 15
SYNC rising edge to 24th SCLK falling edge
t10 ns
(for successful SYNC interrupt) IOVDD = AVDD = 3.6V to 5.5V 15
IOVDD = AVDD = 2.7V to 3.6V 15
t11 ENABLE falling edge to SYNC falling edge ns
IOVDD = AVDD = 3.6V to 5.5V 15
IOVDD = AVDD = 2.7V to 3.6V 10
t12 24th SCLK falling edge to ENABLE rising edge ns
IOVDD = AVDD = 3.6V to 5.5V 10
IOVDD = AVDD = 2.7V to 3.6V 50
t13 24th SCLK falling edge to LDAC rising edge ns
IOVDD = AVDD = 3.6V to 5.5V 50
IOVDD = AVDD = 2.7V to 3.6V 10
t14 LDAC rising edge to ENABLE rising edge ns
IOVDD = AVDD = 3.6V to 5.5V 10
IOVDD = AVDD = 2.7V to 3.6V 10
t15 LDAC HIGH time ns
IOVDD = AVDD = 3.6V to 5.5V 10
(1) All input signals are specified with tR= tF= 3ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See the Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 50MHz at IOVDD = VDD = 3.6V to 5.5V and 25MHz at IOVDD = AVDD = 2.7V to 3.6V.
Copyright ©20082011, Texas Instruments Incorporated 7
2.503
2.502
2.501
2.500
2.499
2.498
2.497
1200 40 6020 100-40 -20
V (V)
REF
Temperature( C)°
10UnitsShown
80
2.503
2.502
2.501
2.500
2.499
2.498
2.497
1200 40 6020 80 100-40 -20
V (V)
REF
Temperature( C)°
13UnitsShown
40
30
20
10
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Population(%)
TemperatureDrift(ppm/°C)
Typ:2ppm/°C
Max:5ppm/ C°
30
20
10
0
13 5 7 9 11 13 15 17 19
Population(%)
TemperatureDrift(ppm/ C)°
Typ:5ppm/°C
Max:25ppm/ C°
200
150
100
50
0
-50
-100
-150
-200
1800
1900
300 600 900 1200 15000
Drift(ppm)
Time(Hours)
20UnitsShown
Average
40
30
20
10
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Typ:1.2ppm/°C
Max:3ppm/°C
Population(%)
TemperatureDrift(ppm/°C)
DAC8164
SBAS410B FEBRUARY 2008REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS: Internal Reference
At TA= +25°C, unless otherwise noted.
INTERNAL REFERENCE VOLTAGE INTERNAL REFERENCE VOLTAGE
vs vs
TEMPERATURE (Grades C and D) TEMPERATURE (Grades A and B)
Figure 1. Figure 2.
REFERENCE OUTPUT TEMPERATURE DRIFT REFERENCE OUTPUT TEMPERATURE DRIFT
(40°C to +120°C, Grades C and D) (40°C to +120°, Grades A and B)
Figure 3. Figure 4.
REFERENCE OUTPUT TEMPERATURE DRIFT LONG-TERM
(0°C to +120°C, Grades C and D) STABILITY/DRIFT (1)
Figure 5. Figure 6.
(1) Explained in more detail in the Application Information section of this data sheet.
8Copyright ©20082011, Texas Instruments Incorporated
V (5 V/div)m
NOISE
Time(2s/div)
12 V(peak-to-peak)m
2.505
2.504
2.495
25-15 -5 15-25
V (V)
REF
I (mA)
LOAD
2.503
2.501
2.502
+25°C
+120 C°
-40°C
2.500
2.496
2.497
2.498
2.499
5-20 -10 0 10 20
2.505
2.504
2.495
25-15 -5 15-25
V (V)
REF
I (mA)
LOAD
2.503
2.501
2.502
2.500
2.496
2.497
2.498
2.499
5-20 -10 0 10 20
+25°C
-40°C
+120°C
2.503
2.502
2.501
2.498
5.53.0 3.5 4.02.5
V (V)
REF
AV (V)
DD
2.500
4.5 5.0
+120 C°
+25 C°
- °40 C
2.499
2.503
2.502
2.501
2.498
5.53.0 3.5 4.02.5
V (V)
REF
AV (V)
DD
2.500
4.5 5.0
+120 C°
+25 C°
- °40 C
2.499
DAC8164
www.ti.com
SBAS410B FEBRUARY 2008REVISED MAY 2011
TYPICAL CHARACTERISTICS: Internal Reference (continued)
At TA= +25°C, unless otherwise noted.
INTERNAL REFERENCE NOISE DENSITY INTERNAL REFERENCE NOISE
vs
FREQUENCY 0.1Hz TO 10Hz
Figure 7. Figure 8.
INTERNAL REFERENCE VOLTAGE INTERNAL REFERENCE VOLTAGE
vs vs
LOAD CURRENT (Grades C and D) LOAD CURRENT (Grades A and B)
Figure 9. Figure 10.
INTERNAL REFERENCE VOLTAGE INTERNAL REFERENCE VOLTAGE
vs vs
SUPPLY VOLTAGE (Grades C and D) SUPPLY VOLTAGE (Grades A and B)
Figure 11. Figure 12.
Copyright ©20082011, Texas Instruments Incorporated 9
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelA,AV =5V, ternalV =4.99V
DD REF
Ex
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelB,AV =5V, ternalV =4.99V
DD REF
Ex
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelC,AV =5V, ternalV =4.99V
DD REF
Ex
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelD,AV =5V, ternalV =4.99V
DD REF
Ex
DAC8164
SBAS410B FEBRUARY 2008REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 5V
At TA= +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (40°C) vs DIGITAL INPUT CODE (40°C)
Figure 13. Figure 14.
LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (40°C) vs DIGITAL INPUT CODE (40°C)
Figure 15. Figure 16.
10 Copyright ©20082011, Texas Instruments Incorporated
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelA,AV =5V, ternalV =4.99V
DD REF
Ex
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelB,AV =5V,ExternalV =4.99V
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelC,AV =5V, ternalV =4.99V
DD REF
Ex
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelD,AV =5V, ternalV =4.99V
DD REF
Ex
DAC8164
www.ti.com
SBAS410B FEBRUARY 2008REVISED MAY 2011
TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA= +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted. LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C) vs DIGITAL INPUT CODE (+25°C)
Figure 17. Figure 18.
LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C) vs DIGITAL INPUT CODE (+25°C)
Figure 19. Figure 20.
Copyright ©20082011, Texas Instruments Incorporated 11
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelA,AV =5V,ExternalV =4.99V
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelB,AV =4.99V=5V, ternalV
DD REF
Ex
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelC,AV =4.99V=5V,ExternalV
DD REF
2
1
0
-1
-2
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
LE(LSB)
DLE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
ChannelD,AV =5V,ExternalV =4.99V
DD REF
DAC8164
SBAS410B FEBRUARY 2008REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA= +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted. LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C) vs DIGITAL INPUT CODE (+105°C)
Figure 21. Figure 22.
LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C) vs DIGITAL INPUT CODE (+105°C)
Figure 23. Figure 24.
12 Copyright ©20082011, Texas Instruments Incorporated
Temperature( C)°
OffsetError(mV)
40-40 -20 0
4
3
2
1
0
-1
20 60 80 100 120
A =5VVDD
InternalV Enabled
REF ChC
ChB
ChA
ChD
Temperature( C)°
Full-ScaleError(mV)
40-40 -20 0
0.50
0.25
0
-0.25
-0.50
20 60
ChC
ChA ChB
ChD
80 100 120
AVDD =5V
InternalV Enabled
REF
5.5
4.5
3.5
2.5
-0.5
205 10 150
AnalogOutputVoltage(V)
I (mA)
SOURCE/SINK
AV =5V,ChA
DD
InternalReferenceDisabled
1.5
0.5
DACLoadedwith3FFFh
DACLoadedwith0000h
5.5
4.5
3.5
2.5
-0.5
205 10 150
AnalogOutputVoltage(V)
I (mA)
SOURCE/SINK
AV =5V,ChB
DD
InternalReferenceDIsabled
1.5
0.5
DACLoadedwith3FFFh
DACLoadedwith0000h
5.5
4.5
3.5
2.5
-0.5
205 10 150
AnalogOutputVoltage(V)
I (mA)
SOURCE/SINK
AV =5V,ChC
DD
InternalReferenceDisabled
1.5
0.5
DACLoadedwith3FFFh
DACLoadedwith0000h
5.5
4.5
3.5
2.5
-0.5
205 10 150
AnalogOutputVoltage(V)
I (mA)
SOURCE/SINK
AV =5V,ChD
DD
InternalReferenceDisabled
1.5
0.5
DACLoadedwith3FFFh
DACLoadedwith0000h
DAC8164
www.ti.com
SBAS410B FEBRUARY 2008REVISED MAY 2011
TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA= +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted. OFFSET ERROR FULL-SCALE ERROR
vs TEMPERATURE vs TEMPERATURE
Figure 25. Figure 26.
SOURCE AND SINK SOURCE AND SINK
CURRENT CAPABILITY CURRENT CAPABILITY
Figure 27. Figure 28.
SOURCE AND SINK SOURCE AND SINK
CURRENT CAPABILITY CURRENT CAPABILITY
Figure 29. Figure 30.
Copyright ©20082011, Texas Instruments Incorporated 13
0 1638414336122881024081926144
2048 4096
DigitalInputCode
Power-SupplyCurrent( A)m
1300
1200
1100
1000
900
800
AV =5.5V
DD
InternalV Included
REF
Temperature( C)°
Power-SupplyCurrent(mA)
40-40 -20 0
1400
1300
1200
1100
1000
900
800
20 60 80 100 120
AV =5.5V
DD
InternalV Included
REF
DACLoadedwith2000h
1100
1090
1080
1050
5.53.1 3.5 3.92.7
Power-SupplyCurrent( A)m
AV (V)
DD
AV =2.7Vto5.5V
DD
InternalV Included
DACLoadedwith2000h
REF
1070
4.3 4.7 5.1
1060
1.2
1.0
0.2
5.53.1 3.5 3.9 4.32.7
Power-DownCurrent( A)m
AV (V)
DD
0.8
AV =2.7Vto5.5V
DD
REF
InternalV Included
0.6
4.7 5.1
0.4
Temperature( C)°
Power-DownCurrent( A)m
40-40 -20 0
3.0
2.5
2.0
1.5
1.0
0.5
0
20 60 80 100 120
AVDD =5.5V
V (V)
LOGIC
Power-SupplyCurrent(mA)
30 1 2
3200
2800
2400
2000
1600
1200
800
54 6
AV =IOV =5.5V
DD DD REF
,InternalV Included
SYNC Input(allotherdigitalinputs=GND)
Sweepfrom
0Vto5.5V
Sweepfrom
5.5Vto0V
DAC8164
SBAS410B FEBRUARY 2008REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA= +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted. POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE vs TEMPERATURE
Figure 31. Figure 32.
POWER-SUPPLY CURRENT POWER-DOWN CURRENT
vs
POWER-SUPPLY VOLTAGE vs POWER-SUPPLY VOLTAGE
Figure 33. Figure 34.
POWER-DOWN CURRENT POWER-SUPPLY CURRENT
vs TEMPERATURE vs LOGIC INPUT VOLTAGE
Figure 35. Figure 36.
14 Copyright ©20082011, Texas Instruments Incorporated
0 54321
f (kHz)
OUT
THD(dB)
-40
-50
-60
-70
-80
-90
-100
THD
ChannelA,AVDD REF
=5V,ExternalV =4.99V
-1dBFSRDigitalInput,f =225kSPS
S
MeasurementBandwidth=20kHz
3rdHarmonic
2ndHarmonic
0 54321
f (kHz)
OUT
THD(dB)
-40
-50
-60
-70
-80
-90
-100
THD
ChannelB,AV =5V,ExternalV =4.99V
DD REF
-1dBFSRDigitalInput,f =225kSPS
S
MeasurementBandwidth=20kHz
3rdHarmonic
2ndHarmonic
0 54321
f (kHz)
OUT
THD(dB)
-40
-50
-60
-70
-80
-90
-100
THD
ChannelC,AV =5V,ExternalV =4.99V
DD REF
-1dBFSRDigitalInput,f =225kSPS
S
MeasurementBandwidth=20kHz
3rdHarmonic
2ndHarmonic
0 54321
f (kHz)
OUT
THD(dB)
-40
-50
-60
-70
-80
-90
-100
THD
3rdHarmonic
ChannelD,AV =5V,ExternalV =4.99V
DD REF
-1dBFSRDigitalInput,f =225kSPS
S
MeasurementBandwidth=20kHz
2ndHarmonic
60
40
20
0
Occurrence(%)
AV =5.5V
DD
InternalV Included
REF
50
30
10
950 1000 1050 1100 1150 1200