1. General description
The 74HC02; 74HCT02 are high-speed Si-gate CMOS devices that comply with JEDEC
standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC02; 74HCT02 provides a quad 2-input NOR function.
2. Features
nInput levels:
uFor 74HC02: CMOS level
uFor 74HCT02: TTL level
nESD protection:
uHBM JESD22-A114E exceeds 2000 V
uMM JESD22-A115-A exceeds 200 V
nMultiple package options
nSpecified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
74HC02; 74HCT02
Quad 2-input NOR gate
Rev. 03 — 18 September 2008 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC02N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT02N
74HC02D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width
3.9 mm SOT108-1
74HCT02D
74HC02DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm SOT337-1
74HCT02DB
74HC02PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74HCT02PW
74HC02BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 ×3×0.85 mm
SOT762-1
74HCT02BQ
74HC_HCT02_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 18 September 2008 2 of 15
NXP Semiconductors 74HC02; 74HCT02
Quad 2-input NOR gate
4. Functional diagram
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)
mna216
1A
1B 1Y
3
21
2A
2B 2Y
6
54
3A
3B 3Y
9
810
4A
4B 4Y
12
11 13
001aah084
21
3
54
≥1
6
≥1
810
≥1
9
11 13
≥1
12
mna215
A
B
Y
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14
02
1Y VCC
1A 4Y
1B 4B
2Y 4A
2A 3Y
2B 3B
GND 3A
001aac919
1
2
3
4
5
6
78
10
9
12
11
14
13
001aac920
02
Transparent top view
2B 3B
2A 3Y
2Y 4A
1B 4B
1A 4Y
GND
3A
1Y
VCC
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
GND(1)
Table 2. Pin description
Symbol Pin Description
1Y to 4Y 1, 4, 10, 13 data output
1A to 4A 2, 5, 8, 11 data input
1B to 4B 3, 6, 9,12 data input
GND 7 ground (0 V)
VCC 14 supply voltage
74HC_HCT02_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 18 September 2008 3 of 15
NXP Semiconductors 74HC02; 74HCT02
Quad 2-input NOR gate
6. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C.
8. Recommended operating conditions
Table 3. Function table[1]
Input Output
nA nB nY
LLH
XHL
HXL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7 V
IIK input clamping current VI < −0.5 V or VI>V
CC + 0.5 V [1] -±20 mA
IOK output clamping current VO<−0.5 V or VO>V
CC + 0.5 V [1] -±20 mA
IOoutput current −0.5 V < VO < VCC + 0.5 V - ±25 mA
ICC supply current - 50 mA
IGND ground current −50 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation [2]
DIP14 package - 750 mW
SO14, (T)SSOP14 and
DHVQFN14 packages - 500 mW
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC02 74HCT02 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature −40 - +125 −40 - +125 °C
74HC_HCT02_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 18 September 2008 4 of 15
NXP Semiconductors 74HC02; 74HCT02
Quad 2-input NOR gate
9. Static characteristics
∆t/∆V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 5. Recommended operating conditions
…continued
Voltages are referenced to GND (ground = 0 V)
…continued
Symbol Parameter Conditions 74HC02 74HCT02 Unit
Min Typ Max Min Typ Max
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74HC02
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = −4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = −5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC = 6.0 V --±0.1 - ±1-±1µA
ICC supply current VI = VCC or GND; IO=0A;
VCC = 6.0 V - - 2.0 - 20 - 40 µA
CIinput
capacitance - 3.5 - - - - - pF
74HC_HCT02_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 18 September 2008 5 of 15
NXP Semiconductors 74HC02; 74HCT02
Quad 2-input NOR gate
10. Dynamic characteristics
74HCT02
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA 4.4 4.5 - 4.4 - 4.4 - V
IO = −4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 6.0 V - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC = 6.0 V --±0.1 - ±1-±1µA
ICC supply current VI = VCC or GND; IO=0A;
VCC = 6.0 V - - 2.0 - 20 - 40 µA
∆ICC additional
supply current per input pin;
VI=V
CC −2.1 V; IO=0A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
- 150 540 - 675 - 735 µA
CIinput
capacitance - 3.5 - - - - - pF
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
Table 7. Dynamic characteristics
GND=0V;
C
L
=50pF;
for load circuit see Figure 7.
Symbol Parameter Conditions 25 °C−40 °C to +125 °C Unit
Min Typ Max Max
(85 °C) Max
(125 °C)
74HC02
tpd propagation delay nA, nB to nY; see Figure 6 [1]
VCC = 2.0 V - 25 90 115 135 ns
VCC = 4.5 V - 9 18 23 27 ns
VCC = 5.0 V; CL=15pF - 7 - - - ns
VCC = 6.0 V - 7 15 20 23 ns
tttransition time see Figure 6 [2]
VCC = 2.0 V - 19 75 95 110 ns
VCC = 4.5 V - 7 15 19 22 ns
VCC = 6.0 V - 6 13 16 19 ns
CPD power dissipation
capacitance per package; VI= GND to VCC [3] -22- - -pF
74HC_HCT02_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 18 September 2008 6 of 15
NXP Semiconductors 74HC02; 74HCT02
Quad 2-input NOR gate
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD ×VCC2×fi×N+∑ (CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL×VCC2×fo) = sum of outputs.
11. Waveforms
74HCT02
tpd propagation delay nA, nB to nY; see Figure 6 [1]
VCC = 4.5 V - 11 19 24 29 ns
VCC = 5.0 V; CL=15pF - 9 - - - ns
tttransition time VCC = 4.5 V; see Figure 6 [2] - 7 15 19 22 ns
CPD power dissipation
capacitance per package;
VI= GND to VCC −1.5 V [3] -24- - -pF
Table 7. Dynamic characteristics
GND=0V;
C
L
=50pF;
for load circuit see Figure 7.
Symbol Parameter Conditions 25 °C−40 °C to +125 °C Unit
Min Typ Max Max
(85 °C) Max
(125 °C)
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Input to output propagation delays
001aai814
nA, nB input
VI
GND
VOH
VOL
nY output
tTHL tTLH
VM
VM
VX
VY
tPHL tPLH
Table 8. Measurement points
Type Input Output
VMVMVXVY
74HC02 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT02 1.3 V 1.3 V 0.1VCC 0.9VCC
74HC_HCT02_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 18 September 2008 7 of 15
NXP Semiconductors 74HC02; 74HCT02
Quad 2-input NOR gate
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 7. Load circuitry for measuring switching times
001aah768
tW
tW
tr
tr
tf
VM
VI
negative
pulse
GND
VI
positive
pulse
GND
10 %
90 %
90 %
10 % VMVM
VM
tf
VCC
DUT
RT
VIVO
CL
G
Table 9. Test data
Type Input Load Test
VItr, tfCL
74HC02 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HCT02 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HC_HCT02_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 18 September 2008 8 of 15
NXP Semiconductors 74HC02; 74HCT02
Quad 2-input NOR gate
12. Package outline
Fig 8. Package outline SOT27-1 (DIP14)
UNIT A
max. 1 2 (1) (1)
b1cD (1)
Z
Ee M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT27-1 99-12-27
03-02-13
A
min. A
max. bmax.
w
ME
e1
1.73
1.13 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 2.24.2 0.51 3.2
0.068
0.044 0.021
0.015 0.77
0.73
0.014
0.009 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.0870.17 0.02 0.13
050G04 MO-001 SC-501-14
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
14
1
8
7
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC_HCT02_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 18 September 2008 9 of 15
NXP Semiconductors 74HC02; 74HCT02
Quad 2-input NOR gate
Fig 9. Package outline SOT108-1 (SO14)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HC_HCT02_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 18 September 2008 10 of 15
NXP Semiconductors 74HC02; 74HCT02
Quad 2-input NOR gate
Fig 10. Package outline SOT337-1 (SSOP14)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25 0.2
7.9
7.6 1.03
0.63 0.9
0.7 1.4
0.9 8
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
A
max.
2
74HC_HCT02_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 18 September 2008 11 of 15
NXP Semiconductors 74HC02; 74HCT02
Quad 2-input NOR gate
Fig 11. Package outline SOT402-1 (TSSOP14)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
74HC_HCT02_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 18 September 2008 12 of 15
NXP Semiconductors 74HC02; 74HCT02
Quad 2-input NOR gate
Fig 12. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
74HC_HCT02_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 18 September 2008 13 of 15
NXP Semiconductors 74HC02; 74HCT02
Quad 2-input NOR gate
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT02_3 20080918 Product data sheet - 74HC_HCT02_CNV_2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Added type numbers 74HC02BQ and 74HCT02BQ (DHVQFN14 package)
74HC_HCT02_CNV_2 19970827 Product specification - -
74HC_HCT02_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 18 September 2008 14 of 15
NXP Semiconductors 74HC02; 74HCT02
Quad 2-input NOR gate
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74HC02; 74HCT02
Quad 2-input NOR gate
© NXP B.V. 2008. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 September 2008
Document identifier: 74HC_HCT02_3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Functional description . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Recommended operating conditions. . . . . . . . 3
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16 Contact information. . . . . . . . . . . . . . . . . . . . . 14
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
