CS70DL Embedded DRAM 0.18m Leff Features * * * * * * * * * 0.18m Leff channel length Synchronous DRAM Macro Single core supply voltage: 2.5V 0.2 CAS latency (CL) = 2, Burst length (BL) = 1 Speed: 4 Mb @ 133 MHz, 16 Mb @ 100 MHz Separate Write Data Input and Read Data Output 2.5V, 3.3V, and 5V-tolerant I/O options Advanced packaging Proven design methodology and tool support Description Fujitsu's CS70DL, a 0.25m drawn (0.18m Leff) embedded DRAM product, is based on Fujitsu's state-ofthe-art CMOS process technology-a process designed for demanding performance and integration. Along with superior performance, the CS70DL family offers high density logic gates and embedded DRAMs, with as many as five layers of metal. The CS70DL standard cell library, which is optimized for synthesis-based designs, is the most enhanced library for implementing today's deep submicron system-onsilicon designs. The core process operates at 2.5V 0.2V, and the I/Os operate at 2.5V, 3.3V, and 5V-tolerant conditions. In addition to the traditional QFP packages, the CS70DL family is available in Ball Grid Array and Flip Chip packages. It also offers a rich set of ADCs and DACs, digital and analog PLLs, high-speed RAMs, ROMs, and DRAMs, as well as a variety of other embedded functions. The logic portion of the CS70DL is compatible with the CE71/CS71 series (0.25m embedded arrays and standard cells). Design Methodology Fujitsu's design methodology ensures first-silicon success by integrating proprietary point tools with the most popular sign-off quality, industry-standard CAD tools. The following are among these tools: * * * * Logic design rule checker Delay calculator Quasi three-dimensional parasitic extraction tool BankBase-DRAM Compiler Fujitsu's clock-driven design methodology is devised for low power and low skew. It identifies the best-suited clock distribution strategy for a given design and predicts performance in advance. Fujitsu supports co-simulation, emulation, and high-level floorplanning to ease the power, timing, and size estimation of the design. This enables the designer to make effective architectural-level decisions to achieve optimal design solutions. Fujitsu's design methodology supports cycle-based simulators and formal verification, as well as static timing analysis and the more conventional VHDL and Verilog simulators. Fujitsu's designfor-test strategy includes boundary scan (JTAG), full and partial scan, as well as a built-in self-test for memory. Applications Besides offering exceptional integration and low power consumption, the CS70DL also offers advanced performance, area-optimized memories. High-performance transmission and switching applications, such as high-end graphics PCs and notebooks, game consoles, networking gear, engineering workstations, and mobile communications, can benefit from this technology. CS70DL Embedded DRAM 0.25m DRAM Macro Lineup x32 x48 x64 x96 x128 x192 x256 0.75M 1M 1.5M 2M 2.25M 3M 3.75M 4M 4.5M 5M 5.25M 6M 7M 7.5M 8M 9M 10M 10.5M 12M 14M 16M 133 MHz @2.5V Memory Macros * SRAM compiler: single and dual port (1 R/W, 1R), up to 72 Kb per block * Large size SRAM: 288 Kb * ROM compiler: up to 512 Kb per block Phase-Locked Loops * Analog: up to 400 MHz (622 MHz, 1 GHz under development) I/Os * 2.5V, 3.3V, 5V tolerant * Slew-rate controlled * CMOS, TTL, PCML/PECL, LVDS, PCI, SSTL, AGP, GTL+, 1X, 2X, 4X (under development) 100 MHz @2.5V supported by DRAM compiler supported upon request DRAM and Logic Test Flow Start Wafer Burn-In Probe Test 1 -DRAM DC/Function/AC Tests -DRAM Redundancy Test Laser Repair Probe Test 2 -Logic DC/Function/AC Tests Probe Test 3 -DRAM DC/Function/AC Tests -Logic DC/Function/AC Tests Mixed-Signal Macros D/A Converters * 8-bit, 30 MHz * 8-bit, 250 MHz * 10-bit, 30 MHz * 8-bit, 500 MHz * 10-bit, 1.5 MHz A/D Converters * 6-bit, 300 MHz * 8-bit, 50 MHz * 12-bit, 1 MHz * 10-bit, 20 MHz * 8-bit, 200 kHz Comparator, Voltage Reference ASIC Design Kit and EDA Support Verifire (VCS, Cadence Tools, Synopsys Synthesis) VCS, Verilog-XL, Sign-off Simulation, Veritime, Verifault, Design Compiler (Synopsys) Vhdlfire All Vital compliance tools, Sign-off Simulation, Design Time, Design Compiler Other EDA Tools Primetime, Sunrise, HLD, DesignPower Package Availability No. of Pins Package/Assembly Final Test -DRAM DC/Function/ACTests -Logic DC/Function/AC Tests -DRAM BIST under development End FUJITSU MICROELECTRONICS, INC. Corporate Headquarters 3545 North First Street, San Jose, California 95134-1804 Tel: (800) 866-8608 Fax: (408) 922-9179 E-mail: fmicrc@fmi.fujitsu.com Web Site: http://www.fujitsumicro.com Thin QFP Package (0.5 mm pitch) 100, 120, 144 176 Shrink QFP Package (0.5 mm pitch) 176, 208, 240 Heatspreader QFP Package (0.5 mm pitch) 208, 240, 304 Ball Grid Array (1.27 mm pitch) 256, 352, 420, 672 Tab Ball Grid Array (0.8, 1.0 mm pitch) 304, 352, 420, 520, 620, 720 (c) 1999 Fujitsu Microelectronics, Inc. All company and product names are trademarks or registered trademarks of their respective owners. Printed in the U.S.A. ASIC-FS-20798-3/99