IS63WV1024LL ISSI®
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
1
Rev. 00A
04/23/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
128K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access time: 20ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE options
•CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 2.5V-3.6V VDD power supply
• Packages available:
– 32-pin TSOP (Type II)
– 32-pin sTSOP (Type I)
– 36-Ball miniBGA (6mm x 8mm)
– 44-pin TSOP (Type II)
DESCRIPTION
The ISSI IS63WV1024LL is a very high-speed, low
power, 131,072-word by 8-bit CMOS static RAM. The
IS63WV1024LL is fabricated using ISSI's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design
techniques, yields higher performance and low power
consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input
levels.
The IS63WV1024LL operates from a single VDD power
supply. The IS63WV1024LL is available in 32-pin TSOP
(Type II), 32-pin sTSOP (Type I), 36-Ball miniBGA (6mm
x 8mm), and 44-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
CE
OE
WE
128K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
PRELIMINARY INFORMATION
APRIL 2003
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
04/23/03
IS63WV1024LL ISSI
®
PIN CONFIGURATION
44-Pin TSOP (Type II) (T2)
PIN DESCRIPTIONS
A0-A16 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Bidirectional Ports
VDD Power
GND Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A12
A11
A10
A9
A8
PIN CONFIGURATION
32-Pin TSOP (Type II) (T)
32-Pin sTSOP (Type I) (H)
PIN CONFIGURATION
36-mini BGA (B) (6 mm x 8 mm)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0 A1 NC A3 A6 A8
I/O4 A2 WE A4 A7 I/O0
I/O5 NC A5 I/O1
GND VDD
VDD GND
I/O6 NC NC I/O2
I/O7 OE CE A16 A15 I/O3
A9 A10 A11 A12 A13 A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
V
DD
GND
I/O2
I/O3
WE
A16
A15
A14
A13
NC
NC
NC
NC
NC
NC
A5
A6
A7
A8
OE
I/O7
I/O6
GND
V
DD
I/O5
I/O4
A9
A10
A11
A12
NC
NC
NC
NC
44
43
42
41
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
3
Rev. 00A
04/23/03
IS63WV1024LL ISSI
®
TRUTH TABLE
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE I/O Operation VDD Current
Not Selected X H X High-Z ISB1, I SB2
(Power-down)
Output Disabled H L H High-Z ICC1, ICC2
Read H L L DOUT ICC1, ICC2
Write L L X DIN ICC1, ICC2
OPERATING RANGE (VDD)
Range Ambient Temperature IS63WV1024LL
Commercial 0°C to +70°C 2.5V-3.6V
Industrial –40°C to +85°C 2.5V-3.6V
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to VDD+0.5 V
TSTG Storage Temperature –65 to +150 ° C
PTPower Dissipation 1.5 W
VDD VDD Related to GND -0.2 to +3.9 V
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
04/23/03
IS63WV1024LL ISSI
®
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –1.0 mA 2.2 — V
VOL Output LOW Voltage VDD = Min., IOL = 1.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VDD + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.6 V
ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled – 1 1 µA
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
CAPACITANCE(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 p F
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-20 ns
Symbol Parameter Test Conditions Options Min. Max. Unit
ICC VDD Dynamic Operating VDD = Max.,
COM.
—25 mA
Supply Current IOUT = 0 mA, f = fMAX
IND.
—30
typ.
(2)
—15
ICC1Operating Supply VDD = Max.,
COM.
—5 mA
Current Iout = 0mA, f = 0
IND.
—5
ISB1TTL Standby Current VDD = Max.,
COM.
—2 mA
(TTL Inputs) VIN = VIH or VIL
IND.
—3
CE ≥ VIH, f = 0
ISB2CMOS Standby VDD = Max.,
COM.
—20 uA
Current (CMOS Inputs) CE ≥ VDD – 0.2V,
IND.
—20
VIN ≥ VDD – 0.2V, or typ.
(2)
—4
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=2.5V, TA=25oC. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com —
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5
Rev. 00A
04/23/03
IS63WV1024LL ISSI
®
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0.4V to VDD-0.3V
Input Rise and Fall Times 1.5ns
Input and Output Timing 1.25V
and Reference Level (VRef)
Output Load See Figures 1a and 1b
AC TEST LOADS
Figure 1a. Figure 1b.
30 pF
Including
jig and
scope
Zo=50Ω
OUTPUT VRef
50Ω
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
2.5V
6
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
04/23/03
IS63WV1024LL ISSI
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-20 ns
Symbol Parameter Min. Max. Unit
tRC Read Cycle Time 20 — ns
tAA Address Access Time — 2 0 ns
tOHA Output Hold Time 3 — ns
tACE CE Access Time — 20 n s
tDOE OE Access Time — 8 n s
tLZOE
(2)
OE to Low-Z Output 0 — ns
tHZOE
(2)
OE to High-Z Output 0 8 ns
tLZCE
(2)
CE to Low-Z Output 3 — ns
tHZCE
(2)
CE to High-Z Output 0 8 ns
tPU CE to Power Up Time 0 — n s
tPD CE to Power Down Time — 2 0 n s
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
VDD-0.3V and output loading specified in Figure 1.
2. Tested with the loading specified in Figure 1. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
7
Rev. 00A
04/23/03
IS63WV1024LL ISSI
®
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t AA
t OHA t OHA
t RC
D
OUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
DOUT
t
HZCE
READ CYCLE NO. 2(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
04/23/03
IS63WV1024LL ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-20 ns
Symbol Parameter Min. Max. Unit
tWC Write Cycle Time 20 — n s
tSCE CE to Write End 12 — ns
tAW Address Setup Time to 12 — n s
Write End
tHA Address Hold from 0 — ns
Write End
tSA Address Setup Time 0 — ns
tPWE
1(1)
WE Pulse Width (OE High) 12 — ns
tPWE
2(2)
WE Pulse Width (OE Low) 17 — ns
tSD Data Setup to Write End 9 — ns
tHD Data Hold from Write End 0 — ns
tHZWE
(2)
WE LOW to High-Z Output — 9 n s
tLZWE
(2)
WE HIGH to Low-Z Output 3 — n s
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
VDD-0.3V and output loading specified in Figure 1a.
2. Tested with the loading specified in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
9
Rev. 00A
04/23/03
IS63WV1024LL ISSI
®
AC WAVEFORMS
WRITE CYCLE NO. 2(1)
(WE Controlled, OE = HIGH during Write Cycle)
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR2.eps
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
04/23/03
IS63WV1024LL ISSI
®
DATA RETENTION WAVEFORM (CE Controlled)
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Operations Min. Typ.
(1)
Max. Unit
VDR VDD for Data Retention See Data Retention Waveform 1.2 — 3.6 V
IDR Data Retention Current VDD = 1.2V, CE ≥ VDD – 0.2V
COM.
—420 µA
IND.
—420
tSDR Data Retention Setup Time See Data Retention Waveform 0 — — ns
tRDR Recovery Time See Data Retention Waveform tRC —— ns
Note:
1. Typical values are measured at V
DD
= 2.5V, T
A
= 25
O
C. Not 100% tested.
V
DD
CE ≥ V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
Data Retention Mode
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
11
Rev. 00A
04/23/03
IS63WV1024LL ISSI
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
20 IS63WV1024LL-20T 32-pin TSOP (Type II)
IS63WV1024LL-20H sTSOP (Type I) (8mm x13.4mm)
IS63WV1024LL-20T2 44-pin TSOP (Type II)
IS63WV1024LL-20B mBGA(6mmx8mm)
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
20 IS63WV1024LL-20TI 32-pin TSOP (Type II)
IS63WV1024LL-20HI sTSOP (Type I) (8mm x13.4mm)
IS63WV1024LL-20T2I 44-pin TSOP (Type II)
IS63WV1024LL-20BI mBGA(6mmx8mm)
PACKAGING INFORMATION ISSI®
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. E
01/15/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Mini Ball Grid Array
Package Code: B (36-pin)
Notes:
1. Controlling dimensions are in millimeters.
mBGA - 6mm x 8mm
MILLIMETERS INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 36 36
A — — 1.20 — — 0.047
A1 0.24 — 0.30 0.009 — 0.012
A2 0.60 — — 0.024 — —
D 7.90 8.00 8.10 0.311 0.315 0.319
D1 5.25BSC 0.207BSC
E 5.90 6.00 6.10 0.232 0.236 0.240
E1 3.75BSC 0.148BSC
e 0.75BSC 0.030BSC
b 0.30 0.35 0.40 0.012 0.014 0.016
mBGA - 8mm x 10mm
MILLIMETER INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 36 36
A — — 1.20 — — 0.047
A1 0.24 — 0.30 0.009 — 0.012
A2 0.60 — — 0.024 — —
D 9.90 10.00 10.10 0.390 0.394 0.398
D1 5.25BSC .207BSC
E 7.90 8.00 8.10 0.311 0.315 0.319
E1 3.75BSC 0.148BSC
e 0.75BSC 0.030BSC
b 0.30 0.35 0.40 0.012 0.014 0.016
SEATING PLANE
A
A1
A2
A
B
C
D
E
F
G
H
e
e
D1
E1E
D
φ b (36x)
Top View Bottom View
6 5 4 3 2 11 2 3 4 5 6
A
B
C
D
E
F
G
H
Integrated Silicon Solution, Inc.
PACKAGING INFORMATION ISSI®
Plastic STSOP - 32 pins
Package Code: H (Type I)
Notes:
1. Controlling dimension: millimeters, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protru-
sions and
should be measured from the bottom of the package
.
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
Plastic STSOP (H - Type I)
Millimeters Inches
Symbol Min Max Min Max
Ref. Std.
N 32
A — 1.25 — 0.049
A1 0.05 — 0.002 —
A2 0.95 1.05 0.037 0.041
b 0.17 0.23 0.007 0.009
C 0.14 0.16 0.0055 0.0063
D 13.20 13.60 0.520 0.535
D1 11.70 11.90 0.461 0.469
E 7.90 8.10 0.311 0.319
e 0.50 BSC 0.020 BSC
L 0.30 0.70 0.012 0.028
S 0.28 Typ. 0.011 Typ.
α0° 5° 0° 5°
PK13197H32 Rev. B 04/21/03
D1 SEATING PLANE
C
D
1N
e
S
b
A1
A
A2
E
L
α
PACKAGING INFORMATION ISSI®
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. E
02/20/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Plastic TSOP
Package Code: T (Type II)
D
SEATING PLANE
b
eC
1N/2
N/2+1N
E1
A1
A
E
Lα
ZD
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the bottom of
the package
.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
Plastic TSOP (T - Type II)
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
Ref. Std.
No. Leads (N) 32 44 50
A — 1.20 — 0.047 — 1.20 — 0.047 — 1.20 — 0.047
A1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006
b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018
C 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008
D 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830
E1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471
e 1.27 BSC 0.050 BSC 0.80 BSC 0.032 BSC 0.80 BSC 0.031 BSC
L 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024
ZD 0.95 REF. 0.037 REF. 0.81 REF. 0.032 REF. 0.88 REF. 0.035 REF
α0° 5° 0° 5° 0° 5° 0° 5° 0° 5° 0° 5°
