Low Distortion, High Speed
Rail-to-Rail Input/Output Amplifiers
Data Sheet
AD8027/AD8028
Rev. D Document Feedback
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FEATURES
High speed
190 MHz, −3 dB bandwidth (G = +1)
100 V/µs slew rate
Low distortion
120 dBc at 1 MHz SFDR
80 dBc at 5 MHz SFDR
Selectable input crossover threshold
Low noise
4.3 nV/√Hz
1.6 pA/√Hz
Low offset voltage: 900 µV maximum
Low power: 6.5 mA per amplifier supply current
Power-down mode
No phase reversal: VIN > |VS| + 200 mV
Wide supply range: 2.7 V to 12 V
Small packaging: 8-lead SOIC, 6-lead SOT-23, 10-lead MSOP
Qualified for automotive applications (AD8028WARMZ-R7 only)
APPLICATIONS
Filters
ADC drivers
Level shifting
Buffering
Professional video
Low voltage instrumentation
GENERAL DESCRIPTION
The AD8027/AD80281 are high speed amplifiers with rail-to-rail
input and output that operate on low supply voltages and are
optimized for high performance and a wide dynamic signal range.
The AD8027/AD8028 have low noise (4.3 nV/√Hz, 1.6 pA/√Hz)
and low distortion (120 dBc at 1 MHz). In applications that use a
fraction of or use the entire input dynamic range and require
low distortion, the AD8027/AD8028 are ideal choices.
Many rail-to-rail input amplifiers have an input stage that switches
from one differential pair to another as the input signal crosses
a threshold voltage, which causes distortion. The AD8027/AD8028
have a unique feature that allows the user to select the input
crossover threshold voltage through the DISABLE/SELECT pin
(DISABLE/SELECT x in the 10-lead MSOP, hereafter referred
to as DISABLE/SELECT throughout this data sheet). This feature
controls the voltage at which the complementary transistor
input pairs switch. The AD8027/AD8028 also have intrinsically
low crossover distortion.
1 Protected by U.S. patent numbers 6,486,737B1; 6,518,842B1.
PIN CONNECTION DIAGRAM
Figure 1. 8-Lead SOIC, AD8027
See the Pin Configurations and Function Descriptions section
for additional pin configurations and information about the pin
functions.
With their wide supply voltage range (2.7 V to 12 V) and wide
bandwidth (190 MHz), the AD8027/AD8028 amplifiers are
designed to work in a variety of applications where speed and
performance are needed on low supply voltages. The high per-
formance of the AD8027/AD8028 is achieved with a quiescent
current of only 6.5 mA (typical) per amplifier. The AD8027/
AD8028 have a shutdown mode that is controlled via
the DISABLE/SELECT pin.
The AD8027/AD8028 are available in 8-lead SOIC, 6-lead SOT-23,
and 10-lead MSOP packages. The AD8028WARMZ-R7 is an
automotive grade version, qualified for automotive applications.
See the Automotive Products section for more details. The
AD8027/AD8028 family is designed to work over the extended
temperature range of −40°C to +125°C.
Figure 2. SFDR vs. Output Voltage
DNC = DO NOT CONNECT. DO NOT
CONNECT TO THIS PIN.
DNC
1
–IN
2
+IN
3
–V
S4
+V
S
V
OUT
DNC
8
7
6
5
DISABLE/SELECT
AD8027
03327-101
OUTPUT VOLTAGE (V p-p)
0 1 2 3 4 5 6 7 8 9 10
–140
–120
–100
–80
–60
–40
–20
SF DR ( dB)
G = +1
FRE Q UE NCY = 100kHz
R
L
= 1kΩ
V
S
= ±5V
V
S
= +3V V
S
= +5V
03327-063
AD8027/AD8028 Data Sheet
Rev. D | Page 2 of 27
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Connection Diagram ................................................................ 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 7
Maximum Power Dissipation ..................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 10
Test Circuit ...................................................................................... 19
Theory of Operation ...................................................................... 20
Input Stage ................................................................................... 20
Crossover Selection .................................................................... 20
Output Stage ................................................................................ 21
DC Errors .................................................................................... 21
Wideband Operation ..................................................................... 22
Circuit Considerations .............................................................. 22
Applications Information .............................................................. 24
Using the DISABLE/SELECT Pin ............................................ 24
Driving a 16-Bit ADC ................................................................ 24
Band-Pass Filter .......................................................................... 25
Design Tools and Technical Support ....................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 27
Automotive Products ................................................................. 27
REVISION HISTORY
7/15—Rev. C to Rev. D
Changed SELECT to DISABLE/SELECT, NC to DNC, VS+ to
+VS, and VS− to −VS ....................................................... Throughout
Changes to Features Section, Figure 1, and General Description
Section ................................................................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Added Pin Configurations and Function Descriptions Section 8
Added Figure 4, Figure 5, Table 5, and Table 6; Renumbered
Sequentially ....................................................................................... 8
Added Figure 6, Figure 7, Table 7, and Table 8 ............................. 9
Changes to Figure 10 Caption and Figure 13 Caption .............. 10
Changes to Figure 16 Caption and Figure 19 Caption .............. 11
Changes to Figure 20 Caption and Figure 21 ............................. 12
Changes to Figure 26 Caption....................................................... 13
Changes to Figure 36 and Figure 37............................................. 14
Changes to Figure 42 ...................................................................... 15
Changes to Figure 50 Caption....................................................... 17
Added Test Circuit Section and Figure 59 .................................. 19
Changes to Theory of Operation Section .................................... 20
Changes to Crossover Selection Section and Figure 61 ............ 21
Changes to Wideband Operation Section, Figure 62, Figure 63,
and Figure 64 ................................................................................... 22
Changes to PCB Layout Section ................................................... 23
Changes to Using the DISABLE/SELECT Pin Section and
Table 6 .............................................................................................. 24
Changes to Figure 67 and Design Tools and Technical Support
Section .............................................................................................. 25
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 27
Added Automotive Products Section .......................................... 27
3/05—Rev. B to Rev. C
Updated Format .................................................................. Universal
Change to Figure 1 ............................................................................ 1
10/03—Rev. A to Rev. B
Changes to Figure 1 ........................................................................... 1
8/03—Rev. 0 to Rev. A
Addition of AD8028 ........................................................... Universal
Changes to General Description ..................................................... 1
Changes to Figure 1, Figure 3, Figure 4, Figure 8, Figure 13,
Figure 15, Figure 17 .......................................................... 1, 6, 7, 8, 9
Changes to Figure 58, Figure 60 ............................................. 18, 20
Changes to Specifications ................................................................. 3
Updated Outline Dimensions ....................................................... 22
Updated Ordering Guide .............................................................. 23
3/03—Revision 0: Initial Version
Data Sheet AD8027/AD8028
Rev. D | Page 3 of 27
SPECIFICATIONS
VS = ±5 V at TA = 25°C, RL = 1 kΩ to midsupply, G = +1, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth G = +1, V
OUT
= 0.2 V p-p 138 190 MHz
AD8028W only: T
MIN
to T
MAX
138 MHz
G = +1, V
OUT
= 2 V p-p 20 32 MHz
AD8028W only: T
MIN
to T
MAX
20 MHz
Bandwidth for 0.1 dB Flatness G = +2, V
OUT
= 0.2 V p-p 16 MHz
Slew Rate
G = +1, VOUT = 2 V step
90
V/µs
G = −1, V
OUT
= 2 V step 100 V/µs
Settling Time to 0.1% G = +2, V
OUT
= 2 V step 35 ns
NOISE/DISTORTION PERFORMANCE
Spurious-Free Dynamic Range
(SFDR)
fC = 1 MHz, VOUT = 2 V p-p, RF = 24.9 Ω 120 dBc
f
C
= 5 MHz, V
OUT
= 2 V p-p, R
F
= 24.9 Ω 80 dBc
Input Voltage Noise f = 100 kHz 4.3 nV/√Hz
Input Current Noise f = 100 kHz 1.6 pA/√Hz
Differential Gain Error NTSC, G = +2, R
L
= 150 Ω 0.1 %
Differential Phase Error NTSC, G = +2, R
L
= 150 Ω 0.2 Degrees
Crosstalk, Output to Output G = +1, R
L
= 100 Ω, V
OUT
= 2 V p-p, V
S
= ±5 V at 1 MHz −93 dB
DC PERFORMANCE
Input Offset Voltage DISABLE/SELECT = tristate or open, PNP active 200 800 µV
AD8028W only: T
MIN
to T
MAX
850 µV
DISABLE/SELECT = high, NPN active 240 900 µV
AD8028W only: TMIN to TMAX
900
µV
Input Offset Voltage Drift T
MIN
to T
MAX
1.50 µV/°C
Input Bias Current
1
V
CM
= 0 V, NPN active 4 6 µA
T
MIN
to T
MAX
4 µA
AD8028W only: T
MIN
to T
MAX
6 µA
V
CM
= 0 V, PNP active −8 −11 µA
T
MIN
to T
MAX
−8 µA
AD8028W only: T
MIN
to T
MAX
−11 µA
Input Offset Current AD8028W only: T
MIN
to T
MAX
±0.1 ±0.9 µA
Open-Loop Gain V
OUT
= ±2.5 V, AD8028W only: T
MIN
to T
MAX
100 110 dB
INPUT CHARACTERISTICS
Input Impedance 6 MΩ
Input Capacitance 2 pF
Input Common-Mode Voltage
Range
−5.2 to +5.2 V
Common-Mode Rejection Ratio V
CM
= ±2.5 V 90 110 dB
AD8028W only: T
MIN
to T
MAX
88 dB
DISABLE/SELECT PIN
Selection Input Voltage
Crossover Low T
MIN
to T
MAX
−3.0 V
Crossover High2 Tristate < ±20 µA, T
MIN
to T
MAX
−3.9 to −3.7 V
Disable Input Voltage T
MIN
to T
MAX
−4.6 V
Disable Switching Speed 50% of input to <10% of final V
OUT
980 ns
Enable Switching Speed 45 ns
AD8027/AD8028 Data Sheet
Rev. D | Page 4 of 27
Parameter Test Conditions/Comments Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
(Rising/Falling Edge)
VIN = +6 V to −6 V, G = −1 40/45 ns
Output Voltage Swing AD8028W only: T
MIN
to T
MAX
−4.9 to +4.9 −4.94 to +4.94 V
Short-Circuit Output Sinking and sourcing 120 mA
Off Isolation VIN = 0.2 V p-p, f = 1 MHz, DISABLE/SELECT = low −49 dB
Capacitive Load Drive 30% overshoot 20 pF
POWER SUPPLY
Operating Range 2.7 12 V
Quiescent Current per Amplifier 6.5 8.5 mA
AD8028W only: T
MIN
to T
MAX
9.5 mA
Quiescent Current (Disabled) DISABLE/SELECT = low 370 500 µA
AD8028W only: T
MIN
to T
MAX
500 µA
Power Supply Rejection Ratio
VS ± 1 V, AD8028W only: TMIN to TMAX
90
110
dB
1 No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.
2 It is recommended to float the DISABLE/SELECT pin for crossover high mode.
VS = 5 V at TA = 25°C, RL = 1 kΩ to midsupply, G = +1, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth G = +1, V
OUT
= 0.2 V p-p 131 185 MHz
AD8028W only: T
MIN
to T
MAX
131 MHz
G = +1, V
OUT
= 2 V p-p 18 28 MHz
AD8028W only: T
MIN
to T
MAX
18 MHz
Bandwidth for 0.1 dB Flatness G = +2, V
OUT
= 0.2 V p-p 12 MHz
Slew Rate
G = +1, VOUT = 2 V step
85
V/µs
G = −1, V
OUT
= 2 V step 100 V/µs
Settling Time to 0.1% G = +2, V
OUT
= 2 V step 40 ns
NOISE/DISTORTION PERFORMANCE
Spurious-Free Dynamic Range (SFDR) f
C
= 1 MHz, V
OUT
= 2 V p-p, R
F
= 24.9 Ω 90 dBc
f
C
= 5 MHz, V
OUT
= 2 V p-p, R
F
= 24.9 Ω 64 dBc
Input Voltage Noise f = 100 kHz 4.3 nV/√Hz
Input Current Noise f = 100 kHz 1.6 pA/√Hz
Differential Gain Error NTSC, G = +2, R
L
= 150 Ω 0.1 %
Differential Phase Error NTSC, G = +2, R
L
= 150 Ω 0.2 Degrees
Crosstalk, Output to Output G = +1, RL = 100 Ω, VOUT = 2 V p-p,
V
S
= ±5 V at 1 MHz
−92 dB
DC PERFORMANCE
Input Offset Voltage DISABLE/SELECT = tristate or open, PNP active 200 800 µV
AD8028W only: T
MIN
to T
MAX
850 µV
DISABLE/SELECT = high NPN active 240 900 µV
AD8028W only: TMIN to TMAX
900
µV
Input Offset Voltage Drift T
MIN
to T
MAX
2 µV/°C
Input Bias Current
1
V
CM
= 2.5 V, NPN active 4 6 µA
T
MIN
to T
MAX
4 µA
AD8028W only: T
MIN
to T
MAX
6 µA
V
CM
= 2.5 V, PNP active −8 −11 µA
T
MIN
to T
MAX
−8 µA
AD8028W only: T
MIN
to T
MAX
−11 µA
Input Offset Current AD8028W only: T
MIN
to T
MAX
±0.1 ±0.9 µA
Open-Loop Gain V
OUT
= 1 V to 4 V, AD8028W only: T
MIN
to T
MAX
96 105 dB
Data Sheet AD8027/AD8028
Rev. D | Page 5 of 27
Parameter Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Input Impedance 6 MΩ
Input Capacitance 2 pF
Input Common-Mode Voltage Range −0.2 to +5.2 V
Common-Mode Rejection Ratio
VCM = 0 V to 2.5 V
90
105
dB
AD8028W only: T
MIN
to T
MAX
84 dB
DISABLE/SELECT PIN
Selection Input Voltage
Crossover Low T
MIN
to T
MAX
2.0 V
Crossover High
2
Tristate < ±20 µA, T
MIN
to T
MAX
1.1 to 1.3 V
Disable Input Voltage T
MIN
to T
MAX
0.4 V
Disable Switching Speed 50% of input to <10% of final V
OUT
1100 ns
Enable Switching Speed 50 ns
OUTPUT CHARACTERISTICS
Overdrive Recovery Time
(Rising/Falling Edge)
VIN = −6 V to +1 V, G = −1 50/50 ns
Output Voltage Swing AD8028W only: T
MIN
to T
MAX
0.08 to 4.92 0.04 to 4.96 V
Off Isolation VIN = 0.2 V p-p, f = 1 MHz, DISABLE/SELECT = low −49 dB
Short-Circuit Current Sinking and sourcing 105 mA
Capacitive Load Drive 30% overshoot 20 pF
POWER SUPPLY
Operating Range 2.7 12 V
Quiescent Current per Amplifier 6 8.5 mA
AD8028W only: T
MIN
to T
MAX
9 mA
Quiescent Current (Disabled)
DISABLE
/SELECT = low
320
450
µA
AD8028W only: T
MIN
to T
MAX
450 µA
Power Supply Rejection Ratio V
S
± 1 V, AD8028W only: T
MIN
to T
MAX
90 105 dB
1 No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.
2 It is recommended to float the DISABLE/SELECT pin for crossover high mode.
VS = 3 V at TA = 25°C, RL = 1 kΩ to midsupply, G = +1, unless otherwise noted.
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth G = +1, V
OUT
= 0.2 V p-p 125 180 MHz
AD8028W only: T
MIN
to T
MAX
125 MHz
G = +1, V
OUT
= 2 V p-p 19 29 MHz
AD8028W only: T
MIN
to T
MAX
19 MHz
Bandwidth for 0.1 dB Flatness G = +2, V
OUT
= 0.2 V p-p 10 MHz
Slew Rate G = +1, V
OUT
= 2 V step 73 V/µs
G = −1, V
OUT
= 2 V step 100 V/µs
Settling Time to 0.1% G = +2, V
OUT
= 2 V step 48 ns
NOISE/DISTORTION PERFORMANCE
Spurious-Free Dynamic Range (SFDR) f
C
= 1 MHz, V
OUT
= 2 V p-p, R
F
= 24.9 Ω 85 dBc
f
C
= 5 MHz, V
OUT
= 2 V p-p, R
F
= 24.9 Ω 64 dBc
Input Voltage Noise f = 100 kHz 4.3 nV/√Hz
Input Current Noise
f = 100 kHz
1.6
pA/√Hz
Differential Gain Error NTSC, G = +2, R
L
= 150 Ω 0.15 %
Differential Phase Error NTSC, G = +2, R
L
= 150 Ω 0.20 Degrees
Crosstalk, Output to Output G = +1, RL = 100 Ω, VOUT = 2 V p-p, VS = 3 V at
1 MHz
−89 dB
AD8027/AD8028 Data Sheet
Rev. D | Page 6 of 27
Parameter Test Conditions/Comments Min Typ Max Unit
DC PERFORMANCE
Input Offset Voltage DISABLE/SELECT = tristate or open, PNP active 200 800 µV
AD8028W only: T
MIN
to T
MAX
850 µV
DISABLE/SELECT = high NPN active 240 900 µV
AD8028W only: TMIN to TMAX
900
µV
Input Offset Voltage Drift T
MIN
to T
MAX
2 µV/°C
Input Bias Current
1
V
CM
= 1.5 V, NPN active 4 6 µA
T
MIN
to T
MAX
4 µA
AD8028W only: T
MIN
to T
MAX
6 µA
V
CM
= 1.5 V, PNP active −8 −11 µA
T
MIN
to T
MAX
−8 µA
AD8028W only: T
MIN
to T
MAX
−11 µA
Input Offset Current AD8028W only: T
MIN
to T
MAX
±0.1 ±0.9 µA
Open-Loop Gain V
OUT
= 1 V to 2 V, AD8028W only: T
MIN
to T
MAX
90 100 dB
INPUT CHARACTERISTICS
Input Impedance 6 MΩ
Input Capacitance 2 pF
Input Common-Mode Voltage Range R
L
= 1 kΩ −0.2 to +3.2 V
Common-Mode Rejection Ratio
VCM = 0 V to 1.5 V
88
100
dB
AD8028W only: T
MIN
to T
MAX
78 dB
DISABLE/SELECT PIN
Selection Input Voltage
Crossover Low T
MIN
to T
MAX
2.0 V
Crossover High
2
Tristate < ±20 µA, T
MIN
to T
MAX
1.1 to 1.3 V
Disable Input Voltage T
MIN
to T
MAX
0.4 V
Disable Switching Speed 50% of input to <10% of final V
OUT
1150 ns
Enable Switching Speed 50 ns
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
(Rising/Falling Edge)
VIN = −4 V to +1 V, G = −1 55/55 ns
Output Voltage Swing AD8028W only: T
MIN
to T
MAX
0.07 to 4.93 0.03 to 4.97 V
Short-Circuit Current Sinking and sourcing 72 mA
Off Isolation VIN = 0.2 V p-p, f = 1 MHz, DISABLE/SELECT = low −49 dB
Capacitive Load Drive 30% overshoot 20 pF
POWER SUPPLY
Operating Range 2.7 12 V
Quiescent Current per Amplifier 6.0 8.0 mA
AD8028W only: T
MIN
to T
MAX
9 mA
Quiescent Current (Disabled) DISABLE/SELECT = low 300 420 µA
AD8028W only: T
MIN
to T
MAX
420 µA
Power Supply Rejection Ratio V
S
± 1 V, AD8028W only: T
MIN
to T
MAX
88 100 dB
1 No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.
2 It is recommended to float the DISABLE/SELECT pin for crossover high mode.
Data Sheet AD8027/AD8028
Rev. D | Page 7 of 27
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 12.6 V
Power Dissipation
See Figure 3
Common-Mode Input Voltage ±V
S
± 0.5 V
Differential Input Voltage ±1.8 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +125°C
Lead Temperature Range (Soldering 10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8027/AD8028
package is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8027/AD8028.
Exceeding a junction temperature of 175°C for an extended
period of time can result in changes in the silicon devices,
potentially causing failure.
The still air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and the total power dissipated in the
package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as
TJ = TA + (PD × θJA)
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some in the load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
PD = Quiescent Power + (Total Drive Power − Load Power)
( )
L
OUT
L
OUTS
SS
D
R
V
R
V
V
IVP
2
–
2
×+×=
It is recommended that rms output voltages be considered. If RL
is referenced to –VS, as in single-supply operation, the total
drive power is VS × IOUT.
If the rms signal levels are indeterminate, consider the worst
case, when VOUT = VS/4 for RL to midsupply.
( ) ( )
L
S
SS
D
R
V
IVP
2
4/
+×=
In single-supply operation with RL referenced to –VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θJA. Care must be taken to minimize parasitic capacitances
at the input leads of high speed op amps, as described in the
PCB Layout section.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(125°C/W), 6-lead SOT-23 (170°C/W), and 10-lead MSOP
(130°C/W) packages on a JEDEC standard 4-layer board.
Output Short Circuit
Shorting the output to ground or drawing excessive current
from the AD8027/AD8028 can cause catastrophic failure.
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
AMBI E NT TE M P E RATURE (°C)
MAXIMUM POWER DISSIPATIO N (W)
–55 –35 –15 525 45 65 85 105 125
0
0.5
1.0
1.5
2.0
6-L E AD S OT-23
8-L E AD S O IC
10-L E AD M S OP
03327-002
AD8027/AD8028 Data Sheet
Rev. D | Page 8 of 27
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. 8-Lead SOIC, AD8027 Pin Configuration
Table 5. 8-Lead SOIC, AD8027 Pin Function Descriptions
Pin No. Mnemonic Description
1, 5 DNC Do Not Connect. Do not connect to these pins.
2 −IN Negative Input.
3 +IN Positive Input.
4 −VS Negative Supply.
6 VOUT Output Voltage.
7 +VS Positive Supply
8 DISABLE/SELECT Power-Down/Select. The power-down function places the device into low power
consumption mode. The select function of this pin shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to the other) closer to either the positive
supply rail or the negative supply rail.
Figure 5. 6-Lead SOT-23, AD8027 Pin Configuration
Table 6. 6-Lead SOT-23, AD8027 Pin Function Descriptions
Pin No. Mnemonic Description
1 VOUT Output Voltage.
2 −VS Negative Supply.
3 +IN Positive Input.
4 −IN Negative Input.
5 DISABLE/SELECT Power-Down/Select. The power-down function places the device into low power
consumption mode. The select function of this pin shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to the other) closer to either the positive
supply rail or the negative supply rail.
6 +VS Positive Supply.
DNC = DO NOT CONNECT. DO NOT
CONNECT TO THIS PIN.
DNC
1
–IN
2
+IN
3
–V
S4
+V
S
V
OUT
DNC
8
7
6
5
DISABLE/SELECT
AD8027
03327-001
V
OUT 1
–V
S2
+IN
3
5
6
+V
S
DISABLE/SELECT
4
–IN
+–
AD8027
03327-102
Data Sheet AD8027/AD8028
Rev. D | Page 9 of 27
Figure 6. 8-Lead SOIC, AD8028 Pin Configuration
Table 7. 8-Lead SOIC, AD8028 Pin Function Descriptions
Pin No. Mnemonic Description
1 VOUTA Output Voltage, Channel A.
2 −IN A Negative Input, Channel A.
3 +IN A Positive Input, Channel A.
4 −VS Negative Supply.
5 +IN B Positive Input, Channel B.
6 −IN B Negative Input, Channel B.
7 VOUTB Output Voltage, Channel B.
8 +VS Positive Supply.
Figure 7. 10-Lead MSOP, AD8028 Pin Configuration
Table 8. 10-Lead MSOP, AD8028 Pin Function Descriptions
Pin No. Mnemonic Description
1 VOUTA Output Voltage, Channel A.
2 −IN A Negative Input, Channel A.
3 +IN A Positive Input, Channel A.
4 −VS Negative Supply.
5 DISABLE/SELECT A Power-Down/Select, Channel A. The power-down function places the device into low power
consumption mode. The select function of this pin shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to the other) closer to either the positive
supply rail or the negative supply rail.
6 DISABLE/SELECT B Power-Down/Select, Channel B. The power-down function places the device into low power
consumption mode. The select function of this pin shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to the other) closer to either the positive
supply rail or the negative supply rail.
7 +IN B Positive Input, Channel B.
8 −IN B Negative Input, Channel B.
9 VOUTB Output Voltage, Channel B.
10 +VS Positive Supply.
V
OUTA 1
–IN A
2
+IN A
3
–V
S4
V
OUTB
–IN B
+IN B
8
7
6
5
+V
S
+
–
–
+
AD8028
03327-103
03327-104
V
OUTB
10
9
+V
S
DISABLE/SELECT B
–IN B
+IN B
8
7
6
DISABLE/SELECT A
V
OUTA 1
–IN A
2
+IN A
3
–V
S4
5
+
–
+
–
AD8028
AD8027/AD8028 Data Sheet
Rev. D | Page 10 of 27
TYPICAL PERFORMANCE CHARACTERISTICS
Default conditions: VS = 5 V at TA = 25°C, RL = 1 kΩ, unless otherwise noted.
Figure 8. Small Signal Frequency Response for Various Gains
Figure 9. AD8027 Small Signal Frequency Response for Various Supplies
Figure 10. Large Signal Frequency Response for Various Supplies, G = +1
Figure 11. Small Signal Frequency Response for Various Supplies
Figure 12. AD8028 Small Signal Frequency Response for Various Supplies
Figure 13. Large Signal Frequency Response for Various Supplies, G = +2
FREQUENCY (MHz)
0.1 1 10 100 1000
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
NORMALIZED CLOSED-LOOP GAIN (dB)
V
OUT
= 200mV p-p AD8027
G = +1
AD8028
G = +1
G = +10
G = –1
G = +2
03327-003
FREQUENCY (MHz)
0.1 1 10 100 1000
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
CLOSED- LOOP GAIN (dB)
G = +1
V
OUT
= 200mV p-p
V
S
= +5V
V
S
= 5V
V
S
= +3V
03327-004
100
FREQUENCY (MHz)
0.1 1 10 1000
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
CLOSED-LOOP GAIN (dB)
G = +1
V
OUT
= 2V p-p
V
S
= +5V
V
S
= 5V
V
S
= +3V
03327-005
FREQUENCY (MHz)
0.1 1 10 100 1000
–4
–3
–2
–1
0
1
2
3
4
5
6
7
8
CLOSED-LOOP GAIN (dB)
G = +2
V
OUT
= 200mV p-p
V
S
= +5V
V
S
= 5V
V
S
= +3V
03327-006
FREQUENCY (MHz)
0.1 1 10 100 1000
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
CLOSED-LOOP GAIN (dB)
G = +1
V
OUT
= 200mV p-p
V
S
=±5V
V
S
= +5V
V
S
= +3V
03327-007
FREQUENCY (MHz)
0.1 1 10 100 1000
–4
–3
–2
–1
0
1
2
3
4
5
6
7
8
CLOSED-LOOP GAIN (dB)
G = +2
V
OUT
= 2V p-p
V
S
= 5V
V
S
= +3V
V
S
= +5V
03327-008
Data Sheet AD8027/AD8028
Rev. D | Page 11 of 27
Figure 14. AD8027 Small Signal Frequency Response for Various CLOAD Values
Figure 15. Frequency Response for Various Output Amplitudes
Figure 16. AD8027 Small Signal Frequency Response vs. Frequency for
Various Temperatures
Figure 17. AD8028 Small Signal Frequency Response for Various CLOAD Values
Figure 18. Small Signal Frequency Response for Various RLOAD Values
Figure 19. AD8028 Small Signal Frequency Response vs. Frequency for
Various Temperatures
FREQUENCY (MHz)
0.1 1 10 100 1000
CLOSED-LOOP GAIN (dB)
G = +1
V
OUT
= 200mV p-p
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
C
L
= 0pF
C
L
= 20pF
C
L
= 5pF
03327-009
FREQUENCY (MHz)
0.1 1 10 100 1000
–4
–3
–2
–1
0
1
2
3
4
5
6
7
8
CLOSED-LOOP GAIN (dB)
G = +2 V
OUT
= 200mV p-p
V
OUT
= 2V p-p
V
OUT
= 4V p-p
03327-010
FREQUENCY (MHz)
0.1 1 10 100 1000
–8
–7
–6
–5
–4
–3
–2
–1
1
0
2
CLOSED-LOOP GAIN (dB)
+125°C
–40°C
+25°C
G = +1
V
OUT
= 200mV p-p
03327-011
FREQUENCY (MHz)
0.1 1 10 100 1000
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
3
2
CLOSED-LOOP GAIN (dB)
C
L
= 0pF
C
L
= 20pF
C
L
= 5pF
G = +1
V
OUT
= 200mV p-p
03327-012
FREQUENCY (MHz)
0.1 1 10 100 1000
–4
–3
–2
–1
0
1
2
3
5
4
6
7
8
CLOSED-LOOP GAIN (dB)
G = +2
V
OUT
= 0.2V p-p
R
L
= 1k
V
OUT
= 2.0V p-p
R
L
= 1k
V
OUT
= 2.0V p-p
R
L
= 150
V
OUT
= 0.2V p-p
R
L
= 150
03327-013
FREQUENCY (MHz)
0.1 1 10 100 1000
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
CLOSED-LOOP GAIN (dB)
G = +1
VOUT = 200mV p-p +25°C
–40°C
+125°C
03327-014
AD8027/AD8028 Data Sheet
Rev. D | Page 12 of 27
Figure 20. Small Signal Frequency Response vs. Frequency for Various Input
Common-Mode Voltages
Figure 21. AD8028 Crosstalk, Output to Output (see Figure 59)
Figure 22. Open-Loop Gain and Phase vs. Frequency
Figure 23. Voltage and Current Noise vs. Frequency
Figure 24. 0.1 dB Flatness Frequency Response
Figure 25. Harmonic Distortion vs. Frequency and Supply Voltage
FREQUENCY (MHz)
0.1 1 10 100 1000
CLOSED-LOOP GAIN (dB)
G = +1
V
OUT
= 200mV p-p
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
V
ICM
= +V
S
– 0.2V
DISABLE/SELECT = HIGH
V
ICM
= 0V
DISABLE/SELECT = HIGH OR TRI
V
ICM
= –V
S
+ 0.2V
DISABLE/SELECT = TRI
V
ICM
= +V
S
– 0.3V
DISABLE/SELECT = HIGH
03327-015
V
ICM
= –V
S
+ 0.3V
DISABLE/SELECT = TRI
FREQUENCY (MHz)
0.001 0.01 0.1 1 10 100 1000
–130
–140
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–
10
CROSSTALK (dB)
ATO B
BTOA
03327-016
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
PHASE (Degrees)
10 100 1k 10k 100k 1M 10M 100M 1G
–25
–5
15
35
55
75
95
115
135
–10
0
10
20
30
40
50
60
70
80
90
100
110
GAIN
PHASE
03327-017
1
10 100 1k 10k 100k
FREQUENCY (Hz)
1M 10M 100M 1G
10
100
CURRENT NOISE (pA/ Hz)
1
10
100
VOL
T
AGE NOISE (nV/ Hz)
VOLTAGE
CURRENT
03327-018
100
FREQUENCY (MHz)
0.1 1 10 1000
5.9
6.0
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
CLOSED-LOOP GAIN (dB)
G = +2
R
L
= 150
V
OUT
= 2V p-p
V
OUT
= 200mV p-p
03327-019
FREQUENCY (MHz)
0.1 1 2010
DISTORTION (dB)
–140
–120
–100
–80
–60
–40
–
20
G = +1
V
OUT
= 2V p-p
R
L
= 1k
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
V
S
= +3V
V
S
= +5V
V
S
= 5V
03327-020
Data Sheet AD8027/AD8028
Rev. D | Page 13 of 27
Figure 26. Harmonic Distortion vs. Output Voltage
Figure 27. Harmonic Distortion vs. Input Common-Mode Voltage,
DISABLE/SELECT = High
Figure 28. Harmonic Distortion vs. Frequency and Load
Figure 29. Harmonic Distortion vs. Input Common-Mode Voltage, VS = 5 V
Figure 30. Harmonic Distortion vs. Input Common-Mode Voltage,
DISABLE/SELECT = Trisate or Open
Figure 31. Harmonic Distortion vs. Frequency and Gain
OUTPUT VOLTAGE (V p-p)
012345678910
–140
–120
–100
–80
–60
–40
–
20
DISTORTION (dB)
V
S
= 5V
V
S
= +3V V
S
= +5V
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
03327-021
INPUT COMMON-MODE VOLTAGE (V)
0.51.01.52.02.53.03.54.04.5
DISTORTION (dB)
–140
–130
–120
–110
–100
–90
–80
–70
–60
–
50
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
VS = +3V
VS = +5V
03327-022
FREQUENCY (MHz)
0.1 1 10 20
DISTORTION (dB)
–140
–120
–100
–80
–60
–40
–
20 G = +1 (RF = 24.9
)
VOUT = 2.0V p-p
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
RL = 150
RL = 1k
03327-023
INPUT COMMON-MODE VOLTAGE (V)
0.51.01.52.02.53.03.54.04.5
DISTORTION (dB)
–125
–115
–105
–95
–85
–75
–65
–55
–45
DISABLE/SELECT = HIGH
DISABLE/SELECT = TRI
03327-024
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
INPUT COMMON-MODE VOLTAGE (V)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
DISTORTION (dB)
–140
–130
–120
–110
–100
–90
–80
–70
–60
–
50
G = +1 (R
F
= 24.9
)
V
OUT
= 1.0V p-p AT 100kHz
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
V
S
= +3V
V
S
= +5V
03327-025
FREQUENCY (MHz)
0.1 1 10 20
DISTORTION (dB)
–140
–120
–100
–80
–60
–40
–
20 V
S
= +5
V
OUT
= 2.0V p-p
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
G = +2
G = +1
G = +10
03327-026
AD8027/AD8028 Data Sheet
Rev. D | Page 14 of 27
Figure 32. Small Signal Transient Response
Figure 33. Large Signal Transient Response, G = +1
Figure 34. Large Signal Transient Response, G = +2
Figure 35. Small Signal Transient Response with Capacitive Load
Figure 36. Overdrive Recovery, G = −1
Figure 37. Overdrive Recovery, G = +1
–0.20
–0.15
–0.10
–0.05
0.05
0
0.10
0.15
0.20
G = +1
V
S
=±2.5V
20ns/DIV50mV/DIV
03327-027
–
2.0
–
1.0
0
1.0
2.0
100ns/DIV500mV/DIV
G = +1
V
S
= ±2.5V
V
OUT
= 4V p-p
V
OUT
= 2V p-p
03327-028
–
2.5
–
2.0
–
1.5
–
1.0
–
0.5
0
0.5
1.0
1.5
2.0
2.5
G = +2
V
S
= ±2.5V
V
OUT
= 4V p-p
V
OUT
= 2V p-p
20ns/DIV50mV/DIV
03327-029
–0.20
–0.15
–0.10
–0.05
0.05
0
0.10
0.15
0.20
G = +1
V
S
= ±2.5V C
L
= 20pF
C
L
= 5pF
20ns/DIV50mV/DIV
03327-030
–
4.0
–
3.0
–
2.0
–
1.0
0
1.0
2.0
3.0
4.0
–
3.5
–
2.5
–
1.5
–
0.5
0.5
1.5
2.5
3.5
50ns/DIV500mV/DIV
G = –1
R
L
= 1k
V
S
= ±2.5V
03327-031
INVERTED
INPUT
–
4.0
–
3.0
–
2.0
–
1.0
0
1.0
2.0
3.0
4.0
–
3.5
–
2.5
–
1.5
–
0.5
0.5
1.5
2.5
3.5
50ns/DIV500mV/DIV
G = +1
R
L
= 1k
V
S
= ±2.5V
03327-032
INPUT
Data Sheet AD8027/AD8028
Rev. D | Page 15 of 27
Figure 38. Long-Term Settling Time
Figure 39. 0.1% Short-Term Settling Time
Figure 40. Input Bias Current vs. Temperature
Figure 41. Input Bias Current vs. Input Common-Mode Voltage
Figure 42. Input Offset Voltage Distribution
Figure 43. Input Offset Voltage vs. Temperature
–0.1%
+0.1%
5s/DIV
VIN (200mV/DIV)
VOUT – 2VIN (2mV/DIV)
G = +2
03327-033
–0.1%
+0.1%
20ns/DIV
VIN (200mV/DIV)
VOUT (400mV/DIV)
VOUT – 2VIN (0.1%/DIV)
03327-034
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 11095 125
2.5
3.0
3.5
4.0
4.5
–
6.5
–7.0
–7.5
–8.0
–8.5
V
S
= +3V V
S
= +5V
V
S
=±5V
DISABLE/SELECT = TRI
DISABLE/SELECT = HIGH
03327-035
INPUT BIAS CURRENT [DISABLE/SELECT = HIGH] (µA)
INPUT BIAS CURRENT [DISABLE/SELECT = TRI] (µA)
INPUT COMMON-MODE VOLTAGE (V)
INPUT BIAS CURRENT (A)
012345678910
10
8
6
4
2
0
–2
–4
–6
–8
–
10
V
S
=5V
DISABLE/SELECT = TRI
V
S
= +3V
V
S
= +5V
DISABLE/SELECT = HIGH
03327-036
–800 –600 –400 –200 0 200 400 600 800
INPUT OFFSET VOLTAGE (µV)
0
50
100
150
200
250
FREQUENCY
DISABLE/SELECT = TRI
DISABLE/ SELECT = HIGH
03327-037
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE
(
V)
–40 –25 –10 5 20 35 50 65 80 11095 125
60
80
100
120
140
160
180
200
220
240
260
280
300
320
340
360
DISABLE/SELECT = TRI
V
S
=
5V
V
S
= +5V
DISABLE/SELECT = HIGH
V
S
= +3V
03327-038
AD8027/AD8028 Data Sheet
Rev. D | Page 16 of 27
Figure 44. Input Offset Voltage vs. Input Common-Mode Voltage, VS = ±5 V
Figure 45. Input Offset Voltage vs. Input Common-Mode Voltage, VS = 5 V
Figure 46. Input Offset Voltage vs. Input Common-Mode Voltage, VS = 3 V
Figure 47. Common-Mode Rejection Ratio (CMRR) vs. Frequency
Figure 48. Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 49. Off Isolation vs. Frequency
INPUT COMMON-MODE VOLTAGE (V)
INPUT OFFSET VOLTAGE (
V)
–5–4–3–2–1012345
150
290
170
190
210
230
250
270
DISABLE/SELECT = HIGH
DISABLE/SELECT = TRI
V
S
=
5V
03327-039
INPUT COMMON-MODE VOLTAGE (V)
INPUT OFFSET VOLTAGE (
V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
150
290
170
190
210
230
250
270
DISABLE/SELECT = HIGH
DISABLE/SELECT = TRI
V
S
= +5V
03327-040
INPUT COMMON-MODE VOLTAGE (V)
INPUT OFFSET VOLTAGE (V)
0 0.50 1.00 1.50 2.00 2.50 3.00
150
270
170
190
210
230
250
DISABLE/SELECT = HIGH
DISABLE/SELECT = TRI
V
S
= +3V
03327-041
FREQUENCY (Hz)
CMRR (dB)
1k 10k 100k 1M 10M 100M
0
20
40
60
80
100
120
03327-042
FREQUENCY (Hz)
PSSR (dB)
100 1k 10k 100k 1M 10M 100M 1G
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
–PSRR
+PSRR
03327-043
FREQUENCY (Hz)
OFF ISOLATION (dB)
10k 100k 1M 10M 100M 1G
–100
–90
–80
–70
–60
–50
–40
–30
–
20 V
IN
= 0.2V p-p
G = +1
DISABLE/SELECT = LOW
03327-044
Data Sheet AD8027/AD8028
Rev. D | Page 17 of 27
Figure 50. Output Saturation Voltage vs. Load Resistance
Figure 51. Output Enabled—Impedance vs. Frequency
Figure 52. Output Saturation Voltage vs. Temperature
Figure 53. Open-Loop Gain vs. Load Current
Figure 54. Output Disabled—Impedance vs. Frequency
Figure 55. DISABLE/SELECT Current vs.
DISABLE/SELECT Voltage and Temperature
LOAD RESISTANCE (
)
OUTPUT SATURATION VOLTAGE (mV)
100 1000 10000
–200
200
150
100
50
0
–50
–100
–150
V
S
= +3V V
S
= +5V V
S
=
5V
V
OH
– V
S+
V
OL
– V
S–
LOAD RESISTANCE TIED
TO MIDSUPPLY
03327-045
FREQUENCY (Hz)
1k 10k 100k 1M 10M 100M 1G
0.001
0.01
0.1
1
10
100
OUTPUT IMPEDANCE ()
G = +2
G = +1
G = +5
03327-046
TEMPERATURE (°C)
OUTPUT SATURATION VOLTAGE (mV)
–40 –25 –10 5 20 35 50 65 80 11095 125
25
30
35
40
45
V
OL
– –V
S
V
S
= +5V
R
L
= 1kTIED TO MIDSUPPLY
+V
S
– V
OH
03327-047
I
LOAD
(mA)
OPEN-LOOP GAIN (dB)
0 102030405060
60
130
70
80
90
100
110
120
5V
+5V
+3V
03327-048
FREQUENCY (Hz)
OUTPUT IMPEDANCE (
)
100k 1M 10M 100M 1G
10
100
1k
10k
100k
1M
DISABLE/SELECT = LOW
03327-049
DISABLE/SELECT VOLTAGE (V)
DISABLE/SELECT CURRENT (
A)
0 0.5 1.0 1.5 2.0 2.5 3.0
–80
–60
–40
–20
0
20
40
60
80
V
S
= +5V
V
S
= +10V
AT +25°C
+125°C
+25°C
–40°C
03327-050
AD8027/AD8028 Data Sheet
Rev. D | Page 18 of 27
Figure 56. Enable Turn On Timing
Figure 57. Disable Turn-Off Timing
Figure 58. Quiescent Supply Current vs. Temperature and Supply Voltage
TIME (ns)
OUT PUT VOLTAG E (V)
0 50 100 150 200 250
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
DISABLE/ SELECT PIN
(–2.0V TO –0.5V)
OUTPUT
G = –1
V
S
=2.5V
V
IN
= –1.0V
03327-051
OUTPUT VOLTAGE (V)
0.512345678910
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
G = –1
V
S
=
2.5V
V
IN
= –1.0V
DISABLE/SELECT PIN (–2.0V TO –0.5V)
OUTPUT
0
3327-052
TEMPERATURE ( °C)
SUPPLY CURRENT (mA)
–40 –25 –10 5 20 35 50 65 80 11095 125
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
V
S
= +3V
V
S
= +5V
V
S
=
5V
03327-053
AD8027/AD8028 Data Sheet
Rev. D | Page 20 of 27
THEORY OF OPERATION
The AD8027/AD8028 are rail-to-rail input/output amplifiers
designed in the Analog Devices, Inc., extra fast complementary
bipolar (XFCB) process. The XFCB process enables the
AD8027/AD8028 to run on 2.7 V to 12 V supplies with 190 MHz
of bandwidth and a 100 V/μs slew rate. The AD8027/AD8028
have 4.3 nV/√Hz of wideband noise with 17 nV/√Hz noise at
10 Hz. This noise performance, with an offset of less than
900 μV maximum and drift performance of 1.50 μV/°C typical,
makes the AD8027/AD8028 ideal for high speed, precision
applications. Additionally, the input stage operates 200 mV
beyond the supply rails and shows no phase reversal. The
amplifiers feature overvoltage protection on the input stage.
When the inputs exceed the supply rails by 0.7 V, ESD protection
diodes turn on, drawing excessive current through the differen-
tial input pins. Include a series input resistor to limit the input
current to less than 10 mA.
INPUT STAGE
The rail-to-rail input performance is achieved by operating
complementary input pairs. The common-mode level of the
differential input signal determines which pair is on. As shown
in Figure 60, a tail current (ITAIL) is generated that sources the
PNP differential input structure consisting of Q1 and Q2. A
reference voltage is generated internally that is connected to the
base of Q5. This voltage is continually compared against the
common-mode input voltage. When the common-mode level
exceeds the internal reference voltage, Q5 diverts the tail
current (ITAIL) from the PNP input pair to a current mirror that
sources the NPN input pair consisting of Q3 and Q4.
The NPN input pair can then operate at 200 mV above the
positive rail. Both input pairs are protected from differential
input signals above 1.4 V by four diodes across the input (see
Figure 60). In the event of differential input signals that exceed
1.4 V, the diodes conduct and excessive current flows through
them. Include a series input resistor to limit the input current to
10 mA.
CROSSOVER SELECTION
The AD8027/AD8028 have a crossover selection feature that
allows the user to choose the crossover point between the
PNP/NPN differential pairs. Although the crossover region is
small, avoid operating in this region because it can introduce
offset and distortion to the output signal. To help avoid operat-
ing in the crossover region, the AD8027/AD8028 allow the user
to select from two preset crossover locations (voltage levels)
using the DISABLE/SELECT pin. The crossover region is about
200 mV and is defined by the voltage level at the base of Q5 in
Figure 60. Internally, two separate voltage sources are created
approximately 1.2 V from either rail. One rail or the other is
connected to Q5, based on the voltage applied to the DISABLE/
SELECT pin. This allows either dominant PNP pair operation,
when the DISABLE/SELECT pin is left open, or dominant NPN
pair operation, when the DISABLE/SELECT pin is pulled high.
The DISABLE/SELECT pin also provides the traditional power-
down function when it is pulled low. This pin allows the designer
to achieve the best precision and ac performance for high-side
and low-side signal applications. See Figure 54 through Figure 57
for DISABLE/SELECT pin characteristics.
Figure 60. Simplified Input Stage
VCC
1.2V
+
–
VEE
I
TAIL
1.2V
+
–
LOGIC
V
SEL VP
Q5 Q3 Q1 Q2 Q4 VN
VOUTP
VOUTN
I
CMFB
VCC
VEE
I
CMFB
03327-054
Data Sheet AD8027/AD8028
Rev. D | Page 21 of 27
In the event that the crossover region cannot be avoided, spe-
cific attention is given to the input stage to ensure constant
transconductance and minimal offset in all regions of operation.
The regions are PNP input pair running, NPN input pair
running, and both running at the same time (in the 200 mV
crossover region). Maintaining constant transconductance in
all regions ensures the best wideband distortion performance
when going between these regions. With this technique, the
AD8027/AD8028 can typically achieve 85 dBc SFDR for a
2 V p-p, 1 MHz, and G = +1 signal on ±1.5 V supplies. Another
requirement needed to achieve this level of distortion is that the
offset of each pair must be laser trimmed, even for low frequency
signals.
OUTPUT STAGE
The AD8027/AD8028 use a common emitter output structure
to achieve rail-to-rail output capability. The output stage is
designed to drive 50 mA of linear output current, 40 mA within
200 mV of the rail, and 2.5 mA within 35 mV of the rail.
Loading of the output stage, including any possible feedback
network, lowers the open-loop gain of the amplifier. Refer to
Figure 53 for the loading behavior. Capacitive load can degrade
the phase margin of the amplifier. The AD8027/AD8028 can
drive up to 20 pF, G = +1, as shown in Figure 14. Include a
small (25 Ω to 50 Ω) series resistor, RSNUB, if the capacitive load
is to exceed 20 pF for a gain of 1. Increasing the closed-loop
gain increases the amount of capacitive load that can be driven
before a series resistor must be included.
DC ERRORS
The AD8027/AD8028 use two complementary input stages to
achieve rail-to-rail input performance, as described in the Input
Stage section. To use the dc performance over the entire common-
mode range, the input bias current and input offset voltage of
each pair must be considered.
Referring to Figure 61, the output offset voltage of each pair is
calculated by
+
=
G
F
G
PNPOS
OUTPNPOS
R
RR
VV
,
,,
+
=
G
F
G
NPNOS
OUTNPNOS
R
R
R
VV
,
,,
where the difference of the two input stages is the discontinuity
experienced when going through the crossover region.
The size of the discontinuity is defined as
( )
+
×−=
G
F
G
NPNOS,PNPOS,DIS
R
RR
VVV
Using the crossover select feature of the AD8027/AD8028 helps
to avoid this region. In the event that the region cannot be
avoided, the quantity (VOS, PNP − VOS, NPN) is trimmed to
minimize this effect.
Because the input pairs are complementary, the input bias cur-
rent reverses polarity when going through the crossover region
shown in Figure 41. The offset between pairs is described by
( )
−
+
×−=−
F
G
F
G
S
NPNB,PNPB,
NPNOS,PNPOS,
R
R
RR
RIIVV
where:
IB, PNP is the input bias current of either input when the PNP
input pair is active.
IB, NPN is the input bias current of either input pair when the
NPN pair is active.
If RS is sized so that it equals RF when multiplied by the gain
factor, this effect is eliminated. It is strongly recommended to
balance the impedances in this manner when traveling through
the crossover region to minimize the dc error and distortion. As
an example, assuming that the PNP input pair has an input bias
current of 6 µA and the NPN input pair has an input bias
current of −2 µA, a 200 µV shift in offset occurs when traveling
through the crossover region with RF equal to 0 Ω and RS equal
to 25 Ω.
In addition to the input bias current shift between pairs, each
input pair has an input bias current offset that contributes to the
total offset in the following manner:
FB
G
F
G
S
B
OS
RI
R
RR
RIV
−+
−
+
=F
Figure 61. Op Amp DC Error Sources
V
OUT
I
B
+
R
F
R
G
I
B
–
V
OS
R
S
+ –
+ –
V
IN
+–
–V
S
+V
S
–
+
AD8027/
AD8028
03327-055
DISABLE/SELECT
AD8027/AD8028 Data Sheet
Rev. D | Page 22 of 27
WIDEBAND OPERATION
Voltage feedback amplifiers can use a wide range of resistor
values to set their gain. Proper design of the feedback network
of the application requires consideration of the following issues:
Poles formed by the amplifier input capacitances with the
resistances seen at the amplifier input terminals
Effects of mismatched source impedances
Resistor value impact on the voltage noise of the
application
Amplifier loading effects
The AD8027/AD8028 have an input capacitance of 2 pF. This
input capacitance forms a pole with the amplifier feedback
network, destabilizing the loop. For this reason, it is generally
desirable to keep the source resistances below 500 Ω, unless
some capacitance is included in the feedback network. Likewise,
keeping the source resistances low also takes advantage of the
AD8027/AD8028 low input voltage noise of 4.3 nV/√Hz.
With a wide bandwidth of 190 MHz, the AD8027/AD8028 have
numerous applications and configurations. The AD8027/AD8028
device shown in Figure 62 is configured as a noninverting ampli-
fier. Table 9 provides an easy selection table of gain, resistor
values, bandwidth, and noise performance, and Figure 63 shows
the inverting configuration.
Figure 62. Wideband Noninverting Gain Configuration
Figure 63. Wideband Inverting Gain Configuration
CIRCUIT CONSIDERATIONS
Balanced Input Impedances
Balanced input impedances can help to improve distortion
performance. When the amplifier transitions from PNP pair
to NPN pair operation, a change in both the magnitude and
direction of the input bias current occurs. When multiplied by
imbalanced input impedances, a change in offset can result. The
key to minimizing this distortion is to keep the input impedances
balanced on both inputs. Figure 64 shows the effect of the
imbalance and degradation in SFDR performance for a 50 Ω
source impedance, with and without a 50 Ω balanced feedback
path.
Figure 64. SFDR vs. Frequency and Various RF
Table 9. Component Values, Bandwidth, and Noise Performance (VS = ±2.5 V)
Noise Gain
(Noninverting) RSOURCE (Ω) RF (Ω) RG (Ω) −3 dB Small Signal BW (MHz) Output Noise with Resistors (nV/√Hz)
1 50 0 Not applicable 190 4.4
2 50 499 499 95 10
10 50 499 54.9 13 45
C2
10F
C1
0.1F
C4
0.1F
C3
10F
VOUT
RG
R1
RF
VIN
R1 = RF||RG
AD8027/
AD8028
+
–
03327-056
DISABLE/SELECT
+VS
–VS
+V
S
–V
S
C2
10F
C1
0.1F
C4
0.1F
C3
10F
R1
C5
V
OUT
R
G
R1 = R
F
||R
G
R
F
V
IN
AD8027/
AD8028
+
–
C
F
03327-057
DISABLE/SELECT
FREQUENCY (MHz)
0.1 1 10 20
SF DR ( dB)
–100
–90
–80
–70
–60
–50
–40
–30
–
20 G = +1
V
OUT
= 2V p-p
R
L
= 1k
V
S
= +3V
R
F
= 24.9
R
F
= 49.9
R
F
= 0
03327-058
Data Sheet AD8027/AD8028
Rev. D | Page 23 of 27
PCB Layout
As with all high speed op amps, achieving optimum perform-
ance from the AD8027/AD8028 requires careful attention to
PCB layout. Particular care must be exercised to minimize lead
lengths of the bypass capacitors. Excess lead inductance can
influence the frequency response and even cause high fre-
quency oscillations. The use of a multilayer board with an
internal ground plane can reduce ground noise and enable a
tighter layout.
To achieve the shortest possible lead length at the inverting
input, position the feedback resistor, RF, beneath the board so
that it spans the distance from the output, to the inverting
input. Situate the return node of the resistor, RG, as closely as
possible to the return node of the negative supply bypass
capacitor.
On multilayer boards, clear all layers underneath the op amp of
metal to avoid creating parasitic capacitive elements. This is
especially true at the summing junction (the negative input).
Extra capacitance at the summing junction can cause increased
peaking in the frequency response and lower phase margin.
Grounding
To minimize parasitic inductances and ground loops in high
speed, densely populated boards, a ground plane layer is critical.
Understanding where the current flows in a circuit is critical in
the implementation of high speed circuit design. The length of
the current path is directly proportional to the magnitude of the
parasitic inductances and, therefore, the high frequency imped-
ance of the path. Fast current changes in an inductive ground
return can create unwanted noise and ringing.
The length of the high frequency bypass capacitor pads and
traces is critical. A parasitic inductance in the bypass grounding
works against the low impedance created by the bypass capacitor.
Because load currents flow from supplies as well as ground,
place the load at the same physical location as the bypass capacitor
ground. For large values of capacitors, which are intended to be
effective at lower frequencies, the current return path length is
less critical.
Power Supply Bypassing
Power supply pins are actually inputs, and care must be taken to
provide a clean, low noise, dc voltage source to these inputs.
The bypass capacitors have two functions.
• Provide a low impedance path for unwanted frequencies
from the supply inputs to ground, thereby reducing the
effect of noise on the supply lines.
• Provide sufficient localized charge storage, for fast
switching conditions and minimizing the voltage drop at
the supply pins and the output of the amplifier. This is
usually accomplished with larger electrolytic capacitors.
Decoupling methods are designed to minimize the bypassing
impedance at all frequencies. This can be accomplished with a
combination of capacitors in parallel to ground.
Use high quality ceramic chip capacitors and always keep them
as close as possible to the amplifier package. A parallel combina-
tion of a 0.01 µF ceramic and a 10 µF electrolytic covers a wide
range of rejection for unwanted noise. The 10 µF capacitor is
less critical for high frequency bypassing, and, in most cases,
one per supply line is sufficient.
AD8027/AD8028 Data Sheet
Rev. D | Page 24 of 27
APPLICATIONS INFORMATION
USING THE DISABLE/SELECT PIN
The AD8027/AD8028 unique DISABLE/SELECT pin has two
functions:
• The power-down function places the AD8027/AD8028
into low power consumption mode. In power-down mode,
the amplifiers draw 500 µA maximum of supply current.
• The second function, as described in the Crossover
Selection section, shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to
the other) closer to either the positive supply rail or the
negative supply rail. This selectable crossover point allows
the user to minimize distortion based on the input signal
and environment. The default state is −1.2 V from the
positive power supply, with the DISABLE/SELECT pin left
floating or in tristate mode. In tristate mode, it is important
that current to the pin is limited to ±20 μA maximum.
Table 10 lists the voltage levels and modes of operation for
the DISABLE/SELECT pin over the full temperature range.
Table 10. DISABLE/SELECT Pin Mode Control
Mode DISABLE/SELECT Pin Voltage (V)
Disable −V
S
to –V
S
+ 0.4
Crossover Referenced −1.2 V
to Positive Supply
−VS + 1.1 to –VS +1.3
Crossover Referenced +1.2 V
to Negative Supply
−VS + 2.0 to +VS
When the input stage transitions from one input differential
pair to the other, there is virtually no noticeable change in the
output waveform.
The disable time of the AD8027/AD8028 amplifiers is load
dependent. Table 11 lists typical enable/disable times. See
Figure 56 and Figure 57 for the actual switching measurements.
Table 11. DISABLE/SELECT Switching Speeds
Time
Supply Voltages (R
L
= 1 kΩ)
±5 V +5 V +3 V
t
ON
45 ns 50 ns 50 ns
t
OFF
980 ns 1100 ns 1150 ns
DRIVING A 16-BIT ADC
With the adjustable crossover distortion selection point and low
noise, the AD8028 is an ideal amplifier for driving or buffering
input signals into high resolution ADCs such as the AD7677, a
16-bit, 1 LSB INL, 1 MSPS differential ADC. Figure 65 shows
the typical schematic for driving the ADC. The AD8028 driving
the AD7677 offers performance close to nonrail-to-rail amplifiers
and avoids the need for an additional supply other than the
single 5 V supply already used by the ADC.
In this application, the DISABLE/SELECT pins are biased to
avoid the crossover region of the AD8028 for low distortion
operation.
Table 12 lists summary test data for the schematic shown in
Figure 65.
Table 12. ADC Driver Performance, fC = 100 kHz,
VOUT = 4.7 V p-p
Parameter Measurement
Second Harmonic Distortion −105 dB
Third Harmonic Distortion −102 dB
Total Harmonic Distortion −102 dB
SFDR 105 dBc
Figure 65. Unity-Gain Differential Drive
+5V
+5V
+
–
AD8028
ANALOG INPUT +
INPUT RANG E
(0.15V TO 2.65V)
+
–
ANALOG INPUT –
AD7677
+5V
16 BITS
15Ω
15Ω
2.7nF 4MHz LPF
4MHz LPF
2.7nF
0.1µF
0.1µF
AD8028
03327-059
DISABLE/SELECT
(OPEN)
DISABLE/SELECT
(OPEN)
Data Sheet AD8027/AD8028
Rev. D | Page 25 of 27
As shown in Figure 66, the AD8028 and AD7677 combination
offers excellent integral nonlinearity (INL).
Figure 66. Integral Nonlinearity
BAND-PASS FILTER
In communication systems, active filters are used extensively in
signal processing. The AD8027/AD8028 are excellent choices
for active filter applications. In realizing this filter, it is impor-
tant that the amplifier have a large signal bandwidth of at least
10× the center frequency, fO. Otherwise, a phase shift can occur
in the amplifier, causing instability and oscillations.
In Figure 67, the AD8027/AD8028 device is configured as a
1 MHz band-pass filter. The target specifications are fO = 1 MHz
and a −3 dB pass band of 500 kHz. To start the design, select fO,
Q, C1, and R4. Then use the following equations to calculate the
remaining variables:
(MHz)
(MHz)
PassBand
f
QO
k = 2πfOC1
C2 = 0.5C1
R1 = 2/k, R2 = 2/(3k), R3 = 4/k
H = 1/3(6.5 − 1/Q)
R5 = R4/(H − 1)
Figure 67. Band-Pass Filter Schematic
The test data shown in Figure 68 indicates that this design
yields a filter response with a center frequency of fO = 1 MHz,
and a bandwidth of 450 kHz.
Figure 68. Band-Pass Filter Response
DESIGN TOOLS AND TECHNICAL SUPPORT
Analog Devices is committed to simplifying the design process
by providing technical support and online design tools. Analog
Devices offers technical support via evaluation boards, sample
ICs, interactive evaluation tools, data sheets, SPICE models,
application notes, and phone and email support available at
www.analog.com.
CODE
0 16384 32768 49152 65536
–1.0
–0.5
0
0.5
1.0
INL (LSB)
03327-060
+5V
–5V
C3
0.1µF
C4
0.1µF
R4
523Ω
R5
523Ω
C2
500pF
C1
1000pF
R3
634Ω
V
OUT
R1
316Ω
R2
105Ω
V
IN
AD8027/
AD8028
+
–
03327-061
DISABLE/
SELECT
0.1
CH1 S21 LO
G
5dB/REF 6.342dB 1:6.3348dB 1.00 000MHz
1
FREQUENCY – MHz
10
1
03327-062
AD8027/AD8028 Data Sheet
Rev. D | Page 26 of 27
OUTLINE DIMENSIONS
Figure 69. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Figure 70. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES)AREROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATEFOR USE IN DESIGN.
COMPLIANT TOJEDECSTANDARDS MS-012-AA
012407-A
0.25(0.0098)
0.17 (0.0067)
1.27(0.0500)
0.40(0.0157)
0.50 (0.0196)
0.25 (0.0099)45°
8°
0°
1.75(0.0688)
1.35(0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27(0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51(0.0201)
0.31(0.0122)
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-178-AB
10°
4°
0°
SEATING
PLANE
1.90
BSC
0.95 BSC
0.60
BSC
6 5
1 2 3
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0.15 MAX
0.05 MIN
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.30 MIN
0.55
0.45
0.35
PIN 1
INDICATOR
12-16-2008-A
Data Sheet AD8027/AD8028
Rev. D | Page 27 of 27
Figure 71. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range Package Description Package Option Ordering Quantity Branding3
AD8027ARZ −40°C to +125°C 8-Lead SOIC_N R-8 1
AD8027ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 2500
AD8027ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 1000
AD8027ARTZ-R2 −40°C to +125°C 6-Lead SOT-23 RJ-6 250 H4B#
AD8027ARTZ-REEL7
−40°C to +125°C
6-Lead SOT-23
RJ-6
3000
H4B#
AD8028ARZ −40°C to +125°C 8-Lead SOIC_N R-8 1
AD8028ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 2500
AD8028ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 1000
AD8028ARMZ −40°C to +125°C 10-Lead MSOP RM-10 1 H5B#
AD8028ARMZ-REEL7 −40°C to +125°C 10-Lead MSOP RM-10 1000 H5B#
AD8028WARMZ-R7 −40°C to +125°C 10-Lead MSOP RM-10 1000 Y5R#
AD8027ART-EBZ Evaluation Board
AD8028AR-EBZ Evaluation Board
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 # denotes lead-free, may be top or bottom marked.
AUTOMOTIVE PRODUCTS
The AD8028W model is available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for this model.
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
©2003–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03327-0-7/15(D)
