October 1987
Revised January 1999
CD4017BC • CD4022BC Decade Counter/Divider with 10 Decoded Outputs • Divide-by -8 Counter /Divider with 8
Decoded Outputs
© 1999 Fairchild Semicond uctor Corpor ation DS005950.prf www.fairchildsemi.com
CD4017BC • CD4022BC
Decade Counter/Divider with 10 Decoded Outputs •
Divide-by-8 Counter/Divider with 8 Decoded Outputs
General Descript ion
The C D401 7B C is a 5- sta ge divi d e-by-10 J ohn son co unt er
with 10 decoded outputs and a carry out bit.
The CD4022BC is a 4-stage divide-by-8 Johnson counter
with 8 decoded outputs and a carry-out bit.
These cou nters a re cl eared to their zero coun t by a lo gical
“1” on their reset line. These counters are advanced on the
positive edge of the clock signal when the clock enable sig-
nal is in the logical “0” state.
The configuration of the CD4017BC and CD4022BC per-
mits medium speed operation and assures a hazard free
counting sequence. The 10/8 decoded outputs are nor-
mally in the l ogical “0” state a nd go to the logi cal “1” state
only at their respective time slot. Each decoded output
remains high for 1 full clock cycle. The carry-out signal
completes a fu ll cyc le for every 10/8 clo ck input cycle s a nd
is used as a ripple carry signal to any succeeding stages.
Features
■Wide supply voltage range: 3.0V to 15V
■High noise immunity: 0.45 VDD (typ.)
■Low power F an out of 2 driving 74L
TTL compatibility: or 1 driving 74LS
■Medium speed operation: 5.0 MHz (typ.)
with 10V VDD
■Low power: 10 µW (typ.)
■Fully static operation
Applications
• Automotive
• Instrumentation
• Medical electronics
• Alarm systems
• Industrial electronics
• Remote metering
Ordering Code:
Devices also available in Tape and Reel. Spe c if y by appendin g t he suffix lett er “X” to the order ing code.
Connection Diagrams
Pin Assignments for DIP, SOIC and SOP
CD4017B
Top View
Pin Assignments for DIP and SOI C
CD4022B
Top View
Order Number Package Number Package Description
CD4017BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4017BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE I I, 5.3mm Wide
CD4017BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD4022BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4022BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
www.fairchildsemi.com 2
CD4017BC • CD4022BC
Logic Diagrams
CD4017B
Termin al N o. 8 = GND
Termin al N o. 16 = VDD
CD4022B
Termin al N o. 16 = VDD
Termin al N o. 8 = GND
3 www.fairchildsemi.com
CD4017BC • CD4022BC
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions (Note 2)
Note 1: “Absolute Ma ximum Rating s” are those values beyond w hich the
safety of the device cannot be guaranteed, they are not meant to imply that
the devices should be operated at these limits. The table of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provides
conditions for actual device opera ti on.
Note 2: VSS = 0V unles s ot herwise specified .
DC Electrical Characteristics (Note 2)
Note 3: IOL and IOH are tes t ed one ou tp ut at a ti m e.
DC Supply Voltage (VDD)−0.5 VDC to +18 VDC
Input Voltage (VIN)−0.5 VDC to VDD +0.5 VDC
Storage Temperature (TS)−65°C to +150°C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering, 10 seco nds ) 260°C
DC Supply Voltage (VDD)+3 VDC to +15 VDC
Input Voltage (VIN) 0 to VDD VDC
Operating Temperature Range (TA)−40°C to +85°C
Symbol Parameter Conditions −40°C+25°+85°CUnits
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD = 5V 20 0.5 20 150 µA
Current VDD = 10V 40 1.0 40 300 µA
VDD = 15V 80 5.0 80 600 µA
VOL LOW Level |IO| < 1.0 µA
Output Voltage VDD = 5V 0.05 0 0.05 0.05 V
VDD = 10V 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05 V
VOH HIGH Level |IO| < 1.0 µA
Output Voltage VDD = 5V 4.95 4.95 5 4.95 V
VDD = 10V 9.95 9.95 10 9.95 V
VDD = 15V 14.95 14.95 15 14.95 V
VIL LOW Level |IO| < 1.0 µA
Input Voltage VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5 V
VDD = 10V, VO = 1.0V or 9.0V 3.0 3.0 3.0 V
VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0 V
VIH HIGH Level |IO| < 1.0 µA
Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 V
VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 7.0 V
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 V
IOL LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
Current (Note 3) V DD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA
VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA
IOH HIGH Level Output VDD = 5V, VO = 4.6V −0.2 −0.16 −0.36 −0.12 mA
Current (Note 3) V DD = 10V, VO = 9.5V −0.5 −0.4 −0.9 −0.3 mA
VDD = 15V, VO = 13.5V −1.4 −1.2 −3.5 −1.0 mA
IIN Input Current VDD = 15V, VIN = 0V −0.3 −10−5−0.3 −1.0 µA
VDD = 15V, VIN = 15V 0.3 10−50.3 1.0 µA
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CD4017BC • CD4022BC
AC Electrical Characteristics (Note 4)
TA= 25°C, C L= 50 pF, RL= 200k, trCL and tfCL= 20 ns, unless otherwise specified
Note 4: AC Parameters are guaranteed by DC cor related test ing.
AC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF, RL = 200k, trCL and tfCL = 20 ns, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
CLOCK OPERATION
tPHL, tPLH Propagation Delay Time Carry Out Line VDD = 5V 415 800 ns
VDD = 10V 160 320 ns
VDD = 15V 130 250 ns
Carry Out Line VDD = 5V CL = 15 pF 240 480 ns
VDD = 10V 85 170 ns
VDD = 15V 70 140 ns
Decode Out Lines VDD = 5V 500 1000 ns
VDD = 10V 200 400 ns
VDD = 15V 160 320 ns
tTLH, tTHL Transition Time Carry Out and Decode Out Lines
tTLH VDD = 5V 200 360 ns
VDD = 10V 100 180 ns
VDD = 15V 80 130 ns
tTHL VDD = 5V 100 200 ns
VDD = 10V 50 100 ns
VDD = 15V 40 80 ns
fCL Maximum Clock Frequency VDD = 5V Measured with 1.0 2 MHz
VDD = 10V Respect to Carry 2.5 5 MHz
VDD = 15V Output Line 3.0 6 MHz
tWL, tWH Minimum Clock Pulse Width VDD = 5V 125 250 ns
VDD = 10V 45 90 ns
VDD = 15V 35 70 ns
trCL, tfCL Clock Rise and Fall Time VDD = 5V 20 µs
VDD = 10V 15 µs
VDD = 15V 5 µs
tSU Minimum Clock Inhibit Data Setup Time VDD = 5V 120 240 ns
VDD = 10V 40 80 ns
VDD = 15V 32 65 ns
CIN Average Input Capacitance 57.5pF
Symbol Parameter Conditions Min Typ Max Units
RESET OPERATION
tPHL, tPLH Propagation Delay Time
Carry Out Line VDD = 5V 415 800 ns
VDD = 10V 160 320 ns
VDD = 15V 130 250 ns
Carry Out Line VDD = 5V 240 480 ns
VDD = 10V CL = 15 pF 85 170 ns
VDD = 15V 70 140 ns
Decode Out Lines VDD = 5V 500 1000 ns
VDD = 10V 200 400 ns
VDD = 15V 160 320 ns
tWMinimum Re set VDD = 5V 200 400 ns
Pulse Width VDD = 10V 70 14 0 ns
VDD = 15V 55 110 ns
tREM Minimum Reset VDD = 5V 75 150 ns
Removal Time VDD = 10V 30 60 ns
VDD = 15V 25 50 ns
5 www.fairchildsemi.com
CD4017BC • CD4022BC
Timing Diagrams
CD4017B
CD4022B
www.fairchildsemi.com 6
CD4017BC • CD4022BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
F airchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are im plied and Fairchild reserves the right at any time w ithout notice to change said circuitry and specifications.
CD4017BC • CD4022BC Decade Counter/Divider with 10 Decoded Outputs • Divide-b y-8 Counter/Divider with 8
Decoded Outputs
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support d evices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A cr itical c ompon ent in any com ponent of a li fe support
device or system whose failure to perform can be rea-
sonably expected to cause th e failure of the li fe suppor t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-1, 0.300” Wide
Package Number N16E
