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GENERAL DESCRIPTION
The DS33Z41 design kit is an easy-to-use evaluation
board for the DS33Z41 Ethernet transport-over-serial
link device. The DS33Z41DK is intended to be used
with a resource card for the serial link. The serial link
resource cards are complete with transceivers,
transformers, and network connections. Dallas’
ChipView software is provided with the design kit,
giving point-and-click access to configuration and
status registers from a Windows®-based PC.
On-board LEDs indicate receive loss-of-signal, queue
overflow, Ethernet link, Tx/Rx, and interrupt status.
Windows is a registered trademark of Microsoft Corp.
ORDERING INFORMATION
PART DESCRIPTION
DS33Z41DK DS33Z41 demo card, T1/E1 transceiver
resource card included
FEATURES
Demonstrates Key Functions of DS33Z41
Ethernet Transport Chipset
Includes Resource Card for DS21458 T1/E1
quad Transceiver with Transformers, RJ48
Network Connectors, and Termination
Provides Support for Hardware and Software
Modes
On-Board MMC2107 Processor and ChipView
Software Provide Point-and-Click Access to
the DS33Z41 Register Set
All DS33Z41 Interface Pins are Easily
Accessible for External Data Source/Sink
LEDs for Loss-of-Signal, Queue Overflow,
Ethernet Link, Tx/Rx, and Interrupt Status
Easy-to-Read Silkscreen Labels Identify the
Signals Associated with All Connectors,
Jumpers, and LEDs
DESIGN KIT CONTENTS
• DS33Z41DK Main Board
• Quad-Port Serial Card with DS21458 T1/E1
• CD_ROM
o ChipView Software and Manual
o DS33Z41DK Data Sheet
o Configuration Files
www.maxim-ic.com
DS33Z41DK
Ethernet Transport Design Kit
DS33Z41DK
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TABLE OF CONTENTS
GENERAL DESCRIPTION..........................................................................................................1
ORDERING INFORMATION .......................................................................................................1
DESIGN KIT CONTENTS............................................................................................................1
COMPONENT LIST.....................................................................................................................3
PC BOARD ERRATA..................................................................................................................9
FILE LOCATIONS.......................................................................................................................9
BASIC OPERATION..................................................................................................................10
POWERING UP THE DESIGN KIT ...............................................................................................................10
General............................................................................................................................................................... 10
BASIC DS33Z41 INITIALIZATION (USED FOR ALL QUICK SETUPS) .............................................................10
Quick Setup #1 (Device Driver + DS21458 T1/E1)............................................................................................ 11
Quick Setup #2 (DS21458 T1/E1, Register Based)........................................................................................... 11
Configuration Note: Using a Single System....................................................................................................... 11
Configuration Note: A Mixing Device Driver and Register-Based Modes.......................................................... 11
CONFIGURATION SWITCHES AND JUMPERS......................................................................12
ADDRESS MAP (ALL CARDS) ................................................................................................14
QUAD T1/E1 RESOURCE CARD FPGA REGISTER MAP ............................................................................14
ID REGISTERS..........................................................................................................................14
CONTROL REGISTERS .......................................................................................................................15
DS33Z41 INFORMATION..........................................................................................................16
DS33Z41DK INFORMATION ....................................................................................................16
TECHNICAL SUPPORT............................................................................................................16
DOCUMENT REVISION HISTORY ...........................................................................................16
SCHEMATICS ...........................................................................................................................17
LIST OF FIGURES
Figure 1. System Floorplan.......................................................................................................................................... 8
Figure 2. DS21458 Resource Card Floorplan ............................................................................................................. 8
Figure 3. Schematic Hierarchy and Floorplan ........................................................................................................... 17
LIST OF TABLES
Table 1. Component List (Decoupling Caps Not Shown)............................................................................................ 3
Table 2. Main Board PC Board Configuration ........................................................................................................... 12
Table 3. Overview of Daughter Card Address Map................................................................................................... 14
Table 4. Quad T1/E1 Processor Card FPGA Register Map...................................................................................... 14
DS33Z41DK
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COMPONEN T LIST
Table 1 shows the component list for the DS33Z44 and DS33Z11/DS33Z41 design kits and resource cards. This
BOM contains the part listing for five boards. These boards are the DS33Z41DK, DS33Z44DK, DS21458RC,
DS3174RC, and DS2155-DS21348-DS3170RC. Each reference designator is only used once. For example, U18
only appears on the DS33Z41DK and is not used on any of the other boards. See Table 2.
Table 1. Component List (Decoupling Caps Not Shown)
DESIGNATION QTY DESCRIPTION SUPPLIER PART
U18 1
ELITE 10/100 ETHERNET TRANSPORT OVER
SERIAL LINK 14X14 CSBGA 169 PIN Dallas Semiconductor DS33Z41
U20 1
3.3V T1.E1.J1 QUAD TRANSCEIVER 0-70C 256P
BGA Dallas Semiconductor DS21458
U22 1
QUAD 10/100 ETHERNET EXTENSION TO WAN
17X17 PBGA 256 PIN Dallas Semiconductor DS33Z44
U23 1 DS3/E3 SCT, 11X11 CSBGA, 100 PIN Dallas Semiconductor DS3170
U24 1 T1/E1/J1 XCVR 100P QFP 0-70C Dallas Semiconductor DS2156L
U25 1 3.3V LIU Dallas Semiconductor DS21348
UB08 1
QUAD TRIPLE DUAL SINGLE ATM PACKET PHYS
FOR DS3 E3 STS1 0-70C 400P BGA Dallas Semiconductor DS3184
U01, U09 2 SOIC 8PIN STEP-UP DC-DC CONVERTER 0.5A
LIMIT Maxim MAX1675EUA
U07, U11 2 8-Pin μMAX/SOIC 1.8V or Adj Maxim MAX1792EUA18
U13, UB01 2 MICROPROCESSOR VOLTAGE MONITOR, 2.93V
RESET, 4PIN SOT143 Maxim MAX811SEUS-T
U21, UB07 2 Dual RS-232 transceivers with 3.3V/5V internal
capacitors MAXIM NA
U31, UB06, UB11 3 8-Pin μMAX/SOIC 2.5V or Adj Maxim MAX1792EUA25
C11, C13, C16, C25, C27,
C31–C35, C37, C41, C47,
CB10, CB63, CB114, CB128,
CB164, CB496
19 1206 CERAM 10uF 10V 20% Panasonic ECJ-3YB1A106M
CB390, CB391, CB395, CB396 4 1206 CERAM 0.1uF 25V 10% Panasonic ECJ-3VB1E104K
D01–D03, D05, DB03–DB05 7 SCHOTTKY DIODE, 1 AMP 40 VOLT International Rectifier 10BQ040
DS01, DS07, DS10–DS12,
DS17, DS20 7 LED, AMBER, SMD Panasonic LN1451C
DS02, DS03, DS09, DS14,
DS15 5 L_LED, GREEN, SMD Panasonic LN1351C
DS04–DS06, DS08, DS13,
DS16, DS18, DS27, DS28,
DS35, DS37, DS38, DS40
13 LED, RED, SMD Panasonic LN1251C
DS19, DS43 2 LED, GREEN, SMD Panasonic LN1351C
DS21–DS26, DS30, DS32–
DS34, DS36, DS39, DS41,
DS42, DS44–DS48
19 L_LED, RED, SMD Panasonic LN1251C
GND_TP01–GND_TP07,
GND_TP09-–GND_TP44,
GND_TP46–GND_TP68,
GND_TPB01–GND_TPB10
76 STANDARD GROUND CLIP KEYSTONE 4954
H1–H8, H17–H19 8 KIT, 4-40 HARDWARE, .50 NYLON STANDOFF AND
NYLON HEX-NUT NA Lab Stock
DS33Z41DK
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DESIGNATION QTY DESCRIPTION SUPPLIER PART
H9–H16 16
KIT, 4-40 HARDWARE, 1.12 NYLON STANDOFF
AND NYLON HEX-NUT (1.12 STANDOFF PN =
4807K-ND)
NA Lab Stock
J01–J05 5 CONNECTOR, FASTJACK SINGLE, 8 PIN Halo Electronics HFJ11-2450E
J06, J41 2 100 MIL 2*7 POS JUMPER NA Lab Stock
J07–J12 6
RECEPTACLE, SMD, 140 PIN, .8MM, 2 ROW
VERTICAL AMP 5-179010-6
J13–J22 10
L_TERMINAL STRIP, 10 PIN, DUAL ROW, VERT DO
NOT POPLUATE NA Lab Stock
J23, J29, J32, J38, J39, J43,
J44, J47, JB07 9 L_TERMINAL STRIP, SHROUDED, 10 PIN, DUAL
ROW, VERT 3M Electronics 2510-6002UB
J24, J30, J31, J33 4 100 MIL 2 POS JUMPER NA Lab Stock
J25, J26, J45, J46 4 TERMINAL STRIP, 10 PIN, DUAL ROW, VERT NA Lab Stock
J27, J42 2 CONN 50 PIN, 2 ROW, POSTS VERT,
MOTHERBOARD FOOTPRINT SAMTEC TSW-125-07-T-D
J28, J36 2 L_CONN, DB9 RA, LONG CASE AMP 747459-1
J48, J54, JB01 3 SOCKET, BANANA PLUG, HORIZONTAL, BLACK Mouser Electronics 164-6218
J49–J52 4 CONNECTOR BNC 75 OHM VERTICAL 5PIN Cambridge CP-BNCPC-004
J53, JB02, JB08 3 SOCKET, BANANA PLUG, HORIZONTAL, RED Mouser Electronics 164-6219
J55, JB11 2 L_RJ48 8 PIN SINGLE PORT CONNECTOR MOLEX 15-43-8588
J56–J59, J61, J63 6 CONNECTOR BNC 75 OHM RA 5PIN Trompetor UCBJR220
J60, J62, J64, J65 4 CONNECTOR BNC RA 5PIN Trompetor UCBJR220
JB05, JB06, JB09, JB10, JB13,
JB14 6 PLUG, SMD, 140 PIN, .8MM, 2 ROW VERTICAL AMP 179031-6
JB12 1 RA RJ45 8PIN 4PORT JACK MOL 43223-8140
JP01–JP19 19 100 MIL 3 POS JUMPER NA NA
L01, L03–L08, LB01, LB02 9 FERRITE 3A 100 OHM AT 100 MHZ 1206 SMD Steward HI1206N101R-00
L02, L09 2 INDUCTOR 22.0uH 2PIN SMT 20% Coiltronics UP1B-220
L10 1 XFMR 1-2CT XMIT, 1-1CT RCV, 40P WIDE SOIC Pulse T1068
R01, R02, RB10, RB11, RB18,
RB19, RB22, RB23, RB26,
RB27
10 RES 0603 54.9 Ohm 1/16W 1% Panasonic ERJ-3EKF54R9V
R03, R04, RB12, RB13, RB20,
RB21, RB24, RB25, RB28,
RB29
10 RES 0603 49.9 Ohm 1/16W 1% Panasonic ERJ-3EKF49R9V
R05, R06, R08, R09, R11 5 RES 0603 10.0K Ohm 1/16W 1% - Must be 1%
tolerance Panasonic ERJ-3EKF1002V
R07, R12, R16, R79, R160,
R244, R248, R250, R251,
R254, R255, RB126, RB143,
RB147, RB150, RB157
16 RES 0603 1.0K Ohm 1/16W 5% Panasonic ERJ-3GEYJ102V
R10, R107 2 RES 1206 5.6 Ohm 1/8W 5% Panasonic ERJ-
8GEYJ5R6V
R132, R137, R142, R144,
R156, RB194, RB208, RB227 8 L_RES 0603 0 Ohm 1/16W 1% AVX CJ10-000F
DS33Z41DK
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DESIGNATION QTY DESCRIPTION SUPPLIER PART
R13–R15, R18–R20, R22, R23,
R29, R30, RB01, RB03, RB07,
RB09, RB15–RB17, RB30–
RB32, RB34–RB38, RB41,
RB44, RB47, RB48, RB50–
RB52, B55, RB60, RB62, RB72,
RB73, RB75, RB80, RB82
40 RES 0603 5.1K Ohm 1/16W 5% Panasonic ERJ-3GEYJ512V
R17, R21, R25–R28, R31, R55,
R57–R59, R71, R74–R76, R83,
R96–R102, R105, R106, R109,
R111, R112, R115–R117,
R120, R122–R126, R128,
R133, R134, R140, R141,
RB61, RB96, RB97, RB99,
RB100, RB102–RB110, RB112,
RB114–RB119, RB121,
RB123–RB125, RB127, RB128,
RB130, RB131, RB133,
RB135–RB138, RB145, RB148,
RB149, RB160, RB161, RB164,
RB165, RB167–RB171,
RB173–RB181, RB184, RB187,
RB311, RB320, RB335, RB339,
RB359
104 RES 0603 30 Ohm 1/16W Panasonic ERJ-3GEYJ300V
R171, R172, R174, R175,
R190, R191, R240, R241 8 L_RES 0805 0.0 Ohm 1/10W 5% Panasonic ERJ-
6GEY0R00V
R198–R200, R210–R213,
RB306, RB325, RB326 10 RES 0603 332 Ohm 1/16W 1% Panasonic ERJ-3EKF3320V
R201–R208, RB321–RB324,
RB327–RB330 16 RES 1206 0 Ohm 1/8W 5% Panasonic ERJ-
8GEYJ0R00V
R239, RB349 2 RES 0805 51.1 Ohm 1/10W 1% Panasonic ERJ-6ENF51R1V
R24, R114, R197, RB14, RB33,
RB40, RB42, RB43, RB49,
RB53, RB54, RB57–RB59,
RB71, RB77, RB78, RB152–
RB156, RB221, RB234, RB251,
RB284, RB304, RB331, RB332,
RB342, RB344, RB350, RB354,
RB360
34 L_RES 0603 330 Ohm 1/16W 5% Panasonic ERJ-3GEYJ331V
R242, R243, RB144, RB166,
RB355–RB358, RB368–RB371 12 RES 0603 51 Ohm 1/16W 5% Panasonic ERJ-3GEYJ510V
R32, R70, R78, R161, R176,
R194, R195, R237, R238,
RB129, RB134, RB146, RB193
13 RES 0603 330 Ohm 1/16W 5% Panasonic ERJ-3GEYJ331V
R33–R54, R60–R69, R72, R73,
R131, R136, R143, R147,
R150, R154, R158, R163,
R166, R169, R173, R178–
R189, R215–R228, RB89–
RB95, RB101, RB188–RB191,
RB196–RB199, RB202–RB205,
RB210–RB213, RB216–RB219,
RB223–RB226, RB230–RB233,
RB239–RB242, RB244–RB249,
RB252–RB260, RB265–RB268,
RB270-RB282, RB289–RB297
152 RES 0402 30 Ohm 1/16W 5% Panasonic ERJ-2GEJ300X
R56, R90 2 RES 0603 1.0M Ohm 1/16W 5% Panasonic ERJ-3GEYJ105V
R77, RB159 2 L_RES 1206 0 Ohm 1/8W 5% Panasonic ERJ-
8GEYJ0R00V
R80, R81, R84, R87, R89, R91–
R93, R95, R108, R110, R118,
R127, R152, R153, R196,
R209, R214, R229–R236,
RB200, RB237, RB238, RB263,
RB264, RB286, RB287, RB300,
RB301, RB333, RB364
37 RES 0603 10K Ohm 1/16W 5% Panasonic ERJ-3GEYJ103V
DS33Z41DK
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DESIGNATION QTY DESCRIPTION SUPPLIER PART
R85, R88, R94, R104, R113,
RB02, RB04–RB06, RB08,
RB39, RB45, RB46, RB56,
RB63–RB70, RB76, RB83,
RB98, RB183, RB185, RB192,
RB209, RB228, RB302, RB303,
RB305, RB338, RB340, RB341,
RB346–RB348, RB351–RB353,
RB361–RB363, RB365–RB367
48 RES 0603 2.0K Ohm 1/16W 5% Panasonic ERJ-3GEYJ202V
R86, R103, R119, R121, R129,
R130, R135, R138, R139,
R145, R146, R149, R151,
R157, R162, R164, R167,
R168, R170, R177, R192,
R193, R245-R247, R249, R252,
R253, R256, R257, RB74,
RB79, RB132, RB139-RB141,
RB151, RB162, RB163, RB172,
RB182, RB186, RB206, RB207,
RB214, RB215, RB220, RB222,
RB229, RB235, RB236, RB243,
RB250, RB261, RB262, RB269,
RB308–RB310, RB343, RB345
61 L_RES 0603 10K Ohm 1/16W 5% Panasonic ERJ-3GEYJ103V
RB201, RB285 2 RES 0805 330 Ohm 1/10W 5% Panasonic ERJ-6GEYJ331V
RB283 1
RES 0603 10K Ohm 1/10W 5% - SEE SPECIAL
INSTRUCTIONS Panasonic 603_ERJ-
3GEYJ103V
RB298, RB299, RB312–RB319,
RB336, RB337 12 RES 0805 61.9 Ohm 1/10W 1% Panasonic ERJ-6ENF61R9V
RB81, RB84–RB88, RB111,
RB113, RB120, RB122 10 RES 0603 DO NOT POPULATE NA NA
SW01–SW05, SW08–SW21,
SW24–SW26, SW29–SW31,
SW33–SW44
37 L_SWITCH, SP3T SLIDE, 4PIN TH Tyco 3-1437575-3
SW06, SW22 2 L_SWITH 8POS 16PIN DIP LOW PROFILE AMP 435668-7
SW07, SW23 2 SWITCH MOM 4PIN SINGLE POLE Panasonic EVQPAE04M
SW27, SW28, SW32 3 L_DIPSWITCH, 10 POS AMP 435668-9
T01, T03 2 XFMR 16P SMT Pulse TX1099
T02, TB01 2 XFMR, OCTAL T3/E3, 1 TO 2, SMT 32 PIN Pulse T3049
TP01–TP78, TPB01, TPB02 80 TESTPOINT, 1 PLATED HOLE, DO NOT STUFF NA NA
U02–U06 5
IC, DsPHYTER11-SINGLE 10/100 ETHERNET
TRANSCEIVER, 65 PIN LLP
National
Semiconductor
DP83847ALQA5
6A
U08, U12, U29 3 1MBit Flash based config mem Avnet XCF01SV020C
U10 1 XILINX SPARTAN xc200 2.5V FPGA,256 PIN BGA Xilinx XC2S200-
5FG256C
U14, U26, U30, UB05 4 CYPRESS SRAM, LAB STOCK NA NA
U15, U19 2 mmc2107 processor Motorola MMC2107
U16, U27 2 XILINX SPARTAN 2.5V FPGA,256 PIN BGA Xilinx XC2S50-
5FG256C
U17, U28, U32 3 10 pin res pack, 10K ohm NA NA
UB02, UB03, UB04 3 100 PIN CPLD XILINX XC95144XL-
10TQ100C
UB09, UB10 2 SYNCHRONOUS DRAM, 1MEGX32X4 BANKS,
TSOP 86 PIN Micron MT48LC4M32B2
TG-7
DS33Z41DK
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DESIGNATION QTY DESCRIPTION SUPPLIER PART
UX01–UX12, UXB02–UXB04,
UXB06–UXB08 18 HIGH SPEED BUFFER Fairchild NC7SZ86
UXB01, UXB05 2 HIGH SPEED INVERTER Fairchild NC7SZ86
X01, X02 2 XTAL LOW PROFILE 8.0MHZ ECL EC1-8.000M
Y01, Y09 2 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 25.000
MHZ, Low Jitter required for PHY SaRonix NTH089AA3-
25.000
Y02, Y13 2 SPI SERIAL EEPROM 16K 8 PIN DIP 2.7V NEEDS
SOCKET Atmel AT25160A-10PI-
2.7
Y03 1 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 2.048 MHZ SaRonix NTH039A3-
2.0480
Y05, Y06 2 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 100.000
MHZ SaRonix NTH089A3-
100.0000
Y07 1 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 44.736 MHZ SaRonix NTH089AA3-
44.736
Y08 1 OSCILLATOR, CRYSTAL CLOCK, 5.0V - 44.736 MHZ SaRonix NTH089AA-
44.736
YB02 1
L_OSCILLATOR, CRYSTAL CLOCK, 3.3V - 2.048
MHZ SaRonix NTH039A3-
2.0480
DS33Z41DK
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Figure 1. System Floorplan
Figure 2 shows the DS21458 quad T1/E1 PC board floorplan. The current configuration is to populate oscillators
for MCLK1 with a 8.192MHz oscillator. Testpoints for port 3 and port 4 are provided on the WAN card, and
testpoints for ports 1 and 2 are provided on the motherboard.
Figure 2. DS21458 Resource Card Floorplan
DS33Z41 MAINBOARD
DS33Z41
SDRAM
ETHERNET PHY,
MAGNETIC,
LEDS, AND
JUMPERS
MICROPROCESSOR
AND SERIAL PORT
(57600-8-N-1)
HARDWARE
MODE SWITCHES
FOR DS33Z41
SERIAL INTERFACE
2 X 140 PIN CONNECTORS
LEDS AND TESTPOINTS DS21458 RESOURCE CARD
(DETAIL PROVIDED BELOW)
PORT 2
PORT 4
PORT 1
PORT 3
DS21458
QUAD-PORT
T1/E1
TRANSCEIVER
140 PIN CONNECTORS
TEST POINTS
FPGA
OSC
MCLK1, 2
J
TA
G
QUAD-PORT RJ45
QUAD
TRANSFORMER
RLOS LEDS
INT LED
DS33Z41DK
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PC BOARD ERRATA
• Silkscreen for JTAG connector signal descriptions is incorrect on the quad T1/E1 card. This should be
corrected with an adhesive label.
FILE LOCATIONS
This design kit relies upon several supporting files, which are provided on the CD and are available as a zip file
from the Maxim website at www.maxim-ic.com/DS33Z41DK.
All locations are given relative to the top directory of the CD/zip file.
• DS33Z41 register definition files and configuration files:
o .\cfg_demo_gui\DS33Z41_cfg_demo_gui\DS33Z41.def
o .\DS33Z41_cfg_demo_gui\SU_LI_PORT1.def
o .\DS33Z41_cfg_demo_gui\z41_basic.mfg
• DS21458 register definition files and configuration files:
o .\DS33Z41_cfg_demo_gui\Qt1e1_DS21458\DS21458RC_FPGA.def
o .\DS33Z41_cfg_demo_gui\Qt1e1_DS21458\DS21458RC.def
o .\DS33Z41_cfg_demo_gui\Qt1e1_DS21458\T1_IBO_ LoopTime.ini
o .\DS33Z41_cfg_demo_gui\Qt1e1_DS21458\T1_IBO_ SourceTime.ini
o .\DS33Z41_cfg_demo_gui\Qt1e1_DS21458\E1_CRC_HDB3_IBO_ SourceTime.ini
o .\DS33Z41_cfg_demo_gui\Qt1e1_DS21458\E1_CRC_HDB3_IBO_ LoopTime.ini
DS33Z41DK
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BASIC OPERATION
Powering Up the Design Kit
• Attach DS21458 resource card to main board.
• Connect PCB 3.3V and GND banana plugs to power supply. At power-up the system should draw
approximately 1A.
• Set switches for software mode as described in Table 2 (short description follows).
• Top left bank: All low, except for MODEC0, which is high.
• Top right bank: A2, A1, A0 in mid position, SCANTRI low
• Bottom Bank: All high (AFCS, FULLDS, H1OS)
General
• Upon power-up, the processor FPGA Status LEDs (DS43 green) will be lit. Interrupt LEDs (DS44 red) will not
be lit. DS33Z11 Queue overflow LEDs (DS39 red) will not be lit. PHY LINK LED (DS06 green) should be lit if
the Ethernet is connected.
Following are several basic system initializations. These initializations assume that there are two boards present
(DS33Z41 and / or DS33R41). A note is provided below to assist with using a system that only contains one board.
Basic DS33Z41 Initialization (Used for All Quick Setups)
This section covers four basic methods for configuring the DS33Z41. Any one of these initializations can be used
with the following Quick Setup examples:
1. Upon power-up, the on-board device driver provides a basic configuration for the DS33Z41 and attached
serial cards. This enables traffic to pass from the Ethernet port to the serial port. Consult the device driver
documentation for further details. Device driver behavior is dependant upon jumper settings, which are
detailed in Table 2.
2. Launch ChipView.exe and select Register View. When prompted for a definition file, pick the file named
DS33Z41.def. Following this load the definition file named DS21458RC_FPGA.def
3. Hardware Mode is not available with this DK
4. EEPROM mode is not available with this DK.
5. Ethernet Traffic generation and analysis:
a. Using a patch cable, connect the Ethernet connector to an ordinary PC, or network test equipment.
This should cause the link LED to turn on.
b. Although ping is mentioned it is *not* recommended. The ping command goes through the
computers TCPIP stack, and will sometimes will not be sent out the PCs network connector (i.e. if
the PCs ARP cache is out of date). Additionally ping requires two PCs, as a PC can not ping itself
(a local ping gets sent to ‘localhost’ instead of out the connector). With that said – ping is still a
valuable test once the prototyping stage is complete.
c. Generation and capture of arbitrary (raw) packets can be accomplished using CommView. A time-
limited demo is available at the website www.tamos.com/products/commview.
d. Ethereal is an excellent (and free) packet capture utility. Download is available at
www.ethereal.com.
e. Adding additional Ethernet ports to a PC is rather simple when a USB-to-Ethernet adapter is used.
This allows for end-to-end testing using a single PC. When using two adapters the PC will have a
different IP address for each adapter. Test equipment will allow selection of either adapter.
Operating system based network traffic will be sent out the default adapter, usually this is the
adapter that has recently had connection to a real network.
DS33Z41DK
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Quick Setup #1 (Device Driver + DS21458 T1/E1)
• Select TCLK source for the DS21458 resource card. If this is the only DS33Z41 in the system (i.e. used in
loopback) then select TCLK=MCLK. From Table 2, this requires that the J45.3+J45.4 jumper is not installed. If
this is the second DS33Z41 in the system select TCLK=RCLK, which requires that J45.3+J45.4 jumper is
installed. Note: The TCLK source settings can be changed using the driver interface, which is described
below.
• Complete the hardware configuration and one of the basic DS33Z41 configurations as described in the
previous section.
• At this point any packets sent to the DS33Z41 are sent out the T1/E1 ports. Incoming Ethernet packets should
cause the RX LED to blink, transmitted packets cause the TX LED should also blink.
• Launch ChipView.exe, select Register View
• To interact with the device driver go to ChipView and select from the drop down menu:
• Tools→Plugins→Load Plugins. When asked if DLLs have already registered select yes
• Select Tools→Plugins→DS33Z41/11/41 Device Driver Demo
• A new form called ‘Zchip Configuration’ appears
• Preload basic configuration for the GUI by selecting File→Load Settings (in the ‘Zchip Configuration’ form).
Select the file named ‘basic_Config.eset’
Quick Setup #2 (DS21458 T1/E1, Register Based)
1. Disable device drivers and callbacks – remove all jumpers from J45 header. Press the reset button, or cycle
power on the board to restore the system to its power-on state.
2. Configure the DS33Z41. After the definition files load, go to the File menu and select File→Memory Config
File→Load .MFG file. When prompted, select the file named z41_basic.mfg.
3. Set the DS2148 serial card for IBO mode. Using the menu marked ‘Def File Selection’ switch to the
DS21458RC_FPGA def file. Set the register MO+CLK to 0x47.
4. Configure the DS21458. Go to the File menu and select File→Register INI File→Load .INI file. When
prompted, select either the file named T1_IBO_ SourceTime.ini (TCLK=MCLK) or T1_IBO_ LoopTime.ini
(TCLK=RCLK). Set one board to be the source of network timing (TCLK=MCLK), and one board to follow the
timing source (TCLK=RCLK). The RLOS LEDs should go out when this step is complete for both boards.
5. Additional setup (for both boards):
• Switch to the DS33Z41 def file and set the following:
• Set the GL.IMUXCN register to 0x0F (both systems)
• Set GL.IMUXC register to 0x00 then to 0x82 (both systems)
• Check GL.IMUXSS register. They should be 0xFF on both systems
• Return to GL.IMUXCN and set the bits RXE and SENDE
• The system should now be configured to pass Ethernet traffic into one system and out of the other.
Configuration Note: Using a Single System
The DS33Z41 is intended for use in a system with a DS33Z41 at each end. However, the system may be tested
with only a single DS33Z41 system. This configuration requires that the DS21458 serial link is in loopback, either
internal loopback or hardware loopback may be used. In this configuration any packets sent to the Ethernet side
will be echoed back. In this configuration the setting for DS21458 TCLK=MCLK should be used (see Table 2) and
steps intended for the “second” system may be ignored.
Configuration Note: A Mixing Device Driver and Register-Based Modes
Quick setup #1 discuses device driver based operation. Quick setup #2 discusses register based operation. To
some extent both modes may be used simultaneously to gain insight to device configuration. For example:
• In register view click “Read All” this causes all registers to be read, changed registers turn green.
• Switch to the device driver GUI, select one of the forms, make changes, and click “send configuration”
• Switch back to register view and click “Read All”. Newly changed registers will turn green, showing which
registers changed as a result of settings selected in the device driver GUI
A second type of device driver/register-based configuration is to power the board with the device drivers enabled,
and then remove the jumpers that enable the device drivers. This allows for a fast initial configuration.
DS33Z41DK
12 of 44
CONFIGURATION SWITCHES AND JUMPERS
The DS33Z41DK has several configuration switches, banana plugs, oscillators, and jumpers. Table 2 provides a
description of these signals, given in order of appearance on the PC board (going from left to right, top to bottom).
Table 2. Main Board PC Board Configuration
BASIC SETTING
SILKSCREEN
REFERENCE FUNCTION SW MODE HW MODE DESCRIPTION
J45.9 + J45.10 Reserved Not installed —
This jumper is not for use with
the DS33Z41 design kit. Pin
J25.10 has been removed to
prevent accidental installation
J45.7 + J45.8 Enable device driver User decision —
When installed the device driver
will configure the DS33Z41 and
the Transceiver during power-up.
J45.5 + J45.6 Enable callbacks User decision — When installed the driver will
respond to interrupts
J45.3 + J45.4 Select TCLK source User decision —
When installed the driver will
configure DS21458 TCLK to be
sourced from DS21458 RCLK.
When not installed DS21458
scaled MCLK is used. This
setting is only applied at reset. If
only one board is used select
TCLK = MCLK.
GROUND
(banana plug) Power supply ground — — System Ground. Always
connected to power supply.
VDD 3.3V
(banana plug) Power supply VDD — — System VDD. Always connected
to power supply.
OnCe BDM — — Debug connector for processor
DCEDTES
(3pos switch)
DS33Z41 mode pin;
DTE/DCE selection LOW LOW Low for DTE
RMIIMII
(3pos switch) DS33Z41 mode pin LOW LOW High for RMII, low for MII
CKPHA
(3pos switch) DS33Z41 mode pin LOW LOW SPI EEPROM hardware mode
configuration switch
MODEC0
(3pos switch) DS33Z41 mode pin HIGH LOW Software mode selected
MODEC1
(3pos switch) DS33Z41 mode pin LOW LOW Software mode selected
HWMODE
(3pos switch) DS33Z41 mode pin LOW LOW Hardware/software mode
(software mode selected)
SCANMO
(3pos switch) DS33Z41 mode pin LOW LOW Set low for normal operation
SCANTRI
(3pos switch) DS33Z41 mode pin LOW LOW Set low for normal operation
….testpoints…. DS33Z41 testpoints — — Processor bus, JTAG and LAN
side testpoints for Zchip
Z-RESET (button) DS33Z41 reset — — System reset
A2, A1, A0
(3pos switches) DS33Z41/SPI pins Mid position Mid position
Address pin/EEPROM config
switch. Set to mid position to
allow connection to processor.
SDRAM CLOCK DS33Z41 SDRAM
clock Installed Installed
100MHz oscillator to drive
SDRAM clock
MII CLOCK PHY MII clock Installed Installed 25MHz oscillator to drive SDRAM
clock
DS33Z41DK
13 of 44
BASIC SETTING
SILKSCREEN
REFERENCE FUNCTION SW MODE HW MODE DESCRIPTION
spi_cs, spi_ck,
spi_miso,
spi_mosi
— — —
SPI signals (for EEPROM
memory)
….testpoints….. DS33Z41 testpoints — — DS33Z41 serial port testpoints
AFCS
(1 per port) DS33Z41 mode pin HW mode only HIGH Set high to enable auto flow
control.
FULLDS
(1 per port) DS33Z41 mode pin HW mode only HIGH Set high to enable full duplex.
H10S
(1 per port) DS33Z41 mode pin HW mode only HIGH Set high to confg for 100Mb.
GROUND/VDD
(banana plug)
Power supply
ground/3.3V — —
Redundant connection to system
power. Use plugs at either top or
bottom of board.
VDD 3.3V
(banana plug) Power supply VDD — —
Redundant connection to system
power. Use plugs at either top or
bottom of board.
DS33Z41DK
14 of 44
ADDRESS MAP (ALL CARDS)
Motorola resource card address space begins at 0x81000000. All offsets given below are relative to the beginning
of the daughter card address space (shown previously).
Table 3. Overview of Daughter Card Address Map
OFFSET DEVICE DESCRIPTION
0X0000 to
0X0087 FPGA Processor board identification
0X1000 to
0X1FFF DS33Z41 DS33Z41. Uses CS_X1.
0X2000 to
0X2FFF DS21458 T1/E1 DS21458 resource card. Uses CS_X2.
0X4000 to
0X4010 FPGA
FPGA on DS21458 resource card. Used to facilitate IBO mode.
Default configuration of FPGA is compatible with non-IBO mode
functionality. The FPGA settings will require modification for use
with the DS33Z41 when device drivers are disabled.
Registers in the DS33Z41 and DS21458 can be easily modified using the ChipView host-based user-interface
software with the definition files previously mentioned.
Quad T1/E1 Resource Card FPGA Register Map
Table 4. Quad T1/E1 Processor Card FPGA Register Map
OFFSET REGISTER
NAME TYPE DESCRIPTION
0X4000 Rev Read only FPGA Rev
0X4001 delay_line1 Control Line 1 number of frame delay
0X4002 delay_line2 Control Line 2 number of frame delay
0X4003 delay_line3 Control Line 3 number of frame delay
0X4004 delay_line4 Control Line 4 number of frame delay
0X4005 MO+CLK Control Mode and clock ctrl
0X4006 UNUSED Control Unused / test
0X4007 UNUSED Control Unused / test
ID REGISTERS
REV: FPGA REV (Offset=0X4000)
FPGA Rev is read only, showing the current FPGA revision
DS33Z41DK
15 of 44
CONTROL REGISTERS
Register Name: delay_line1, delay_line2, delay_line3, delay_line4
Register Description: DS33Z41 frame delay
Register Offset: 0X4001, 0X4002, 0X4003, 0X4004
Bit # 7 6 5 4 3 2 1 0
Name — — B5 B4 B3 B2 B1 B0
Default — — — — 0 0 0 0
Bits 5 to 0: B5 to B0. Number of frame delay for a given line.
Register Name: MO+CLK
Register Description: DS33ZXY Mode and Clock Settings
Register Offset: 0X4005
Bit # 7 6 5 4 3 2 1 0
Name LB MC IR tgapclk rgapclk comm_tclk common_rclk z41_mode
Default 0 — — 1 1 0 0 0
Bit 7: LB
0 = Normal operation, traffic goes from the Z chip through the FPGA and to the DS21458.
1 = Loopback, Z chip rser is driven by Z chip tser. Clocks, and frame sync for Z41, are still driven by DS21458.
Bit 6: INVERT_RCL Kh
0 = Do not invert RCLK.
1 = Invert RCLK.
Bit 5: MclkHiBpclkLow
0 = Use BPCLK for clock signals below.
1 = Use MCLK for clock signals below.
This signal drives the following clocks: TCLK (when bit for common_tclk is set); RCLK (when bit for common_rclk is
set); TSYSCLK and RSYSCLK (when bit for Z41_mode is set).
Bit 4: TGAPCLK
0 = Drive internal TGAPCLKx signal with TCLKx.
1 = Drive internal TGAPCLKx signal with TGAPCLK pin.
Bit 3: RGAPCLK
0 = Drive internal RGAPCLKx signal with RCLKx.
1 = Drive internal RGAPCLKx signal with RGAPCLK pin.
Bit 2: Common TCLK
0 = Drive TCLKx with internal TGAPCLKx signal (see bit 4)
1 = Drive Z chip TCLKx with BPCLK
Bit 1: Common RC LK
0 = Drive RCLKx with internal RGAPCLKx signal (see bit 3).
1 = Drive Z chip RCLKx with BPCLK.
Bit 0: Z41 Mode
0 = Not in Z41 mode.
1 = In Z41 mode.
DS33Z41DK
16 of 44
DS33Z41 INFORMATION
For more information about the DS33Z41, consult the DS33Z41 data sheet available on our website at
www.maxim-ic.com/DS33Z41.
DS33Z41DK INFORMATION
For more information about the DS33Z41DK, including software downloads, consult the DS33Z41DK data sheet
available on the our websit e at www.maxim-ic.com/DS33Z41DK.
TECHNICAL S UPPORT
For additional technical support, go to www.maxim-ic.com/support.
DOCUMENT REVISION HISTORY
REVISION
DATE DESCRIPTION
051505 Initial DS33Z41DK data sheet release.
080706 Updated Table 2.
110106 Updated schematics.
DS33Z41DK
17 of 44
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
SCHEMATICS
The DS33Z41DK schematics are featured in the following pages. As this is a hierarchal schematic some
explanation is in order. The main board is composed of six hierarchal blocks: the processor block, the DS33Z41
block, and four Ethernet blocks inside the DS33Z41 block, which is a nested hierarchy block. The DS21458
consists of a single hierarchy block, which connects to a 140-pin AV bus that snaps into the mainboard.
All signals inside a hierarchy block are local, with exception for VCC and ground. In-port and out-port connectors are
used to allow signals inside a hierarchy block to become accessible as pins on the hierarchy blocks symbol. From
here, blocks are wired together as if they were ordinary components. The system diagram is shown again below,
with schematic page numbers given for each functional block.
This system contained other hierarchy blocks that are not shown (primarily a single-port serial card, T3E3 serial
card and the DS33Z44 mainboard). Due to this, page numbers will not be continuous and some gaps in numbering
will be seen when referring to the total page count. However, page numbers inside any given hierarchy block will
be continuous.
Figure 3. Schematic Hierarchy and Floorplan
DS33Z11 BLOCK
PAGE 3. SYMBOL
SCHEMATIC
PAGES 5-10
µP BLOCK
PAGE 4 SYMBOL
SCHEMATIC
PAGES 13-19
DS33Z11 MAINBOARD TOP LEVEL SCHEMATIC
ETHERNET PHY
PAGE 8 SYMBOL
SCHEMATIC
PAGES 11-12
SERIAL INTERFACE
2 X 140 PIN CONNECTORS
DS21458 RESOURCE CARD
SCHEMATIC
PAGES 46-55
PAGES 5-10
P2 CONNECTOR (PLUG)
MOTHERBOARD CONNECTORS FOR WAN R.C.
P1 CONNECTOR (PLUG)
HIERARCHICAL BLOCK
DS33Z11/Z41 TOP LEVEL
Z44_RSER<1>
Z44_TCLK<1>
Z44_RCLK<1>
Z44_TSER<3>
Z44_TDEN<3>
Z44_TCLK<3>
BTS_DUT
D_DUT<7..0>
RESET_B
Z44_TDEN<1>
Z44_RDEN<1>
RD_DUT
INT2
Z44_TSER<1>
A_DUT<9..0>
CS_X1
WR_DUT
BIS1_DUT
BIS0_DUT
Z41TSYNC
Z41RSYNC
JB09
GND
SIG_RETURN
RW_X
WR_X
GND
GND
XD<7..0>
GND
OSC1_NU
XD<7..0>
GND
GND
JB13
GND
GND
OSC3_NU
GND
Z44_TCLK<2>
Z44_TCLK<1>
GND
V3_3
Z44_TSER<4>
Z44_TDEN<4>
Z44_TCLK<4>
SIG_RETURN
Z44_RDEN<4>
Z44_RCLK<4>
GND
GND
GND
GND
Z44_RSER<3>
Z44_TDEN<1>
SIG_RETURN
Z44_TSER<1>
GND
CS_X2
CS_X3
V3_3
GND
Z44_RCLK<1>
Z44_RDEN<1>
Z44_RSER<1>
INT2
GND INT2
GND
Z41TSYNC
Z41RSYNC
RESET_B
INT4
GND
GND
CS_X5
GND
V3_3
Z44_RDEN<3>
SIG_RETURN
GND
GND
PLUG
3
1
0
7
5
2
4
6
1
3
5
6
0
2
4
7
8
9
11
GND
V3_3
GND
GND
GND
GND
GND
GND
GND
GND
V3_3
Z44_RSER<4>
GND
Z44_RCLK<3>
V3_3
GND
GND
GND
XA<15..0>
GND
V3_3
GND
GND
GND
Z44_TSER<2>
Z44_TDEN<2>
GND
GND
GND
GND
GND
TDO_NU
TCK_NU
GND
GND
GND
GND
OSC4_NU
OSC2_NU
V3_3
GND
GND
GND
V3_3
TMS_NU
TDI_NU
GND
GND
GND
V3_3
Z44_RCLK<2>
Z44_RDEN<2>
Z44_RSER<2>
GND
GND
GND
GND
INT5
GND
GND
V3_3
GND
10
XA<15..0>
GND
GND
V3_3
GND
GND
GND
GND
GND
V3_3
GND
GND
INT3 GND ALE
CS_X4
PLUG
3/71(TOTAL)
BLOCK NAME: _z11top_dn. PARENT BLOCK: \_ztopdn_\
STEVE SCULLY
1/2(BLOCK)
09/16/2004
DS33Z11/41/44DK01A0
CR-3
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1
PRINTED
Fri
Oct
20
10:50:40
2006
4B5<
5A5v
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4C3>
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3A4
3C2>
5C5v
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3D8>
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3D8
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3D8>
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4D8>
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3A5<>3A8<>3B5<> 3B8<>3C5<>3C8<>
3D8>
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3D8
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3A5<> 3A8<> 3B5<> 3B8<> 3C5<> 3C8<>
3D8
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3A8
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3D8>
4D8>
3D8
4D8
4D5<
3C6<>
5A5v
4D8
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
8
81
83
84
85
92
93 24
91
23
35
105
63
123
6
14
17
22
19
21
26
27
25
29
32
30
33
31
34
36
39
40
46
47
49
54
52
50
51
53
58
56
55
57
59
62
60
61
66
28
42
65
64
74
78
77
76
75
79
89
88
86
94
95
99
97
96
100
103
102
101
109
106
114
111
115
120
119
118
117
116
122
121
135
133
136
140
139
138
137
70
69
48
41
38
37
45
110
104
98
87
73
71
9
80
13
11
10
15
90
16
68
67
134
132
131
130
129
128
127
126
125
124
72
5
82
18
20
12
7
4
107
108
112
113 44
43
3
2
1
VDD
V3_3
8
81
83
84
85
92
93 24
91
23
35
105
63
123
6
14
17
22
19
21
26
27
25
29
32
30
33
31
34
36
39
40
46
47
49
54
52
50
51
53
58
56
55
57
59
62
60
61
66
28
42
65
64
74
78
77
76
75
79
89
88
86
94
95
99
97
96
100
103
102
101
109
106
114
111
115
120
119
118
117
116
122
121
135
133
136
140
139
138
137
70
69
48
41
38
37
45
110
104
98
87
73
71
9
80
13
11
10
15
90
16
68
67
134
132
131
130
129
128
127
126
125
124
72
5
82
18
20
12
7
4
107
108
112
113 44
43
3
2
1
_z11andlan_dn
HWMODE
DAT<7..0>
RESET_B
TDEN
RDEN
RD
INT
TSER
TCLKI
RCLKI
ADDR<9..0>
RSER
CS
WR
MODEC1
MODEC0
Z41TSYNC
Z41RSYNC
PAGES 13-19
GND
V3_3
I47
A_DUT<11..0>
D_DUT<7..0>
CS_X1
BTS_DUT
BIS1_DUT
BIS0_DUT
WR_DUT
RD_DUT
INT5
INT4
INT3
INT2
TMS_NU
TDI_NU
TDO_NU
TCK_NU
XD<7..0>
XA<15..0>
CS_X5
RESET_B
RW_X
CS_X4
CS_X3
CS_X2
WR_X
DS33Z11/41/44DK01A0
09/16/2004
4/71(TOTAL)
STEVE SCULLY
BLOCK
NAME:
_z11top_dn.
PARENT
BLOCK:
\_ztopdn_\
2/2(BLOCK)
CR-4
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE2
4D8
3D8
3D8>
3C8<>3C5<>3B8<>3B5<>3A8<>3A5<>
17A6v 17A5v
3D3<
17D5v
3D3<
17B3v
3D3<
17C3v
3D1>
17C3v
3C1>
17C3v
3C1>
17C3v
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17C3v
3D3<
14D4v
3C8<>
13B7v
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3C7<>
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19A7v
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19A7v
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19A7v
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17C7v
3A8
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13A5v
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3C7<>
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3A4<>
17A4v
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17B3v
3A5<>
17B3v
3A5<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
_motprocrescard_dn
CS_X1
CS_X2
CS_X3
RESET_B
CS_X5
CS_X4
TDO_NU
TCK_NU
TDI_NU
TMS_NU
INT2
INT3
INT4
INT5
RD_DUT
WR_DUT
D_DUT<7..0>
A_DUT<11..0>
BIS0_DUT
BIS1_DUT
BTS_DUT
XD<7..0>
XA<15..0>
WR
RW_X
V3_3
(INPUT)
PROC (FPGA) AUTOMATICALY IMPLEMENTS BUS MODE
HW MODE PINS ARE OUTPUTS FROM Z MODULE TO PROC
LED+TP
(OUTPUT)
DS33Z11/Z41
3C2^
3D2^
5B1<
3C2^
3D2^
5B2<
3C2^
3C2^
3C2^
3C2^
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3C1^
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3C1^
9D2<
3D1^
9D4<
3D2^
3D2^
3D2^
5A6<>3D1^
TP35
U18
RB174
J29
TP72
TP71
TP78
TP74
TP75
TP77
UXB06
RB359
RB342
DS44
UXB08
TP53
DS39
R197
TP36
SW26
SW25
SW24
R74
RB173
RB176
RB175
R55
RB178
RB177
Y13
RB345
RB343
RED
330
ZADDR0
JTDI
JTDO
RCLKI
ZMOSI
ZADDR1
ZADDR0
ADDR<9..0>
7
5
TDEN
INT
30
9
4
6
3
6
0
1
RED
330
5
10K
0
1
10K
2
30
2
3
4
7
ZADDR2
JTCLK
JTMS
JTDO
ADDR<9..0>
JTDI
TCK_NU
TXD2<1>
TXD3<1>
MDC
MDIO
30
30
TX_EN<1>
RDEN
TSER
RSER
TCLKI
30
30
TXD1<1>
TXD0<1>
JMP_3
JTRST
TDO_NU
8
ZSPICS
ZSPISCK
ZMISO
2.7V
TDI_NU
TMS_NU
DAT<7..0>
VALUE=30
VALUE=30
JTMS
JTRST
JTCLK
ZADDR2
ZMISO
ZSPISCK
ZADDR1
ZMOSI
COL_DET<1>
RXD1<1>
RXD3<1>
RXDV<1>
CKPHA
SCANMOD
SCANEN
AFCS
H10S
FULLDS
RMIIMIIS
DCEDTES
MODEC1
MODEC0
HWMODE
RESET_B
WR
ZSPICS
CS
RD
INT
RXD2<1>
TX_CLK<1>
RXD0<1>
RX_CLK<1>
RX_CRS<1>
RX_ERR<1>
REF_CLKO
30
BUFFER
BUFFER
REF_CLK
09/16/2004
1/6(BLOCK)
5/71(TOTAL)
STEVE SCULLY
DS33Z11/41/44DK01A0
CR-5 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_Z11ANDLAN_DN\(SCH_1):PAGE1
1
2
4
11
2
4
1
1 1 1111
65
4
9
7
3
10
8
1
2
B11
E10
E9
A10
B12
C8
E13
C7
F7
E6
D4
A2
A3
B3
A4
C3
B4
A6
A7
B6
F1
C2
B7
B1
A1
B2
C12
C5
C6
A5
B5
F5
H2
E4
D9
C9
B13
C11
A11
D10
G2
F6
E8
E7
C10
B10
A9
C4
A13
D7
D6
D5
D8
E2
B8
C1
E5
C13
E1
F3
D11
F2
D13
A8
B9
H1
1
6
2
8
7
3
4
5
4
4
4
5B2<>
5A3<>
5A3<>
5B4<>
5C3<
5C3<
5A6>
3D1^
5C3<
5D5<
5D5<
5D5<>
5D5<
8C5<
8C5<
8B4>
8B4>
8C5<
8C5<
8D5<
5D5<
5A5>
5B4<>
5B4<>
5A3<>
5A3<>
5A3<>
5A2<>
5C2>
5C2<
5B2<>
5C2<
8C3>
8C3>
8C3>
8C3>
9B4<
9B2<
9B4<
9C2<
9C4<
9C2<
9C4<
9D2<
3D2^
8B4<
5C2<
8C3>
8C5<
8D3>
8C3>
8C3>
8C3>
8A1<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
V3_3
SP3T
SP3T
SP3T
AT25160A_U
SI
GND
WP*
HOLD*
VCC
SO
SCK
CS*
OUT
IO
IN
IN
IN
OUT
IN
IN
IN
IN
IO
V3_3
JTAG
LINE IO
MICRO PORT/SPI MASTER PORT
MII/RMII PORTS
DS33Z11_U3
RSER
TXD<0>
TX_CLK
REF_CLK
TSER
RXD<2>
INT*
RD*/DS*
MDIO
JTDO
CS*
SPI_CS*
WR*/RW*
RST*
HWMODE
MODEC<0>
MODEC<1>
DCEDTES
RMIIMIIS
FULLDS
H10S
AFCS
SCAN/EN
SCAN/MODE
CKPHA
RCLKI
RXDV
RXD<3>
RXD<1>
COL_DET
TXD<1>
TXD<2>
JTDI
RDEN/RBSYNC
TDEN/TBSYNC
D<3>
D<0>/MOSI
D<7>
D<6>
MDC
A<3>
A<0>
A<1>
D<5>
A<4>
TCLKI
D<4>
D<2>/SPICK
D<1>/MISO
A<9>
A<7>
A<8>
A<6>
A<5>
A<2>
JTCLK
JTRST
JTMS
QOVF
REF_CLKO
RX_CRS/CRS_DV
RX_ERR
RX_CLK
TXD<3>
TX_EN
RXD<0>
OUT
OUT
OUT
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
NC7SZ86_U
V3_3
NC7SZ86_U
IN
SD_CLKO MAY BE DELAYED
AND CONNECTING
BY REMOVING 0 OHM RESISTOR
JUMPERS WITH 75 OHM COAX
UNMARKED RESISTORS ARE 30 OHMS
30
SD_CLKI
I228
NA
DS33Z11
10UF
V1_8ZCHIP
V1_8ZCHIP
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
10UF
10UF
10UF
10UF
0.1UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
470UF
470UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
10UF
10UF
Z41TSYNC
SD_RAS
SD_A<11..0>
SD_BA0
SD_BA1
SD_DQM2
SD_DQM1
SD_DQM0
SD_CAS
10
11
9
8
7
6
5
4
3
2
1
0
26
25
23
22
21
18
17
16
15
14
13
12
11
10
9
8
7
5
4
3
2
1
0
31
29
28
27
19
20
6
SD_CS
SD_DQM3
24
SD_DQ<31..0>
Z41RSYNC
0.1UF
0.1UF
NC_PINF9
SD_WE
R187
RB252
RB270
RB272
RB294
RB276
RB275
R220
R221
R222
R188
RB253
R185
RB259
R184
R183
RB258
RB257
RB245
R182
R223
R224
R225
R226
RB297
R227
RB260
R228
R181
R186
RB273
R180
R179
RB271
RB244
R178
R215
R216
R217
RB290
RB289
RB291
RB292
R218
RB256
RB255
RB296
RB274
R219
R189
RB293
RB295
RB278
RB277
RB254
TP46
TP70
TP69
CB428
CB351
CB170
CB136
CB430
CB153
CB129
CB159
CB173
CB249
CB235
CB303
CB226
CB214
CB434
CB213
CB437
CB281
CB244
CB451
CB141
CB186
CB425
CB452
CB413
CB382
CB419
CB418
CB224
CB354
CB175
CB433
CB432
CB183
CB426
CB182
CB252
U18
SD_CLKO
3D2^
3D2^
6/71(TOTAL)
09/16/2004
2/6(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
BLOCK
NAME:
_z11andlan_dn.
PARENT
BLOCK:
\_z11top_dn\
CR-6
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_Z11ANDLAN_DN\(SCH_1):PAGE2
111
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
F4
G6
H6
F10
L3
E11
E12
D12
M13
N2
M2
L2
N1
M1
K1
J1
J2
H3
M3
J3
L4
N4
N3
L1
K2
J12
M5
M7
M8
N8
G4
M10
M9
G13
K6
N5
L6
E3
D2
M12
H11
M11
N13
N11
L13
N12
K13
J13
M4
H4
M6
N7
L12
L5
L7
L8
L9
N9
G5
D3
H5
H10
K12
F12
F13
J10
J8
J9
K8
K7
J11
J6
F8
H7
J7
H13
H12
G12
F11
G11
L10
A12
K9
H9
K5
J5
K10
K3
F9
G1
G3
D1
H8
K11
L11
N10
G8
G7
G9
G10
N6
K4
J4
9D5<
10A4< 6B5<
10B4<>
10A4< 6D4<
10B4<>
7C4<
7A3>
7B4<
7B4<
7C4<
7C4<
7C4<
7C4<
7C4<
7C4<
7D7
7C4<
7C3<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
PWR/GND
SDRAM CONTROLLER SYSTEM
DS33Z11_U3
4VDD1.8
5VDD1.8
SDMASK<0>
5VDD3.3
4VDD3.3
2VDD3.3
3VDD3.3
SDA<1>
SDA<2>
SDA<3>
9VDD3.3
VSS0
NC3
NC2
NC1
VSS1
VSS2
VSS4
VSS5
10VDD3.3
VSS13
VSS18
SDATA<31>
SDATA<30>
SDATA<29>
SDATA<28>
SDATA<27>
SDATA<26>
VSS8
8VDD3.3
VSS3
VSS6
VSS7
VSS9
VSS11
VSS12
VSS10
VSS14
VSS17
VSS16
VSS15
11VDD3.3
6VDD3.3
0VDD1.8
0VDD3.3
SDA<0>
SDA<6>
SDA<5>
SDA<4>
SDA<7>
12VDD1.8
SBA<1>
SBA<0>
SCAS*
SWE*
SDATA<24>
SDATA<23>
SDATA<22>
SDATA<21>
SDATA<20>
SDATA<19>
SDATA<18>
SDATA<17>
SDATA<16>
1VDD1.8
2VDD1.8
SDCS*
SDCLKO
SRAS*
SYSCLKI
SDMASK<3>
SDMASK<2>
SDMASK<1>
SDA<11>
SDA<10>
SDA<9>
SDA<8>
SDATA<25>
SDATA<14>
SDATA<15>
SDATA<6>
SDATA<5>
SDATA<7>
SDATA<8>
SDATA<9>
SDATA<10>
SDATA<12>
SDATA<11>
SDATA<13>
SDATA<0>
SDATA<2>
SDATA<1>
SDATA<3>
SDATA<4>
11VDD1.8
10VDD1.8
9VDD1.8
8VDD1.8
6VDD1.8
7VDD1.8
7VDD3.3
1VDD3.3
3VDD1.8
V3_3
V3_3
IN
IN
MT48LC4M32B2 - 1 MEG X 32 X 4 BANKS
SYNCHRONOUS DRAM
FROM Z11 SYSCLKO
0
9
10
11
0
1
31
30
2
1
3
4
5
7
6
8
9
10
11
12
2
13
14
15
16
17
18
19
20
21
3
22
23
24
25
26
27
28
29
4
5
6
7
8
SD_DQ<31..0>
SD_BA1
SD_BA0
SD_DQM3
SD_CLKO
SD_DQM1
SD_DQM0
SD_RAS
SD_CAS
SD_WE
SD_CS
SD_A<11..0>
SD_DQM2
UB10
7/71(TOTAL)
09/16/2004
3/6(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
BLOCK
NAME:
_z11andlan_dn.
PARENT
BLOCK:
\_z11top_dn\
CR-7
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_Z11ANDLAN_DN\(SCH_1):PAGE3
43
29
55
3
68
20
67
18
17
16
19
71
28
59
22
23
25
26
60
27
61
63
62
65
64
66
24
21
10
11
13
74
76
77
79
80
83
82
85
31
33
34
37
36
39
42
40
47
45
48
50
51
53
49
41
8
15
1
5
7
4
2
54
56
84
52
78
46
32
38
6
12
72
86
44
58
75
81
35
9
6A2
6C7<
6D7<
6B8<
6B8<
6B8<
6B8<
6B8<
6B8<
6A8<
6B8<
6C8
6B8<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
MT48LC4M32B2_TSOP_U
VDDQ2
VDDQ3
VDDQ8
VDDQ7
VSS2
VSS1
VSS4
VSS3
VSSQ2
VSSQ1
VSSQ4
VSSQ3
VSSQ5
VSSQ7
VSSQ6
VSSQ8
DQ<31>
DQ<30>
DQ<0>
DQ<1>
DQ<3>
DQ<2>
VDD1
VDD2
DQ<4>
VDDQ4
VDDQ5
DQ<29>
DQ<28>
DQ<27>
DQ<26>
DQ<24>
DQ<25>
DQ<22>
DQ<23>
DQ<21>
DQ<19>
DQ<20>
DQ<18>
DQ<17>
DQ<16>
DQ<15>
DQ<13>
DQ<14>
DQ<12>
DQ<11>
DQ<10>
DQ<9>
DQ<8>
DQ<7>
DQ<6>
DQ<5>
A<11>
A<10>
A<9>
A<7>
A<8>
A<5>
A<6>
A<4>
A<2>
A<3>
A<1>
A<0>
BA<1>
BA<0>
DQM<3>
DQM<2>
DQM<1>
RAS*
DQM<0>
WE*
CAS*
CKE
CS*
CLK
VDDQ1
VDDQ6
VDD3
VDD4
V3_3
CHASSIS GND FOR PHY
HIERARCHICAL BLOCK
PAGES 11-12
I70
I69
100O100MZH
100O100MZH
10UF
10UF
0.1UF
TX_CLK<1>
TX_EN<1>
LED_DPLX_A0<1>
RXD2<1>
RXD1<1>
30
REF_CLK
MII_CLK
30
RED
AMBER
GREEN
LED_COL_A1<1>
LED_GDLINK_A2<1>
LED_RX_A4<1>
5.1K
RXDV<1>
MII_CLK
MDC
MDIO
LED_TX_A3<1>
TXD2<1>
RX_CLK<1>
RX_ERR<1>
RX_CRS<1>
RXD3<1>
RXD0<1>
25.000MHZ_3.3V
330
5.1K
330
5.1K
5.1K
LED_RX_A4<1>
LED_GDLINK_A2<1>
LED_COL_A1<1>
LED_TX_A3<1>
330
COL_DET<1>
5.1K
LED_DPLX_A0<1>
RESET_B
Y09
R140
RB44
RB48
RB72
RB60
RB47
DS15
DS11
DS06
RB78
RB54
RB57 R133
C10
CB04
CB05
L04
LB01
11C7v 5A5< 3D2^
TXD0<1>
TXD1<1>
TXD3<1>
BLOCK
NAME:
_z11andlan_dn.
PARENT
BLOCK:
\_z11top_dn\
8/71(TOTAL)
DS33Z11/41/44DK01A0
09/16/2004
4/6(BLOCK)
STEVE SCULLY
CR-8
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_Z11ANDLAN_DN\(SCH_1):PAGE4
1
8
4 5
1
2
1
2
1
2
2
1
1
2
1
2
11A5v 5B7<>
11A5v
5B8<
11C5v
8B8<
11A7v
5B7<
11A7v
5C7<
5C7<>
11C7v
8B3>
11C5v
8C6<
11C5v
8C6<
11C5v
8B6<
11A7v
5B7<
11C7v
8A1<
11C5v
5B7<
11C5v
5B7<
11C5v 8A8<>
11A5v
5B7<
11A5v
5B7<
11A5v
5B7<
11A5v
5B7<
11A7v5C7<>
11A7v
5C7<
11A7v
5C7<
11A7v
5B7<
11A7v
5C7<
11C5v 8A8<>
11C5v 8A8<>
11C5v
8B8<
11C5v
8B6<
11A7v
5B7<
11C5v
8C6<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
CHASSIS
V3_3
V3_3
VCC
1
OSC
GND OUT
IN
_mii_wan_dn
TXD0
TXD1
RX_CLK
RX_ERR
RX_CRS
RXD3
RXD2
RXD1
RXD0
RXDV
MII_CLK
MDC
MDIO
RESET_B
TX_EN
TX_CLK
LED_GDLINK_ADD2
LED_DPLX_ADD0
LED_COL_ADD1
TXD3
TXD2
COL_DET
LED_RX_ADD4
LED_TX_ADD3
CONNECT ANYWHERE
SIGNAME_TRI DOES NOT
MOTOROLA NON-MUX, MII, FULL DUPLEX, 100 MBIT, AUTO-FLOW CONTROL
MODE (SHOWN BELOW SIGNAL) RESULTS IN:
LOW
LOW
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
(HELPS PCB NETLIST)
CONFIG SWITCHES FOR Z11
CKPHA
SCANEN
RMIIMIISTRI
H10STRI
2.0K
SCANMOD
SD_CLKI
RMIIMIIS
2.0K
MODEC0
DCEDTES
2.0K
2.0K
SCANMODTRI
OSC100MHZ
2.0K
2.0K
2.0K
AFCSTRI
SCANENTRI
FULLDSTRI
MODEC0TRI
DCEDTESTRI
2.0K
HWMODETRI
CKPHATRI
2.0K
2.0K
MODEC1TRI
30
100.000MHZ_3.3V
30
2.0K
HWMODE
MODEC1
H10S
AFCS
FULLDS
R120
UXB04
Y06
RB67
SW14
SW17
RB70
RB366
SW43
SW44
RB367
RB64
SW11
RB65
SW12
SW13
RB66
RB69
SW16
SW42
RB365
RB63
SW10
SW15
RB68
R128
DS33Z11/41/44DK01A0
BLOCK
NAME:
_z11andlan_dn.
PARENT
BLOCK:
\_z11top_dn\
STEVE SCULLY
5/6(BLOCK)
09/16/2004
9/71(TOTAL)
CR-9
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_Z11ANDLAN_DN\(SCH_1):PAGE5
2
1
4
1
2
4
1
3
2
4
1
3
2
1
2
1
2
4
1
3
2
4
1
3
2
1
2
1
2
4
1
3
2
1
2
4
1
3
2
4
1
3
2
1
2
1
2
4
1
3
2
4
1
3
2
1
2
1
2
4
1
3
2
4
1
3
2
1
1
8
4 5
5A4<
5A4< 5A4<
6B8<
5A5<
3C1^
5A5>
5A5<
3D1^
5A5>
3C1^
5A5>
5A4< 5A4<
5A5<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
VCC
1
OSC
GND OUT
SP3T
SP3T
SP3T
SP3T
SP3T
SP3T
V3_3
V3_3
SP3T
SP3T
SP3T
SP3T
SP3T
NC7SZ86_U
V3_3
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
I39
1UF
1UF
1UF
1UF
10UF
1UF
1UF
BLACK BLACK
I38
RED
0.1UF
0.1UF
0.1UF
0.1UF
RED
V1_8ZCHIP
1UF
V1_8ZCHIP
CB131
2
1
CB139
2
1
C46
2
1
CB110
2
1
U07
CB102
C38
C45
1
2
C70
2
1
JB01
JB02
J54
JB08
CB253
CB234
CB456
CB217
CB192
CB345
CB225
CB344
CB355
CB181
CB436
CB454
CB453
CB304
CB280
CB435
CB455
CB450
BLOCK
NAME:
_z11andlan_dn.
PARENT
BLOCK:
\_z11top_dn\
6/6(BLOCK)
10/71(TOTAL)
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
CR-10
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_Z11ANDLAN_DN\(SCH_1):PAGE6
3
4
2
8
5
6
7
1
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
10A4<6D4<6B5<
6D4< 6B5<
10B4<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
CONN_BANANA_2P
B
A
CONN_BANANA_2P
B
A
CONN_BANANA_2P
B
A
CONN_BANANA_2P
B
A
V3_3
V3_3
MAX1792
IN
OUT
SET
GND
OUT
IN
SHDN
RST
0.2 BETWEEN CONNECTORS.
ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW
ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE
TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO
PLACEMENT NOTE:
LEDS NEED TO BE ATTACHED
OUTSIDE OF MODULE DUE TO
STRAP ADAPTING OPTION OF DP83847
COMPONETS FOR
C1 AND RBIAS MUST
BE PLACED CLOSE TO PIN
MII_CLK
RESET_B
LED_TX_ADD3
LED_COL_ADD1
LED_DPLX_ADD0
TXD0
TXD2
AN1
TXD1
MDC
10UF
5.1K
TX_CLK
TXD3
TX_EN
RXDV
RXD0
RXD1
RXD2
RXD3
10UF
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
LED_GDLINK_ADD2
30
LED_RX_ADD4
AN_V3_3
AN_V3_3
0.1UF
0.1UF
10UF
100O100MZH
RX_CLK
RX_ERR
COL_DET
RX_CRS
AN_EN
5.1K
AN0
5.1K
MDIO
0.1UF
10.0K
RBIAS
C1PIN
11/71(TOTAL)
BLOCK
NAME:
_mii_wan_dn.
PARENT
BLOCK:
\_z11andlan_dn\
PRINTED
Fri
Oct
20
10:50:42
2006
1/2(BLOCK)
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
CR-11
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page1_i1@\_ztop_lib\.\_z11andlan_dn\(sch_1):page4_i32@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-11
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page1_i1@\_ztop_lib\.\_z11andlan_dn\(sch_1):page4_i32@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-11
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page1_i1@\_ztop_lib\.\_z11andlan_dn\(sch_1):page4_i32@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-11
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page1_i1@\_ztop_lib\.\_z11andlan_dn\(sch_1):page4_i32@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
CR-11
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page1_i1@\_ztop_lib\.\_z11andlan_dn\(sch_1):page4_i32@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
8B4^
1
3
2
JP14
1
3
2
JP15
1
3
2
JP09
RB07
RB52
RB55
R109
1
TP03
50
51
54
55
61
58
60
62
64
65
44
47
5
8
9
12
13
34
28
56
14
57
59
63
2
1
3
46
42
48
49
15
16
17
18
19
22
23
24
25
4
21
20
53
52
U04
R08
8B4^
8B4^
2
1
C30
2
1
C32
12C8<
8C5^
12C8<
8C5^
12C8<
8C5^
12C8<
8D5^
12C4<
8C5^
12C8<
8C5^
65
4
9
7
3
10
8
1
2
J13
12C5<
8C3^
12B5<
8C3^
8C3^
12C6<>
12B8<
8D3^
12B8<
8C3^
12B8<
8C3^
12B8<
8C3^
65
4
9
7
3
10
8
1
2
J14
2
1
CB63
2
1
CB238
2
1
C198
2
1
CB39
2
1
CB41
2
1
C16
1
2
L03
CB96
CB497
2
1
CB93
2
1
CB239
2
1
C207
2
1
CB194
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IO
V3_3
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
V3_3
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
6
10
8
4
1
2
3
5
7
9
CONN_10P
IN
OUT
IN
IN
IN
V3_3
IN
IN
IN
CONTROL
DP83847_U1
RESERVED14
RESERVED15
LED_TX/PHYAD3
LED_GDLNK/PHYAD2
RESERVED3
MDC
MDIO
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_RX/PHYAD4
LED_SPEED
AN_EN
AN_1
AN_0
X1
X2
C1
RESET*
RBIAS
RESERVED1
RESERVED2
VDD3
VDD2
VDD1
VDD/ANA_VDD
VDD/IO_VDD2
VDD/IO_VDD1
RESERVED9
RESERVED8
RESERVED7
RESERVED6
RESERVED5
RESERVED4
RESERVED11
RESERVED10
GND5
GND4
GND3
GND2
GND1
RESERVED18
RESERVED17
RESERVED16
RESERVED13
RESERVED12
V3_3
IO
IO
IO
IO
IO
IN
SHOULD BE PLACED CLOSE TO PHY
RESISTORS FOR TD+-/RD+-
SHOULD BE PLACED CLOSE TO XFRM
CAPS FOR XFRM CENTER TAP
DNP
RX_ERR
RD_P
BUFFER
BUFFER
.1UF
30
TD_P
SYM_1
.1UF
54.9
.1UF
54.9
49.9
RD_N
TD_N
10K
30
30
30
30
RXD1
RXD0
RXD2
RXD3
TXD2
RD_P
RD_N
TXD3
TX_EN
TXD0
TXD1
TD_N
TD_P
49.9
30
DNP
30
30
RX_CRS
RX_CLK
TX_CLK
RXDV
COL_DET
12/71(TOTAL)
2/2(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
09/16/2004
BLOCK
NAME:
_mii_wan_dn.
PARENT
BLOCK:
\_z11andlan_dn\
CR-12
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page1_i1@\_ztop_lib\.\_z11andlan_dn\(sch_1):page4_i32@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-12
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page1_i1@\_ztop_lib\.\_z11andlan_dn\(sch_1):page4_i32@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-12
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page1_i1@\_ztop_lib\.\_z11andlan_dn\(sch_1):page4_i32@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-12
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page1_i1@\_ztop_lib\.\_z11andlan_dn\(sch_1):page4_i32@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
CR-12
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page1_i1@\_ztop_lib\.\_z11andlan_dn\(sch_1):page4_i32@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
2
R129
R141
R75
R134
9
2
8
6
3
4
10
1
5
J04
C06
C138
R01
C08
R02
R03
R04
4
1
UX04
RB87
RB109
RB110
4
1
UX03
RB88
R31
R71
43
40
7
6
26
41
32
29
30
27
11
10
45
36
35
37
38
39
31
33
U04
R76
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
PORT
DP83847_U1
RX_ER/PAUSE_EN*
RX_DV
TXD<1>
TXD<0>
TX_EN
TX_ER
TX_CLK
CRS/LED_CFG*
TD+
TD-
RXD<2>
RXD<0>
RXD<1>
RX_CLK
TXD<3>
RXD<3>
RD-
RD+
TXD<2>
COL
CHASSIS
CHASSIS
CHASSIS
NC7SZ86_U
NC7SZ86_U
V3_3
CONN_HFJ11_2450_U
J1
J2
J3
J6
J4,5
J7,8
P5
P1
SH2
P4
P3
P6
P8
P2
SH1
PROCESSOR RESOURCE CARD
MMC2107
I64
1
2
1
2
14
15
22
1
PD<31..0>
2
PA<22..0>
VDDSYN
GND
14
15
16
I68
11
12
13
16
18
17
19
18
20
21
10
17
9
8
7
6
23
24
25
26
28
19
27
29
30
31
5
4
3
2
0
20
0.0
.1UF
0
1
4
21
3
5
6
7
9
8
10
11
12
13
22
SOT143
2.93V
MAX811SEUS-T
I70
RESET_B
I51
RW
FLASH_VPP
TEA
VRH
OE
RCON
TA
MMC2107
NA
TQFP
I69
MMC2107
NA
TQFP
INT3
USER_LED2
RUN_KIT_USR
INT4
XTAL
MISO
MOSI
YCO
INT2
ONCE_TMS
CS0
RESET_B
CPUCLK_OUT
PROC_RESET_OUT
SCK
ONCE_DE_B
CS2
CS1
CSE0
TC2
TIM_16H_8L
CSE1
2107_TDO
ONCE_TDI
TC1
CS3
SS
ONCE_TRST_B
ONCE_TCLK
OSC_MCU
TIM_STATUS
TEST
USER_LED1
SCI1_IN
SCI1_OUT
SCI2_IN
SCI2_OUT
ICOC10
ICOC11
ICOC12
ICOC13
ICOC20
ICOC21
ICOC22
ICOC23
EB3
EB2
EB1
EB0
PQB3
PQB2
PQB1
PQB0
PQA4
PQA3
PQA1
PQA0
DS33Z11/41/44DK01A0
1/7(BLOCK)
09/16/2004
STEVE SCULLY
PRINTED
Fri
Oct
20
10:50:42
2006
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_z11top_dn\
13/71(TOTAL)
CR-13
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page1
CR-13
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page1
C67
R77
45
9
19
17
20
21
22
25
27
30
31
34
35
16
15
12
10
7
5
4
3
2
1
36
37
38
39
40
41
42
43
46
48
51
114
73
126
140
127
76
64
44
32
18
8
50
49
47
29
28
26
24
23
13
11
6
139
137
136
134
132
131
122
121
119
117
116
144
14
112
59
65
33
123
141
129
77
87
115
74
103
102
92
113
95
97
99
U15
4
3
1
2
SW23
69
68
82
84
75
79
124
91
90
80
71
138
86
118
128
120
93
143
83
85
62
67
98
100
101
104
105
106
88
96
60
135
133
78
81
110
111
109
108
107
94
142
130
125
53
52
55
54
58
57
56
72
63
61
66
89
70
U15
3
1
4
2
U13
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
MAX811_U
RESET*
VCC
GND
MR*
MMC2107
CONTROL
RXD1
INT7*
TXD2
ICOC10
TEST
INT1*
ICOC13
ICOC12
ICOC11
ICOC21
ICOC20
ICOC23
ICOC22
EXTAL
TCLK
TRST*
SS*
PQB0
PQA4
PQA3
PQA0
PQA1
CS3*
TC1
TDI
TDO
CSE1
EB3*
INT6*
PQB1
PQB2
PQB3
EB0*
EB1*
EB2*
TC2
CSE0
CS1*
CS2*
DE*
SCK
RSTOUT*
CLKOUT
RESET*
CS0*
TMS
INT0*
YC0
MOSI
MISO
XTAL
INT3*
INT2*
INT5*
INT4
RXD2
TXD1
MMC2107
PORT
TA*
SHS*
OE*
VRH
VSTBY
TEA*
VDDH
VDDF
VDDA
VPP
VDD6
VDD7
VDD8
VDDSYN
VDD3
VDD5
RW
VRL
A8
D31
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A7
A6
A5
A4
A3
A2
A1
A0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSSSYN
VSSF
VSSA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
VDD2
VDD1
VDD4
V3_3
FLASH ENABLE
INTERNAL
XTAL W/ PLL
MASTER MODE
FULL DRIVE
RESET CONFIGURATION
BOOT
INTERN/EXTERN
BOOT EXT
BOOT INTERNAL
WHEN SET FOR
D18 HAS A 10.5K LOAD TO V3V
RESET AND CHIP CONFIGURATION
D18 HAS A 10K LOAD TO GND
2
1
2
1
2
1
1
2
1
2
2
1
1
2
1
2
1
2
1
2
1
2
2
1
2
1
INT5
INT4
INT3
30
PA<17..1>PA<17..1>
PD<23..16>
PD<31..24>
PD<18>
PD<19>
PD<28>
PD<22>
USERFPGA2
PD<23>
PD<21>
BIS0OBSXI
RCON
BIS1OBSXI
PD<16>
BTS_OBSXI
PD<17>
FLASH_VPP
PD<26>
16
10K
10K
10K
10K
10K
10K
10K
17
10K
1.0K
10K
1.0K
1.0K
1.0K
1.0K
18
I69
ECJ-2VB1C104K
.1UF
0L_SMT0805_10PCT
AMBER
I65
1.0K
1.0K
1.0K
20
9
10
11
12
8
7
6
5
19
13
14
16
15
17
4
3
2
1
24
21
25
26
27
28
29
30
31
10K
22
9
10
11
12
13
14
16
17
23
8
7
6
5
4
3
2
1
15
I18
OE
EB1
CS0
NA
CY62128V
CY62128V
I54
OE
EB0
CS0
NA
CY62128V
CY62128V
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_z11top_dn\
14/71(TOTAL)
2/7(BLOCK)
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
CR-14
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page2
CR-14
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page2
19
18
14
21
15
20
17
13
31
27
28
10
26
11
25
12
9
32
16
24
29
1
23
2
3
4
5
6
7
8
30
22
U26
R229
19
21
18
15
17
14
20
13
28
27
31
4
26
3
25
2
5
32
16
24
29
1
23
12
11
10
9
8
7
6
30
22
U30
R79
R07
R248
1
2
DS20
R83
C12
2
7
8
16
15
12
11
10
9
6
5
4
3
14
13
1
SW06
R12
R16
2
1
R254
2
1
R255
R230
2
1
R160
R152
R236
2
1
R235
R233
R232
2
1
R231
R234
2
1
R196
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
V5_0
SWITCH
8 POS
V3_3
V3_3
V3_3
CY62128V
CE1*
CE2
A7
A6
A5
A4
A3
A2
A1
A0
N_C
WE*
OE*
GND
VCC
A16
A15
A14
A13
A12
A11
A10
A9
A8 IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V3_3
CY62128V
CE1*
CE2
A7
A6
A5
A4
A3
A2
A1
A0
N_C
WE*
OE*
GND
VCC
A16
A15
A14
A13
A12
A11
A10
A9
A8 IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V3_3
JTAG CONFIGURATION
ALIGN KEY
PIN
ONCETDI
MMC2107
ONCETDO
PIN
TDI
...FPGA+FLASH...
BUT DO NOT POPULATE
PLACE PADS FOR CAP
10UF
5.6
1UF
1UF
1UF
1UF
.1UF
8.0MHZ
I47
1.0M
1UF
10K
10K
I35
10K
10K
10K
1UF
10UF
1UF
10K
1UF
1UF
1UF
I13
I11
XTAL
ONCE_TCLK
VDDSYN
PRT1_OUT
PRT1_IN
68UF
1UF
330
22.0UH
SMT1206_5PCT
ERJ-8GEYJ5R6V
68UF
1
2
2
1
2
1
2
1
2
1
2
1
OSC_MCU
I1
RESET_B
2107_TDO
ONCE_TDI
ONCE_TMS
ONCE_DE_B
ONCE_TRST_B
NA
CON14P
CON14P
I31
PRT1_IN
SCI1_OUT
SCI1_IN
PRT1_OUT
NA
MAX3233E
MAX3233E
15/71(TOTAL)
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_z11top_dn\
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
3/7(BLOCK)
CR-15
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page3
CR-15
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page3
13
9
7
5
11
3
1
10
12
8
6
4
14
2
J06
2
1
C26
3
4
2
1
8
5
6
7
U01
2
1
C52
1
2
L02
1
2
CB28
2
1
C40
1
2
C14
2
1
C21
2
1
RB134
R209
1
2
CB113
1
2
C07
1
2
C02
C27
1
2
C33
1
2
C44
2
1
R87
20
1
8
4
5
6
7
9
10
11
12
13
14
15
16
17
18
19
3
2
U21
R95
R110
9
5
4
2
1
3
6
7
8
J28
R80
2
1
R81
2
1
C56
R56
1
2
X01
R10
1
2
C03
1
2
CB488
1
2
CB490
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
V3_3
V3_3
CONN_DB9P
H
G
F
C
A
B
D
E
J
V3_3
MAX3233E
INVALID*
T2IN
T2OUT
GND
V-
C2-
C2+
C1-
C1+
V+2
V+1
FORCEOFF*
VCC
T1OUT
R1OUT
FORCEON
T1IN
R1IN
R2OUT R2IN
V3_3
V5_0
MAX1675
LX
GND
SHDN
OUT FB
LBI
REF
LBO*
CON14P
RED
RED
RED
1
2
1
2
1
2
8
7
6
31
30
29
28
27
26
25
16
24
23
22
21
20
5
4
3
2
1
15
0
16
17
18
19
RED
14
RED
RED
330
330
330
330
GREEN
5
13
4
3
2
1
5
4
3
2
1
12
11
10
9
OE
RW
TA
CS1
CS2
EB0
EB1
CS0
TEA
SCI2_IN
SCI2_OUT
SPARE_B<5..0>
USER_LED1
TIM_INTERUPT
PROC_RESET_OUT
CFG_DIN
PA<16..0>
X_INIT
PD<31..16>
USER_LED2
TIM_INTERUPT_IND
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_z11top_dn\
16/71(TOTAL)
09/16/2004
4/7(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
CR-16
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page4
CR-16
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page4
L12
M13
B6
B4
G13
E14
A9
D12
B10
E13
A3
G15
B11
A5
A4
A6
B3
C9
F14
A7
B5
A8
E7
H14
J13
E6
F12
E10
D5
L16
C5
K13
L15
H16
H15
G16
H13
R16
F15
E16
P16
L13
F13
D7
D14
C15
A10
A11
C12
F16
E15
A13
C16
D16
B12
C8
D9
N15
N14
C6
L14
C7
C10
N16
M16
K14
K16
J16
K15
J15
M14
M15
E11
A12
B16
D11
G14
D10
T15
G12
B8
B7
K12
J14
A14
C11
D6
C13
B13
B9
D8
U27
1
2
DS38
1
2
DS16
1
2
DS18
R176
2
1
R32
R70
R237
1
2
DS43
65
4
9
7
3
10
8
1
2
J45
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
6
10
8
4
1
2
3
5
7
9
CONN_10P
V3_3
XC2S50_BGA
BANK 2
BANK 0
BANK 3
BANK 1
IO10_1
IO9_1\VREF
IO1_1\CS*
IO2_1\WRITE*
IO3_1
IO4_1\VREF
IO5_1
IO4_0
IO3_0
IO2_0\VREF
GCK3
IO15_3
IO14_3
IO23_3
IO22_3
IO21_3
IO20_3
IO19_3
IO18_3
IO17_3
IO16_3
IO13_3\TRDY
IO12_3
IO11_3\D4
IO10_3\VREF
IO9_3
IO8_3\D5
IO7_3\D6
IO6_3
IO5_3
IO4_3\VREF
IO3_3
IO2_3\D7
IO1_3\INIT*
IO24_2
IO23_2
IO22_2
IO21_2
IO20_2
IO19_2
IO18_2
IO17_2
IO16_2
IO15_2
IO14_2
IO13_2\(DOUT,BUSY)
IO12_2\(DIN,D0)
IO11_2
IO10_2\VREF
IO9_2
IO8_2
IO7_2\D1
IO6_2\D2
IO5_2
IO4_2
IO3_2\D3
IO2_2\VREF
IO2_1\IRDY
IO22_1
IO21_1
IO20_1
IO19_1
IO18_1
IO17_1
IO16_1
IO15_1
IO14_1
IO13_1
IO12_1
IO11_1
IO8_1
IO7_1
IO6_1
GCK2
IO20_0
IO19_0
IO18_0
IO17_0
IO16_0
IO15_0
IO14_0
IO13_0
IO12_0
IO11_0
IO10_0
IO9_0
IO8_0
IO7_0\VREF
IO6_0
IO5_0
IO1_0
RW ALSO FUNCTIONS AS ALT_RD_DS
WE ALSO FUNCTIONS AS ALT_WR_RW
BUS MODE
DETECTION (DUT AT CS_X2)
D_DUT<7..0>
A_DUT<11..0>
5
0
CS_X2
BTS_DUT
WR_DUT
ALE_DUT
RD_DUT
CS_X3
CS_X4
CS_X5
CS_X6
ALE
CPUCLK_OUT
I46
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
SPARE_A<10..1>
6
8
9
5
4
7
3
2
1
10
10
5
9
8
7
6
I34
CONN_THRU-HOLE
NA
NA
4
3
2
1
XD<7..0>XD<7..0>
0
1
2
3
4
6
7
8
9
10
XA<11..0>
0
1
2
3
4
5
6
7
8
9
10
11
11
USERFPGA2
INT5
CS_X1
RW_X
WR
BIS0_DUT
BIS1_DUT
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
5/7(BLOCK)
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_z11top_dn\
17/71(TOTAL)
CR-17
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page5
CR-17
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page5
65
4
9
7
3
10
8
1
2
J46
N8
T10
R6
T7
R5
M2
T12
T6
M1
T5
N2
P1
T3
T2
R10
T13
N12
B1
N10
L2
T4
T11
P12
F2
P13
P8
N11
R13
N5
M6
P11
F1
N9
C2
L3
R7
G5
G4
H2
K3
P7
T8
T9
P10
C1
R11
D1
E1
K4
G3
H3
M10
G1
A2
E3
D2
F3
E2
J4
R12
K5
L5
M7
N7
R8
E4
H4
P9
F5
F4
G2
L4
N6
L1
R1
N1
P5
M3
K1
M11
P6
J1
H1
J2
T14
R9
J3
M4
K2
U27
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
BANK 5
BANK 7
XC2S50_BGA
BANK 6
BANK 4
IO11_7
IO19_5
IO4_6\VREF
IO2_4
IO5_5
IO1_6\TRDY
IO2_6
IO3_6
IO5_6
IO6_6
IO7_6
IO8_6
IO9_6
IO10_6\VREF
IO11_6
IO12_6
IO13_6
IO14_6
IO15_6
IO16_6
IO17_6
IO3_4\VREF
IO1_4
IO1_5
GCK1
IO23_7
IO22_7
IO21_7
IO20_7
IO19_7
IO18_7
IO17_7
IO16_7
IO15_7
IO14_7
IO13_7
IO12_7\IRDY
IO10_7
IO9_7\VREF
IO8_7
IO7_7
IO6_7
IO5_7
IO4_7
IO3_7\VREF
IO2_7
IO1_7
IO23_6
IO22_6
IO21_6
IO20_6
IO19_6
IO18_6
IO18_5
IO17_5
IO16_5
IO15_5
IO14_5
IO13_5
IO12_5
IO11_5
IO10_5
IO9_5
IO8_5\VREF
IO7_5
IO6_5
IO4_5
IO3_5
IO2_5\VREF
IO22_4
IO21_4
IO20_4
IO19_4
IO18_4
IO17_4
IO16_4
IO15_4
IO14_4
IO13_4
IO12_4
IO11_4
IO10_4
IO9_4\VREF
IO8_4
IO7_4
IO6_4
IO5_4
IO4_4
GCK0
6
10
8
4
1
2
3
5
7
9
CONN_10P
MBVER
CS_X1
CS_X6
RD_DUT
WR_DUT
CS_X2
CS_X3
ALE_DUT
CS_X5
CS_X4
SS
SCK
MISO
MOSI
RESET_B
D_DUT<7..0>
0
1
2
3
7
6
5
4
2
1
0
10K
10K
10K
10K
7
6
5
4
A_DUT<11..0>
11
10
9
8
A_DUT<11..0>
INT4
INT2
INT3
INT5
INT4
INT5
INT3
INT2
TDO_NU
RESET_B
BIS0_DUT
BTS_DUT
BIS1_DUT
TCK_NU
TMS_NU
TDI_NU
RW_X
WR_DUT
RD_DUT
XA<15..0>
A_DUT<11..0>
D_DUT<7..0>
XD<7..0>
CS_X3
CS_X2
CS_X1
CS_X5
CS_X4
WR
3
6/7(BLOCK)
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_z11top_dn\
18/71(TOTAL)
CR-18
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page6
CR-18
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page6
4B5^
17C3<>
4B4^
19A6<>
4B4^
19A6<>
4B4^
19A6<>
4C3^
17B3<>
4C3^
18A6<>17C3<>
4C5^
18A6<>17C3<>
17B7
4B3^
18C618B717A6
4C5^
45
39
41
43
47
1
3
5
23
21
17
11
9
7
27
25
29
37
35
33
31
15
13
24
22
50
12
14
26
28
30
32
40
46
48
42
34
6
4
10
8
2
36
38
49
44
20
18
16
19
J42
2
1
R257
2
1
R256
2
1
R253
2
1
R252
4C5^
18C6<>14C3<>13A7<>
4C5^
18C6<>17A6<>14C3<>
4D5^
18C6<>14D3<>13A7<>
4D5^
18C6<>13A7<>
4B4^
19A6<>
19B1<18A7<
4C3^
15C3<>13B5<>
13A4>
4C3^
18B6<>17A4<>
4D3^
18B6<>17B3<>
4D3^
18B6<>17B3<>
4C3^
18B6<>17A4<>
4C3^
17B3<>
4C3^
18B6<>17A4<>
4C5^
17C3<>
4B5^
17C3<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
V3_3
V3_3
CONN_50P_T1E1
USER6
INT2
CS1
CS6
AD0
5V2
AD3
AD4
A11
A8
INT5
A10
A9
AD5
AD1
RD
WR
AD2
AD6
AD7
CS2
CS3
INT3
INT4
ALE
CS5
CS4
USER3
USER4
USER12
USER13
USER14
USER15
USER11
USER9
USER10
GND4
USER1
USER2
USER5
USER7
USER8
GND3
GND2
GND1
5V1
3.3V2
3.3V1
USER16
USER17
IO
IO
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
DONE
CCLK
XRST
JTD_SPART2FLASH
XI_TMS
V2_5XI
10UF
330
1UF
1UF
1UF
.1UF
.1UF
.1UF
1UF
.1UF
.1UF
.1UF
.1UF
1UF
1UF
1UF
1UF
1UF
TMS_NU
TDO_NU
TDI_NU
10K
JTD_FLASH_TDO
X_INIT
CFG_DIN
CCLK
JTD_SPART2FLASH
XI_TMS
ONCE_TCLK
DONE
XRST
V2_5XI
XI_TMS
JTD_FLASH_TDO
TCK_NU
10K
ONCE_TCLK
RESET_B
ONCE_TCLK
.1UF
JTD_SPART_TDI
JTD_SPART_TDI
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
1
2
2
1
2
1
1
2
2
1
2
1
1
2
2
1
2
1
2
1
7/7(BLOCK)
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
19/71(TOTAL)
BLOCK
NAME:
_motprocrescard_dn.
PARENT
BLOCK:
\_z11top_dn\
CR-19
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page7
CR-19
:
@\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page7
CB383
1
2
CB412
1
2
CB485
CB69
CB49
C210
C211
CB265
C212
C143
CB121
CB320
CB80
CB122
CB467
CB271
C181
1
2
R214
7
9
2
10
6
5
4
20
18
16
15
14
13
12
11
3
8
19
17
1
U29
RB333
E8
F9
H11
H12
J11
L9
M9
L8
M8
J5
J6
H5
H6
C14
D4
D13
E12
M5
M12
N13
P3
P14
D3
A15
C4
B14
D15
R14
N3
P2
R3
R4
P4
L6
J10
H9
G11
F7
F6
B15
B2
A16
A1
F8
E9
F10
F11
G6
G7
G8
G9
G10
H7
H8
H10
J7
J8
J9
K6
K7
K8
K9
K10
K11
L7
L10
L11
R2
R15
T1
T16
P15
N4
C3
E5
J12
U27
65
4
9
7
3
10
8
1
2
J44
R161
C153
3
4
2
8
5
6
7
1
U31
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
MAX1792
IN
OUT
SET
GND
OUT
IN
SHDN
RST
V3_3
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
XC2S50_BGA
CONTROL
VCCO8
VCCINT5
VCCINT1
VCCINT9
PROGRAM*
GND36
GND35
GND34
GND33
GND32
GND31
GND30
GND28
GND27
GND26
GND25
GND24
GND23
GND21
GND20
GND19
GND18
GND16
GND15
GND13
GND12
GND11
GND10
GND9
GND8
GND7
VCCO3
VCCO2
GND1
GND2
GND3
GND4
GND5
GND6
GND14
GND17
GND22
GND29
NC1
NC2
M2
M1
M0
DONE
CCLK
TDO
TCK
TDI
TMS
VCCINT12
VCCINT11
VCCINT10
VCCINT8
VCCINT7
VCCINT6
VCCINT4
VCCINT3
VCCINT2
VCCO16
VCCO15
VCCO14
VCCO13
VCCO12
VCCO11
VCCO10
VCCO9
VCCO7
VCCO6
VCCO5
VCCO4
VCCO1
CE*
TCK
TMS
CLK
D0
DNC1
OE/RST*
DNC2
TDI
CF*
XILINX_XCF01S
VCCJ
VCCO
VCCINT
TDO
DNC3
GND
DNC6
CEO*
DNC5
DNC4
V3_3
V3_3 V3_3
V3_3
DS21458 WAN INTERFACE BLOCK
2.048MHZ_3.3V
RB160
RB184
LIUC
MCLK
MCLK
30
30
ONCE_TCLK
I73
RESET_AH
10UF
10UF
0.1UF
0.1UF
0.1UF
WR
CS
0.1UF
0.1UF
RESET_B
0.1UF
0.1UF
ESIBR0
ESIBRD
0.1UF
RD
MUX
BTS
10UF
6
5
4
3
2
1
7
0
6
5
4
3
2
1
0
8
7
9
NA
BUFFER
RED
330
I37
I38
NC7SZ86
NA
INVERTER
I41
ADDR<9..0>
DAT<7..0>
RESET_AH
10UF
10UF
10UF
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
ESIBR1
WAN_INT
XI_TMS
NC7SZ86
WAN_INT
U20
UX11
DS25
R114
1
2
UXB05
CB112
CB340
CB151
C103
CB154
CB126
CB236
C48
C42
CB205
2
1
CB138
CB204
CB120
2
1
CB156
CB160
CB161
CB144
CB179
CB220
CB200
CB127
2
1
CB155
2
1
YB02
JTDO458
JTD_FLASH_TDO
MCLK2FPGA
46A1<>
55A3<> 54C7<>
55A4<
55A2<> 54C7<>
55A755A554C7
55A455A254C3
55D5> 46A4<>
PRINTED
Fri
Oct
20
10:50:44
2006
46/71(TOTAL)
09/16/2004
1/10(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
BLOCK NAME: _quadte1wan_dn. PARENT BLOCK: \_wan4z44_dn\
CR-46
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE1
P4
P5
P6
R6
N13
H10
J12
C12
C11
E4
D4
F4
L13
M13
F3
H1
J16
A9
T8
A11
T6
B11
F1
F2
L16
L15
H9
H4
D9
H5
E10
H3
H2
K14
J15
G4
N7
B9
T7
G2
H6
J11
P8
D10
N8
P7
M7
R7
G1
G3
B10
R8
H8
J8
J9
D13
D12
D11
N6
N5
N4
C9
A10
M8
K15
J13
J14
G8
K13
C10
K16
L14
M16
E2
M15
E1
B12
A12
T5
R5
T13
T9
A4
T12
D16
A8
A5
H16
E16
M1
J1
N1
E9
P3
K9
C13
D3
E3
N14
M14
4
11
2
4
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
8
4 5
51D7<
46D7<
46C7<
52C1< 52C8<> 52A7<>
52B1< 55D6<>
51C7<
51C7<
51B7<
51C7<
46B7<
51C7<
52C1< 52C8<> 52A7<>
55D5>46C7>
52A7<>
52C6<>
53B6<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
VCC
1
OSC
GND OUT
V3_3
V3_3
V3_3
IO
V3_3
NC7SZ86_U
V3_3
NC7SZ86_U
CONTROL
DS21458_U
DVDD42
DVDD43
DVDD32
DVDD31
DVDD23
NC1
NC2
NC3
RVSS11
RVSS12
RVSS13
RVSS21
RVSS22
RVSS31
RVSS32
RVSS23
RVSS41
RVSS33
RVSS43
RVSS42
TVSS11
TVSS12
TVSS21
TVSS22
TVSS31
TVSS41
TVSS32
TVSS42
DVDD41
JTCLK
JTDI
JTDO
RPOSI
TEST1
TEST2
TSTRST
CS*
RD*
WR*
DVSS11
DVSS12
DVSS13
DVSS21
DVSS22
DVSS23
ESIBS<1>
ESIBS<0>
ESIBRD
MUX
BTS
AD<7>
AD<6>
AD<5>
AD<4>
AD<3>
AD<2>
AD<1>
AD<0>
A<9>
A<8>
A<7>/ALE_AS
A<6>
A<5>
A<4>
A<3>
JTMS
JTRST
A<0>
A<2>
A<1>
INT*
LIUC
MCLK1
RCLKI
TVDD41
TVDD42
TVDD32
TVDD31
TVDD22
TVDD12
TVDD21
RVDD4
RVDD3
RVDD2
RVDD1
DVDD33
DVSS42
DVSS41
DVSS33
DVSS31
DVSS32
DVDD21
DVDD22
MCLK2
RNEGI
DVSS43
TVDD11
DVDD13
DVDD12
DVDD11
IN
IN
IN
IN
OUT
V3_3
IN
PORT1_RRING = PIN L1
PORT2_RRING = PIN F16
RLOS1
TRING2
TTIP2
TRING1
TTIP1
RRING1
TCLK1
RTIP1
TSER1
RCLK1
RSER1
RRING2
RSER2
RLOS2
RSYNC2
TCLK2
RTIP2
TSER2
TSYSCLK2
RSYSCLK1
BPCLK1
TSYSCLK1
RSYNC1
TSSYNC1
RCLK2
TSYNC1
TSSYNC2
TSYNC2
RSYSCLK2
RGAPCLK2 TGAPCLK2
RGAPCLK1 TGAPCLK1
U20
U20
53B2<>
53B2<>
53B7<>
53C2<
53A7<>
53C2<
53A7<>
53A2<>
53B2<>
53B7<>
53B7<> 53A2<>
53B7<> 53A2<>
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
47/71(TOTAL)
2/10(BLOCK)
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
CR-47
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE2
F16
H14
G15
G10
G11
F15
B14
D14
J10
E15
F14
H15
E14
A14
A13
E13
H12
C16
B16
H13
B13
E11
D15
G14
G13
A15
G12
H11
F10
G16
C15
C14
G9
F13
A16
E12
B15
F11
F12
L1
J4
K2
K3
L2
M2
T3
M4
H7
K5
L3
J3
K6
R3
R4
N2
J6
P1
N3
J5
T4
L7
J7
K4
M3
T2
L5
J2
K8
K1
P2
R1
M6
L4
R2
M5
T1
K7
L6
51A6<>
49B5<
49C5<
49D8<
49D8<
49C8<
49C8<
49A5<
51A6<>
53D5<>
49A5<
53D7<
53D7<
53C6<>
53D7<
53D5<>
53D5<>
53D4<>
53D4<>
53D4<>
53D7<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
IN
OUT
OUT
IN
IN IO
IN IO
OUT
OUT
PORT
DS21458_U
TCLKI
TLINK
TNEGO
TNEGI
TPOSO
TPOSI
TSER
RCLKO
RLINK
RTIP
RCLK
RNEGO
TCLK
TCLKO
RMSYNC
RFSYNC
TCHCLK
TSIG
TRINGB
BPCLK
TSYNC
TLCLK
RPOSO
TCHBLK
TRINGA
TTIPA
RSYNC
RSYSCLK
RSIGF
RLOS/LOTC
TSYSCLK
TSSYNC
TTIPB
RLCLK
RCHCLK
RCHBLK
RSIG
RSER
RRING
PORT
DS21458_U
TCLKI
TLINK
TNEGO
TNEGI
TPOSO
TPOSI
TSER
RCLKO
RLINK
RTIP
RCLK
RNEGO
TCLK
TCLKO
RMSYNC
RFSYNC
TCHCLK
TSIG
TRINGB
BPCLK
TSYNC
TLCLK
RPOSO
TCHBLK
TRINGA
TTIPA
RSYNC
RSYSCLK
RSIGF
RLOS/LOTC
TSYSCLK
TSSYNC
TTIPB
RLCLK
RCHCLK
RCHBLK
RSIG
RSER
RRING
IN
PORT4_RRING = PIN T11
PORT3_RRING = PIN A6
TSYSCLK3 TSYSCLK4
TSSYNC4
RSYSCLK4
TTIP3
RCLK4
TRING4
TTIP4
TRING3 RRING4
RSER4
RLOS4
RSYNC4
TCLK4
RTIP4
TSER4
RRING3
RLOS3
RSYSCLK3
TCLK3
RCLK3
RTIP3
TSER3RSER3
RSYNC3
TSSYNC3
TSYNC4TSYNC3
RGAPCLK3 TGAPCLK3 RGAPCLK4 TGAPCLK4
U20
U20
53B7<>
53C2<
53A7<>
53A2<>
53B2<>
53A2<>
53B7<>
53B2<>
53C2<
53A7<>
53B7<> 53A2<> 53B7<> 53A2<>
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
48/71(TOTAL)
3/10(BLOCK)
CR-48
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE3
T11
P9
R10
R11
M9
R12
P16
M11
L8
P12
N11
R9
N12
P15
N15
R13
N10
T14
R14
N9
N16
K11
P13
P11
M10
R16
L9
P10
K12
T10
T15
P14
K10
L10
R15
M12
T16
L12
L11
A6
C8
B7
C7
D7
B6
C2
A3
D8
D6
E7
B8
B5
C1
D1
C5
F9
C4
B3
E8
D2
F5
B4
C6
E6
B2
F6
F8
G5
A7
C3
A2
G6
D5
B1
E5
A1
G7
F7
53C7< 53C7<
53D4<>
53D7<
50D8<
50B5<
50C5<
50D8< 50A5<
51A6<>
53D4<>
50A5<
50C8<
51A6<>
53D7<
50C8<
53D4<>
53D4<>
53D4<>
53D4<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IN
IN
OUT
OUT
IN
IN
IO
IO
IN
OUT
OUT
PORT
DS21458_U
TCLKI
TLINK
TNEGO
TNEGI
TPOSO
TPOSI
TSER
RCLKO
RLINK
RTIP
RCLK
RNEGO
TCLK
TCLKO
RMSYNC
RFSYNC
TCHCLK
TSIG
TRINGB
BPCLK
TSYNC
TLCLK
RPOSO
TCHBLK
TRINGA
TTIPA
RSYNC
RSYSCLK
RSIGF
RLOS/LOTC
TSYSCLK
TSSYNC
TTIPB
RLCLK
RCHCLK
RCHBLK
RSIG
RSER
RRING
PORT
DS21458_U
TCLKI
TLINK
TNEGO
TNEGI
TPOSO
TPOSI
TSER
RCLKO
RLINK
RTIP
RCLK
RNEGO
TCLK
TCLKO
RMSYNC
RFSYNC
TCHCLK
TSIG
TRINGB
BPCLK
TSYNC
TLCLK
RPOSO
TCHBLK
TRINGA
TTIPA
RSYNC
RSYSCLK
RSIGF
RLOS/LOTC
TSYSCLK
TSSYNC
TTIPB
RLCLK
RCHCLK
RCHBLK
RSIG
RSER
RRING
IN
THE PCB LAYOUT INCORRECTLY USES PINS 38-40, 33-35, 28-30 AND 23-25
AS THE TX PRIMARY. THIS HAS BEEN CORRECTED IN THE SCHEMATIC,
THE PCB / ASSEMBLY HAS BEEN MODIFIED TO ACCOMMODATE THIS.
RJ45_4PORT
I13
R207
R208
CB390
RB313
RB312
RB321
RB322
L10
JB12
CB395
RB317
RB316
RB327
RB328
L10
R203
R204 C173
1UF
I14
0
0
61.9
61.9
0.1UF
I25
RJ45_4PORT
I26
0
0
61.9
61.9
0.1UF
0
0
0
0
TRING2
TTIP2
RRING1
RTIP1
RRING2
RTIP2
TTIP1
TRING1
JB12
1UF
C176
I11
L10
I2
L10
CR-49
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE4
4/10(BLOCK)
49/71(TOTAL)
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
7
6
33
34
35
2
1
C6
C4
C3
C5
C2
C1
C7
C8
8
31
10
32
9
2
1
2
1
2
1
2
1
17
16
23
24
25
1
2
A6
A4
A3
A5
A2
A1
A7
A8
18
21
20
22
19
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
47C2>
47C2>
47C4<
47C4<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
RCV
6
5
RJ45
7
4
3
2
1
8
XMIT
RCV
6
5
RJ45
7
4
3
2
1
8
XMIT
THE PCB LAYOUT INCORRECTLY USES PINS 38-40, 33-35, 28-30 AND 23-25
THE PCB / ASSEMBLY HAS BEEN MODIFIED TO ACCOMMODATE THIS.
AS THE TX PRIMARY. THIS HAS BEEN CORRECTED IN THE SCHEMATIC,
CB396
RB319
RB318
R201
R202
RB329
L10
CB391
RB315
RB314
RB323
RB324
R206
R205
C174
L10
JB12
TRING3
TTIP3
TTIP4
TRING4
RTIP3
RRING3
RRING4
RTIP4
I9
I8
RJ45_4PORT
0.1UF
61.9
61.9
0
0
I25
0.1UF
61.9
61.9
RJ45_4PORT
I19
0
0
0
0
1UF
0
0
RB330
1UF
C175
JB12
I24
L10
I7
L10
5/10(BLOCK)
50/71(TOTAL)
DS33Z11/41/44DK01A0
09/16/2004
STEVE SCULLY
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
CR-50
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE5
2
1
2
1
2
1
2
1
2
1
D6
D4
D3
D5
D2
D1
D7
D8
2
1
2
1
1
2
2
1
38
39
40
3
36
5
37
4
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
12
11
28
29
30
B6
B4
B3
B5
B2
B1
B7
B8
13
26
15
27
14
48C1>
48C1>
48C4<
48C4<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
RCV
6
5
RJ45
7
4
3
2
1
8
XMIT
RCV
XMIT
6
5
RJ45
7
4
3
2
1
8
ALL UNMARKED BIAS RESISTORS ARE 10K
MOT
NOTMUX
RLOS1
RLOS2
RLOS3
RLOS4
LIUC
ESIBRD
ESIBR0
ESIBR1
MUX
BTS
2.0K
2.0K
2.0K
330
2.0K
330
330
330
2.0K
2.0K
RB185
RB209
RB192
RB228
DS30
RB221
DS32
DS33
DS34
RB234
RB251
RB284
RB183
RB303
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
51/71(TOTAL)
DS33Z11/41/44DK01A0
STEVE SCULLY
09/16/2004
6/10(BLOCK)
CR-51
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE6
1
2
2
1
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
47A8>
47A4>
48A8>
48A4>
46C7<
46A2<>
46A2<>
46A2<>
46A2<
46A2<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
XRST
DONE
CCLK
JTD_SPART2FLASH
ONCE_TCLK
JTD_SPART_TDI
XI_TMS
0.1UF
0.1UF
0.1UF
0.1UF
.1UF
.1UF
0.1UF
0.1UF
JTDO458
JTD_SPART_TDI
ONCE_TCLK
XI_TMS
TDI_NU
X_INIT
CFG_DIN
.1UF
330
1UF
.1UF
.1UF
.1UF
.1UF 1UF
1UF
1UF
.1UF
1UF
10K
V2_5XI
XRST
DONE
JTD_SPART2FLASH
CCLK
V2_5XI
XI_TMS
ONCE_TCLK
JTD_FLASH_TDO
TMS_NU
TCK_NU
TDO_NU
1UF
1UF
10UF
1UF
RESET_B
1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
RB129
1
2
CB274
1
2
CB230
1
2
C86
1
2
C114
1
2
UB06
CB66
2
1
CB65
2
1
C192
2
1
CB269
1
2
CB338
2
1
CB278
2
1
CB337
1
2
CB216
2
1
CB135
2
1
C23
2
1
C22
2
1
C188
2
1
CB275
1
2
C77
2
1
U10
R84
1
2
U08
JB07
C108
CB134
CB168
CB150
CB190
CB257
C125
C142
C123
CB62
C135
C85
1
2
CB245
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
7/10(BLOCK)
52/71(TOTAL)
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
CR-52
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE7
E8
F9
H11
H12
J11
L9
M9
L8
M8
J5
J6
H5
H6
C14
D4
D13
E12
M5
M12
N13
P3
P14
D3
A15
C4
B14
D15
R14
N3
P2
R3
R4
P4
L6
J10
H9
G11
F7
F6
B15
B2
A16
A1
F8
E9
F10
F11
G6
G7
G8
G9
G10
H7
H8
H10
J7
J8
J9
K6
K7
K8
K9
K10
K11
L7
L10
L11
R2
R15
T1
T16
P15
N4
C3
E5
J12
7
9
2
10
6
5
4
20
18
16
15
14
13
12
11
3
8
19
17
1
65
4
9
7
3
10
8
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
3
4
2
8
5
6
7
1
52B8<>
52B8<>
52C8<>
46C7>
52C1<
52C1<46C7<
52C8<>
52C1<46C7<
52C8<>
53B2<>
52B8<
52B1<
52B1<>
52B1<>
52C1<
46C7<
52A7<>
52C1<
46C7<
52A7<>
46C7<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
MAX1792
IN
OUT
SET
GND
OUT
IN
SHDN
RST
V3_3
V3_3
V3_3
6
10
8
4
1
2
3
5
7
9
CONN_10P
CE*
TCK
TMS
CLK
D0
DNC1
OE/RST*
DNC2
TDI
CF*
XILINX_XCF01S
VCCJ
VCCO
VCCINT
TDO
DNC3
GND
DNC6
CEO*
DNC5
DNC4
XC2S50_BGA
CONTROL
VCCO8
VCCINT5
VCCINT1
VCCINT9
PROGRAM*
GND36
GND35
GND34
GND33
GND32
GND31
GND30
GND28
GND27
GND26
GND25
GND24
GND23
GND21
GND20
GND19
GND18
GND16
GND15
GND13
GND12
GND11
GND10
GND9
GND8
GND7
VCCO3
VCCO2
GND1
GND2
GND3
GND4
GND5
GND6
GND14
GND17
GND22
GND29
NC1
NC2
M2
M1
M0
DONE
CCLK
TDO
TCK
TDI
TMS
VCCINT12
VCCINT11
VCCINT10
VCCINT8
VCCINT7
VCCINT6
VCCINT4
VCCINT3
VCCINT2
VCCO16
VCCO15
VCCO14
VCCO13
VCCO12
VCCO11
VCCO10
VCCO9
VCCO7
VCCO6
VCCO5
VCCO4
VCCO1
V3_3 V3_3
V3_3
TSER PULLDNS USED IN IBO MODE
(IMPLEMENTS IMUX)
TSER1
CFG_DIN
RGAPCLK4
RGAPCLK3
RGAPCLK2
RGAPCLK1
TSSYNC4
TSSYNC1
BPCLK1
RSYSCLK1
RSYSCLK2
TSYSCLK3
RSYSCLK3
RSYSCLK
2.0K
2.0K
2.0K
RSER4
RSYNC1
TSER2
TSER3
TSER4
TCLK1
TCLK2
TCLK3
TCLK4
X_INIT
RSER3
RSER2
RSER1
RCLK4
RCLK3
RCLK2
RCLK1
TSYNC4
RSYNC4
TSSYNC3
RSYNC3
RSYNC2
TSSYNC2
TSYNC1
TSYNC2
TSYNC3
TSYSCLK4
TSYSCLK2
TSYSCLK1
RSYSCLK4
2.0K
RSER1
RSER2
RSER3
RSER4
SPARE_TP1
SPARE_TP2
U10
R88
R113
R104
R94
TGAPCLK4
TGAPCLK3
TGAPCLK2
TGAPCLK1
TP30
TP32
TSYSCLK
MCLK2FPGA
STEVE SCULLY
8/10(BLOCK)
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
53/71(TOTAL)
09/16/2004
DS33Z11/41/44DK01A0
CR-53
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE8
A7
A5
C6
B4
A3
B3
D8
A6
C8
D7
E7
B5
D6
A4
E6
D5
C5
C9
B11
A11
C10
A8
C12
D12
B12
A13
D11
A12
B10
D10
A10
E10
A9
H16
H15
G16
H13
G13
F15
E16
F14
D16
F13
E13
D14
C15
H14
J13
G14
G15
G12
F16
F12
E15
E14
C16
B16
N15
N14
M13
L14
P16
L13
N16
M16
K14
K16
J16
K15
J15
M14
M15
L12
L16
K13
L15
K12
J14
T15
R16
B8
B7
C7
B6
E11
C11
A14
C13
B13
B9
D9
1 1
47B5<
52C8<>
48B4<
48B8<
47B4<
47B8<
48B1<
47B6<
47B6>
47B8<
47B4<
48B5<
48B8<
53C2< 48B4>
47B8<>
47B1<
48B5<
48B1<
47C5<
47C1<
48C5<
48C1<
52B8<>
53C2< 48B8>
53C2< 47B4>
53C2< 47B8>
48C4>
48C8>
47C4>
47C8>
48B1<>
48B4<>
48B5<
48B8<>
47B4<>
47B2<
47B6<>
47B2<>
48B5<>
48B1<
47B2<
47B6<
48B4<
53A7<>
47B8>
53A7<>
47B4>
53A7<>
48B8>
53A7<>
48B4>
48B1<>
48B5<>
47B1<>
47B5<>
46D7<
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
XC2S50_BGA
BANK 2
BANK 0
BANK 3
BANK 1
IO10_1
IO9_1\VREF
IO1_1\CS*
IO2_1\WRITE*
IO3_1
IO4_1\VREF
IO5_1
IO4_0
IO3_0
IO2_0\VREF
GCK3
IO15_3
IO14_3
IO23_3
IO22_3
IO21_3
IO20_3
IO19_3
IO18_3
IO17_3
IO16_3
IO13_3\TRDY
IO12_3
IO11_3\D4
IO10_3\VREF
IO9_3
IO8_3\D5
IO7_3\D6
IO6_3
IO5_3
IO4_3\VREF
IO3_3
IO2_3\D7
IO1_3\INIT*
IO24_2
IO23_2
IO22_2
IO21_2
IO20_2
IO19_2
IO18_2
IO17_2
IO16_2
IO15_2
IO14_2
IO13_2\(DOUT,BUSY)
IO12_2\(DIN,D0)
IO11_2
IO10_2\VREF
IO9_2
IO8_2
IO7_2\D1
IO6_2\D2
IO5_2
IO4_2
IO3_2\D3
IO2_2\VREF
IO2_1\IRDY
IO22_1
IO21_1
IO20_1
IO19_1
IO18_1
IO17_1
IO16_1
IO15_1
IO14_1
IO13_1
IO12_1
IO11_1
IO8_1
IO7_1
IO6_1
GCK2
IO20_0
IO19_0
IO18_0
IO17_0
IO16_0
IO15_0
IO14_0
IO13_0
IO12_0
IO11_0
IO10_0
IO9_0
IO8_0
IO7_0\VREF
IO6_0
IO5_0
IO1_0
PORTS ARE ENABLED BY DEFAULT ON T1 BRD, AND ARE DISABLED USING JUMPERS ON T3 BRD
WR
Z41TSYNC
5
30
OBS_TCLK<3>
OBS_RSER<3>
OBS_RDEN<4>
30
Z44_TCLK<4>
30
OBS_TCLK<4>
T3ENH_T1ENLPRT1
T3ENH_T1ENLPRT2
T3ENH_T1ENLPRT3
T3ENH_T1ENLPRT4
2.0K
2.0K
2.0K
2.0K
1
30
OBS_RDEN<3>
30
Z44_TDEN<4>
OBS_TDEN<4>
OBS_TDEN<3>
30
Z44_TDEN<3>
Z44_RDEN<3>
Z44_TCLK<3>
Z44_RCLK<3>
Z44_RSER<3>
30
30
Z44_RSER<2>
Z44_TCLK<2>
Z44_RCLK<2>
Z44_RDEN<2>
Z44_TDEN<2>
Z44_RSER<1>
Z44_RCLK<1>
Z44_RDEN<1>
Z44_TCLK<1>
Z44_TDEN<1>
30
30
30
30
30
30
30
30
0
0
2
3
4
6
2
DAT<7..0>
7
1
Z44_RDEN<4>
30
Z44_RCLK<4>
30
RD
Z44_TSER<1>
Z44_TSER<2>
T3ENH_T1ENLPRT1
T3ENH_T1ENLPRT2
T3ENH_T1ENLPRT3
T3ENH_T1ENLPRT4
ADDR<9..0>
30
Z41RSYNC
30
30
CS_X4
Z44_TSER<3>
OBS_RCLK<3>
OBS_RSER<4>
OBS_RCLK<4>
Z44_RSER<4>
30
Z44_TSER<4>
U10
M3
T11
T9
J4
T7
K2
T5
T10
T8
P5
K3
L5
P1
M1
T14
T3
T2
K5
N2 L3
M4
R50
R51
R49
R53
R54
R45
R72
R52
R46
R73
R43
R42
RB94
RB101
R44
R41
R39
RB93
RB92
R40
TP29
TP27
TP15
TP16
TP28
TP26
TP24
TP12
TP25
TP13
TP14
TP17
RB04
RB05
RB45
RB46
R48
R47
09/16/2004
STEVE SCULLY
DS33Z11/41/44DK01A0
54/71(TOTAL)
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
9/10(BLOCK)
CR-54
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE9
N8
R11
M11
N11
T12
R13
P13
M10
R10
P10
R12
P11
T13
N12
P12
N10
T4
N6
R5
R6
M7
P8
N5
M6
N7
T6
P7
R7
M2
C2
B1
C1
E4
D1
E1
F2
G3
H3
G4
G1
A2
E3
D2
F3
E2
F1
F4
F5
G2
H2
H4
R8
N9
P9
K1
R1
N1
L4
K4
L2
L1
J1
H1
J2
P6
R9
J3
G5
1111
111
1
11 1 1
46B7<
55A3<>
55C6<>
55B1<>
55D6<> 54A6<>
55C6<> 54A5<>
55C2<> 54A5<>
55B2<> 54A5<>
55B1<>
55C1<>
55C4<>
55B1<>
55B4<>
55C4<>
55C8<>
55C6<>
55C8<>
55C8<>
55C6<>
55D8<>
55C8<>
55C8<>
55C6<>
55C6<>
55A4 55A2
46B1<>
55B4<>
55B4<>
46B7<
55A2<>
55D6<>
55C6<>
54A8<
55D6<>
54A8<
55C6<>
54A8<
55C2<>
54A8<
55B2<>
55A7 55A5
46C2<
55C6<>
55D2<>
55C1<>
55B4<>
55B1<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
BANK 5
BANK 7
XC2S50_BGA
BANK 6
BANK 4
IO11_7
IO19_5
IO4_6\VREF
IO2_4
IO5_5
IO1_6\TRDY
IO2_6
IO3_6
IO5_6
IO6_6
IO7_6
IO8_6
IO9_6
IO10_6\VREF
IO11_6
IO12_6
IO13_6
IO14_6
IO15_6
IO16_6
IO17_6
IO3_4\VREF
IO1_4
IO1_5
GCK1
IO23_7
IO22_7
IO21_7
IO20_7
IO19_7
IO18_7
IO17_7
IO16_7
IO15_7
IO14_7
IO13_7
IO12_7\IRDY
IO10_7
IO9_7\VREF
IO8_7
IO7_7
IO6_7
IO5_7
IO4_7
IO3_7\VREF
IO2_7
IO1_7
IO23_6
IO22_6
IO21_6
IO20_6
IO19_6
IO18_6
IO18_5
IO17_5
IO16_5
IO15_5
IO14_5
IO13_5
IO12_5
IO11_5
IO10_5
IO9_5
IO8_5\VREF
IO7_5
IO6_5
IO4_5
IO3_5
IO2_5\VREF
IO22_4
IO21_4
IO20_4
IO19_4
IO18_4
IO17_4
IO16_4
IO15_4
IO14_4
IO13_4
IO12_4
IO11_4
IO10_4
IO9_4\VREF
IO8_4
IO7_4
IO6_4
IO5_4
IO4_4
GCK0
P1 CONNECTOR (RECEPTICAL)
P2 CONNECTOR (RECEPTICAL)
WAN R.C. CONNECTOR TO MOTHERBOARD
NOTE 3184 IS ON CS3 WHILE 21455 IS ON CS2/CS4
RECEPTACLE
GND
INT2
RESET_B
T3ENH_T1ENLPRT1
Z44_TSER<1>
Z44_TDEN<1>
Z44_TCLK<1>
Z44_TCLK<2>
TMS_NU
TDI_NU
8
Z44_RSER<1>
GND
GND
Z41RSYNC
Z41TSYNC
RECEPTACLE
INT5
Z44_RDEN<1>
I28
GND
RD
GND
GND
GND
Z44_RSER<2>
GND
Z44_RDEN<3>
TCK_NU
TDO_NU
GND
OSC4_NU
OSC2_NU
V3_3
Z44_RCLK<2>
Z44_RDEN<2>
GND
GND
GND
GND
V3_3
GND
GND
V3_3
GND
GND
GND
GND
GND
OSC3_NU
GND
GND
GND
V3_3
GND
GND
GND
V3_3
GND
Z44_TDEN<2>
V3_3
7
4
2
0
6
5
3
GND
9
1
GND
ADDR<9..0>
ADDR<9..0>
GND
0
3
5
7
2
4
DAT<7..0>
GND
V3_3
GND
ALE
CS_X4
GND
GND
GND
GND
GND
Z44_TDEN<3>
GND
Z44_TCLK<3>
GND
GND
GND
GND
GND
V3_3
GND
GND
GND
GND
GND
GND
GND
V3_3
GND
GND
GND
V3_3
GND
CS_X5
GND
GND
GND
GND
I27
Z44_TCLK<4>
SIG_RETURN
GND
GND
Z44_RCLK<1>
GND
V3_3
INT2
SIG_RETURN
Z44_TDEN<4>
INT3
WAN_INT
GND
GND
OSC1_NU
GND
GND
V3_3
CS_X3
6
DAT<7..0>
I29
CS_X2
CS
GND
Z44_RCLK<4>
GND
Z44_RSER<4>
Z44_RDEN<4>
Z44_RSER<3>
V3_3
Z44_RCLK<3>
GND
GND
Z44_TSER<4>
Z44_TSER<3>
T3ENH_T1ENLPRT3
T3ENH_T1ENLPRT4
WR
GND
GND
SIG_RETURN
Z44_TSER<2>
T3ENH_T1ENLPRT2
GND
SIG_RETURN
1
J12 J09
09/16/2004
55/71(TOTAL)
10/10(BLOCK)
STEVE SCULLY
DS33Z11/41/44DK01A0
BLOCK
NAME:
_quadte1wan_dn.
PARENT
BLOCK:
\_wan4z44_dn\
CR-55
:
@\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE10
55D7<>
52B1<
46A2<>
54A8<
54A6<>
54B8<>
54B8<
54B8<
54B8<
52A8<>
52A8<>
54B8<
54C7<
54C7<
54B8<
46B7<
54C7<>
54A8<
54B1<
52A8<>
52A8<>
54B8<
54B8< 54B8<
55A754C7
46C2<
55A5 54C7
46C2<
55A4
54C3 46B1<>
54C7<>
54B1<
54B1<
54B1<
54B8<
55D6<>
55C6<>
55A1>
54A1<
46C7>
46A4<>
55A2 54C3 46B1<>
46B7<
54B1<
54B1<
54B1<
54B1<
54B1<
54B1<>
54B1<>
54A8<
54A5<>
54A8<
54A5<>
46B7<
54C7<>
55C6<>55B2<>
55A1>
54B8<>
54A8<
54A5<>
55C6<>55B2<>
55A1>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
8
81
83
84
85
92
93 24
91
23
35
105
63
123
6
14
17
22
19
21
26
27
25
29
32
30
33
31
34
36
39
40
46
47
49
54
52
50
51
53
58
56
55
57
59
62
60
61
66
28
42
65
64
74
78
77
76
75
79
89
88
86
94
95
99
97
96
100
103
102
101
109
106
114
111
115
120
119
118
117
116
122
121
135
133
136
140
139
138
137
70
69
48
41
38
37
45
110
104
98
87
73
71
9
80
13
11
10
15
90
16
68
67
134
132
131
130
129
128
127
126
125
124
72
5
82
18
20
12
7
4
107
108
112
113
44
43
3
2
1
VDD
V3_3
8
81
83
84
85
92
93 24
91
23
35
105
63
123
6
14
17
22
19
21
26
27
25
29
32
30
33
31
34
36
39
40
46
47
49
54
52
50
51
53
58
56
55
57
59
62
60
61
66
28
42
65
64
74
78
77
76
75
79
89
88
86
94
95
99
97
96
100
103
102
101
109
106
114
111
115
120
119
118
117
116
122
121
135
133
136
140
139
138
137
70
69
48
41
38
37
45
110
104
98
87
73
71
9
80
13
11
10
15
90
16
68
67
134
132
131
130
129
128
127
126
125
124
72
5
82
18
20
12
7
4
107
108
112
113 44
43
3
2
1