NXP Semiconductors Data Sheet WCT101XADS Features Compliant with the latest version Wireless Power Consortium (WPC) power class 0 specification power transmitter design Supports wide transmitter DC input voltage range of 6V (limited duration at Start/Stop operation) to 16V Integrated digital demodulation Supports two-way communication, transmitter to receiver by FSK and receiver to transmitter by ASK Supports Q factor detection and calibrated power loss based Foreign Object Detection (FOD) framework Supports low standby power Uses rail voltage control, phase difference control or duty cycle control with the fixed operation frequency to alleviate EMI in automotive system Supports key FOB avoidance function Supports operation frequency dithering technology to eliminate AM band interference Supports CAN/LIN/IIC/SCI/SPI interfaces LED for system status indication Over-voltage/current/temperature protection Software based solution to provide maximum design freedom and product differentiation AECQ-100 grade 2 certification Applications Automotive Extended Power Profile Power Transmitter o WPC compliant or customer properties Wireless Charging System Functional Diagram Document Number: WCT101XADS Rev. 0 09/2016 , Overview Description The WCT101xA is a wireless power transmitter controller that integrates all required functions for WPC "Qi" compliant wireless power transmitter design. It is an intelligent device that works with the NXP touch sensing technology or uses periodically analog PING to detect a mobile device for charging while gaining super low standby power. Once the mobile device is detected, the WCT101xA controls the power transfer by adjusting the rail voltage, the phase difference, or the duty cycle of the power stage according to message packets sent by the mobile device. To maximize the design freedom and product differentiation, the WCT101xA supports the extended power profile consumer power transmitter design (WPC MP-Ax types, MP-Bx types or customization) using the fixed operation frequency control methods such as rail voltage control, phase difference control or duty cycle control etc. by software based solution, which can support wireless charging with both extended power profile power receiver and baseline power profile power receiver. In addition, the easy-to-use FreeMASTER GUI tool has configuration, calibration and debugging functions to provide the user-friendly design experience and reduce time-to-market. The WCT101xA includes a digital demodulation module to reduce the external components, an FSK modulation module to support two-way communication, a protection module to handle the over-voltage/current/temperature protection, an FOD module to protect from overheating by misplaced metallic foreign objects, and general CAN/IIC/SCI/SPI interfaces for external communications. It also handles any abnormal condition and operational status and provides comprehensive indicator outputs for robust system design. Contents 1 Absolute Maximum Ratings .................................................................................................................... 4 1.1 Electrical operating ratings...................................................................................................................................... 4 1.2 Thermal handling ratings ........................................................................................................................................ 5 1.3 ESD handling ratings ............................................................................................................................................... 5 1.4 Moisture handling ratings ....................................................................................................................................... 5 2 Electrical Characteristics ......................................................................................................................... 6 2.1 General characteristics ............................................................................................................................................ 6 2.2 Device characteristics .............................................................................................................................................. 8 2.3 Thermal operating characteristics ......................................................................................................................... 22 3 Typical Performance Characteristics ............................................................................................... 23 3.1 System efficiency .................................................................................................................................................. 23 3.2 Standby power ...................................................................................................................................................... 23 3.3 Digital demodulation ............................................................................................................................................ 23 3.4 Two-way communication ...................................................................................................................................... 23 3.5 Foreign object detection ....................................................................................................................................... 23 4 Device Information ................................................................................................................................. 24 4.1 Functional block diagram ...................................................................................................................................... 24 4.2 Product features overview .................................................................................................................................... 24 4.3 Pinout diagram ..................................................................................................................................................... 26 4.4 Pin function description ........................................................................................................................................ 26 WCT101XADS, Rev. 0, 09/2016 2 NXP Semiconductors 4.5 Ordering information ............................................................................................................................................ 37 4.6 Package outline drawing ....................................................................................................................................... 37 5 Software Library ...................................................................................................................................... 38 5.1 Memory map ........................................................................................................................................................ 38 5.2 Software library and API description ..................................................................................................................... 38 6 Design Considerations ........................................................................................................................... 39 6.1 Electrical design considerations ............................................................................................................................ 39 6.2 PCB layout considerations ..................................................................................................................................... 40 6.3 Thermal design considerations.............................................................................................................................. 40 7 Links ............................................................................................................................................................. 42 8 Revision History ....................................................................................................................................... 42 WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 3 1 Absolute Maximum Ratings 1.1 Electrical operating ratings Table 1. Absolute maximum electrical ratings (VSS = 0 V, VSSA = 0 V) Characteristic Symbol Notes 1 Min. Max. Unit Supply Voltage Range VDD -0.3 4.0 V Analog Supply Voltage Range VDDA -0.3 4.0 V ADC High Voltage Reference VREFHx -0.3 4.0 V Voltage difference VDD to VDDA VDD -0.3 0.3 V Voltage difference VSS to VSSA Vss -0.3 0.3 V VIN Pin Group 1 -0.3 5.5 V VIN_RESET Pin Group 2 -0.3 4.0 V Oscillator Input Voltage Range VOSC Pin Group 4 -0.4 4.0 V Analog Input Voltage Range VINA Pin Group 3 -0.3 4.0 V VIC - -5.0 mA VOC - 20.0 mA IIcont -25 25 mA Digital Input Voltage Range Input Voltage Range Input clamp current, per pin (VIN < VSS - 0.3 V) Output clamp current, per pin 2, 3 4 Contiguous pin DC injection current--regional limit sum of 16 contiguous pins Output Voltage Range (normal push-pull mode) Output Voltage Range (open drain mode) Output Voltage Range DAC Output Voltage Range Ambient Temperature Storage Temperature Range 1. 2. 3. 4. VOUT Pin Group 1,2 -0.3 4.0 V VOUTOD Pin Group 1 -0.3 5.5 V VOUTOD_RESET Pin Group 2 -0.3 4.0 V VOUT_DAC Pin Group 5 -0.3 4.0 V TA -40 105 C TSTG -55 150 C Default Mode: Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: Pin Group 3: ADC and Comparator Analog Inputs Pin Group 4: XTAL, EXTAL Pin Group 5: DAC analog output Continuous clamp current. All 5 volt tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN greater than VDIO_MIN (=VSS -0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed, then a current limiting resistor is required. I/O is configured as push-pull mode. WCT101XADS, Rev. 0, 09/2016 4 NXP Semiconductors 1.2 Thermal handling ratings Table 2. Thermal handling ratings Symbol 1. 2. Description TSTG Storage temperature TSDR Solder temperature, lead-free Min. Max. Unit Notes -55 150 C 1 - 260 C 2 Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Table 3. ESD handling ratings Characteristic 1. 1 Min. Max. Unit ESD for Human Body Model (HBM) -2000 +2000 V ESD for Machine Model (MM) -200 +200 V ESD for Charge Device Model (CDM) -500 +500 V Latch-up current at TA= 85C (ILAT) -100 +100 mA Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. 1.4 Moisture handling ratings Table 4. Moisture handling ratings Symbol MSL 1. Description Moisture sensitivity level Min. Max. Unit Notes - 3 - 1 Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 5 2 Electrical Characteristics 2.1 General characteristics Table 5. General electrical characteristics Recommended operating conditions (VREFLx = 0 V, VSSA = 0 V, VSS = 0 V) Characteristic 2 Supply Voltage Symbol VDD ,VDDA ADC (Cyclic) Reference VREFHA Voltage High VREFHB ADC (SAR) Reference Voltage High Notes VREFHC 3 Test Min. Typ. Max. Unit 2.7 3.3 3.6 V - 3.0 VDDA V - 2.0 VDDA V conditions Voltage difference VDD to VDDA VDD -0.1 0 0.1 V - Voltage difference VSS to VSSA Vss -0.1 0 0.1 V - 5.5 V - VDD V - 0.35xVDD V - Input Voltage High (digital inputs) Voltage High Input Voltage Low (digital inputs) VIH 1 (Pin Group 1) 0.7xVDD VIH_RESET 1 (Pin Group 2) 0.7xVDD VIL 1 (Pin Group 1,2) VIHOSC 1 (Pin Group 4) 2.0 VDD + 0.3 V - VILOSC 1 (Pin Group 4) -0.3 0.8 V - IOH 1 (Pin Group 1) - -2 - Oscillator Input Voltage High XTAL driven by an external clock source Oscillator Input Voltage Low Output Source Current High (at VOH min.) 4,5 * Programmed for low drive strength * Programmed for high mA 1 (Pin Group 1) - -9 drive strength WCT101XADS, Rev. 0, 09/2016 6 NXP Semiconductors Output Source Current Low (at VOL max.) 4,5 * Programmed for low drive strength IOL * Programmed for high 1 (Pin Group 1,2) - - 2 mA 1 (Pin Group 1,2) - 9 drive strength Output Voltage High VOH 1 (Pin Group 1) VDD - 0.5 - - V IOH = IOHmax Output Voltage Low VOL 1 (Pin Group 1,2) - - 0.5 V IOL = IOLmax pull-up enabled or disabled Comparator Input Current VIN = 2.4 V to 5.5 V 1 (Pin Group 1) Digital Input Current High IIH - 0 +/-2.5 A 0 +/-2 A VIN = VDDA - 0 +/-2 A VIN = VDDA 1 (Pin Group 2) VIN = 2.4 V to VDD IIHC 1 (Pin Group 3) Oscillator Input Current High IIHOSC 1 (Pin Group 4) Internal Pull-Up Resistance RPull-Up 20 - 50 k - RPull-Down 20 - 50 k - High Internal Pull-Down Resistance Comparator Input Current IILC 1 (Pin Group 3) - 0 +/-2 A VIN = 0V Oscillator Input Current Low IILOSC 1 (Pin Group 4) - 0 +/-2 A VIN = 0V DAC Output Voltage Range VDAC 1 (Pin Group 5) V RLD = 3 k, CLD = 400 pF IOZ 1 (Pin Group 1,2) - 0 +/-1 A - VHYS 1 (Pin Group 1,2) 0.06xVDD - - V - CIN - 10 - pF - COUT - 10 - pF - Low VSSA + 0.04 - VDDA 0.04 1 Output Current High Impedance State Schmitt Trigger Input Hysteresis Input capacitance Output capacitance GPIO pin interrupt pulse width 6 Bus TINT_Pulse 7 1.5 - - TPort_H_DIS 8 5.5 - 15.1 ns TPort_H_EN 8 1.5 - 6.8 ns clock Port rise and fall time (high drive strength). Slew disabled. Port rise and fall time (high drive strength). Slew enabled. - 2.7 VDD 3.6 V 2.7 VDD 3.6 V WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 7 Port rise and fall time (low drive strength). Slew disabled. TPort_L_DIS 9 8.2 - 17.8 ns 2.7 VDD 3.6 V Port rise and fall time (low drive strength). Slew enabled. TPort_L_EN 9 3.2 - 9.2 ns 2.7 VDD 3.6 V 0 - 100 MHz - - - 50/100 MHz - Device (system and core) clock frequency fSYSCLK Bus clock fBUS 10 1. Default Mode o Pin Group 1: GPIO, TDI, TDO, TMS, TCK o Pin Group 2: o Pin Group 3: ADC and Comparator Analog Inputs o Pin Group 4: XTAL, EXTAL o Pin Group 5: DAC analog output 2. ADC (Cyclic) specifications are not guaranteed when VDDA is below 3.0 V. 3. ADC (SAR) is only on WCT1013A device. 4. Total chip source or sink current cannot exceed 75 mA. 5. Contiguous pin DC injection current of regional limit--including sum of negative injection currents or sum of positive injection currents of 16 contiguous pins--is 25 mA. 6. Applies to a pin only when it is configured as GPIO and configured to cause an interrupt by appropriately programming GPIOn_IPOLR and GPIOn_IENR. 7. The greater synchronous and asynchronous timing must be met. 8. 75 pF load 9. 15 pF load 10. WCT1011A only supports the maximum bus clock of 50 MHz, and WCT1013A supports 100 MHz maximum bus clock. 2.2 Device characteristics Table 6. General device characteristics Power mode transition Behavior Symbol Description Min. Max. Unit 199 225 s Notes After a POR event, the amount of delay TPOR from when VDD reaches 2.7 V to when the first instruction executes (over the operating temperature range). TS2R STOP mode to RUN mode 6.79 7.27 s 1 TLPS2LPR LPS mode to LPRUN mode 240.9 551 s 2 VLPS mode to VLPRUN mode 1424 1459 s 4 WAIT mode to RUN mode 0.57 0.62 s 3 LPWAIT mode to LPRUN mode 237.2 554 s 2 VLPWAIT mode to VLPRUN mode 1413 1500 s 4 TVLPS2VLPR TW2R TLPW2LPR TVLPW2VLPR Power consumption operating behaviors WCT101XADS, Rev. 0, 09/2016 8 NXP Semiconductors Typical at 3.3 V, 25 C Mode Conditions Max. frequency Notes IDD IDDA 100 MHz 38.1 mA/- 9.9 mA/- 50 MHz/100 27.6 mA/63.7 100 MHz core clock, 50 MHz peripheral clock, regulators are in full regulation, relaxation oscillator on, PLL powered on, continuous MAC instructions with fetches from program Flash, all peripheral modules enabled, TMRs and SCIs using 1x RUN1 peripheral clock, NanoEdge within 5 eFlexPWM using 2x peripheral clock, ADC/DAC (only one 12-bit DAC and all 6-bit DACs) powered on and clocked, comparator powered on, all ports configured as inputs with input low and no DC loads 5 50 MHz/100 MHz core and peripheral clock, regulators are in full regulation, relaxation oscillator on, PLL powered on, continuous MAC instructions with fetches from program Flash, all peripheral modules enabled, TMRs and SCIs using 1x RUN2 peripheral clock, NanoEdge within eFlexPWM using 2x peripheral clock, 5 MHz mA 50 MHz/100 24.0 mA/43.5 9.9 mA/16.7 5 mA ADC/DAC (only one 12-bit DAC and all 6-bit DACs) powered on and clocked, comparator powered on, all ports configured as inputs with input low and no DC loads 5 WAIT 50 MHz/100 MHz core and peripheral clock, regulators are in full regulation, relaxation oscillator on, PLL powered on, core in WAIT state, all peripheral modules enabled, TMRs and SCIs using 1x clock, NanoEdge within eFlexPWM using 2x clock, ADC/DAC (one 12-bit DAC, all 6-bit DACs)/comparator powered off, all ports configured as inputs with input low and no DC loads STOP 4 MHz core and peripheral clock, regulators are in full regulation, relaxation oscillator on, PLL powered off, core in STOP state, all peripheral module and core clocks are off, ADC/DAC/Comparator powered off, all ports configured as inputs with input low and no DC loads 5 MHz mA 4 MHz 6.3 mA/10.1 mA -/- 5 -/- 5 WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 9 200 kHz core and peripheral clock from relaxation oscillator's low speed clock, relaxation oscillator in standby mode, regulators are in standby, PLL disabled, repeat NOP instructions, all peripheral modules enabled, except NanoEdge within eFlexPWM and cyclic ADCs, one 12-bit DAC and all 6-bit DACs enabled, simple loop with running from platform instruction buffer, all ports configured as inputs with input low and no DC loads 2 MHz 200 kHz core and peripheral clock from relaxation oscillator's low speed clock, relaxation oscillator in standby mode, regulators are in standby, PLL disabled, all peripheral modules enabled, except NanoEdge within eFlexPWM and cyclic ADCs, one 12-bit DAC and all 6-bit DACs enabled, core in WAIT mode, all ports configured as inputs with input low and no DC loads 2 MHz LPSTOP 200 kHz core and peripheral clock from relaxation oscillator's low speed clock, relaxation oscillator in standby mode, regulators are in standby, PLL disabled, only PITs and COP enabled, other peripheral modules disabled and clocks gated off, core in STOP mode, all ports configured as inputs with input low and no DC loads 2 MHz 1.2 mA/1.55 mA - 5 VLPRUN 32 kHz core and peripheral clock from a 64 kHz external clock source, oscillator in power down, all relaxation oscillators disabled, large regulator is in standby, small regulator is disabled, PLL disabled, repeat NOP instructions, all peripheral modules, except COP and EWM, disabled and clocks gated off, simple loop running from platform instruction buffer, all ports configured as inputs with input low and no DC loads 200 kHz 0.7 mA/1.18 mA -/- 5 VLPWAIT 32 kHz core and peripheral clock from a 64 kHz external clock source, oscillator in power down, all relaxation oscillators disabled, large regulator is in standby, small regulator is disabled, PLL disabled, all peripheral modules, except COP, disabled and clocks gated off, core in WAIT mode, all ports configured as inputs with input low and no DC loads 200 kHz 0.7 mA/1.1 mA -/- 5 LPRUN LPWAIT 3.1 2.8 mA/2.3 mA mA/2.73 5 mA 3.1 2.7 mA/2.29 mA mA/2.73 5 mA WCT101XADS, Rev. 0, 09/2016 10 NXP Semiconductors VLPSTOP 32 kHz core and peripheral clock from a 64 kHz external clock source, oscillator in power down, all relaxation oscillators disabled, large regulator is in standby, small regulator is disabled, PLL disabled, all peripheral modules, except COP, disabled and clocks gated off, core in STOP mode, all ports configured as inputs with input low and no DC loads 200 kHz 0.7 mA/1.03 mA -/- 5 Min. Max. Unit Notes 16 - ns 6 - ns 7 570.9 ns Min. Typ. Max. Unit - 2.0 - V - 2.7 - V Reset and interrupt timing Symbol tRA Characteristic Minimum desertion to First Address Fetch tRDA tIF Assertion Duration Delay from Interrupt Assertion to Fetch of first instruction (exiting STOP mode) 865 x TOSC + 8 x TSYSCLK 361.3 PMC Low-Voltage Detection (LVD) and Power-On Reset (POR) parameters Symbol Characteristic 8 VPOR_A POR Assert Voltage VPOR_R POR Release Voltage VLVI_2p7 LVI_2p7 Threshold Voltage - 2.73 - V VLVI_2p2 LVI_2p2 Threshold Voltage - 2.23 - V Description Min. Max. Unit Notes fOP TCK frequency of operation DC fSYSCLK/8 (16) MHz 10 tPW TCK clock pulse width 50 - ns tDS TMS, TDI data set-up time 5 - ns tDH TMS, TDI data hold time 5 - ns tDV TCK low to TDO data valid - 30 ns tTS TCK low to TDO tri-state - 30 ns Min. Typ. Max. Unit - 1.22 - V Short Circuit Current - 600 - mA Short Circuit Tolerance (VCAP shorted to ground) - - 30 Mins 9 JTAG timing Symbol Regulator 1.2 V parameters Symbol VCAP ISS TRSC Characteristic Output Voltage 11 12 WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 11 VREF Reference Voltage (after trim) - 1.21 - V Min. Typ. Max. Unit - - 50 MHz External clock timing Symbol Characteristic fOSC Frequency of operation (external clock driver) tPW Clock pulse width trise 13 8 External clock input rise time 14 15 ns - - 1 ns - - 1 ns tfall External clock input fall time Vih Input high voltage overdrive by an external clock 0.85xVDD - - V Vil Input low voltage overdrive by an external clock - - 0.3xVDD V Min. Typ. Max. Unit 8 8 16 MHz 200/240 - 400 MHz 35.5 - 73.2 s 40 50 60 % Min. Typ. Max. Unit 4 8 16 MHz Min. Typ. Max. Unit 7.84 8 8.16 MHz 7.76 8 8.24 MHz - 405 - kHz - +/-1.5 +/-1.5 +/-2 +/-3 % % 194/30.1 200/32 206/33.9 kHz Phase-Locked Loop (PLL) timing Symbol Characteristic fRef_PLL PLL input reference frequency fOP_PLL PLL output frequency 16 17 18 tLock_PLL PLL lock time tDC_PLL Allowed Duty Cycle of input reference External crystal or resonator specifications Symbol Characteristic fXOSC Frequency of operation Relaxation oscillator electrical specifications Symbol Characteristic 20 8 MHz Output Frequency RUN Mode * 0 C to 105 C * -40 C to 105 C Standby Mode (IRC trimmed @ 8 MHz) * -40 C to 105 C fROSC_8M fROSC_8M_Delta 8 MHz Frequency Variation over 25 C RUN Mode Due to temperature * 0 C to 105 C * -40 C to 105 C 19,21 fROSC_200k/32k 20 19, 200 kHz/32 kHz Output Frequency RUN Mode * -40 C to 105 C WCT101XADS, Rev. 0, 09/2016 12 NXP Semiconductors fROSC_200k/32k_D 19,20 elta tStab tDC_ROSC 200 kHz/32 kHz Output Frequency 19,21 Variation over 25 C RUN Mode Due to temperature * 0 C to 85 C 22 * -40 C to 105 C - +/-1.5 +/-1.5 (2.5) +/-2 +/-3 (4) % % Stabilization Time 23 * 8 MHz output 19,24 * 200 kHz/32 kHz output - 0.12 10/14.4 - s s 48 50 52 % Min. Typ. Max. Unit - 7.5 18 s - 13 113 ms - 52 452 ms Output Duty Cycle Flash specifications Symbol thvpgm4 Description Longword Program high-voltage time thversscr Sector Erase high-voltage time thversall Erase All high-voltage time 25 25,26 thversblk32k Erase Block high-voltage time for 32 25,27 KB - 52 452 ms thversblk256k Erase Block high-voltage time for 256 25,27 KB - 104 904 ms trd1sec1k/2k Read 1s Section execution time (flash 28 sector) - - 60 s - - 0.5 1.7 ms ms 27 trd1blk32k trd1blk256k Read 1s Block execution time * 32 KB FlexNVM * 256 KB program Flash tpgmchk Program Check execution time 28 - - 45 s trdrsrc Read Resource execution time 28 - - 30 s tpgm4 Program Longword execution time - 65 145 s - 14 114 ms - 55 122 465 985 ms ms - 2.4 4.7 4.7 9.3 - ms ms ms ms - - - - - 65 tersscr Erase Flash Sector execution time tersblk32k tersblk256k Erase Flash Block execution time * 32 KB FlexNVM * 256 KB program Flash tpgmsec512p tpgmsec512n tpgmsec1kp tpgmsec1kn Program Section execution time * 512 B program Flash * 512 B FlexNVM * 1 KB program Flash * 1 KB FlexNVM trd1all trdonce tpgmonce tersall 27,29 27 Read 1s All Blocks execution time Read Once execution time 28 Program Once execution time Erase All Blocks execution time 29 29 - 70/175 0.9/1.8 30 25 s 30 575/1500 ms s 30 ms WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 13 tvfykey tpgmpart32k tsetramff tsetram8k tsetram32k teewr8bers teewr8b8k teewr8b16k teewr8b32k teewr16bers teewr16b8k teewr16b16k teewr16b32k teewr32bers teewr32b8k teewr32b16k teewr32b32k tflashret10k tflashret1k Verify Backdoor Access Key execution 28 time - - 30 s Program Partition for EEPROM execution 27 time for 32 KB FlexNVM - 70 - ms - 50 0.3 0.7 0.5 1.0 s ms ms - 175 260 s - 340 385 475 1700 1800 2000 s s s - 175 260 s - 340 385 475 1700 1800 2000 s s s - 360 540 s - 545 630 810 1950 2050 2250 s s s 5 50 Set FlexRAM Function execution time * Control Code 0xFF * 8 KB EEPROM backup * 32 KB EEPROM backup 27 Byte-write to erased FlexRAM location 27,31 execution time Byte-write to FlexRAM execution time * 8 KB EEPROM backup * 16 KB EEPROM backup * 32 KB EEPROM backup 27 Word-write to erased FlexRAM location 27 execution time Word-write to FlexRAM execution time * 8 KB EEPROM backup * 16 KB EEPROM backup * 32 KB EEPROM backup 27 Longword-write to erased FlexRAM 27 location execution time Longword-write to FlexRAM execution 27 time * 8 KB EEPROM backup * 16 KB EEPROM backup * 32 KB EEPROM backup Data retention after up to 10 K cycles Data retention after up to 1 K cycles nflashcyc Cycling endurance teeret100 teeret10 33 32 - years 32 - years 32 - cycles - years 32 - years 35 K 175 K - writes 315 K 1.6 M - writes 1.27 M 6.4 M - writes 10 M 50 M - writes 20 M 100 M - writes 20 100 10 K 50 K Data retention up to 100% of write 27 endurance 5 50 Data retention up to 10% of write 27 endurance 20 100 32 27,34 neewr16 neewr128 neewr512 neewr4k neewr8k Write endurance * EEPROM backup to FlexRAM ratio = 16 * EEPROM backup to FlexRAM ratio = 128 * EEPROM backup to FlexRAM ratio = 512 * EEPROM backup to FlexRAM ratio = 4096 * EEPROM backup to FlexRAM ratio = 8192 WCT101XADS, Rev. 0, 09/2016 14 NXP Semiconductors 12-bit cyclic ADC electrical specifications Symbol VDDA VREFHX fADCCLK Characteristic Supply voltage 35 VREFH supply voltage 36 ADC conversion clock Min. Typ. Max. Unit 3.0 3.3 3.6 V VDDA V VDDA - 0.6 37 0.1/0.6 - 10/20 MHz -( VREFH - VREFL) VREFL - VREFH VREFL VREFH V V VREFL VSSA - VREFH VDDA V V - 8/6 - tADCCLK - 13 - tADCCLK - 1.8 - mA - 1 5 9 15 19 - mA mA mA mA mA - 0.1/0.02 - A - 190/0.001 - A - +/- 1.5 (3) +/- 2.2 (5) LSB 44 - +/- 0.5 (0.6) +/- 0.8 (1) LSB 44 - +/- 8 +/- 12 (13.7) - mV mV - 0.996 to 1.004 27 0.801 to 0.809 0.99 to 26 1.101 0.798 to 27 0.814 - - 10.6/9.5 - bits - - +/-3 mA - 4.8 - pF Max. Unit 38 RADC VADCIN tADC tADCPU Conversion range 26 * Fully differential * Single-ended/unipolar Input voltage range (per input) * External Reference * Internal Reference Conversion time 39 40 ADC power-up time (from adc_pdn) 26 ADC RUN current (per ADC block) 27 ADC RUN current (per ADC block) * at 600 kHz ADC clock, LP mode IADCRUN * 8.33 MHz ADC clock, 00 mode * 12.5 MHz ADC clock, 01 mode * 16.67 MHz ADC clock, 10 mode * 20 MHz ADC clock, 11 mode IADPWRDWN IVREFH ADC power down current (adc_pdn 41 enabled) VREFH current (in external mode) 43 INLADC Integral non-linearity DNLADC Differential non-linearity VOFFSET Offset 26 * Fully differential 46 * Single ended/Unipolar 43 42 45 EGAIN Gain Error ENOB Effective number of bits IINJ CADCI Input injection current 47 48 Input sampling capacitance 26 27 16-bit SAR ADC electrical specifications Symbol VDDA VDDA Characteristic Supply voltage Supply voltage delta to VDD Min. Typ. 49 2.7 - 3.6 V - 0.1 0 + 0.1 V WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 15 VSSA Supply voltage delta to VSS - 0.1 0 + 0.1 V VREFH ADC reference voltage high VDDA VDDA VDDA V VREFL ADC reference voltage low VSSA VSSA VSSA V VADIN Input voltage range VSSA - VDDA V CADIN Input capacitance * 16-bit mode * 8-/10-/12-bit mode - 8 4 10 5 pF pF RADIN Input resistance - 2 5 k fADCK ADC conversion clock frequency * 16-bit mode * 8-/10-/12-bit mode 2 1 - 12 18 MHz MHz 37.037 20.000 - 461.467 818.330 ksps ksps - - 1.7 mA 1.2 3.0 2.4 4.4 2.4 4.0 5.2 6.2 3.9 7.3 6.1 9.5 MHz MHz MHz MHz - +/- 7.0 +/- 1.0 +/- 0.5 - 2.7 to + 1.9 - 0.7 to + 0.5 LSB 52 LSB 52 LSB - - 1.0 to + 4.0 +/- 0.7 +/- 0.2 - 0.3 to + 0.5 LSB 52 LSB 52 LSB - -4 - 1.4 - 5.4 - 1.8 LSB 52 LSB - - 1 to 0 - +/- 0.5 LSB 52 LSB 50 ADC conversion rate without ADC Crate IDDA_ADC hardware averaging * 16-bit mode * 8-/10-/12-bit mode 51 Supply current fADACK ADC asynchronous clock source * ADLPC = 1, ADHSC = 0 * ADLPC = 1, ADHSC = 1 * ADLPC = 0, ADHSC = 0 * ADLPC = 0, ADHSC = 1 INLAD Integral non-linearity * 16-bit mode * 12-bit mode * < 12-bit modes DNLAD Differential non-linearity * 16-bit mode * 12-bit mode * < 12-bit modes 53 52 53 EFS Full-scale error (VADIN = VDDA) * 12-bit mode * < 12-bit modes EQ Quantization error * 16-bit mode * 12-bit mode 52 53 52 52 WCT101XADS, Rev. 0, 09/2016 16 NXP Semiconductors Effective number of bits ENOB STEMP VTEMP25 54 16-bit single-ended mode * Avg = 32 * Avg = 4 12.2 11.4 13.9 13.1 - bits bits 12-bit single-ended mode * Avg = 32 * Avg = 4 - 10.8 10.2 - bits bits Temp sensor slope under -40 C to 105 C - 1.715 - mV/C - 722 - mV Min. Typ. Max. Unit - 1 - s - - 11 s - +/- 3 +/- 4 LSB 57 - +/- 0.8 +/- 0.9 LSB 57 Temp sensor voltage 55 at 25 C 12-bit DAC electrical specifications Symbol Characteristic 56 tSETTLE Settling time under RLD = 3 k, CLD = 400 pF tDACPU DAC power-up time (from PWRDWN release to valid DACOUT) 58 INLDAC Integral non-linearity DNLDAC Differential non-linearity MONDAC Monotonicity (> 6 sigma monotonicity, < 3.4 ppm non-monotonicity) VOFFSET Offset error 58 58 58 (5% to 95% of full range) - - + 25 + 35 mV - +/- 0.5 +/- 1.5 % EGAIN Gain error VOUT Output voltage range VSSA + 0.04 - VDDA - 0.04 V SNR Signal-to-noise ratio - 85 - dB Effective number of bits - 11 - bits Min. Typ. Max. Unit 2.7 - 3.6 V - 300/- -/200 A - 36/- -/20 A Vss - VDD V - - 20 mV ENOB (5% to 95% of full range) Guaranteed Comparator and 6-bit DAC electrical specifications Symbol VDD IDDHS IDDLS Description Supply voltage Supply current, High-speed mode(EN=1, PMODE=1) 59 Supply current, Low-speed mode(EN=1, PMODE=0) 59 VAIN Analog input voltage VAIO Analog input offset voltage WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 17 Analog comparator hysteresis * CR0[HYSTCTR]=00 * CR0[HYSTCTR]=01 * CR0[HYSTCTR]=10 * CR0[HYSTCTR]=11 VH 60 - 5 13 mV - 25/10 48 mV - 55/20 105 mV - 80/30 148 mV VCMPOh Output high VDD - 0.5 - - V VCMPOl Output low - - 0.5 V - - 50 ns - - 200 ns - 40 - s - 7 - A Propagation delay, high-speed tDHS mode(EN=1, PMODE=1) 61 Propagation delay, low-speed tDLS mode(EN=1, PMODE=0) tDInit 61 Analog comparator initialization delay 62 IDAC6b 6-bit DAC current adder (enabled) RDAC6b 6-bit DAC reference inputs VDDA - VDD V INLDAC6b 6-bit DAC integral non-linearity -0.5 - 0.5 LSB 63 DNLDAC6b 6-bit DAC differential non-linearity -0.3 - 0.3 LSB 63 Min. Typ. Max. Unit - 100 - MHz - 312 - ps 1 - - ns - 25 - s Min. Max. Unit Notes Timer input period 2Ttimer + 6 - ns 67 PINHL Timer input high/low period 1Ttimer + 3 - ns 67 POUT Timer output period 2Ttimer - 2 - ns 67 Timer output high/low period 1Ttimer - 2 - ns 67 PWM timing parameters Symbol Characteristic fPWM PWM clock frequency 64,65 SPWMNEP NanoEdge Placement (NEP) step size tDFLT Delay for fault input activating to PWM output deactivated 66 tPWMPU Power-up time Quad timer timing Symbol Characteristic PIN POUTHL QSPI timing 68 Min. Symbol tC Max. Characteristic Cycle time Unit Master Slave Master Slave 60/35 60/35 - - ns tELD Enable lead time - 20/17.5 - - ns tELG Enable lag time - 20/17.5 - - ns tCH Clock (SCLK) high time 28/16.6 28/16.6 - - ns WCT101XADS, Rev. 0, 09/2016 18 NXP Semiconductors tCL Clock (SCLK) low time 28/16.6 28/16.6 - - ns tDS Data set-up time required for inputs 20/16.5 1 - - ns tDH Data hold time required for inputs 1 3 - - ns tA Access time (time to data active from high-impedance state) 5 - ns tD Disable time (hold time to high-impedance state) 5 - ns tDV Data valid for outputs - - -/5 -/15 ns tDI Data invalid 0 0 - - ns tR Rise time - - 1 1 ns tF Fall time - - 1 1 ns QSCI timing Symbol Characteristic Min. Max. Unit Notes - (fMAX_SCI /16) Mbit/s 69 BRSCI Baud rate PW RXD RXD pulse width 0.965/BRSCI 1.04/BRSCI s PW TXD TXD pulse width 0.965/BRSCI 1.04/BRSCI s LIN Slave Mode Deviation of slave node clock from nominal clock rate before synchronization - 14 14 % Deviation of slave node clock relative to the master node clock after synchronization -2 2 % 13 - Mater node bit periods 11 - Slave node bit periods Min. Max. Unit Baud rate - 1 Mbit/s TWAKEUP CAN Wakeup dominant pulse filtered - 1.5/2 s TWAKEUP CAN Wakeup dominant pulse pass 5 - s FTOL_UNSYNCH FTOL_SYNCH TBREAK Minimum break character length CAN timing Symbol BRCAN Characteristic Notes 70 IIC timing Min. Symbol Max. Characteristic Unit Min. Max. Min. Max. SCL clock frequency 0 100 0 400 kHz tHD_STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 - 0.6 - s tSCL_LOW LOW period of the SCL clock 4.7 - 1.3 - s fSCL Notes WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 19 tSCL_HIGH 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. - 0.6 - s - 0.6 - s 73 0.9 Set-up time for a repeated START condition 4.7 tHD_DAT Data hold time for IIC bus devices 0 Data set-up time 71 250 74 3.45 72 - 0 100 75 71 s - ns 72 tr Rise time of SDA and SCL signals - 1000 20 + 0.1Cb 300 ns 76 tf Fall time of SDA and SCL signals - 300 20 + 0.1Cb 300 ns 75 tSU_STOP Set-up time for STOP condition 4 - 0.6 - s tBUS_Free Bus free time between STOP and START condition 4.7 - 1.3 - s Pulse width of spikes that must be suppressed by the input filter N/A N/A 0 50 ns tSP 2. 3. 4. 5. 4 tSU_STA tSU_DAT 1. HIGH period of the SCL clock CPU clock = 4 MHz and System running from 8 MHz IRC Applicable to all wakeup times: Wakeup times (in 1,2,3,4) are measured from GPIO toggle for wakeup till GPIO toggle at the wakeup interrupt subroutine from respective stop/wait mode. CPU clock = 200 kHz and 8 MHz IRC on standby. Exit via interrupt on Port C GPIO. Clock configuration: CPU and system clocks= 100 MHz; Bus Clock = 50 MHz. Exit via an interrupt on PortC GPIO. Using 64 KHz external clock; CPU Clock = 32 KHz. Exit via an interrupt on PortC GPIO. WCT1011A supports maximum 100 MHz CPU clock and 50 MHz peripheral bus clock, maximum 100 MHz CPU and peripheral bus clock for WCT1013A. In total, WCT1013A has higher power consumption than WCT1011A in the same operating mode. For the current consumption data, the former is for WCT1011A, and the latter for WCT1013A. If the pin filter is enabled by setting the RST_FLT bit in the SIM_CTRL register to 1, the minimum pulse assertion must be greater than 21 ns. TOSC means oscillator clock cycle; TSYSCLK means system clock cycle. During 3.3 V VDD power supply ramp down. During 3.3 V VDD power supply ramp up (gated by LVI_2p7). The maximum TCK operation frequency is fSYSCLK/8 for WCT1011A, fSYSCLK/16 for WCT1013A. Value is after trim. Guaranteed by design. The chip may not function if the high or low pulse width is smaller than 6.25 ns. External clock input rise time is measured from 10% to 90%. External clock input fall time is measured from 90% to 10%. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8 MHz input. The frequency of the core system clock cannot exceed 100 MHz. If the NanoEdge PWM is available, the PLL output must be set to 400 MHz. And the minimum PLL output frequency is 200 MHz for WCT1011A, 240 MHz for WCT1013A. This is the time required after the PLL is enabled to ensure reliable operation. 200 kHz internal RC oscillator is on WCT1011A, 32 kHz internal RC oscillator on WCT1013A. Frequency after application of 8 MHz trimmed. Frequency after application of 200 kHz/32 kHz trimmed. Typical +/-1.5%, maximum +/-3% frequency variation for 200 kHz internal RC oscillator, and typical +/-2.5%, maximum +/-4% frequency variation for 32 kHz internal RC oscillator. Standby to run mode transition. Power down to run mode transition. Typical 10 s stabilization time for 200 kHz internal RC oscillator, and 14.4 s stabilization time for 32 kHz internal RC oscillator. Maximum time based on expectations at cycling end-of-life. The specification is only for WCT1011A. The specification is only for WCT1013A. Assumes 25 MHz flash clock frequency. Maximum times for erase parameters based on expectations at cycling end-of-life. All blocks size is 64 KB on WCT1011A, 256 KB on WCT1013A. Longer all blocks command operation time for WCT1013A. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25C use WCT101XADS, Rev. 0, 09/2016 20 NXP Semiconductors profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 33. Cycling endurance represents number of program/erase cycles at -40C Tj 125C. 34. Write endurance represents the number of writes to each FlexRAM location at -40C Tj 125C influenced by the cycling endurance of the FlexNVM and the allocated EEPROM backup. Minimum and typical values assume all byte-writes to FlexRAM. 35. The ADC functions up to VDDA = 2.7 V. When VDDA is below 3.0 V, ADC specifications are not guaranteed. 36. When the input is at the VREFL level, the resulting output will be all zeros (hex 000), plus any error contribution due to offset and gain error. When the input is at the VREFH level, the output will be all ones (hex FFF), minus any error contribution due to offset and gain error. 37. ADC clock duty cycle is 45% ~ 55%. WCT1011A only supports the maximum ADC clock of 10 MHz and minimum ADC clock of 0.1 MHz, and WCT1013A supports 20 MHz maximum ADC clock and 0.6 MHz minimum ADC clock. 38. Conversion range is defined for x1 gain setting. For x2 and x4 the range is 1/2 and 1/4, respectively. 39. In unipolar mode, positive input must be ensured to be always greater than negative input. 40. For WCT1011A, the first conversion takes 10 clock cycles, 8 clock cycles for the subsequent conversion; On WCT1013A, 8.5 clock cycles for the first conversion, 6 clock cycles for the subsequent conversion. 41. For WCT1011A, the power down current of ADC is 0.1 A, and 0.02 A for WCT1013A. 42. For WCT1011A, the VREFH current of ADC is 190 A, and 0.001 A for WCT1013A. 43. INLADC/DNLADC is measured from VADCIN = VREFL to VADCIN = VREFH using Histogram method at x1 gain setting. On WCT1011A, typical value is +/- 1.5 LSB, and maximum value +/- 2.2 LSB for INLADC; typical value is +/- 0.5 LSB, and maximum value +/- 0.8 LSB for DNLADC. On WCT1013A, typical value is +/- 3 LSB, and maximum value +/- 5 LSB for INLADC; typical value is +/- 0.6 LSB, and maximum value +/- 1 LSB for DNLADC. 44. Least Significant Bit = 0.806 mV at 3.3 V VDDA, x1 gain setting. 45. Any off-channel with 50 kHz full-scale input to the channel being sampled with DC input (isolation crosstalk). 46. Typical +/- 12 mV offset for WCT1011A, +/- 13.7 mV offset for WCT1013A. 47. Typical ENOB is 10.6 bits for WCT1011A, 9.5 bits for WCT1013A. 48. The current that can be injected into or sourced from an unselected ADC input without affecting the performance of the ADC. 49. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 50. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear. 51. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock speed. N 52. 1 LSB = (VREFH - VREFL)/2 . 53. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11). 54. Input data is 100 Hz sine wave; ADC conversion clock < 12 MHz. 55. System clock = 4 MHz, ADC clock = 2 MHz, AVG = Max, Long Sampling = Max. 56. Settling time is swing range from VSSA to VDDA. 57. LSB = 0.806 mV. 58. No guaranteed specification within 5% of VDDA or VSSA. 59. Typical supply current with high-speed mode is 300 A, typical supply current with low-speed mode is 36 A on WCT1011A. Maximum supply current with high-speed mode is 200 A, maximum supply current with low-speed mode is 20 A on WCT1013A. 60. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD-0.7 V. On WCT1011A, typical 25 mV for CR0[HYSTCTR] = 01, typical 55 mV for CR0[HYSTCTR] = 10, typical 80 mV for CR0[HYSTCTR] = 11. On WCT1013A, typical 10 mV for CR0[HYSTCTR] = 01, typical 20 mV for CR0[HYSTCTR] = 10, typical 30 mV for CR0[HYSTCTR] = 11. 61. Signal swing is 100 mV. 62. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 63. 1 LSB = Vreference/64. 64. Reference IPbus clock of 100 MHz in NanoEdge Placement mode. 65. Temperature and voltage variations do not affect NanoEdge Placement step size. 66. Powerdown to NanoEdge mode transition. 67. Ttimer = Timer input clock cycle. For 100 MHz operation, Ttimer = 10 ns. 68. For QSPI specifications, all data with xx/xx format, the former is for WCT1011A, the latter is for WCT1013A. 69. fMAX_SCI is the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock or 2x bus clock for the device. 70. WCT1011A supports maximum 1.5 us pulse filtered, and WCT1013A supports maximum 2 us pulse filtered. 71. The master mode IIC deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 72. The maximum tHD_DAT must be met only if the device does not stretch the LOW period (tSCL_LOW) of the SCL signal. WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 21 73. Input signal Slew = 10 ns and Output Load = 50 pF 74. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 75. A Fast mode IIC bus device can be used in a Standard mode IIC bus system, but the requirement tSU_DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU_DAT = 1000 + 250 = 1250 ns (according to the Standard mode IIC bus specification) before the SCL line is released. 76. Cb = total capacitance of the one bus line in pF. 2.3 Thermal operating characteristics Table 7. General thermal characteristics Symbol Description Min Max Unit TJ Die junction temperature -40 125 C TA Ambient temperature -40 105 C WCT101XADS, Rev. 0, 09/2016 22 NXP Semiconductors 3 Typical Performance Characteristics 3.1 System efficiency The typical system efficiency (receiver output power vs. transmitter input power) on NXP WCT101xA-based transmitter solutions can usually reach more than 65%. The detailed number depends on the specific solution type. For example, NXP WCT-15WTXAUTO reference solution has more than 70% system efficiency with the MP Qi Receiver Simulator. Note: Power components are the main factor to determine the system efficiency, such as drivers and MOSFETs. 3.2 Standby power The purpose of the standby mode of operation is to reduce the power consumption of a wireless power transfer system when power transfer is not required. There are two ways to enter standby mode. The first is when the transmitter does not detect the presence of a valid receiver. The second is when the receiver sends only an End Power Transfer Packet. In standby mode, the transmitter only monitors if a receiver is placed on the active charging area of the transmitter or removed from there. It is recommended that the power consumption of the transmitter in standby mode meets the relative regional regulations especially for "No-load power consumption". 3.3 Digital demodulation To optimize system BOM cost, the WCT101xA solution employs digital demodulation algorithm to communicate with the receiver. This method can achieve high performance, low cost, and very simple coil signal sensing circuit with less components number. 3.4 Two-way communication The WCT101xA solution supports two-way communication and uses FSK to send messages to receiver. This method allows transmitter to negotiate with receiver to establish advanced power transfer contract, and calibrate power loss for more precise FOD protection. 3.5 Foreign object detection The WCT101xA solution supports power class 0 FOD framework, which is based on calibrated power loss method and quality factor (Q factor) method. With NXP FreeMASTER GUI tool, the FOD algorithm can be easily calibrated to get accurate power loss information especially for very sensitive foreign objects. WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 23 4 Device Information 4.1 Functional block diagram This functional block diagram shows the common pin assignment information by all members of the family. For the detailed pin multiplexing information, see Section 4.4 "Pin Function Description". Figure 1. WCT1011/3AVLH function block diagram 4.2 Product features overview The following table lists the features that differ among members of the family. Features not listed are shared in common by all members of the family. Table 8. Feature comparison between WCT1011A and WCT1013A Part WCT1011A WCT1013A 100/50 100/100 38.1 (VDD) + 9.9 (VDDA) 63.7 (VDD) + 16.7 (VDDA) Program Flash Memory 64 256 FlexNVM/FlexRAM 0/0 32/2 Total Flash Memory 64 288 8 32 Memory Resource Protection Yes Yes Inter-Peripheral Crossbar Switches with AOI Yes Yes Maximum Core/Bus Clock (MHz) Maximum Fully Run Current Consumption (mA) On-Chip Flash Memory Size (KB) On-Chip SRAM Memory Size (KB) WCT101XADS, Rev. 0, 09/2016 24 NXP Semiconductors On-Chip Relaxation Oscillator 1 (8 MHz) + 1 (200 kHz) 1 (8 MHz) + 1 (32 kHz) 1 (windowed) 1 External Watchdog Monitor 1 1 Cyclic Redundancy Check 1 1 Periodic Interrupt Timer 2 2 1x4 2x4 Programmable Delay Block 0 2 12-bit Cyclic ADC Channels 2x8 2x8 0 1x8 High-Resolution 8 8 Standard 4 1 12-bit DAC 2 1 Analog Comparator /w 6-bit REF DAC 4 4 DMA Channels 4 4 Queued Serial Communications Interface 2 2 Queued Serial Peripheral Interface 2 1 Inter-Integrated Circuit 1 2 1 (MSCAN) 1 (FlexCAN) 54 54 64 LQFP 64 LQFP Computer Operating Properly (Watchdog) Quad Timer 16-bit SAR ADC Channels PWM Channels Controller Area Network GPIO Package WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 25 4.3 Pinout diagram Figure 2. WCT1011/3AVLH pinout diagram 4.4 Pin function description By default, each pin is configured for its primary function (listed first). Any alternative functionality, shown in parentheses, can be programmed through GPIO module peripheral enable registers and SIM module GPIO peripheral select registers. Table 9. Pin signal descriptions Signal name Pin No. Multiplexing signals Function description Test Clock Input -- This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pull-up resistor. A Schmitt-trigger input is used for noise immunity. TCK 1 GPIOD2 Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TCK. WCT101XADS, Rev. 0, 09/2016 26 NXP Semiconductors -- This input is a direct hardware reset on the processor. When is asserted low, the device is initialized and placed in the reset state. A Schmitt-trigger input is used for noise immunity. The internal reset signal is de-asserted synchronous with the internal clocks after a fixed number of internal clocks. 2 GPIOD4 Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. If functionality is disabled in this mode and the chip can be reset only via POR, COP reset, or software reset. After reset, the default state is . Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOC0 3 EXTAL/CLKIN0 EXTAL -- External Crystal Oscillator Input. This input connects the internal crystal oscillator input to an external crystal or ceramic resonator. CLKIN0 -- This pin serves as an external clock input 0. After reset, the default state is GPIOC0. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOC1 4 XTAL XTAL -- External Crystal Oscillator Output. This output connects the internal crystal oscillator output to an external crystal or ceramic resonator. After reset, the default state is GPIOC1. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. TXD0 -- The SCI0 transmit data output or transmit/receive in single wire operation. GPIOC2 5 TXD0/XB_OUT 11(TB0)/XB_IN 2/CLKO0 XB_OUT11 -- Crossbar module output 11 only on WCT1011A. TB0 -- Quad timer module B channel 0 input/output only on WCT1013A. XB_IN2 -- Crossbar module input 2. CLKO0 -- This is a buffered clock output 0; the clock source is selected by clock out select (CLKOSEL) bits in the clock output select register (CLKOUT) of the SIM. After reset, the default state is GPIOC2. Port F GPIO -- This GPIO pin can be individually programmed as an input or output pin. RXD0 -- The SCI0 receive data input. GPIOF8 6 RXD0/XB_OUT 10(TB1)/CMPD _O/PWM_2X XB_OUT10 -- Crossbar module output 10 only on WCT1011A. TB1 -- Quad timer module B channel 1 input/output only on WCT1013A. CMPD_O -- Analog comparator D output. PWM_2X -- NanoEdge eFlexPWM sub-module 2 output X or input capture X only on WCT1011A. GPIOC3 7 TA0/CMPA_O/ RXD0/CLKIN1 After reset, the default state is GPIOF8. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 27 TA0 -- Quad timer module A channel 0 input/output. CMPA_O -- Analog comparator A output. RXD0 -- The SCI0 receive data input. CLKIN1 -- This pin serves as an external clock input 1. After reset, the default state is GPIOC3. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. TA1 -- Quad timer module A channel 1 input/output. GPIOC4 8 TA1/CMPB_O/X B_IN6(XB_IN8)/ CMPB_O -- Analog comparator B output. XB_IN6 -- Crossbar module input 6 only on WCT1011A. XB_IN8 -- Crossbar module input 8 only on WCT1013A. -- External watchdog monitor output. After reset, the default state is GPIOC4. Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOA7 9 ANA7&CMPD_I N3(ANC11) ANA7&CMPD_IN3 -- Analog input to channel 7 of ADCA and input 3 of analog comparator D only on WCT1011A. When used as an analog input, the signal goes to the ANA7 and CMPD_IN3. ANA7&ANC11 -- Analog input to channel 7 of ADCA and analog input 11 of ADCC only on WCT1013A. When used as an analog input, the signal goes to the ANA7 and ANC11. After reset, the default state is GPIOA7. Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOA6 10 ANA6&CMPD_I N2(ANC10) ANA6&CMPD_IN2 -- Analog input to channel 6 of ADCA and input 2 of analog comparator D only on WCT1011A. When used as an analog input, the signal goes to the ANA6 and CMPD_IN2. ANA6&ANC10 -- Analog input to channel 6 of ADCA and analog input 10 of ADCC only on WCT1013A. When used as an analog input, the signal goes to the ANA6 and ANC10. After reset, the default state is GPIOA6. Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOA5 GPIOA4 11 12 ANA5&CMPD_I N1(ANC9) ANA4&CMPD_I N0&ANC8 ANA5&CMPD_IN1 -- Analog input to channel 5 of ADCA and input 1 of analog comparator D only on WCT1011A. When used as an analog input, the signal goes to the ANA5 and CMPD_IN1. ANA5&ANC9 -- Analog input to channel 5 of ADCA and analog input 9 of ADCC only on WCT1013A. When used as an analog input, the signal goes to the ANA5 and ANC9. After reset, the default state is GPIOA5. Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. ANA4&CMPD_IN0 -- Analog input to channel 4 of ADCA and input 0 of analog comparator D only on WCT1011A. When used as an analog input, WCT101XADS, Rev. 0, 09/2016 28 NXP Semiconductors the signal goes to the ANA4 and CMPD_IN0. ANA4&CMPD_IN0&ANC8 -- Analog input to channel 4 of ADCA and input 0 of analog comparator D and analog input to channel 8 of ADCC only on WCT1013A. When used as an analog input, the signal goes to the ANA4 and CMPD_IN0 and ANC8. After reset, the default state is GPIOA4. Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOA0 13 ANA0&CMPA_I N3/CMPC_O ANA0&CMPA_IN3 -- Analog input to channel 0 of ADCA and input 3 of analog comparator A. When used as an analog input, the signal goes to the ANA0 and CMPA_IN3. CMPC_O -- Analog comparator C output. After reset, the default state is GPIOA0. Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOA1 14 ANA1&CMPA_I N0 ANA1 and CMPA_IN0 -- Analog input to channel 1 of ADCA and input 0 of analog comparator A. When used as an analog input, the signal goes to the ANA1 and CMPA_IN0. After reset, the default state is GPIOA1. Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOA2 15 ANA2&VREFH A&CMPA_IN1 ANA2&VREFHA&CMPA_IN1 -- Analog input to channel 2 of ADCA and analog references high of ADCA and input 1 of analog comparator A. When used as an analog input, the signal goes to ANA2 and VREFHA and CMPA_IN1. ADC control register configures this input as ANA2 or VREFHA. After reset, the default state is GPIOA2. Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOA3 16 ANA3&VREFLA &CMPA_IN2 ANA3&VREFLA&CMPA_IN2 -- Analog input to channel 3 of ADCA and analog references low of ADCA and input 2 of analog comparator A. When used as an analog input, the signal goes to ANA3 and VREFLA and CMPA_IN2. ADC control register configures this input as ANA3 or VREFLA. After reset, the default state is GPIOA3. Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOB7 17 ANB7&CMPB_I N2&ANC15 ANB7&CMPB_IN2 -- Analog input to channel 7 of ADCB and input 2 of analog comparator B only on WCT1011A. When used as an analog input, the signal goes to the ANB7 and CMPB_IN2. ANB7&CMPB_IN2&ANC15 -- Analog input to channel 7 of ADCB and input 2 of analog comparator B and analog input to channel 15 of ADCC only on WCT1013A. When used as an analog input, the signal goes to the ANB7 and CMPB_IN2 and ANC15. After reset, the default state is GPIOB7. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOC5 18 DAC_O/XB_IN7 DAC_O -- 12-bit Digital-to-Analog Converter output. For WCT1011A, it's DACA output. WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 29 XB_IN7 -- Crossbar module input 7. After reset, the default state is GPIOC5. Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOB6 19 ANB6&CMPB_I N1&ANC14 ANB6&CMPB_IN1 -- Analog input to channel 6 of ADCB and input 1 of analog comparator B only on WCT1011A. When used as an analog input, the signal goes to the ANB6 and CMPB_IN1. ANB6&CMPB_IN1&ANC14 -- Analog input to channel 6 of ADCB and input 1 of analog comparator B and analog input to channel 14 of ADCC only on WCT1013A. When used as an analog input, the signal goes to the ANB6 and CMPB_IN1 and ANC14. After reset, the default state is GPIOB6. Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOB5 20 ANB5&CMPC_I N2&ANC13 ANB5&CMPC_IN2 -- Analog input to channel 5 of ADCB and input 2 of analog comparator C only on WCT1011A. When used as an analog input, the signal goes to the ANB5 and CMPC_IN2. ANB5&CMPC_IN2&ANC13 -- Analog input to channel 5 of ADCB and input 2 of analog comparator C and analog input to channel 13 of ADCC only on WCT1013A. When used as an analog input, the signal goes to the ANB5 and CMPC_IN2 and ANC13. After reset, the default state is GPIOB5. Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOB4 21 ANB4&CMPC_I N1&ANC12 VDDA 22 - VSSA 23 - GPIOB0 24 ANB0&CMPB_I N3 ANB4&CMPC_IN1 -- Analog input to channel 4 of ADCB and input 1 of analog comparator C only on WCT1011A. When used as an analog input, the signal goes to the ANB4 and CMPC_IN1. ANB4&CMPC_IN1&ANC12 -- Analog input to channel 4 of ADCB and input 1 of analog comparator C and analog input to channel 12 of ADCC only on WCT1013A. When used as an analog input, the signal goes to the ANB4 and CMPC_IN1 and ANC12. After reset, the default state is GPIOB4. Analog Power -- This pin supplies 3.3 V power to the analog modules. It must be connected to a clean analog power supply. Analog Ground -- This pin supplies an analog ground to the analog modules. It must be connected to a clean power supply. Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. ANB0&CMPB_IN3 -- Analog input to channel 0 of ADCB and input 3 of analog comparator B. When used as an analog input, the signal goes to ANB0 and CMPB_IN3. After reset, the default state is GPIOB0. Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOB1 25 ANB1&CMPB_I N0/DACB_O ANB1&CMPB_IN0 -- Analog input to channel 1 of ADCB and input 0 of analog comparator B. When used as an analog input, the signal goes to ANB1 and CMPB_IN0. DACB_O -- 12-bit Digital-to-Analog Converter B output only on WCT1011A. WCT101XADS, Rev. 0, 09/2016 30 NXP Semiconductors VCAP1 26 - After reset, the default state is GPIOB1. Connect a 2.2 F or greater bypass capacitor between this pin and VSS to stabilize the core voltage regulator output required for proper device operation. Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOB2 27 ANB2&VREFH B&CMPC_IN3 ANB2&VREFHB&CMPC_IN3 -- Analog input to channel 2 of ADCB and analog references high of ADCB and input 3 of analog comparator C. When used as an analog input, the signal goes to ANB2 and VREFHB and CMPC_IN3. ADC control register configures this input as ANB2 or VREFHB. After reset, the default state is GPIOB2. Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOB3 28 ANB3&VREFLB &CMPC_IN0 VDD1 VSS1 29 30 - ANB3&VREFLB&CMPC_IN0 -- Analog input to channel 3 of ADCB and analog references low of ADCB and input 0 of analog comparator C. When used as an analog input, the signal goes to ANB3 and VREFLB and CMPC_IN0. ADC control register configures this input as ANB3 or VREFLB. After reset, the default state is GPIOB3. I/O Power -- Supplies 3.3 V power to on-chip digital module. I/O Ground -- Provides ground on-chip digital module. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. TA2 -- Quad timer module A channel 2 input/output. GPIOC6 31 TA2/XB_IN3/C MP_REF/ XB_IN3 -- Crossbar module input 3. CMP_REF -- Input 5 of analog comparator A and B and C and D. -- is used in slave mode to indicate to the SPI0 module that the current transfer is to be received. This signal is only on WCT1011A. After reset, the default state is GPIOC6. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. -- is used in slave mode to indicate to the SPI0 module that the current transfer is to be received. GPIOC7 32 /TXD0/XB_I N8 TXD0 -- SCI0 transmit data output or transmit/receive in single wire operation. XB_IN8 -- Crossbar module input 8 only on WCT1011A. After reset, the default state is GPIOC7. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOC8 33 MISO0 /RXD0/XB_IN9/ XB_OUT6 MISO0 -- Master in/slave out. In master mode, this pin serves as the data input. In slave mode, this pin serves as the data output. The MISO0 line of a slave device is placed in the high-impedance state if the slave device is not selected. RXD0 -- SCI0 receive data input. WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 31 XB_IN9 -- Crossbar module input 9. XB_OUT6 -- Crossbar module output 6 only on WCT1011A. After reset, the default state is GPIOC8. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. SCLK0 -- The SPI0 serial clock. In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. GPIOC9 34 SCLK0/XB_IN4/ TXD0/XB_OUT 8 XB_IN4 -- Crossbar module input 4. TXD0 -- SCI0 transmit data output or transmit/receive in single wire operation. This signal is only on WCT1011A. XB_OUT8 -- Crossbar module output 8 only on WCT1011A. After reset, the default state is GPIOC9. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. MOSI0 -- Master out/slave in. In master mode, this pin serves as the data output. In slave mode, this pin serves as the data input. GPIOC10 35 XB_IN5 -- Crossbar module input 5. MOSI0 /XB_IN5/MISO0 /XB_OUT9 MISO0 -- Master in/slave out. In master mode, this pin serves as the data input. In slave mode, this pin serves as the data output. The MISO0 line of a slave device is placed in the high-impedance state if the slave device is not selected. XB_OUT9 -- Crossbar module output 9 only on WCT1011A. After reset, the default state is GPIOC10. Port F GPIO -- This GPIO pin can be individually programmed as an input or output pin. XB_IN6 -- Crossbar module input 6. GPIOF0 36 XB_IN6/TB2/SC LK1 TB2 -- Quad timer module B channel 2 input/output only on WCT1013A. SCLK1 -- The SPI1 serial clock. In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. After reset, the default state is GPIOF0. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. CANTX -- CAN transmit data output. GPIOC11 37 CAN_TX/SCL0( SCL1)/TXD1 SCL0 -- IIC0 serial clock only on WCT1011A. SCL1 -- IIC1 serial clock only on WCT1013A. TXD1 -- SCI1 transmit data output or transmit/receive in single wire operation. After reset, the default state is GPIOC11. WCT101XADS, Rev. 0, 09/2016 32 NXP Semiconductors Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. CANRX -- CAN receive data input. GPIOC12 38 CAN_RX/SDA0( SDA1)/RXD1 SDA0 -- IIC0 serial data line only on WCT1011A. SDA1 -- IIC1 serial data line only on WCT1013A. RXD1 -- SCI1 receive data input. After reset, the default state is GPIOC12. Port F GPIO -- This GPIO pin can be individually programmed as an input or output pin. SCL0 -- IIC0 serial clock only on WCT1011A. SCL1 -- IIC1 serial clock only on WCT1013A. GPIOF2 39 SCL0(SCL1)/XB _OUT6/MISO1 XB_OUT6 -- Crossbar module output 6. MISO1 -- Master in/slave out. In master mode, this pin serves as the data input. In slave mode, this pin serves as the data output. The MISO1 line of a slave device is placed in the high-impedance state if the slave device is not selected. This signal is only on WCT1011A. After reset, the default state is GPIOF2. Port F GPIO -- This GPIO pin can be individually programmed as an input or output pin. SDA0 -- IIC0 serial data line only on WCT1011A. SDA1 -- IIC1 serial data line only on WCT1013A. GPIOF3 40 SDA0(SDA1)/X B_OUT7/ MOSI1 XB_OUT7 -- Crossbar module output 7. MOSI1 -- Master out/slave in. In master mode, this pin serves as the data output. In slave mode, this pin serves as the data input. This signal is only on WCT1011A. After reset, the default state is GPIOF3. Port F GPIO -- This GPIO pin can be individually programmed as an input or output pin. TXD1 -- The SCI1 transmit data output or transmit/receive in single wire operation. GPIOF4 41 TXD1/XB_OUT 8/PWM_0X/PW M_FAULT6 XB_OUT8 -- Crossbar module output 8. PWM_0X -- NanoEdge eFlexPWM sub-module 0 output X or input capture X only on WCT1011A. PWM_FAULT6 -- NanoEdge eFlexPWM fault input 6 only on WCT1011A. After reset, the default state is GPIOF4. Port F GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOF5 42 RXD1/XB_OUT 9/PWM_1X/PW M_FAULT7 RXD1 -- The SCI1 receive data input. XB_OUT9 -- Crossbar module output 9. PWM_1X -- NanoEdge eFlexPWM sub-module 1 output X or input capture X only on WCT1011A. WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 33 PWM_FAULT7 -- NanoEdge eFlexPWM fault input 7 only on WCT1011A. VSS2 VDD2 43 44 - GPIOE0 45 PWM_0B After reset, the default state is GPIOF5. I/O Ground -- Provides ground to on-chip digital module. I/O Power -- Supplies 3.3 V power to on-chip digital module. Port E GPIO -- This GPIO pin can be individually programmed as an input or output pin. PWM_0B -- NanoEdge eFlexPWM sub-module 0 output B or input capture B. After reset, the default state is GPIOE0. Port E GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOE1 46 PWM_0A -- NanoEdge eFlexPWM sub-module 0 output A or input capture A. PWM_0A After reset, the default state is GPIOE1. Port E GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOE2 47 PWM_1B -- NanoEdge eFlexPWM sub-module 1 output B or input capture B. PWM_1B After reset, the default state is GPIOE2. Port E GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOE3 48 PWM_1A -- NanoEdge eFlexPWM sub-module 1 output A or input capture A. PWM_1A After reset, the default state is GPIOE3. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. TA3 -- Quad timer module A channel 3 input/output. GPIOC13 49 TA3/XB_IN6/ XB_IN6 -- Crossbar module input 6. -- External watchdog monitor output. After reset, the default state is GPIOC13. Port F GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOF1 50 CLKO1/XB_IN7/ CMPD_O CLKO1 -- This is a buffered clock output 1; the clock source is selected by clock out select (CLKOSEL) bits in the clock output select register (CLKOUT) of the SIM. XB_IN7 -- Crossbar module input 7. CMPD_O -- Analog comparator D output. GPIOE4 51 PWM_2B/XB_I N2 After reset, the default state is GPIOF1. Port E GPIO -- This GPIO pin can be individually programmed as an input or output pin. PWM_2B -- NanoEdge eFlexPWM sub-module 2 output B or input capture WCT101XADS, Rev. 0, 09/2016 34 NXP Semiconductors B. XB_IN2 -- Crossbar module input 2. After reset, the default state is GPIOE4. Port E GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOE5 52 PWM_2A -- NanoEdge eFlexPWM sub-module 2 output A or input capture A. PWM_2A/XB_I N3 XB_IN3 -- Crossbar module input 3. After reset, the default state is GPIOE5. Port E GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOE6 53 PWM_3B -- NanoEdge eFlexPWM sub-module 3 output B or input capture B. PWM_3B/XB_I N4 XB_IN4 -- Crossbar module input 4. After reset, the default state is GPIOE6. Port E GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOE7 54 PWM_3A -- NanoEdge eFlexPWM sub-module 3 output A or input capture A. PWM_3A/XB_I N5 XB_IN5 -- Crossbar module input 5. After reset, the default state is GPIOE7. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOC14 55 SDA0 -- IIC0 serial data line. SDA0/XB_OUT 4/PWM_FAULT 4 XB_OUT4 -- Crossbar module output 4. PWM_FAULT4 -- NanoEdge eFlexPWM fault input 4 only on WCT1011A. After reset, the default state is GPIOC14. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. GPIOC15 56 SCL0 -- IIC0 serial clock. SCL0/XB_OUT 5/PWM_FAULT 5 XB_OUT5 -- Crossbar module output 5. PWM_FAULT5 -- NanoEdge eFlexPWM fault input 5 only on WCT1011A. VCAP2 57 - GPIOF6 58 TB2/PWM_3X/X B_IN2 After reset, the default state is GPIOC15. Connect a 2.2 F or greater bypass capacitor between this pin and VSS to stabilize the core voltage regulator output required for proper device operation. Port F GPIO -- This GPIO pin can be individually programmed as an input or output pin. TB2 -- Quad timer module B channel 2 input/output only on WCT1013A. WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 35 PWM_3X -- NanoEdge eFlexPWM sub-module 3 output X or input capture X. XB_IN2 -- Crossbar module input 2. After reset, the default state is GPIOF6. Port F GPIO -- This GPIO pin can be individually programmed as an input or output pin. TB3 -- Quad timer module B channel 3 input/output only on WCT1013A. GPIOF7 59 TB3/CMPC_O/ /XB_IN3 CMPC_O-- Analog comparator C output. -- is used in slave mode to indicate to the SPI1 module that the current transfer is to be received. XB_IN3 -- Crossbar module input 3. VDD3 VSS3 60 61 - TDO 62 GPIOD1 After reset, the default state is GPIOF7. I/O Power -- Supplies 3.3 V power to on-chip digital module. I/O Ground -- Provides ground to on-chip digital module. Test Data Output -- This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK. Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDO. Test Mode Select Input -- This input pin is used to sequence the JTAG TAP controller's state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. TMS 63 GPIOD3 Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TMS. NOTE: Always tie the TMS pin to VDD through a 2.2 k resistor if need to keep on-board debug capability. Otherwise, directly tie to VDD. Test Data Input -- This input pin provides a serial input data stream to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. TDI 64 GPIOD0 Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDI. WCT101XADS, Rev. 0, 09/2016 36 NXP Semiconductors 4.5 Ordering information Table 10 lists the pertinent information needed to place an order. Consult a NXP Semiconductors sales office to determine availability and to order this device. Table 10. MWCT101xAVLH ordering information Device Supply voltage Package type Pin count Ambient temp. Order number MWCT1011AVLH 3.0 to 3.6V LQFP 64 -40 to +105 MWCT1011AVLH MWCT1013AVLH 3.0 to 3.6V LQFP 64 -40 to +105 MWCT1013AVLH 4.6 Package outline drawing To find a package drawing, go to nxp.com and perform a keyword search for the drawing's document number of 98ASS23234W. WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 37 5 Software Library The software for WCT101xA is matured and tested for production ready. NXP provides a Wireless Charging Transmitter (WCT) software library for speeding user designs. In this library, low-level drivers of HAL (Hardware Abstract Layer), callback functions for library access are open to user. For the software API and library details, see the WCT101xA TX Library User's Guide (WCT101XALIBUG). 5.1 Memory map WCT101xA has large on-chip Flash memory and RAM for user design. Besides wireless charging transmitter library code, the user can develop private functions and link it to library through predefined APIs. Table 11. WCT101xA memory footprint Part Memory Total size Library size FreeMASTER size EEPROM size Free size Flash 64 Kbytes 41.9 Kbytes 3.5 Kbytes 1 Kbytes 17.6 Kbytes RAM 8 Kbytes 3.22 Kbytes 0.13 Kbytes 0 Kbytes 4.65 Kbytes Flash 288 Kbytes 41.9 Kbytes 3.5 Kbytes 1 Kbytes 241.6 Kbytes RAM 32 Kbytes 3.22 Kbytes 0.13 Kbytes 0 Kbytes 28.65 Kbytes WCT1011A WCT1013A 5.2 Software library and API description For more information about WCT software library and API definition, see the WCT101xA TX Library User's Guide (WCT101XALIBUG). WCT101XADS, Rev. 0, 09/2016 38 NXP Semiconductors 6 Design Considerations 6.1 Electrical design considerations To ensure correct operations on the device and system, pay attention to the following points: The minimum bypass requirement is to place 0.01 - 0.1F capacitors positioned as near as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better tolerances. Bypass the VDD and VSS with approximately 10F, plus the number of 0.1F ceramic capacitors. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. Take special care to minimize noise levels on the VDDA and VSSA pins. It is recommended to use separate power planes for VDD and VDDA and use separate ground planes for VSS and VSSA. Connect the separate analog and digital power and ground planes as near as possible to power supply outputs. If an analog circuit and digital circuit are powered by the same power supply, connect a small inductor or ferrite bead in serial with VDDA trace. If desired, connect an external RC circuit to the RESET pin. The resistor value should be in the range of 4.7 k - 10 k; and the capacitor value should be in the range of 0.1F - 4.7F. Add a 2.2 k external pull-up on the TMS pin of the JTAG port to keep device in a restate during normal operation if JTAG converter is not present. During reset and after reset but before I/O initialization, all I/O pins are at input mode with internal weak pull-up. To eliminate PCB trace impedance effect, each ADC input should have a no less than 33pF/10 RC filter. To assure chip reliable operation, reserve enough margin for chip electrical design. Figure 3 shows the relationship between electrical ratings and electrical operating characteristics for correct chip operation. WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 39 g tin l ra ica ctr e l E Fatal range Expected permanent failure ) in. (m lo ica ctr Ele Degraded operating range - No permanent failure - Possible decreased life per atin ) in. (m cs i t s eri act har gc Normal operating range - No permanent failure - Correct operation - Possible incorrect operation lo ica ctr Ele per atin ) ax. (m cs i t s eri act har gc g tin l ra ica ctr e l E Degraded operating range - No permanent failure - Possible decreased life ) ax. (m Fatal range Expected permanent failure - Possible incorrect operation Operating (power on) nd Ha g lin ing rat ) in. (m nd Ha g lin ing rat ) ax. (m Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure Handling (power off) Figure 3. Relationship between ratings and operating characteristics 6.2 PCB layout considerations Provide a low-impedance path from the board power supply to each VDD pin on the device and from the board ground to each VSS pin. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS pins are as short as possible. PCB trace lengths should be minimal for high-frequency signals. Physically separate analog components from noisy digital components by ground planes. Do not place an analog trace in parallel with digital traces. Place an analog ground trace around an analog signal trace to isolate it from digital traces. The decoupling capacitors of 0.1F must be placed on the VDD pins as close as possible, and place those ceramic capacitors on the same PCB layer with WCT101xA device. VIA is not recommend between the VDD pins and decoupling capacitors. As the wireless charging system functions as a switching-mode power supply, the power components layout is very important for the whole system power transfer efficiency and EMI performance. The power routing loop should be as small and short as possible. Especially for the resonant network, the traces of this circuit should be short and wide, and the current loop should be optimized smaller for the MOSFETs, resonant capacitor and primary coil. Another important thing is that the control circuit and power circuit should be separated. 6.3 Thermal design considerations WCT101xA power consumption is not so critical, so there is not additional part needed for power dissipation. However, the power inverter needs the additional PCB Cu copper to dissipate the heat, so WCT101XADS, Rev. 0, 09/2016 40 NXP Semiconductors good thermal package MOSFET is recommended, such as DFN package, and for the resonant capacitor, COG material, and 1206 or 1210 package are recommended to meet the thermal requirement. The worst thermal case is on the inverter, so the user should make some special actions to dissipate the heat for good transmitter system thermal performance. WCT101XADS, Rev. 0, 09/2016 NXP Semiconductors 41 7 Links nxp.com nxp.com/products/power-management/wireless-charging-ics www.wirelesspowerconsortium.com 8 Revision History This table summarizes revisions to this document. Table 12. Revision history Revision number Date Substantial changes 0 09/2016 Initial release. WCT101XADS, Rev. 0, 09/2016 42 NXP Semiconductors How to Reach Us: Home Page: www.nxp.com Web Support: www.nxp.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/SalesTermsandConditions. Freescale, the Freescale logo, and Kinetis are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. All rights reserved. (c) 2016 Freescale Semiconductor, Inc. All rights reserved. Document Number: WCT101XADS Rev. 0 09/2016